1 /** 2 ****************************************************************************** 3 * @file stm32wlxx_hal_pwr_ex.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2020 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WLxx_HAL_PWR_EX_H 21 #define STM32WLxx_HAL_PWR_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wlxx_hal_def.h" 29 30 /** @addtogroup STM32WLxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup PWREx PWREx 35 * @brief PWR Extended HAL module driver 36 * @{ 37 */ 38 39 40 /* Exported types ------------------------------------------------------------*/ 41 42 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief PWR PVM configuration structure definition 48 */ 49 typedef struct 50 { 51 uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. 52 This parameter can be a value of @ref PWREx_PVM_Type. 53 @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. 54 */ 55 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 56 This parameter can be a value of @ref PWREx_PVM_Mode. */ 57 } PWR_PVMTypeDef; 58 59 /** 60 * @} 61 */ 62 63 /* Private constants ---------------------------------------------------------*/ 64 /** @defgroup PWREx_Private_Constants PWR Extended Private Constants 65 * @{ 66 */ 67 #define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polarity */ 68 69 /** @defgroup PWR_FLAG_REG PWR flag register 70 * @{ 71 */ 72 #define PWR_FLAG_REG_SR1 (0x20UL) /* Bitfield to indicate PWR flag located in register PWR_SR1 */ 73 #define PWR_FLAG_REG_SR2 (0x40UL) /* Bitfield to indicate PWR flag located in register PWR_SR2 */ 74 #define PWR_FLAG_REG_EXTSCR (0x60UL) /* Bitfield to indicate PWR flag located in register PWR_EXTSCR */ 75 #define PWR_FLAG_REG_MASK_POS (5UL) /* Bitfield mask position to indicate PWR flag location in PWR register */ 76 #define PWR_FLAG_REG_MASK (PWR_FLAG_REG_SR1 | PWR_FLAG_REG_SR2 | PWR_FLAG_REG_EXTSCR) /* Bitfield mask to indicate PWR flag location in PWR register */ 77 #define PWR_FLAG_EXTSCR_CLR_POS (16UL) /* Bitfield for register PWR_EXTSCR clearable bits positions: position of bitfield in flag literals */ 78 #if defined(DUAL_CORE) 79 #define PWR_FLAG_EXTSCR_CLR_MASK ((PWR_EXTSCR_C1CSSF_Pos | PWR_EXTSCR_C2CSSF_Pos) << PWR_FLAG_EXTSCR_CLR_POS) /* Bitfield for register PWR_EXTSCR clearable bits positions: mask of bitfield in flag literals */ 80 #else 81 #define PWR_FLAG_EXTSCR_CLR_MASK ((PWR_EXTSCR_C1CSSF_Pos) << PWR_FLAG_EXTSCR_CLR_POS) /* Bitfield for register PWR_EXTSCR clearable bits positions: mask of bitfield in flag literals */ 82 #endif 83 /** 84 * @} 85 */ 86 87 /** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask 88 * @{ 89 */ 90 /* Note: On STM32WL series, power PVD event is not available on EXTI lines */ 91 /* (only interruption is available through EXTI line 16). */ 92 #define PVM_MODE_IT (0x00010000UL) /*!< Mask for interruption yielded by PVM threshold crossing */ 93 #define PVM_RISING_EDGE (0x00000001UL) /*!< Mask for rising edge set as PVM trigger */ 94 #define PVM_FALLING_EDGE (0x00000002UL) /*!< Mask for falling edge set as PVM trigger */ 95 #define PVM_RISING_FALLING_EDGE (0x00000003UL) /*!< Mask for rising and falling edges set as PVM trigger */ 96 97 /** 98 * @} 99 */ 100 101 /** 102 * @} 103 */ 104 105 /* Exported constants --------------------------------------------------------*/ 106 107 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 108 * @{ 109 */ 110 111 /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins 112 * @{ 113 */ 114 #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 115 #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 116 #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 117 118 #define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */ 119 #define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */ 120 #define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */ 121 /** 122 * @} 123 */ 124 125 /* Literals kept for legacy purpose */ 126 #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 127 #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 128 #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 129 130 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type 131 * @{ 132 */ 133 #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ 134 /** 135 * @} 136 */ 137 138 /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode 139 * @{ 140 */ 141 /* Note: On STM32WL series, power PVM event is not available on EXTI lines */ 142 /* (only interruption is available through EXTI line 34). */ 143 #define PWR_PVM_MODE_NORMAL (0x00000000UL) /*!< basic mode is used */ 144 145 #define PWR_PVM_MODE_IT_RISING (PVM_MODE_IT | PVM_RISING_EDGE) /*!< External Interrupt Mode with Rising edge trigger detection */ 146 #define PWR_PVM_MODE_IT_FALLING (PVM_MODE_IT | PVM_FALLING_EDGE) /*!< External Interrupt Mode with Falling edge trigger detection */ 147 #define PWR_PVM_MODE_IT_RISING_FALLING (PVM_MODE_IT | PVM_RISING_FALLING_EDGE) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 148 /** 149 * @} 150 */ 151 152 /** @defgroup PWREx_Flash_PowerDown Flash Power Down modes 153 * @{ 154 */ 155 #define PWR_FLASHPD_LPRUN PWR_CR1_FPDR /*!< Enable Flash power down in low power run mode */ 156 #define PWR_FLASHPD_LPSLEEP PWR_CR1_FPDS /*!< Enable Flash power down in low power sleep mode */ 157 /** 158 * @} 159 */ 160 161 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale 162 * @{ 163 */ 164 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */ 165 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz */ 166 /** 167 * @} 168 */ 169 170 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection 171 * @{ 172 */ 173 #define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000UL) /*!< VBAT charging through a 5 kOhms resistor */ 174 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 175 /** 176 * @} 177 */ 178 179 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging 180 * @{ 181 */ 182 #define PWR_BATTERY_CHARGING_DISABLE (0x00000000UL) 183 #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE 184 /** 185 * @} 186 */ 187 188 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode 189 * @{ 190 */ 191 #define PWR_GPIO_BIT_0 PWR_PUCRB_PB0 /*!< GPIO port I/O pin 0 */ 192 #define PWR_GPIO_BIT_1 PWR_PUCRB_PB1 /*!< GPIO port I/O pin 1 */ 193 #define PWR_GPIO_BIT_2 PWR_PUCRB_PB2 /*!< GPIO port I/O pin 2 */ 194 #define PWR_GPIO_BIT_3 PWR_PUCRB_PB3 /*!< GPIO port I/O pin 3 */ 195 #define PWR_GPIO_BIT_4 PWR_PUCRB_PB4 /*!< GPIO port I/O pin 4 */ 196 #define PWR_GPIO_BIT_5 PWR_PUCRB_PB5 /*!< GPIO port I/O pin 5 */ 197 #define PWR_GPIO_BIT_6 PWR_PUCRB_PB6 /*!< GPIO port I/O pin 6 */ 198 #define PWR_GPIO_BIT_7 PWR_PUCRB_PB7 /*!< GPIO port I/O pin 7 */ 199 #define PWR_GPIO_BIT_8 PWR_PUCRB_PB8 /*!< GPIO port I/O pin 8 */ 200 #define PWR_GPIO_BIT_9 PWR_PUCRB_PB9 /*!< GPIO port I/O pin 9 */ 201 #define PWR_GPIO_BIT_10 PWR_PUCRB_PB10 /*!< GPIO port I/O pin 10 */ 202 #define PWR_GPIO_BIT_11 PWR_PUCRB_PB11 /*!< GPIO port I/O pin 11 */ 203 #define PWR_GPIO_BIT_12 PWR_PUCRB_PB12 /*!< GPIO port I/O pin 12 */ 204 #define PWR_GPIO_BIT_13 PWR_PUCRB_PB13 /*!< GPIO port I/O pin 14 */ 205 #define PWR_GPIO_BIT_14 PWR_PDCRB_PB14 /*!< GPIO port I/O pin 14 */ 206 #define PWR_GPIO_BIT_15 PWR_PUCRB_PB15 /*!< GPIO port I/O pin 15 */ 207 /** 208 * @} 209 */ 210 211 /** @defgroup PWREx_GPIO GPIO port 212 * @{ 213 */ 214 #define PWR_GPIO_A (0x00000000UL) /*!< GPIO port A */ 215 #define PWR_GPIO_B (0x00000001UL) /*!< GPIO port B */ 216 #define PWR_GPIO_C (0x00000002UL) /*!< GPIO port C */ 217 #define PWR_GPIO_H (0x00000007UL) /*!< GPIO port H */ 218 /** 219 * @} 220 */ 221 222 /** @defgroup PWR_EC_EOL_OPERATING_MODES Monitoring of supply voltage for radio operating level (radio End Of Life) 223 * @{ 224 */ 225 #define PWR_RADIO_EOL_DISABLE (0x00000000UL) /*!< Monitoring of supply voltage for radio operating level (radio End Of Life) disable */ 226 #define PWR_RADIO_EOL_ENABLE (PWR_CR5_RFEOLEN) /*!< Monitoring of supply voltage for radio operating level (radio End Of Life) enable */ 227 /** 228 * @} 229 */ 230 231 /** @defgroup PWR_EC_SMPS_OPERATING_MODES SMPS Step down converter operating modes 232 * @{ 233 */ 234 #define PWR_SMPS_BYPASS (0x00000000UL) /*!< SMPS step down in bypass mode */ 235 #define PWR_SMPS_STEP_DOWN (PWR_CR5_SMPSEN) /*!< SMPS step down in step down mode if system low power mode is run, LP run or stop0. If system low power mode is stop1, stop2, standby, shutdown, then SMPS is forced in mode open to preserve energy stored in decoupling capacitor as long as possible. Note: In case of a board without SMPS coil mounted, SMPS should not be activated. */ 236 /** 237 * @} 238 */ 239 240 /** @defgroup PWR_EC_RADIO_BUSY_POLARITY Radio busy signal polarity 241 * @{ 242 */ 243 #define PWR_RADIO_BUSY_POLARITY_RISING (0x00000000UL) /*!< Radio busy signal polarity to rising edge (detection on high level). */ 244 #define PWR_RADIO_BUSY_POLARITY_FALLING (PWR_CR4_WRFBUSYP) /*!< Radio busy signal polarity to falling edge (detection on low level). */ 245 /** 246 * @} 247 */ 248 249 /** @defgroup PWR_EC_RADIO_BUSY_TRIGGER Radio busy trigger 250 * @{ 251 */ 252 #define PWR_RADIO_BUSY_TRIGGER_NONE (0x00000000UL) /*!< Radio busy trigger action: no wake-up from low-power mode and no interruption sent to the selected CPU. */ 253 #define PWR_RADIO_BUSY_TRIGGER_WU_IT (PWR_CR3_EWRFBUSY) /*!< Radio busy trigger action: wake-up from low-power mode Standby and interruption sent to the selected CPU. */ 254 /** 255 * @} 256 */ 257 258 /** @defgroup PWR_EC_RADIO_IRQ_TRIGGER Radio IRQ trigger 259 * @{ 260 */ 261 #define PWR_RADIO_IRQ_TRIGGER_NONE (0x00000000UL) /*!< Radio IRQ trigger action: no wake-up from low-power mode and no interruption sent to the selected CPU. */ 262 #define PWR_RADIO_IRQ_TRIGGER_WU_IT (PWR_CR3_EWRFIRQ) /*!< Radio IRQ trigger action: wake-up from low-power mode Standby and interruption sent to the selected CPU. */ 263 /** 264 * @} 265 */ 266 267 /** @defgroup PWREx_Flag PWR Status Flags 268 * Elements values convention: 0000 0000 0XXY YYYYb 269 * - Y YYYY : Flag position in the XX register (5 bits) 270 * - XX : Status register (2 bits) 271 * - 01: SR1 register 272 * - 10: SR2 register 273 * - 11: EXTSCR register 274 * @{ 275 */ 276 /*--------------------------------SR1-------------------------------*/ 277 #define PWR_FLAG_WUF1 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF1_Pos) /*!< Wakeup event on wakeup pin 1 */ 278 #define PWR_FLAG_WUF2 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF2_Pos) /*!< Wakeup event on wakeup pin 2 */ 279 #define PWR_FLAG_WUF3 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF3_Pos) /*!< Wakeup event on wakeup pin 3 */ 280 #define PWR_FLAG_WU (PWR_FLAG_REG_SR1 | PWR_SR1_WUF) /*!< Encompass wakeup event on all wakeup pins */ 281 #define PWR_FLAG_WPVD (PWR_FLAG_REG_SR1 | PWR_SR1_WPVDF_Pos) /*!< Wakeup PVD flag */ 282 #define PWR_FLAG_HOLDC2I (PWR_FLAG_REG_SR1 | PWR_SR1_C2HF_Pos) /*!< CPU2 on-Hold Interrupt Flag */ 283 #define PWR_FLAG_WUFI (PWR_FLAG_REG_SR1 | PWR_SR1_WUFI_Pos) /*!< Wakeup on internal wakeup line */ 284 #define PWR_FLAG_WRFBUSY (PWR_FLAG_REG_SR1 | PWR_SR1_WRFBUSYF_Pos) /*!< Wakeup radio busy flag (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software) */ 285 /*--------------------------------SR2-------------------------------*/ 286 #define PWR_FLAG_LDORDY (PWR_FLAG_REG_SR2 | PWR_SR2_LDORDY_Pos) /*!< Main LDO ready flag */ 287 #define PWR_FLAG_SMPSRDY (PWR_FLAG_REG_SR2 | PWR_SR2_SMPSRDY_Pos) /*!< SMPS ready Flag */ 288 #define PWR_FLAG_REGLPS (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPS_Pos) /*!< Low-power regulator started and ready flag */ 289 #define PWR_FLAG_REGLPF (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPF_Pos) /*!< Low-power regulator (main regulator or low-power regulator used) flag */ 290 #define PWR_FLAG_REGMRS (PWR_FLAG_REG_SR2 | PWR_SR2_REGMRS_Pos) /*!< Main regulator supply from LDO or SMPS or directly from VDD */ 291 #define PWR_FLAG_FLASHRDY (PWR_FLAG_REG_SR2 | PWR_SR2_FLASHRDY_Pos) /*!< Flash ready flag */ 292 #define PWR_FLAG_VOSF (PWR_FLAG_REG_SR2 | PWR_SR2_VOSF_Pos) /*!< Voltage scaling flag */ 293 #define PWR_FLAG_PVDO (PWR_FLAG_REG_SR2 | PWR_SR2_PVDO_Pos) /*!< Power Voltage Detector output flag */ 294 #define PWR_FLAG_PVMO3 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO3_Pos) /*!< Power Voltage Monitoring 3 output flag */ 295 #define PWR_FLAG_RFEOL (PWR_FLAG_REG_SR2 | PWR_SR2_RFEOLF_Pos) /*!< Power Voltage Monitoring Radio end of life flag */ 296 #define PWR_FLAG_RFBUSYS (PWR_FLAG_REG_SR2 | PWR_SR2_RFBUSYS_Pos) /*!< Radio busy signal flag (current status) */ 297 #define PWR_FLAG_RFBUSYMS (PWR_FLAG_REG_SR2 | PWR_SR2_RFBUSYMS_Pos) /*!< Radio busy masked signal flag (current status) */ 298 #define PWR_FLAG_C2BOOTS (PWR_FLAG_REG_SR2 | PWR_SR2_C2BOOTS_Pos) /*!< CPU2 boot request source information flag */ 299 /*------------------------------EXTSCR------------------------------*/ 300 #define PWR_FLAG_SB (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1SBF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Standby flag for CPU1 */ 301 #define PWR_FLAG_STOP2 (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1STOP2F_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop 2 flag for CPU1 */ 302 #define PWR_FLAG_STOP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1STOPF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop 0 or Stop 1 flag for CPU1 */ 303 #if defined(DUAL_CORE) 304 #define PWR_FLAG_C2SB (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2SBF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Standby flag for CPU2 */ 305 #define PWR_FLAG_C2STOP2 (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2STOP2F_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop 2 flag for CPU2 */ 306 #define PWR_FLAG_C2STOP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2STOPF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop 0 or Stop 1 flag for CPU2 */ 307 #endif 308 309 #define PWR_FLAG_LPMODES (PWR_FLAG_SB) /*!< System flag encompassing all low-powers flags (Stop0, 1, 2 and Standby) for CPU1, used when clearing flags */ 310 #if defined(DUAL_CORE) 311 #define PWR_FLAG_C2LPMODES (PWR_FLAG_C2SB) /*!< System flag encompassing all low-powers flags (Stop0, 1, 2 and Standby) for CPU2, used when clearing flags */ 312 #endif 313 314 #define PWR_FLAG_C1DEEPSLEEP (PWR_EXTSCR_C1DS_Pos | PWR_FLAG_REG_EXTSCR) /*!< CPU1 DeepSleep Flag */ 315 #if defined(DUAL_CORE) 316 #define PWR_FLAG_C2DEEPSLEEP (PWR_EXTSCR_C2DS_Pos | PWR_FLAG_REG_EXTSCR) /*!< CPU2 DeepSleep Flag */ 317 #endif 318 /** 319 * @} 320 */ 321 322 /** @defgroup PWREx_Core_Select PWREx Core definition 323 * @{ 324 */ 325 #define PWR_CORE_CPU1 (0x00000000UL) 326 #if defined(DUAL_CORE) 327 #define PWR_CORE_CPU2 (0x00000001UL) 328 #endif 329 /** 330 * @} 331 */ 332 333 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines 334 * @{ 335 */ 336 #define PWR_EXTI_LINE_PVM3 (LL_EXTI_LINE_34) /*!< External interrupt line 34 connected to PVM3 */ 337 /** 338 * @} 339 */ 340 341 /** 342 * @} 343 */ 344 345 /* Exported macros -----------------------------------------------------------*/ 346 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 347 * @{ 348 */ 349 350 /** 351 * @brief Enable the PVM3 Extended Interrupt line. 352 * @retval None 353 */ 354 #if defined(CORE_CM0PLUS) 355 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3) 356 #else 357 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3) 358 #endif 359 360 /** 361 * @brief Disable the PVM3 Extended Interrupt line. 362 * @retval None 363 */ 364 #if defined(CORE_CM0PLUS) 365 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3) 366 #else 367 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3) 368 #endif 369 370 /** 371 * @brief Enable the PVM3 Event line. 372 * @retval None 373 */ 374 #if defined(CORE_CM0PLUS) 375 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3) 376 #else 377 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3) 378 #endif 379 380 /** 381 * @brief Disable the PVM3 Event line. 382 * @retval None 383 */ 384 #if defined(CORE_CM0PLUS) 385 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3) 386 #else 387 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3) 388 #endif 389 390 /** 391 * @brief Enable the PVM3 Extended Interrupt Rising Trigger. 392 * @note PVM3 flag polarity is inverted compared to EXTI line, therefore 393 * EXTI rising and falling logic edges are inverted versus PVM3 voltage edges. 394 * @retval None 395 */ 396 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableFallingTrig_32_63(PWR_EXTI_LINE_PVM3) 397 398 /** 399 * @brief Disable the PVM3 Extended Interrupt Rising Trigger. 400 * @note PVM3 flag polarity is inverted compared to EXTI line, therefore 401 * EXTI rising and falling logic edges are inverted versus PVM3 voltage edges. 402 * @retval None 403 */ 404 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableFallingTrig_32_63(PWR_EXTI_LINE_PVM3) 405 406 /** 407 * @brief Enable the PVM3 Extended Interrupt Falling Trigger. 408 * @note PVM3 flag polarity is inverted compared to EXTI line, therefore 409 * EXTI rising and falling logic edges are inverted versus PVM3 voltage edges. 410 * @retval None 411 */ 412 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableRisingTrig_32_63(PWR_EXTI_LINE_PVM3) 413 414 415 /** 416 * @brief Disable the PVM3 Extended Interrupt Falling Trigger. 417 * @note PVM3 flag polarity is inverted compared to EXTI line, therefore 418 * EXTI rising and falling logic edges are inverted versus PVM3 voltage edges. 419 * @retval None 420 */ 421 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableRisingTrig_32_63(PWR_EXTI_LINE_PVM3) 422 423 /** 424 * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. 425 * @retval None 426 */ 427 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ 428 do { \ 429 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ 430 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ 431 } while(0) 432 433 /** 434 * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. 435 * @retval None 436 */ 437 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ 438 do { \ 439 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ 440 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ 441 } while(0) 442 443 /** 444 * @brief Generate a Software interrupt on selected EXTI line. 445 * @retval None 446 */ 447 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_32_63(PWR_EXTI_LINE_PVM3) 448 449 /** 450 * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. 451 * @retval EXTI PVM3 Line Status. 452 */ 453 #define __HAL_PWR_PVM3_EXTI_GET_FLAG() LL_EXTI_ReadFlag_32_63(PWR_EXTI_LINE_PVM3) 454 455 /** 456 * @brief Clear the PVM3 EXTI flag. 457 * @retval None 458 */ 459 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(PWR_EXTI_LINE_PVM3) 460 461 462 /** 463 * @brief Configure the main internal regulator output voltage. 464 * @param __REGULATOR__ specifies the regulator output voltage to achieve 465 * a tradeoff between performance and power consumption. 466 * This parameter can be one of the following values: 467 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, 468 * typical output voltage at 1.2 V, 469 * system frequency up to 64 MHz. 470 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, 471 * typical output voltage at 1.0 V, 472 * system frequency up to 16 MHz. 473 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check 474 * whether or not VOSF flag is cleared when moving from range 2 to range 1. User 475 * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. 476 * @retval None 477 */ 478 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ 479 __IO uint32_t tmpreg; \ 480 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ 481 /* Delay after an RCC peripheral clock enabling */ \ 482 tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ 483 UNUSED(tmpreg); \ 484 } while(0) 485 486 /** 487 * @} 488 */ 489 490 /* Private macros --------------------------------------------------------*/ 491 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 492 * @{ 493 */ 494 495 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ 496 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ 497 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ 498 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ 499 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ 500 ((PIN) == PWR_WAKEUP_PIN3_LOW)) 501 502 #define IS_PWR_PVM_TYPE(__TYPE__) (((__TYPE__) == PWR_PVM_3)) 503 504 #define IS_PWR_PVM_MODE(__MODE__) (((__MODE__) == PWR_PVM_MODE_NORMAL) ||\ 505 ((__MODE__) == PWR_PVM_MODE_IT_RISING) ||\ 506 ((__MODE__) == PWR_PVM_MODE_IT_FALLING) ||\ 507 ((__MODE__) == PWR_PVM_MODE_IT_RISING_FALLING)) 508 509 #define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) != 0x00UL) && \ 510 (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) == 0x00UL)) 511 512 #define IS_PWR_VOLTAGE_SCALING_RANGE(__RANGE__) (((__RANGE__) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 513 ((__RANGE__) == PWR_REGULATOR_VOLTAGE_SCALE2)) 514 515 #define IS_PWR_BATTERY_RESISTOR_SELECT(__RESISTOR__) (((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 516 ((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 517 518 #define IS_PWR_BATTERY_CHARGING(__CHARGING__) (((__CHARGING__) == PWR_BATTERY_CHARGING_DISABLE) ||\ 519 ((__CHARGING__) == PWR_BATTERY_CHARGING_ENABLE)) 520 521 #define IS_PWR_GPIO_BIT_NUMBER(__BIT_NUMBER__) (((__BIT_NUMBER__) & GPIO_PIN_MASK) != (uint32_t)0x00) 522 523 #define IS_PWR_GPIO(__GPIO__) (((__GPIO__) == PWR_GPIO_A) ||\ 524 ((__GPIO__) == PWR_GPIO_B) ||\ 525 ((__GPIO__) == PWR_GPIO_C) ||\ 526 ((__GPIO__) == PWR_GPIO_H)) 527 528 #define IS_PWR_SMPS_MODE(__SMPS_MODE__) (((__SMPS_MODE__) == PWR_SMPS_BYPASS) ||\ 529 ((__SMPS_MODE__) == PWR_SMPS_STEP_DOWN)) 530 531 #define IS_RADIO_BUSY_POLARITY(__RADIO_BUSY_POLARITY__) (((__RADIO_BUSY_POLARITY__) == PWR_RADIO_BUSY_POLARITY_RISING) ||\ 532 ((__RADIO_BUSY_POLARITY__) == PWR_RADIO_BUSY_POLARITY_FALLING)) 533 534 #define IS_PWR_RADIO_BUSY_TRIGGER(__RADIO_BUSY_TRIGGER__) (((__RADIO_BUSY_TRIGGER__) == PWR_RADIO_BUSY_TRIGGER_NONE) ||\ 535 ((__RADIO_BUSY_TRIGGER__) == PWR_RADIO_BUSY_TRIGGER_WU_IT)) 536 537 #define IS_RADIO_IRQ_TRIGGER(__RADIO_IRQ_TRIGGER__) (((__RADIO_IRQ_TRIGGER__) == PWR_RADIO_IRQ_TRIGGER_NONE) ||\ 538 ((__RADIO_IRQ_TRIGGER__) == PWR_RADIO_IRQ_TRIGGER_WU_IT)) 539 540 #if defined(DUAL_CORE) 541 #define IS_PWR_CORE(__CPU__) (((__CPU__) == PWR_CORE_CPU1) || ((__CPU__) == PWR_CORE_CPU2)) 542 #else 543 #define IS_PWR_CORE(__CPU__) (((__CPU__) == PWR_CORE_CPU1)) 544 #endif 545 546 #if defined(DUAL_CORE) 547 #define IS_PWR_CORE_HOLD_RELEASE(__CPU__) ((__CPU__) == PWR_CORE_CPU2) 548 #endif 549 550 /** 551 * @} 552 */ 553 554 555 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 556 * @{ 557 */ 558 559 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 560 * @{ 561 */ 562 563 564 /* Peripheral Control functions **********************************************/ 565 uint32_t HAL_PWREx_GetVoltageRange(void); 566 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); 567 568 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); 569 void HAL_PWREx_DisableBatteryCharging(void); 570 571 void HAL_PWREx_EnableInternalWakeUpLine(void); 572 void HAL_PWREx_DisableInternalWakeUpLine(void); 573 574 void HAL_PWREx_SetRadioBusyPolarity(uint32_t RadioBusyPolarity); 575 void HAL_PWREx_SetRadioBusyTrigger(uint32_t RadioBusyTrigger); 576 void HAL_PWREx_SetRadioIRQTrigger(uint32_t RadioIRQTrigger); 577 578 void HAL_PWREx_EnableHOLDC2IT(void); 579 void HAL_PWREx_DisableHOLDC2IT(void); 580 581 void HAL_PWREx_HoldCore(uint32_t CPU); 582 void HAL_PWREx_ReleaseCore(uint32_t CPU); 583 584 #ifdef CORE_CM0PLUS 585 void HAL_PWREx_EnableWakeUp_ILAC(void); 586 void HAL_PWREx_DisableWakeUp_ILAC(void); 587 uint32_t HAL_PWREx_IsEnabledWakeUp_ILAC(void); 588 #endif 589 590 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 591 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 592 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 593 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 594 void HAL_PWREx_EnablePullUpPullDownConfig(void); 595 void HAL_PWREx_DisablePullUpPullDownConfig(void); 596 597 void HAL_PWREx_EnableSRAMRetention(void); 598 void HAL_PWREx_DisableSRAMRetention(void); 599 600 void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode); 601 void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode); 602 603 void HAL_PWREx_EnableWPVD(void); 604 void HAL_PWREx_DisableWPVD(void); 605 void HAL_PWREx_EnableBORPVD_ULP(void); 606 void HAL_PWREx_DisableBORPVD_ULP(void); 607 608 void HAL_PWREx_EnablePVM3(void); 609 void HAL_PWREx_DisablePVM3(void); 610 611 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); 612 613 void HAL_PWREx_SetRadioEOL(uint32_t RadioEOL); 614 void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode); 615 uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void); 616 617 /* Low Power modes configuration functions ************************************/ 618 void HAL_PWREx_EnableLowPowerRunMode(void); 619 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); 620 621 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); 622 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); 623 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); 624 void HAL_PWREx_EnterSHUTDOWNMode(void); 625 626 void HAL_PWREx_PVD_PVM_IRQHandler(void); 627 628 void HAL_PWREx_PVM3Callback(void); 629 630 /** 631 * @} 632 */ 633 634 /** 635 * @} 636 */ 637 638 /** 639 * @} 640 */ 641 642 /** 643 * @} 644 */ 645 646 #ifdef __cplusplus 647 } 648 #endif 649 650 651 #endif /* STM32WLxx_HAL_PWR_EX_H */ 652 653
