1 /** 2 ****************************************************************************** 3 * @file stm32wlxx_hal_i2s.h 4 * @author MCD Application Team 5 * @brief Header file of I2S HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2020 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WLxx_HAL_I2S_H 21 #define STM32WLxx_HAL_I2S_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wlxx_hal_def.h" 29 30 /** @addtogroup STM32WLxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup I2S 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup I2S_Exported_Types I2S Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief I2S Init structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Mode; /*!< Specifies the I2S operating mode. 49 This parameter can be a value of @ref I2S_Mode */ 50 51 uint32_t Standard; /*!< Specifies the standard used for the I2S communication. 52 This parameter can be a value of @ref I2S_Standard */ 53 54 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. 55 This parameter can be a value of @ref I2S_Data_Format */ 56 57 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. 58 This parameter can be a value of @ref I2S_MCLK_Output */ 59 60 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. 61 This parameter can be a value of @ref I2S_Audio_Frequency */ 62 63 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. 64 This parameter can be a value of @ref I2S_Clock_Polarity */ 65 } I2S_InitTypeDef; 66 67 /** 68 * @brief HAL State structures definition 69 */ 70 typedef enum 71 { 72 HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ 73 HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ 74 HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ 75 HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ 76 HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ 77 HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ 78 HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */ 79 } HAL_I2S_StateTypeDef; 80 81 /** 82 * @brief I2S handle Structure definition 83 */ 84 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1) 85 typedef struct __I2S_HandleTypeDef 86 #else 87 typedef struct 88 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 89 { 90 SPI_TypeDef *Instance; /*!< I2S registers base address */ 91 92 I2S_InitTypeDef Init; /*!< I2S communication parameters */ 93 94 uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */ 95 96 __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */ 97 98 __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */ 99 100 uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */ 101 102 __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */ 103 104 __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter 105 (This field is initialized at the 106 same value as transfer size at the 107 beginning of the transfer and 108 decremented when a sample is received 109 NbSamplesReceived = RxBufferSize-RxBufferCount) */ 110 DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */ 111 112 DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */ 113 114 __IO HAL_LockTypeDef Lock; /*!< I2S locking object */ 115 116 __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */ 117 118 __IO uint32_t ErrorCode; /*!< I2S Error code 119 This parameter can be a value of @ref I2S_Error */ 120 121 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 122 void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */ 123 void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */ 124 void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */ 125 void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */ 126 void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */ 127 void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */ 128 void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */ 129 130 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 131 } I2S_HandleTypeDef; 132 133 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 134 /** 135 * @brief HAL I2S Callback ID enumeration definition 136 */ 137 typedef enum 138 { 139 HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */ 140 HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */ 141 HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */ 142 HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */ 143 HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */ 144 HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */ 145 HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */ 146 147 } HAL_I2S_CallbackIDTypeDef; 148 149 /** 150 * @brief HAL I2S Callback pointer definition 151 */ 152 typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */ 153 154 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 155 /** 156 * @} 157 */ 158 159 /* Exported constants --------------------------------------------------------*/ 160 /** @defgroup I2S_Exported_Constants I2S Exported Constants 161 * @{ 162 */ 163 /** @defgroup I2S_Error I2S Error 164 * @{ 165 */ 166 #define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */ 167 #define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ 168 #define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */ 169 #define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */ 170 #define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */ 171 #define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */ 172 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 173 #define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */ 174 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 175 #define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */ 176 /** 177 * @} 178 */ 179 180 /** @defgroup I2S_Mode I2S Mode 181 * @{ 182 */ 183 #define I2S_MODE_SLAVE_TX (0x00000000U) 184 #define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) 185 #define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) 186 #define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)) 187 /** 188 * @} 189 */ 190 191 /** @defgroup I2S_Standard I2S Standard 192 * @{ 193 */ 194 #define I2S_STANDARD_PHILIPS (0x00000000U) 195 #define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) 196 #define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) 197 #define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)) 198 #define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)) 199 /** 200 * @} 201 */ 202 203 /** @defgroup I2S_Data_Format I2S Data Format 204 * @{ 205 */ 206 #define I2S_DATAFORMAT_16B (0x00000000U) 207 #define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) 208 #define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) 209 #define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) 210 /** 211 * @} 212 */ 213 214 /** @defgroup I2S_MCLK_Output I2S MCLK Output 215 * @{ 216 */ 217 #define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE) 218 #define I2S_MCLKOUTPUT_DISABLE (0x00000000U) 219 /** 220 * @} 221 */ 222 223 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency 224 * @{ 225 */ 226 #define I2S_AUDIOFREQ_192K (192000U) 227 #define I2S_AUDIOFREQ_96K (96000U) 228 #define I2S_AUDIOFREQ_48K (48000U) 229 #define I2S_AUDIOFREQ_44K (44100U) 230 #define I2S_AUDIOFREQ_32K (32000U) 231 #define I2S_AUDIOFREQ_22K (22050U) 232 #define I2S_AUDIOFREQ_16K (16000U) 233 #define I2S_AUDIOFREQ_11K (11025U) 234 #define I2S_AUDIOFREQ_8K (8000U) 235 #define I2S_AUDIOFREQ_DEFAULT (2U) 236 /** 237 * @} 238 */ 239 240 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity 241 * @{ 242 */ 243 #define I2S_CPOL_LOW (0x00000000U) 244 #define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL) 245 /** 246 * @} 247 */ 248 249 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition 250 * @{ 251 */ 252 #define I2S_IT_TXE SPI_CR2_TXEIE 253 #define I2S_IT_RXNE SPI_CR2_RXNEIE 254 #define I2S_IT_ERR SPI_CR2_ERRIE 255 /** 256 * @} 257 */ 258 259 /** @defgroup I2S_Flags_Definition I2S Flags Definition 260 * @{ 261 */ 262 #define I2S_FLAG_TXE SPI_SR_TXE 263 #define I2S_FLAG_RXNE SPI_SR_RXNE 264 265 #define I2S_FLAG_UDR SPI_SR_UDR 266 #define I2S_FLAG_OVR SPI_SR_OVR 267 #define I2S_FLAG_FRE SPI_SR_FRE 268 269 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE 270 #define I2S_FLAG_BSY SPI_SR_BSY 271 272 #define I2S_FLAG_MASK (SPI_SR_RXNE\ 273 | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY) 274 /** 275 * @} 276 */ 277 278 /** 279 * @} 280 */ 281 282 /* Exported macros -----------------------------------------------------------*/ 283 /** @defgroup I2S_Exported_macros I2S Exported Macros 284 * @{ 285 */ 286 287 /** @brief Reset I2S handle state 288 * @param __HANDLE__ specifies the I2S Handle. 289 * @retval None 290 */ 291 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 292 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \ 293 (__HANDLE__)->State = HAL_I2S_STATE_RESET; \ 294 (__HANDLE__)->MspInitCallback = NULL; \ 295 (__HANDLE__)->MspDeInitCallback = NULL; \ 296 } while(0) 297 #else 298 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) 299 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 300 301 /** @brief Enable the specified SPI peripheral (in I2S mode). 302 * @param __HANDLE__ specifies the I2S Handle. 303 * @retval None 304 */ 305 #define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) 306 307 /** @brief Disable the specified SPI peripheral (in I2S mode). 308 * @param __HANDLE__ specifies the I2S Handle. 309 * @retval None 310 */ 311 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) 312 313 /** @brief Enable the specified I2S interrupts. 314 * @param __HANDLE__ specifies the I2S Handle. 315 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 316 * This parameter can be one of the following values: 317 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable 318 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable 319 * @arg I2S_IT_ERR: Error interrupt enable 320 * @retval None 321 */ 322 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) 323 324 /** @brief Disable the specified I2S interrupts. 325 * @param __HANDLE__ specifies the I2S Handle. 326 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 327 * This parameter can be one of the following values: 328 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable 329 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable 330 * @arg I2S_IT_ERR: Error interrupt enable 331 * @retval None 332 */ 333 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) 334 335 /** @brief Checks if the specified I2S interrupt source is enabled or disabled. 336 * @param __HANDLE__ specifies the I2S Handle. 337 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. 338 * @param __INTERRUPT__ specifies the I2S interrupt source to check. 339 * This parameter can be one of the following values: 340 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable 341 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable 342 * @arg I2S_IT_ERR: Error interrupt enable 343 * @retval The new state of __IT__ (TRUE or FALSE). 344 */ 345 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ 346 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 347 348 /** @brief Checks whether the specified I2S flag is set or not. 349 * @param __HANDLE__ specifies the I2S Handle. 350 * @param __FLAG__ specifies the flag to check. 351 * This parameter can be one of the following values: 352 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag 353 * @arg I2S_FLAG_TXE: Transmit buffer empty flag 354 * @arg I2S_FLAG_UDR: Underrun flag 355 * @arg I2S_FLAG_OVR: Overrun flag 356 * @arg I2S_FLAG_FRE: Frame error flag 357 * @arg I2S_FLAG_CHSIDE: Channel Side flag 358 * @arg I2S_FLAG_BSY: Busy flag 359 * @retval The new state of __FLAG__ (TRUE or FALSE). 360 */ 361 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 362 363 /** @brief Clears the I2S OVR pending flag. 364 * @param __HANDLE__ specifies the I2S Handle. 365 * @retval None 366 */ 367 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \ 368 __IO uint32_t tmpreg_ovr = 0x00U; \ 369 tmpreg_ovr = (__HANDLE__)->Instance->DR; \ 370 tmpreg_ovr = (__HANDLE__)->Instance->SR; \ 371 UNUSED(tmpreg_ovr); \ 372 }while(0U) 373 /** @brief Clears the I2S UDR pending flag. 374 * @param __HANDLE__ specifies the I2S Handle. 375 * @retval None 376 */ 377 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\ 378 __IO uint32_t tmpreg_udr = 0x00U;\ 379 tmpreg_udr = ((__HANDLE__)->Instance->SR);\ 380 UNUSED(tmpreg_udr); \ 381 }while(0U) 382 /** @brief Flush the I2S DR Register. 383 * @param __HANDLE__ specifies the I2S Handle. 384 * @retval None 385 */ 386 #define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\ 387 __IO uint32_t tmpreg_dr = 0x00U;\ 388 tmpreg_dr = ((__HANDLE__)->Instance->DR);\ 389 UNUSED(tmpreg_dr); \ 390 }while(0U) 391 /** 392 * @} 393 */ 394 395 /* Exported functions --------------------------------------------------------*/ 396 /** @addtogroup I2S_Exported_Functions 397 * @{ 398 */ 399 400 /** @addtogroup I2S_Exported_Functions_Group1 401 * @{ 402 */ 403 /* Initialization/de-initialization functions ********************************/ 404 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); 405 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s); 406 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); 407 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); 408 409 /* Callbacks Register/UnRegister functions ***********************************/ 410 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 411 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, 412 pI2S_CallbackTypeDef pCallback); 413 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID); 414 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 415 /** 416 * @} 417 */ 418 419 /** @addtogroup I2S_Exported_Functions_Group2 420 * @{ 421 */ 422 /* I/O operation functions ***************************************************/ 423 /* Blocking mode: Polling */ 424 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); 425 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); 426 427 /* Non-Blocking mode: Interrupt */ 428 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 429 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 430 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); 431 432 /* Non-Blocking mode: DMA */ 433 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 434 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 435 436 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); 437 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); 438 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); 439 440 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ 441 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); 442 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); 443 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); 444 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); 445 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); 446 /** 447 * @} 448 */ 449 450 /** @addtogroup I2S_Exported_Functions_Group3 451 * @{ 452 */ 453 /* Peripheral Control and State functions ************************************/ 454 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); 455 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); 456 /** 457 * @} 458 */ 459 460 /** 461 * @} 462 */ 463 464 /* Private types -------------------------------------------------------------*/ 465 /* Private variables ---------------------------------------------------------*/ 466 /* Private constants ---------------------------------------------------------*/ 467 /* Private macros ------------------------------------------------------------*/ 468 /** @defgroup I2S_Private_Macros I2S Private Macros 469 * @{ 470 */ 471 472 /** @brief Check whether the specified SPI flag is set or not. 473 * @param __SR__ copy of I2S SR register. 474 * @param __FLAG__ specifies the flag to check. 475 * This parameter can be one of the following values: 476 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag 477 * @arg I2S_FLAG_TXE: Transmit buffer empty flag 478 * @arg I2S_FLAG_UDR: Underrun error flag 479 * @arg I2S_FLAG_OVR: Overrun flag 480 * @arg I2S_FLAG_CHSIDE: Channel side flag 481 * @arg I2S_FLAG_BSY: Busy flag 482 * @retval SET or RESET. 483 */ 484 #define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\ 485 & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) 486 487 /** @brief Check whether the specified SPI Interrupt is set or not. 488 * @param __CR2__ copy of I2S CR2 register. 489 * @param __INTERRUPT__ specifies the SPI interrupt source to check. 490 * This parameter can be one of the following values: 491 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable 492 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable 493 * @arg I2S_IT_ERR: Error interrupt enable 494 * @retval SET or RESET. 495 */ 496 #define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\ 497 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 498 499 /** @brief Checks if I2S Mode parameter is in allowed range. 500 * @param __MODE__ specifies the I2S Mode. 501 * This parameter can be a value of @ref I2S_Mode 502 * @retval None 503 */ 504 #define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ 505 ((__MODE__) == I2S_MODE_SLAVE_RX) || \ 506 ((__MODE__) == I2S_MODE_MASTER_TX) || \ 507 ((__MODE__) == I2S_MODE_MASTER_RX)) 508 509 #define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ 510 ((__STANDARD__) == I2S_STANDARD_MSB) || \ 511 ((__STANDARD__) == I2S_STANDARD_LSB) || \ 512 ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ 513 ((__STANDARD__) == I2S_STANDARD_PCM_LONG)) 514 515 #define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \ 516 ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \ 517 ((__FORMAT__) == I2S_DATAFORMAT_24B) || \ 518 ((__FORMAT__) == I2S_DATAFORMAT_32B)) 519 520 #define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \ 521 ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE)) 522 523 #define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \ 524 ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \ 525 ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) 526 527 /** @brief Checks if I2S Serial clock steady state parameter is in allowed range. 528 * @param __CPOL__ specifies the I2S serial clock steady state. 529 * This parameter can be a value of @ref I2S_Clock_Polarity 530 * @retval None 531 */ 532 #define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ 533 ((__CPOL__) == I2S_CPOL_HIGH)) 534 535 /** 536 * @} 537 */ 538 539 /** 540 * @} 541 */ 542 543 /** 544 * @} 545 */ 546 547 #ifdef __cplusplus 548 } 549 #endif 550 551 #endif /* STM32WLxx_HAL_I2S_H */ 552 553
