1 /** 2 ****************************************************************************** 3 * @file stm32wlxx_hal_flash.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2020 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WLxx_HAL_FLASH_H 21 #define STM32WLxx_HAL_FLASH_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wlxx_hal_def.h" 29 30 /** @addtogroup STM32WLxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FLASH 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup FLASH_Exported_Types FLASH Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief FLASH Erase structure definition 45 */ 46 typedef struct 47 { 48 uint32_t TypeErase; /*!< Mass erase or page erase. 49 This parameter can be a value of @ref FLASH_TYPE_ERASE */ 50 uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled 51 This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */ 52 uint32_t NbPages; /*!< Number of pages to be erased. 53 This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)*/ 54 } FLASH_EraseInitTypeDef; 55 56 /** 57 * @brief FLASH Option Bytes Program structure definition 58 */ 59 typedef struct 60 { 61 uint32_t OptionType; /*!< Option byte to be configured. 62 This parameter can be a combination of the values of @ref FLASH_OB_TYPE */ 63 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). 64 Only one WRP area could be programmed at the same time. 65 This parameter can be value of @ref FLASH_OB_WRP_AREA */ 66 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). 67 This parameter must be a value between 0 and (max number of pages - 1) */ 68 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). 69 This parameter must be a value between WRPStartOffset and (max number of pages - 1) */ 70 uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP). 71 This parameter can be a value of @ref FLASH_OB_READ_PROTECTION */ 72 uint32_t UserType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 73 This parameter can be a combination of @ref FLASH_OB_USER_TYPE */ 74 #if defined(DUAL_CORE) /* Comment duplicated for Document generation */ 75 uint32_t UserConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). 76 This parameter can be a combination of the values of 77 @ref FLASH_OB_USER_BOR_LEVEL 78 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, 79 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 80 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 81 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nBOOT1, 82 @ref FLASH_OB_USER_SRAM2_PE, @ref FLASH_OB_USER_SRAM_RST, 83 @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, 84 @ref FLASH_OB_USER_BOOT_LOCK, @ref FLASH_OB_USER_C2BOOT_LOCK */ 85 #else 86 uint32_t UserConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). 87 This parameter can be a combination of the values of 88 @ref FLASH_OB_USER_BOR_LEVEL 89 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, 90 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 91 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 92 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nBOOT1, 93 @ref FLASH_OB_USER_SRAM2_PE, @ref FLASH_OB_USER_SRAM_RST, 94 @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, 95 @ref FLASH_OB_USER_BOOT_LOCK */ 96 #endif 97 uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). 98 This parameter must be a combination of values of @ref FLASH_OB_PCROP_ZONE 99 and @ref FLASH_OB_PCROP_RDP */ 100 uint32_t PCROP1AStartAddr; /*!< PCROP Zone A Start address (used for OPTIONBYTE_PCROP). It represents first address of start block 101 to protect. Make sure this parameter is multiple of PCROP granularity */ 102 uint32_t PCROP1AEndAddr; /*!< PCROP Zone A End address (used for OPTIONBYTE_PCROP). It represents first address of end block 103 to protect. Make sure this parameter is multiple of PCROP granularity */ 104 uint32_t PCROP1BStartAddr; /*!< PCROP Zone B Start address (used for OPTIONBYTE_PCROP). It represents first address of start block 105 to protect. Make sure this parameter is multiple of PCROP granularity */ 106 uint32_t PCROP1BEndAddr; /*!< PCROP Zone B End address (used for OPTIONBYTE_PCROP). It represents first address of end block 107 to protect. Make sure this parameter is multiple of PCROP granularity */ 108 #if defined(DUAL_CORE) 109 uint32_t SecureFlashStartAddr; /*!< Secure Flash start address (used for OPTIONBYTE_SECURE_MODE). 110 This parameter must be a value between begin and end of Flash bank 111 => Contains the start address of the first 2kB page of the secure Flash area */ 112 uint32_t SecureSRAM2StartAddr; /*!< Secure Backup SRAM2 start address (used for OPTIONBYTE_SECURE_MODE). 113 This parameter must be aligned on 1kB boundary */ 114 uint32_t SecureSRAM1StartAddr; /*!< Secure non-Backup SRAM1 start address (used for OPTIONBYTE_SECURE_MODE) 115 This parameter must be aligned on 1kB boundary */ 116 uint32_t HideProtectionStartAddr;/*!< Hide Protection area start address (used for OPTIONBYTE_SECURE_MODE) 117 This parameter must be aligned on 2kB boundary */ 118 uint32_t SecureMode; /*!< Secure mode activated or deactivated. 119 This parameter can be a value of @ref FLASH_OB_SECURITY_MODE */ 120 uint32_t SUBGHZSPISecureAccess; /*!< Sub-GHz radio SPI security access enabled or disabled (used for OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS). 121 This parameter can be a value of @ref FLASH_OB_SUBGHZSPI_SECURE_ACCESS */ 122 uint32_t C2DebugAccessMode; /*!< CPU2 debug access enabled or disabled (used for OPTIONBYTE_C2_DEBUG_ACCESS). 123 This parameter can be a value of @ref FLASH_OB_C2_DEBUG_ACCESS */ 124 uint32_t C2BootRegion; /*!< CPU2 Secure Boot memory region(used for OPTIONBYTE_C2_BOOT_VECT). 125 This parameter can be a value of @ref FLASH_OB_C2_BOOT_REGION */ 126 uint32_t C2SecureBootVectAddr; /*!< CPU2 Secure Boot reset vector (used for OPTIONBYTE_C2_BOOT_VECT). 127 This parameter contains the CPU2 boot reset start address within 128 the selected memory region. Make sure this parameter is word aligned. */ 129 uint32_t IPCCdataBufAddr; /*!< IPCC mailbox data buffer base address (used for OPTIONBYTE_IPCC_BUF_ADDR). 130 This parameter contains the IPCC mailbox data buffer start address area 131 in SRAM1 or SRAM2. Make sure this parameter is double-word aligned. */ 132 #endif /* DUAL_CORE */ 133 } FLASH_OBProgramInitTypeDef; 134 135 /** 136 * @brief FLASH handle Structure definition 137 */ 138 typedef struct 139 { 140 HAL_LockTypeDef Lock; /* FLASH locking object */ 141 uint32_t ErrorCode; /* FLASH error code */ 142 uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ 143 uint32_t Address; /* Internal variable to save address selected for program in IT context */ 144 uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ 145 uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ 146 } FLASH_ProcessTypeDef; 147 148 /** 149 * @} 150 */ 151 152 /* Exported constants --------------------------------------------------------*/ 153 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 154 * @{ 155 */ 156 157 /** @defgroup FLASH_KEYS FLASH Keys 158 * @{ 159 */ 160 #define FLASH_KEY1 0x45670123U /*!< Flash key1 */ 161 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 162 to unlock the FLASH registers access */ 163 164 #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ 165 #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 166 to allow option bytes operations */ 167 /** 168 * @} 169 */ 170 171 /** @defgroup FLASH_LATENCY FLASH Latency 172 * @{ 173 */ 174 #define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero wait state */ 175 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */ 176 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ 177 /** 178 * @} 179 */ 180 181 /** @defgroup FLASH_FLAGS FLASH Flags Definition 182 * @{ 183 */ 184 #ifdef CORE_CM0PLUS 185 #define FLASH_FLAG_EOP FLASH_C2SR_EOP /*!< CPU2 FLASH End of operation flag */ 186 #define FLASH_FLAG_OPERR FLASH_C2SR_OPERR /*!< CPU2 FLASH Operation error flag */ 187 #define FLASH_FLAG_PROGERR FLASH_C2SR_PROGERR /*!< CPU2 FLASH Programming error flag */ 188 #define FLASH_FLAG_WRPERR FLASH_C2SR_WRPERR /*!< CPU2 FLASH Write protection error flag */ 189 #define FLASH_FLAG_PGAERR FLASH_C2SR_PGAERR /*!< CPU2 FLASH Programming alignment error flag */ 190 #define FLASH_FLAG_SIZERR FLASH_C2SR_SIZERR /*!< CPU2 FLASH Size error flag */ 191 #define FLASH_FLAG_PGSERR FLASH_C2SR_PGSERR /*!< CPU2 FLASH Programming sequence error flag */ 192 #define FLASH_FLAG_MISERR FLASH_C2SR_MISERR /*!< CPU2 FLASH Fast programming data miss error flag */ 193 #define FLASH_FLAG_FASTERR FLASH_C2SR_FASTERR /*!< CPU2 FLASH Fast programming error flag */ 194 #define FLASH_FLAG_OPTNV FLASH_C2SR_OPTNV /*!< CPU2 FLASH User Option OPTVAL indication */ 195 #define FLASH_FLAG_RDERR FLASH_C2SR_RDERR /*!< CPU2 FLASH PCROP read error flag */ 196 #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ 197 #define FLASH_FLAG_BSY FLASH_C2SR_BSY /*!< CPU2 FLASH Busy flag */ 198 #define FLASH_FLAG_CFGBSY FLASH_C2SR_CFGBSY /*!< CPU2 FLASH Programming/erase configuration busy */ 199 #define FLASH_FLAG_PESD FLASH_C2SR_PESD /*!< CPU2 FLASH Programming/erase operation suspended */ 200 #else 201 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */ 202 #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */ 203 #define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */ 204 #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */ 205 #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */ 206 #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ 207 #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */ 208 #define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */ 209 #define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */ 210 #define FLASH_FLAG_OPTNV FLASH_SR_OPTNV /*!< FLASH User Option OPTVAL indication */ 211 #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */ 212 #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ 213 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ 214 #define FLASH_FLAG_CFGBSY FLASH_SR_CFGBSY /*!< FLASH Programming/erase configuration busy */ 215 #define FLASH_FLAG_PESD FLASH_SR_PESD /*!< FLASH Programming/erase operation suspended */ 216 #endif 217 218 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 219 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 220 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 221 FLASH_FLAG_OPTVERR) /*!< All SR error flags */ 222 223 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ 224 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ 225 226 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD) 227 228 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) 229 230 /** @defgroup FLASH_INTERRUPT_DEFINITION FLASH Interrupts Definition 231 * @brief FLASH Interrupt definition 232 * @{ 233 */ 234 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ 235 #define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */ 236 #define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source */ 237 #define FLASH_IT_ECCC (FLASH_ECCR_ECCCIE >> FLASH_ECCR_ECCCIE_Pos) /*!< ECC Correction Interrupt source */ 238 /** 239 * @} 240 */ 241 242 /** @defgroup FLASH_ERROR FLASH Error 243 * @{ 244 */ 245 #define HAL_FLASH_ERROR_NONE 0x00000000U 246 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR 247 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR 248 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR 249 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR 250 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR 251 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR 252 #define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR 253 #define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR 254 #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR 255 #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR 256 /** 257 * @} 258 */ 259 260 /** @defgroup FLASH_TYPE_ERASE FLASH Erase Type 261 * @{ 262 */ 263 #define FLASH_TYPEERASE_PAGES FLASH_CR_PER /*!< Pages erase only*/ 264 #define FLASH_TYPEERASE_MASSERASE FLASH_CR_MER /*!< Flash mass erase activation*/ 265 /** 266 * @} 267 */ 268 269 /** @defgroup FLASH_TYPE_PROGRAM FLASH Program Type 270 * @{ 271 */ 272 #define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG /*!< Program a double-word (64-bit) at a specified address.*/ 273 #define FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG /*!< Fast program a 32 double-word (64-bit) row at a specified address. 274 And another 32 double-word (64-bit) row will be programmed */ 275 /** 276 * @} 277 */ 278 279 /** @defgroup FLASH_OB_TYPE FLASH Option Bytes Type 280 * @{ 281 */ 282 #define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ 283 #define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ 284 #define OPTIONBYTE_USER 0x00000004U /*!< User option byte configuration */ 285 #define OPTIONBYTE_PCROP 0x00000008U /*!< PCROP option byte configuration */ 286 #if defined(DUAL_CORE) 287 #define OPTIONBYTE_IPCC_BUF_ADDR 0x00000010U /*!< IPCC mailbox buffer address configuration */ 288 #define OPTIONBYTE_C2_BOOT_VECT 0x00000100U /*!< CPU2 Secure Boot reset vector */ 289 #define OPTIONBYTE_SECURE_MODE 0x00000200U /*!< Secure mode on activated or not */ 290 #define OPTIONBYTE_C2_DEBUG_ACCESS 0x00000400U /*!< CPU2 debug access enabled or disabled */ 291 #define OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS 0x00000800U /*!< Sub-GHz radio SPI security access enabled or disabled */ 292 293 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ 294 OPTIONBYTE_PCROP | OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | \ 295 OPTIONBYTE_SECURE_MODE | OPTIONBYTE_C2_DEBUG_ACCESS | OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS) /*!< All option byte configuration */ 296 #else 297 298 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ 299 OPTIONBYTE_PCROP) /*!< All option byte configuration */ 300 #endif /* DUAL_CORE */ 301 302 /** 303 * @} 304 */ 305 306 /** @defgroup FLASH_OB_WRP_AREA FLASH WRP Area 307 * @{ 308 */ 309 #define OB_WRPAREA_BANK1_AREAA 0x00000000U /*!< Flash Area A */ 310 #define OB_WRPAREA_BANK1_AREAB 0x00000001U /*!< Flash Area B */ 311 /** 312 * @} 313 */ 314 315 /** @defgroup FLASH_OB_READ_PROTECTION FLASH Option Bytes Read Protection 316 * @{ 317 */ 318 #define OB_RDP_LEVEL_0 0x000000AAU 319 #define OB_RDP_LEVEL_1 0x000000BBU 320 #define OB_RDP_LEVEL_2 0x000000CCU /*!< Warning: When enabling read protection level 2 321 it's no more possible to go back to level 1 or 0 */ 322 /** 323 * @} 324 */ 325 326 /** @defgroup FLASH_OB_USER_TYPE FLASH Option Bytes User Type 327 * @{ 328 */ 329 #define OB_USER_BOR_LEV FLASH_OPTR_BOR_LEV /*!< BOR reset Level */ 330 #define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */ 331 #define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */ 332 #define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering the shutdown mode */ 333 #define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */ 334 #define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */ 335 #define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */ 336 #define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Window watchdog selection */ 337 #define OB_USER_nBOOT1 FLASH_OPTR_nBOOT1 /*!< Boot configuration */ 338 #define OB_USER_SRAM2_PE FLASH_OPTR_SRAM2_PE /*!< SRAM2 parity check enable */ 339 #define OB_USER_SRAM_RST FLASH_OPTR_SRAM_RST /*!< SRAM1 and SRAM2 erase when system reset */ 340 #define OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0 /*!< Software BOOT0 */ 341 #define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */ 342 #define OB_USER_BOOT_LOCK FLASH_OPTR_BOOT_LOCK /*!< CPU1 Boot Lock enable option bit */ 343 #if defined(DUAL_CORE) 344 #define OB_USER_C2BOOT_LOCK FLASH_OPTR_C2BOOT_LOCK /*!< CPU2 Boot Lock enable option bit */ 345 #endif 346 347 #if defined(DUAL_CORE) 348 #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ 349 OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ 350 OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \ 351 OB_USER_SRAM2_PE | OB_USER_SRAM_RST | OB_USER_nSWBOOT0 | \ 352 OB_USER_nBOOT0 | OB_USER_BOOT_LOCK | OB_USER_C2BOOT_LOCK) /*!< all option bits */ 353 #else 354 #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ 355 OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ 356 OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \ 357 OB_USER_SRAM2_PE | OB_USER_SRAM_RST | OB_USER_nSWBOOT0 | \ 358 OB_USER_nBOOT0 | OB_USER_BOOT_LOCK) /*!< all option bits */ 359 #endif 360 361 /** 362 * @} 363 */ 364 365 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level 366 * @{ 367 */ 368 #define OB_BOR_LEVEL_0 0x00000000U /*!< Reset level threshold is around 1.7V */ 369 #define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold is around 2.0V */ 370 #define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold is around 2.2V */ 371 #define OB_BOR_LEVEL_3 (FLASH_OPTR_BOR_LEV_0 | FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.5V */ 372 #define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold is around 2.8V */ 373 /** 374 * @} 375 */ 376 377 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 378 * @{ 379 */ 380 #define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */ 381 #define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */ 382 /** 383 * @} 384 */ 385 386 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby 387 * @{ 388 */ 389 #define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */ 390 #define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */ 391 /** 392 * @} 393 */ 394 395 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown 396 * @{ 397 */ 398 #define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */ 399 #define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */ 400 /** 401 * @} 402 */ 403 404 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 405 * @{ 406 */ 407 #define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ 408 #define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */ 409 /** 410 * @} 411 */ 412 413 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop 414 * @{ 415 */ 416 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */ 417 #define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */ 418 /** 419 * @} 420 */ 421 422 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby 423 * @{ 424 */ 425 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */ 426 #define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */ 427 /** 428 * @} 429 */ 430 431 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 432 * @{ 433 */ 434 #define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ 435 #define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */ 436 /** 437 * @} 438 */ 439 440 /** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes SRAM2 parity check 441 * @{ 442 */ 443 #define OB_SRAM2_PARITY_ENABLE 0x00000000U /*!< SRAM2 parity check enable */ 444 #define OB_SRAM2_PARITY_DISABLE FLASH_OPTR_SRAM2_PE /*!< SRAM2 parity check disable */ 445 /** 446 * @} 447 */ 448 449 /** @defgroup FLASH_OB_USER_SRAM_RST FLASH Option Bytes SRAM1 and SRAM2 erase when system reset 450 * @{ 451 */ 452 #define OB_SRAM_RST_ERASE 0x00000000U /*!< SRAM2 and SRAM1 erased when a system reset */ 453 #define OB_SRAM_RST_NOT_ERASE FLASH_OPTR_SRAM_RST /*!< SRAM2 and SRAM1 is not erased when a system reset */ 454 /** 455 * @} 456 */ 457 458 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type 459 * @{ 460 */ 461 #define OB_BOOT1_RESET 0x00000000U /*!< nBOOT1 = 0 */ 462 #define OB_BOOT1_SET FLASH_OPTR_nBOOT1 /*!< nBOOT1 = 1 */ 463 /** 464 * @} 465 */ 466 467 /** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 468 * @{ 469 */ 470 #define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */ 471 #define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from PH3/BOOT0 pin */ 472 /** 473 * @} 474 */ 475 476 /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit 477 * @{ 478 */ 479 #define OB_BOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */ 480 #define OB_BOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */ 481 /** 482 * @} 483 */ 484 485 /** @defgroup FLASH_OB_USER_BOOT_LOCK FLASH Option Bytes CPU1 Boot Lock option bit 486 * @{ 487 */ 488 #define OB_BOOT_LOCK_DISABLE 0x00000000U /*!< BOOT_LOCK = 0 */ 489 #define OB_BOOT_LOCK_ENABLE FLASH_OPTR_BOOT_LOCK /*!< BOOT_LOCK = 1 */ 490 /** 491 * @} 492 */ 493 494 #if defined(DUAL_CORE) 495 /** @defgroup FLASH_OB_USER_C2BOOT_LOCK FLASH Option Bytes CPU2 Boot Lock option bit 496 * @{ 497 */ 498 #define OB_C2BOOT_LOCK_DISABLE 0x00000000U /*!< C2BOOT_LOCK = 0 */ 499 #define OB_C2BOOT_LOCK_ENABLE FLASH_OPTR_C2BOOT_LOCK /*!< C2BOOT_LOCK = 1 */ 500 /** 501 * @} 502 */ 503 #endif /* DUAL_CORE */ 504 505 /** @defgroup FLASH_OB_PCROP_ZONE FLASH PCROP ZONE 506 * @{ 507 */ 508 #define OB_PCROP_ZONE_A 0x00000001U /*!< PCROP Zone A */ 509 #define OB_PCROP_ZONE_B 0x00000002U /*!< PCROP Zone B */ 510 /** 511 * @} 512 */ 513 514 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type 515 * @{ 516 */ 517 #define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level 518 is decreased from Level 1 to Level 0 */ 519 #define OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP /*!< PCROP area is erased when the RDP level is 520 decreased from Level 1 to Level 0 (full mass erase) */ 521 /** 522 * @} 523 */ 524 525 #if defined(DUAL_CORE) 526 /** @defgroup FLASH_OB_SECURITY_MODE Option Bytes FLASH Secure mode 527 * @{ 528 */ 529 #define OB_SECURE_SYSTEM_AND_FLASH_ENABLE 0x00000001U /*!< Flash and System secure area enabled */ 530 #define OB_SECURE_HIDE_PROTECTION_ENABLE 0x00000002U /*!< Hide Protection area enabled */ 531 #define OB_SECURE_SRAM1_ENABLE 0x00000004U /*!< SRAM1 area enabled */ 532 #define OB_SECURE_SRAM2_ENABLE 0x00000008U /*!< SRAM2 area enabled */ 533 #define OB_SECURE_SYSTEM_AND_FLASH_DISABLE 0x00000010U /*!< Flash and System secure area disabled */ 534 #define OB_SECURE_HIDE_PROTECTION_DISABLE 0x00000020U /*!< Hide Protection area disabled */ 535 #define OB_SECURE_SRAM1_DISABLE 0x00000040U /*!< SRAM1 area disabled */ 536 #define OB_SECURE_SRAM2_DISABLE 0x00000080U /*!< SRAM2 area disabled */ 537 #define OB_SECURE_SYSTEM_AND_ALL_AREAS_ENABLE (OB_SECURE_SYSTEM_AND_FLASH_ENABLE | OB_SECURE_HIDE_PROTECTION_ENABLE | \ 538 OB_SECURE_SRAM1_ENABLE | OB_SECURE_SRAM2_ENABLE) /*!< All System in Secure mode : Security enabled on all areas */ 539 #define OB_SECURE_SYSTEM_AND_ALL_AREAS_DISABLE (OB_SECURE_SYSTEM_AND_FLASH_DISABLE | OB_SECURE_HIDE_PROTECTION_DISABLE | \ 540 OB_SECURE_SRAM1_DISABLE | OB_SECURE_SRAM2_DISABLE) /*!< Unsecure mode: Security disabled */ 541 /** 542 * @} 543 */ 544 545 /** @defgroup FLASH_OB_SUBGHZSPI_SECURE_ACCESS Option Bytes Sub-GHz radio SPI Secure Access 546 * @{ 547 */ 548 #define OB_SUBGHZSPI_SECURE_ACCESS_DISABLE FLASH_SFR_SUBGHZSPISD /*!< Sub-GHz radio SPI Secure access disabled */ 549 #define OB_SUBGHZSPI_SECURE_ACCESS_ENABLE 0x00000000U /*!< Sub-GHz radio SPI Secure access enabled */ 550 /** 551 * @} 552 */ 553 554 /** @defgroup FLASH_OB_C2_DEBUG_ACCESS Option Bytes CPU2 Debug Access 555 * @{ 556 */ 557 #define OB_C2_DEBUG_ACCESS_DISABLE FLASH_SFR_DDS /*!< CPU2 debug access disabled */ 558 #define OB_C2_DEBUG_ACCESS_ENABLE 0x00000000U /*!< CPU2 debug access enabled (when also enabled by FLASH_ACR2_C2SWDBGEN) */ 559 /** 560 * @} 561 */ 562 563 /** @defgroup FLASH_OB_C2_BOOT_REGION CPU2 Option Bytes Reset Boot Vector 564 * @{ 565 */ 566 #define OB_C2_BOOT_FROM_SRAM 0x00000000U /*!< CPU2 boot from SRAM1 or SRAM2 */ 567 #define OB_C2_BOOT_FROM_FLASH FLASH_SRRVR_C2OPT /*!< CPU2 boot from Flash */ 568 /** 569 * @} 570 */ 571 #endif /* DUAL_CORE */ 572 /** 573 * @} 574 */ 575 576 /** 577 * @} 578 */ 579 580 /* Exported macros -----------------------------------------------------------*/ 581 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros 582 * @brief macros to control FLASH features 583 * @{ 584 */ 585 586 /** 587 * @brief Set the FLASH Latency. 588 * @param __LATENCY__ FLASH Latency 589 * This parameter can be one of the following values : 590 * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state 591 * @arg @ref FLASH_LATENCY_1 FLASH One wait state 592 * @arg @ref FLASH_LATENCY_2 FLASH Two wait states 593 * @retval None 594 */ 595 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) 596 597 /** 598 * @brief Get the FLASH Latency. 599 * @retval FLASH Latency 600 * Returned value can be one of the following values : 601 * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state 602 * @arg @ref FLASH_LATENCY_1 FLASH One wait state 603 * @arg @ref FLASH_LATENCY_2 FLASH Two wait states 604 */ 605 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) 606 607 /** 608 * @brief Enable the FLASH prefetch buffer. 609 * @retval None 610 */ 611 #ifdef CORE_CM0PLUS 612 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->C2ACR, FLASH_C2ACR_PRFTEN) 613 #else 614 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 615 #endif 616 617 /** 618 * @brief Disable the FLASH prefetch buffer. 619 * @retval None 620 */ 621 #ifdef CORE_CM0PLUS 622 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_PRFTEN) 623 #else 624 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 625 #endif 626 627 /** 628 * @brief Enable the FLASH instruction cache. 629 * @retval none 630 */ 631 #ifdef CORE_CM0PLUS 632 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->C2ACR, FLASH_C2ACR_ICEN) 633 #else 634 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) 635 #endif 636 637 /** 638 * @brief Disable the FLASH instruction cache. 639 * @retval none 640 */ 641 #ifdef CORE_CM0PLUS 642 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_ICEN) 643 #else 644 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) 645 #endif 646 647 /** 648 * @brief Enable the FLASH data cache. 649 * @retval none 650 */ 651 #ifdef CORE_CM0PLUS 652 #else 653 #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) 654 #endif 655 656 /** 657 * @brief Disable the FLASH data cache. 658 * @retval none 659 */ 660 #ifdef CORE_CM0PLUS 661 #else 662 #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) 663 #endif 664 665 /** 666 * @brief Reset the FLASH instruction Cache. 667 * @note This function must be used only when the Instruction Cache is disabled. 668 * @retval None 669 */ 670 #ifdef CORE_CM0PLUS 671 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->C2ACR, FLASH_C2ACR_ICRST); \ 672 CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_ICRST); \ 673 } while (0) 674 #else 675 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 676 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 677 } while (0) 678 #endif 679 680 /** 681 * @brief Reset the FLASH data Cache. 682 * @note This function must be used only when the data Cache is disabled. 683 * @retval None 684 */ 685 #ifdef CORE_CM0PLUS 686 #else 687 #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 688 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 689 } while (0) 690 #endif 691 692 /** 693 * @} 694 */ 695 696 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros 697 * @brief macros to handle FLASH interrupts 698 * @{ 699 */ 700 701 /** 702 * @brief Enable the specified FLASH interrupt. 703 * @param __INTERRUPT__ FLASH interrupt 704 * This parameter can be any combination of the following values: 705 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 706 * @arg @ref FLASH_IT_OPERR Error Interrupt 707 * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt 708 * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt 709 * @retval none 710 */ 711 #ifdef CORE_CM0PLUS 712 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\ 713 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->C2CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 714 } while(0) 715 #else 716 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\ 717 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 718 } while(0) 719 #endif 720 721 /** 722 * @brief Disable the specified FLASH interrupt. 723 * @param __INTERRUPT__ FLASH interrupt 724 * This parameter can be any combination of the following values: 725 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 726 * @arg @ref FLASH_IT_OPERR Error Interrupt 727 * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt 728 * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt 729 * @retval none 730 */ 731 #ifdef CORE_CM0PLUS 732 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\ 733 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->C2CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 734 } while(0) 735 #else 736 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\ 737 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 738 } while(0) 739 #endif 740 741 /** 742 * @brief Check whether the specified FLASH flag is set or not. 743 * @param __FLAG__ specifies the FLASH flag to check. 744 * This parameter can be one of the following values: 745 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 746 * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag 747 * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag 748 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag 749 * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag 750 * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag 751 * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag 752 * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag 753 * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag 754 * @arg @ref FLASH_FLAG_OPTNV FLASH User Option OPTVAL indication 755 * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag 756 * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag 757 * @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag 758 * @arg @ref FLASH_FLAG_CFGBSY Programming/erase configuration busy 759 * @arg @ref FLASH_FLAG_PESD FLASH Programming/erase operation suspended 760 * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected 761 * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected 762 * @retval The new state of FLASH_FLAG (SET or RESET). 763 */ 764 #ifdef CORE_CM0PLUS 765 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) ? \ 766 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 767 ((((__FLAG__) & FLASH_FLAG_OPTVERR) != 0U) ? \ 768 (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)) : \ 769 (READ_BIT(FLASH->C2SR, (__FLAG__)) == (__FLAG__)))) 770 #else 771 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) ? \ 772 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 773 (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) 774 #endif 775 /** 776 * @brief Clear the FLASH's pending flags. 777 * @param __FLAG__ specifies the FLASH flags to clear. 778 * This parameter can be any combination of the following values: 779 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 780 * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag 781 * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag 782 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag 783 * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag 784 * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag 785 * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag 786 * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag 787 * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag 788 * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag 789 * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag 790 * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected 791 * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected 792 * @arg @ref FLASH_FLAG_SR_ERRORS FLASH All SR errors flags 793 * @arg @ref FLASH_FLAG_ECCR_ERRORS FLASH All ECCR errors flags 794 * @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags 795 * @retval None 796 */ 797 #ifdef CORE_CM0PLUS 798 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS))); }\ 799 if(((__FLAG__) & FLASH_FLAG_OPTVERR) != 0U) { SET_BIT(FLASH->SR, FLASH_FLAG_OPTVERR); }\ 800 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->C2SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ 801 } while(0) 802 #else 803 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS))); }\ 804 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ 805 } while(0) 806 #endif 807 /** 808 * @} 809 */ 810 811 /* Include FLASH HAL Extended module */ 812 #include "stm32wlxx_hal_flash_ex.h" 813 /* Exported variables --------------------------------------------------------*/ 814 /** @defgroup FLASH_Exported_Variables FLASH Exported Variables 815 * @{ 816 */ 817 extern FLASH_ProcessTypeDef pFlash; 818 /** 819 * @} 820 */ 821 822 /* Exported functions --------------------------------------------------------*/ 823 /** @addtogroup FLASH_Exported_Functions 824 * @{ 825 */ 826 827 /* Program operation functions ***********************************************/ 828 /** @addtogroup FLASH_Exported_Functions_Group1 829 * @{ 830 */ 831 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 832 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 833 /* FLASH IRQ handler method */ 834 void HAL_FLASH_IRQHandler(void); 835 /* Callbacks in non blocking modes */ 836 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 837 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 838 /** 839 * @} 840 */ 841 842 /* Peripheral Control functions **********************************************/ 843 /** @addtogroup FLASH_Exported_Functions_Group2 844 * @{ 845 */ 846 HAL_StatusTypeDef HAL_FLASH_Unlock(void); 847 HAL_StatusTypeDef HAL_FLASH_Lock(void); 848 /* Option bytes control */ 849 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 850 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 851 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 852 /** 853 * @} 854 */ 855 856 /* Peripheral State functions ************************************************/ 857 /** @addtogroup FLASH_Exported_Functions_Group3 858 * @{ 859 */ 860 uint32_t HAL_FLASH_GetError(void); 861 /** 862 * @} 863 */ 864 865 /** 866 * @} 867 */ 868 869 /* Private types --------------------------------------------------------*/ 870 /** @defgroup FLASH_Private_types FLASH Private Types 871 * @{ 872 */ 873 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 874 /** 875 * @} 876 */ 877 878 /* Private constants --------------------------------------------------------*/ 879 /** @defgroup FLASH_Private_Constants FLASH Private Constants 880 * @{ 881 */ 882 #define FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE - 1U) 883 884 #define FLASH_BANK_SIZE FLASH_SIZE /*!< FLASH Bank Size */ 885 #define FLASH_PAGE_SIZE 0x00000800U /*!< FLASH Page Size, 2 KBytes */ 886 #define FLASH_PAGE_NB 128U 887 #define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */ 888 889 #define FLASH_PCROP_GRANULARITY_OFFSET 10U /*!< FLASH Code Readout Protection granularity offset */ 890 #define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 1 KBytes */ 891 892 #define FLASH_TYPENONE 0x00000000U /*!< No Programmation Procedure On Going */ 893 894 /** @defgroup SRAM_MEMORY_SIZE SRAM memory size 895 * @{ 896 */ 897 #define SRAM_SECURE_PAGE_GRANULARITY_OFFSET 10U /*!< Secure SRAM1 and SRAM2 Protection granularity offset */ 898 #define SRAM_SECURE_PAGE_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< Secure SRAM1 and SRAM2 Protection granularity, 1KBytes */ 899 /** 900 * @} 901 */ 902 903 /** 904 * @} 905 */ 906 907 /* Private macros ------------------------------------------------------------*/ 908 /** @defgroup FLASH_Private_Macros FLASH Private Macros 909 * @{ 910 */ 911 #define IS_FLASH_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) 912 913 #define IS_FLASH_FAST_PROGRAM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 256UL)) && (((__VALUE__) % 256UL) == 0UL)) 914 915 #define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) 916 917 #define IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__) (((__VALUE__) >= OTP_AREA_BASE) && ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) 918 919 #define IS_FLASH_PROGRAM_ADDRESS(__VALUE__) (IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) || IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__)) 920 921 #define IS_FLASH_PAGE(__VALUE__) ((__VALUE__) < FLASH_PAGE_NB) 922 923 #define IS_ADDR_ALIGNED_64BITS(__VALUE__) (((__VALUE__) & 0x7U) == (0x00UL)) 924 925 #define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \ 926 ((__VALUE__) == FLASH_TYPEERASE_MASSERASE)) 927 928 #define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ 929 ((__VALUE__) == FLASH_TYPEPROGRAM_FAST)) 930 931 #if defined(DUAL_CORE) 932 #define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~0x7FFU) == (__VALUE__))) 933 #define IS_OB_HDPSA_START_ADDR(__VALUE__) IS_OB_SFSA_START_ADDR(__VALUE__) 934 #define IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2_BASE) && ((__VALUE__) <= (SRAM2_BASE + SRAM2_SIZE)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) 935 #define IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM1_BASE) && ((__VALUE__) <= (SRAM1_BASE + SRAM1_SIZE)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) 936 937 #define IS_OB_SECURE_MODE(__VALUE__) ( (((__VALUE__) & (OB_SECURE_SYSTEM_AND_ALL_AREAS_ENABLE | OB_SECURE_SYSTEM_AND_ALL_AREAS_DISABLE)) != 0U) && \ 938 (((__VALUE__) & ~(OB_SECURE_SYSTEM_AND_ALL_AREAS_ENABLE | OB_SECURE_SYSTEM_AND_ALL_AREAS_DISABLE)) == 0U) && \ 939 (((__VALUE__) & (OB_SECURE_SYSTEM_AND_FLASH_ENABLE | OB_SECURE_SYSTEM_AND_FLASH_DISABLE)) != (OB_SECURE_SYSTEM_AND_FLASH_ENABLE | OB_SECURE_SYSTEM_AND_FLASH_DISABLE)) && \ 940 (((__VALUE__) & (OB_SECURE_HIDE_PROTECTION_ENABLE | OB_SECURE_HIDE_PROTECTION_DISABLE)) != (OB_SECURE_HIDE_PROTECTION_ENABLE | OB_SECURE_HIDE_PROTECTION_DISABLE)) && \ 941 (((__VALUE__) & (OB_SECURE_SRAM1_ENABLE | OB_SECURE_SRAM1_DISABLE)) != (OB_SECURE_SRAM1_ENABLE | OB_SECURE_SRAM1_DISABLE)) && \ 942 (((__VALUE__) & (OB_SECURE_SRAM2_ENABLE | OB_SECURE_SRAM2_DISABLE)) != (OB_SECURE_SRAM2_ENABLE | OB_SECURE_SRAM2_DISABLE)) ) 943 #endif /* DUAL_CORE */ 944 945 #if defined(DUAL_CORE) 946 #define IS_OPTIONBYTE(__VALUE__) ((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \ 947 OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | OPTIONBYTE_SECURE_MODE | \ 948 OPTIONBYTE_C2_DEBUG_ACCESS | OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS)) 949 950 #else 951 952 #define IS_OPTIONBYTE(__VALUE__) ((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)) 953 #endif /* DUAL_CORE */ 954 955 #define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_BANK1_AREAA) || ((__VALUE__) == OB_WRPAREA_BANK1_AREAB)) 956 957 #define IS_OB_RDP_LEVEL(__VALUE__) (((__VALUE__) == OB_RDP_LEVEL_0) ||\ 958 ((__VALUE__) == OB_RDP_LEVEL_1) ||\ 959 ((__VALUE__) == OB_RDP_LEVEL_2)) 960 961 #define IS_OB_USER_TYPE(__VALUE__) ((((__VALUE__) & OB_USER_ALL) != 0U) && \ 962 (((__VALUE__) & ~OB_USER_ALL) == 0U)) 963 964 #define IS_OB_USER_CONFIG(__TYPE__, __VALUE__) ((((__TYPE__) & OB_USER_BOR_LEV) == OB_USER_BOR_LEV) \ 965 ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_0) || \ 966 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_1) || \ 967 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_2) || \ 968 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_3) || \ 969 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_4)) \ 970 : ((~(__TYPE__) & (__VALUE__)) == 0U)) 971 972 #define IS_OB_USER_BOR_LEVEL(__VALUE__) (((__VALUE__) == OB_BOR_LEVEL_0) || ((__VALUE__) == OB_BOR_LEVEL_1) || \ 973 ((__VALUE__) == OB_BOR_LEVEL_2) || ((__VALUE__) == OB_BOR_LEVEL_3) || \ 974 ((__VALUE__) == OB_BOR_LEVEL_4)) 975 976 #define IS_OB_PCROP_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U) 977 978 #if defined(DUAL_CORE) 979 #define IS_OB_IPCC_BUF_ADDR(__VALUE__) (IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__)) 980 981 #define IS_OB_BOOT_VECTOR_ADDR(__VALUE__) (IS_OB_SFSA_START_ADDR(__VALUE__) || IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__)) 982 #define IS_OB_BOOT_REGION(__VALUE__) (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) || ((__VALUE__) == OB_C2_BOOT_FROM_SRAM)) 983 984 #define IS_OB_SUBGHZSPI_SECURE_ACCESS(__VALUE__) (((__VALUE__) == OB_SUBGHZSPI_SECURE_ACCESS_ENABLE) || ((__VALUE__) == OB_SUBGHZSPI_SECURE_ACCESS_DISABLE)) 985 986 #define IS_OB_C2_DEBUG_MODE(__VALUE__) (((__VALUE__) == OB_C2_DEBUG_ACCESS_ENABLE) || ((__VALUE__) == OB_C2_DEBUG_ACCESS_DISABLE)) 987 #endif /* DUAL_CORE */ 988 989 #define IS_FLASH_LATENCY(__VALUE__) (((__VALUE__) == FLASH_LATENCY_0) || \ 990 ((__VALUE__) == FLASH_LATENCY_1) || \ 991 ((__VALUE__) == FLASH_LATENCY_2)) 992 993 /** 994 * @} 995 */ 996 997 /** 998 * @} 999 */ 1000 1001 /** 1002 * @} 1003 */ 1004 1005 #ifdef __cplusplus 1006 } 1007 #endif 1008 1009 #endif /* STM32WLxx_HAL_FLASH_H */ 1010 1011
