1 /** 2 ****************************************************************************** 3 * @file stm32wlxx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2020 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32WLxx_HAL_H 22 #define __STM32WLxx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif /* __cplusplus */ 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32wlxx_hal_conf.h" 30 #include "stm32wlxx_ll_system.h" 31 32 /** @addtogroup STM32WLxx_HAL_Driver 33 * @{ 34 */ 35 36 /** @defgroup HAL HAL 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup HAL_Exported_Structures HAL Exported Structures 42 * @{ 43 */ 44 45 /** @defgroup HAL_TICK_FREQ Tick Frequency 46 * @{ 47 */ 48 typedef enum 49 { 50 HAL_TICK_FREQ_10HZ = 100U, 51 HAL_TICK_FREQ_100HZ = 10U, 52 HAL_TICK_FREQ_1KHZ = 1U, 53 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 54 } HAL_TickFreqTypeDef; 55 56 /** 57 * @} 58 */ 59 60 #if defined(DUAL_CORE) 61 /** @defgroup HAL_SYSCFG_IM HAL SYSCFG Interrupt Mask 62 * @{ 63 */ 64 /** 65 * @brief SYSCFG Interrupt Mask structure definition 66 */ 67 typedef struct 68 { 69 uint32_t InterruptMask1; /*!< The SYSCFG Interrupt Mask to be configured. 70 This parameter can be a combination of @ref SYSCFG_IM_GRP1 */ 71 uint32_t InterruptMask2; /*!< The SYSCFG Interrupt Mask to be configured. 72 This parameter can be a combination of @ref SYSCFG_IM_GRP2 */ 73 } SYSCFG_InterruptTypeDef; 74 75 /** 76 * @} 77 */ 78 #endif /* DUAL_CORE */ 79 80 #if defined(STM32WL5Mxx) 81 /** @defgroup HAL_RADIO_SWITCH_CONFIG RADIO Switch Config 82 * @{ 83 */ 84 typedef enum 85 { 86 RADIO_SWITCH_OFF = 0, 87 RADIO_SWITCH_RX = 1, 88 RADIO_SWITCH_RFO_LP = 2, 89 RADIO_SWITCH_RFO_HP = 3, 90 } HAL_RADIO_SwitchConfig_TypeDef; 91 92 typedef enum 93 { 94 RADIO_RFO_LP_MAXPOWER = 0, 95 RADIO_RFO_HP_MAXPOWER, 96 } HAL_RADIO_RFOMaxPowerConfig_TypeDef; 97 98 /** 99 * @} 100 */ 101 #endif /* STM32WL5Mxx */ 102 103 /** 104 * @} 105 */ 106 107 108 /* Exported constants --------------------------------------------------------*/ 109 /** @defgroup HAL_Exported_Constants HAL Exported Constants 110 * @{ 111 */ 112 113 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 114 * @{ 115 */ 116 117 /** @defgroup SYSCFG_BootMode BOOT Mode 118 * @{ 119 */ 120 #define SYSCFG_BOOT_MAINFLASH LL_SYSCFG_REMAP_FLASH /*!< Main Flash memory mapped at 0x00000000 */ 121 #define SYSCFG_BOOT_SYSTEMFLASH LL_SYSCFG_REMAP_SYSTEMFLASH /*!< System Flash memory mapped at 0x00000000 */ 122 #define SYSCFG_BOOT_SRAM LL_SYSCFG_REMAP_SRAM /*!< SRAM1 mapped at 0x00000000 */ 123 /** 124 * @} 125 */ 126 127 /** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31) 128 * @{ 129 */ 130 #define SYSCFG_SRAM2WRP_PAGE0 LL_SYSCFG_SRAM2WRP_PAGE0 /*!< SRAM2 Write protection page 0 */ 131 #define SYSCFG_SRAM2WRP_PAGE1 LL_SYSCFG_SRAM2WRP_PAGE1 /*!< SRAM2 Write protection page 1 */ 132 #define SYSCFG_SRAM2WRP_PAGE2 LL_SYSCFG_SRAM2WRP_PAGE2 /*!< SRAM2 Write protection page 2 */ 133 #define SYSCFG_SRAM2WRP_PAGE3 LL_SYSCFG_SRAM2WRP_PAGE3 /*!< SRAM2 Write protection page 3 */ 134 #define SYSCFG_SRAM2WRP_PAGE4 LL_SYSCFG_SRAM2WRP_PAGE4 /*!< SRAM2 Write protection page 4 */ 135 #define SYSCFG_SRAM2WRP_PAGE5 LL_SYSCFG_SRAM2WRP_PAGE5 /*!< SRAM2 Write protection page 5 */ 136 #define SYSCFG_SRAM2WRP_PAGE6 LL_SYSCFG_SRAM2WRP_PAGE6 /*!< SRAM2 Write protection page 6 */ 137 #define SYSCFG_SRAM2WRP_PAGE7 LL_SYSCFG_SRAM2WRP_PAGE7 /*!< SRAM2 Write protection page 7 */ 138 #define SYSCFG_SRAM2WRP_PAGE8 LL_SYSCFG_SRAM2WRP_PAGE8 /*!< SRAM2 Write protection page 8 */ 139 #define SYSCFG_SRAM2WRP_PAGE9 LL_SYSCFG_SRAM2WRP_PAGE9 /*!< SRAM2 Write protection page 9 */ 140 #define SYSCFG_SRAM2WRP_PAGE10 LL_SYSCFG_SRAM2WRP_PAGE10 /*!< SRAM2 Write protection page 10 */ 141 #define SYSCFG_SRAM2WRP_PAGE11 LL_SYSCFG_SRAM2WRP_PAGE11 /*!< SRAM2 Write protection page 11 */ 142 #define SYSCFG_SRAM2WRP_PAGE12 LL_SYSCFG_SRAM2WRP_PAGE12 /*!< SRAM2 Write protection page 12 */ 143 #define SYSCFG_SRAM2WRP_PAGE13 LL_SYSCFG_SRAM2WRP_PAGE13 /*!< SRAM2 Write protection page 13 */ 144 #define SYSCFG_SRAM2WRP_PAGE14 LL_SYSCFG_SRAM2WRP_PAGE14 /*!< SRAM2 Write protection page 14 */ 145 #define SYSCFG_SRAM2WRP_PAGE15 LL_SYSCFG_SRAM2WRP_PAGE15 /*!< SRAM2 Write protection page 15 */ 146 #define SYSCFG_SRAM2WRP_PAGE16 LL_SYSCFG_SRAM2WRP_PAGE16 /*!< SRAM2 Write protection page 16 */ 147 #define SYSCFG_SRAM2WRP_PAGE17 LL_SYSCFG_SRAM2WRP_PAGE17 /*!< SRAM2 Write protection page 17 */ 148 #define SYSCFG_SRAM2WRP_PAGE18 LL_SYSCFG_SRAM2WRP_PAGE18 /*!< SRAM2 Write protection page 18 */ 149 #define SYSCFG_SRAM2WRP_PAGE19 LL_SYSCFG_SRAM2WRP_PAGE19 /*!< SRAM2 Write protection page 19 */ 150 #define SYSCFG_SRAM2WRP_PAGE20 LL_SYSCFG_SRAM2WRP_PAGE20 /*!< SRAM2 Write protection page 20 */ 151 #define SYSCFG_SRAM2WRP_PAGE21 LL_SYSCFG_SRAM2WRP_PAGE21 /*!< SRAM2 Write protection page 21 */ 152 #define SYSCFG_SRAM2WRP_PAGE22 LL_SYSCFG_SRAM2WRP_PAGE22 /*!< SRAM2 Write protection page 22 */ 153 #define SYSCFG_SRAM2WRP_PAGE23 LL_SYSCFG_SRAM2WRP_PAGE23 /*!< SRAM2 Write protection page 23 */ 154 #define SYSCFG_SRAM2WRP_PAGE24 LL_SYSCFG_SRAM2WRP_PAGE24 /*!< SRAM2 Write protection page 24 */ 155 #define SYSCFG_SRAM2WRP_PAGE25 LL_SYSCFG_SRAM2WRP_PAGE25 /*!< SRAM2 Write protection page 25 */ 156 #define SYSCFG_SRAM2WRP_PAGE26 LL_SYSCFG_SRAM2WRP_PAGE26 /*!< SRAM2 Write protection page 26 */ 157 #define SYSCFG_SRAM2WRP_PAGE27 LL_SYSCFG_SRAM2WRP_PAGE27 /*!< SRAM2 Write protection page 27 */ 158 #define SYSCFG_SRAM2WRP_PAGE28 LL_SYSCFG_SRAM2WRP_PAGE28 /*!< SRAM2 Write protection page 28 */ 159 #define SYSCFG_SRAM2WRP_PAGE29 LL_SYSCFG_SRAM2WRP_PAGE29 /*!< SRAM2 Write protection page 29 */ 160 #define SYSCFG_SRAM2WRP_PAGE30 LL_SYSCFG_SRAM2WRP_PAGE30 /*!< SRAM2 Write protection page 30 */ 161 #define SYSCFG_SRAM2WRP_PAGE31 LL_SYSCFG_SRAM2WRP_PAGE31 /*!< SRAM2 Write protection page 31 */ 162 163 /** 164 * @} 165 */ 166 167 #if defined(VREFBUF) 168 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 169 * @{ 170 */ 171 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 LL_VREFBUF_VOLTAGE_SCALE0 /*!< Voltage reference scale 0 (VREF_OUT1) */ 172 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 LL_VREFBUF_VOLTAGE_SCALE1 /*!< Voltage reference scale 1 (VREF_OUT2) */ 173 174 /** 175 * @} 176 */ 177 178 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 179 * @{ 180 */ 181 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 182 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 183 184 /** 185 * @} 186 */ 187 #endif /* VREFBUF */ 188 189 /** @defgroup SYSCFG_SRAM_flags_definition SRAM Flags 190 * @{ 191 */ 192 193 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ 194 #define SYSCFG_FLAG_SRAM_BUSY SYSCFG_SCSR_SRAMBSY /*!< SRAM1 or SRAM2 erase operation is ongoing */ 195 #define SYSCFG_FLAG_PKASRAM_BUSY SYSCFG_SCSR_PKASRAMBSY /*!< PKA SRAM busy by erase operation */ 196 /** 197 * @} 198 */ 199 200 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 201 * @{ 202 */ 203 204 /** @brief Fast-mode Plus driving capability on a specific GPIO 205 */ 206 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 207 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 208 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 209 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 210 211 /** 212 * @} 213 */ 214 215 #if defined(DUAL_CORE) 216 /** @defgroup SYSCFG_IM_GRP1 SYSCFG INTERRUPT MASK GROUP1 217 * @{ 218 */ 219 220 #define HAL_SYSCFG_GRP1_RESERVED 0x00U /*!< Define user to differentiate Group1 to Group 2 */ 221 222 #if defined(CORE_CM0PLUS) 223 /** @brief Interrupt mask related to CPU2 NVIC 224 */ 225 #define HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS (LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC TimeStamp, RTC Tampers 226 and LSE Clock Security System to CPU2 */ 227 #define HAL_SYSCFG_GRP1_RTCALARM (LL_C2_SYSCFG_GRP1_RTCALARM | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC Alarms to CPU2 */ 228 #define HAL_SYSCFG_GRP1_RTCSSRU (LL_C2_SYSCFG_GRP1_RTCSSRU | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC SSRU to CPU2 */ 229 #define HAL_SYSCFG_GRP1_RTCWKUP (LL_C2_SYSCFG_GRP1_RTCWKUP | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC Wakeup to CPU2 */ 230 #define HAL_SYSCFG_GRP1_RCC (LL_C2_SYSCFG_GRP1_RCC | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RCC to CPU2 */ 231 #define HAL_SYSCFG_GRP1_FLASH (LL_C2_SYSCFG_GRP1_FLASH | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from FLASH to CPU2 */ 232 #define HAL_SYSCFG_GRP1_PKA (LL_C2_SYSCFG_GRP1_PKA | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from PKA to CPU2 */ 233 #define HAL_SYSCFG_GRP1_AES (LL_C2_SYSCFG_GRP1_AES | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from AES to CPU2 */ 234 #define HAL_SYSCFG_GRP1_COMP (LL_C2_SYSCFG_GRP1_COMP | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from Comparator to CPU2 */ 235 #define HAL_SYSCFG_GRP1_ADC (LL_C2_SYSCFG_GRP1_ADC | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from Analog Digital Converter to CPU2 */ 236 #define HAL_SYSCFG_GRP1_DAC (LL_C2_SYSCFG_GRP1_DAC | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from Digital Analog Converter to CPU2 */ 237 238 #define HAL_SYSCFG_GRP1_EXTI0 (LL_C2_SYSCFG_GRP1_EXTI0 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 0 to CPU2 */ 239 #define HAL_SYSCFG_GRP1_EXTI1 (LL_C2_SYSCFG_GRP1_EXTI1 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 1 to CPU2 */ 240 #define HAL_SYSCFG_GRP1_EXTI2 (LL_C2_SYSCFG_GRP1_EXTI2 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 2 to CPU2 */ 241 #define HAL_SYSCFG_GRP1_EXTI3 (LL_C2_SYSCFG_GRP1_EXTI3 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 3 to CPU2 */ 242 #define HAL_SYSCFG_GRP1_EXTI4 (LL_C2_SYSCFG_GRP1_EXTI4 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 4 to CPU2 */ 243 #define HAL_SYSCFG_GRP1_EXTI5 (LL_C2_SYSCFG_GRP1_EXTI5 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 5 to CPU2 */ 244 #define HAL_SYSCFG_GRP1_EXTI6 (LL_C2_SYSCFG_GRP1_EXTI6 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 6 to CPU2 */ 245 #define HAL_SYSCFG_GRP1_EXTI7 (LL_C2_SYSCFG_GRP1_EXTI7 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 7 to CPU2 */ 246 #define HAL_SYSCFG_GRP1_EXTI8 (LL_C2_SYSCFG_GRP1_EXTI8 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 8 to CPU2 */ 247 #define HAL_SYSCFG_GRP1_EXTI9 (LL_C2_SYSCFG_GRP1_EXTI9 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 9 to CPU2 */ 248 #define HAL_SYSCFG_GRP1_EXTI10 (LL_C2_SYSCFG_GRP1_EXTI10 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 10 to CPU2 */ 249 #define HAL_SYSCFG_GRP1_EXTI11 (LL_C2_SYSCFG_GRP1_EXTI11 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 11 to CPU2 */ 250 #define HAL_SYSCFG_GRP1_EXTI12 (LL_C2_SYSCFG_GRP1_EXTI12 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 12 to CPU2 */ 251 #define HAL_SYSCFG_GRP1_EXTI13 (LL_C2_SYSCFG_GRP1_EXTI13 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 13 to CPU2 */ 252 #define HAL_SYSCFG_GRP1_EXTI14 (LL_C2_SYSCFG_GRP1_EXTI14 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 14 to CPU2 */ 253 #define HAL_SYSCFG_GRP1_EXTI15 (LL_C2_SYSCFG_GRP1_EXTI15 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 15 to CPU2 */ 254 255 #else 256 257 /** @brief Interrupt mask related to CPU1 NVIC 258 */ 259 #define HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS (LL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTCSTAMPTAMPLSECSS to CPU1 */ 260 #define HAL_SYSCFG_GRP1_RTCSSRU (LL_SYSCFG_GRP1_RTCSSRU | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC SSRU to CPU1 */ 261 #define HAL_SYSCFG_GRP1_EXTI5 (LL_SYSCFG_GRP1_EXTI5 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 5 to CPU1 */ 262 #define HAL_SYSCFG_GRP1_EXTI6 (LL_SYSCFG_GRP1_EXTI6 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 6 to CPU1 */ 263 #define HAL_SYSCFG_GRP1_EXTI7 (LL_SYSCFG_GRP1_EXTI7 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 7 to CPU1 */ 264 #define HAL_SYSCFG_GRP1_EXTI8 (LL_SYSCFG_GRP1_EXTI8 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 8 to CPU1 */ 265 #define HAL_SYSCFG_GRP1_EXTI9 (LL_SYSCFG_GRP1_EXTI9 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 9 to CPU1 */ 266 #define HAL_SYSCFG_GRP1_EXTI10 (LL_SYSCFG_GRP1_EXTI10 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 10 to CPU1 */ 267 #define HAL_SYSCFG_GRP1_EXTI11 (LL_SYSCFG_GRP1_EXTI11 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 11 to CPU1 */ 268 #define HAL_SYSCFG_GRP1_EXTI12 (LL_SYSCFG_GRP1_EXTI12 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 12 to CPU1 */ 269 #define HAL_SYSCFG_GRP1_EXTI13 (LL_SYSCFG_GRP1_EXTI13 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 13 to CPU1 */ 270 #define HAL_SYSCFG_GRP1_EXTI14 (LL_SYSCFG_GRP1_EXTI14 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 14 to CPU1 */ 271 #define HAL_SYSCFG_GRP1_EXTI15 (LL_SYSCFG_GRP1_EXTI15 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 15 to CPU1 */ 272 273 #endif 274 275 /** 276 * @} 277 */ 278 279 /** @defgroup SYSCFG_IM_GRP2 SYSCFG INTERRUPT MASK GROUP2 280 * @{ 281 */ 282 283 #define HAL_SYSCFG_GRP2_RESERVED 0x80U /*!< Define user to differentiate Group1 to Group 2 */ 284 285 #if defined(CORE_CM0PLUS) 286 /** @brief Interrupt mask related to CPU2 NVIC 287 */ 288 #define HAL_SYSCFG_GRP2_DMA1CH1 (LL_C2_SYSCFG_GRP2_DMA1CH1 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 1 to CPU2 */ 289 #define HAL_SYSCFG_GRP2_DMA1CH2 (LL_C2_SYSCFG_GRP2_DMA1CH2 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 2 to CPU2 */ 290 #define HAL_SYSCFG_GRP2_DMA1CH3 (LL_C2_SYSCFG_GRP2_DMA1CH3 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 3 to CPU2 */ 291 #define HAL_SYSCFG_GRP2_DMA1CH4 (LL_C2_SYSCFG_GRP2_DMA1CH4 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 4 to CPU2 */ 292 #define HAL_SYSCFG_GRP2_DMA1CH5 (LL_C2_SYSCFG_GRP2_DMA1CH5 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 5 to CPU2 */ 293 #define HAL_SYSCFG_GRP2_DMA1CH6 (LL_C2_SYSCFG_GRP2_DMA1CH6 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 6 to CPU2 */ 294 #define HAL_SYSCFG_GRP2_DMA1CH7 (LL_C2_SYSCFG_GRP2_DMA1CH7 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 7 to CPU2 */ 295 296 #define HAL_SYSCFG_GRP2_DMA2CH1 (LL_C2_SYSCFG_GRP2_DMA2CH1 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 1 to CPU2 */ 297 #define HAL_SYSCFG_GRP2_DMA2CH2 (LL_C2_SYSCFG_GRP2_DMA2CH2 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 2 to CPU2 */ 298 #define HAL_SYSCFG_GRP2_DMA2CH3 (LL_C2_SYSCFG_GRP2_DMA2CH3 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 3 to CPU2 */ 299 #define HAL_SYSCFG_GRP2_DMA2CH4 (LL_C2_SYSCFG_GRP2_DMA2CH4 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 4 to CPU2 */ 300 #define HAL_SYSCFG_GRP2_DMA2CH5 (LL_C2_SYSCFG_GRP2_DMA2CH5 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 5 to CPU2 */ 301 #define HAL_SYSCFG_GRP2_DMA2CH6 (LL_C2_SYSCFG_GRP2_DMA2CH6 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 6 to CPU2 */ 302 #define HAL_SYSCFG_GRP2_DMA2CH7 (LL_C2_SYSCFG_GRP2_DMA2CH7 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 7 to CPU2 */ 303 304 #define HAL_SYSCFG_GRP2_DMAMUX1 (LL_C2_SYSCFG_GRP2_DMAMUX1 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMAMUX1 to CPU2 */ 305 306 #define HAL_SYSCFG_GRP2_PVM3 (LL_C2_SYSCFG_GRP2_PVM3 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU2 */ 307 #define HAL_SYSCFG_GRP2_PVD (LL_C2_SYSCFG_GRP2_PVD | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Detector to CPU2 */ 308 309 #else 310 311 /** @brief Interrupt mask related to CPU1 NVIC 312 */ 313 #define HAL_SYSCFG_GRP2_PVM3 (LL_SYSCFG_GRP2_PVM3 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU1 */ 314 #define HAL_SYSCFG_GRP2_PVD (LL_SYSCFG_GRP2_PVD | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Detector to CPU1 */ 315 316 #endif 317 /** 318 * @} 319 */ 320 #endif /* DUAL_CORE */ 321 322 #if defined(STM32WL5Mxx) 323 /** @defgroup RADIO_Exported_Constants RADIO Exported Constants 324 * @{ 325 */ 326 #define RADIO_CONF_TCXO_NOT_SUPPORTED 0U 327 #define RADIO_CONF_TCXO_SUPPORTED 1U 328 329 #define RADIO_CONF_DCDC_NOT_SUPPORTED 0U 330 #define RADIO_CONF_DCDC_SUPPORTED 1U 331 332 #define RADIO_CONF_RFO_HP_MAX_22_dBm ((int32_t) 22) 333 #define RADIO_CONF_RFO_HP_MAX_20_dBm ((int32_t) 20) 334 #define RADIO_CONF_RFO_HP_MAX_17_dBm ((int32_t) 17) 335 #define RADIO_CONF_RFO_HP_MAX_14_dBm ((int32_t) 14) 336 #define RADIO_CONF_RFO_LP_MAX_15_dBm ((int32_t) 15) 337 #define RADIO_CONF_RFO_LP_MAX_14_dBm ((int32_t) 14) 338 #define RADIO_CONF_RFO_LP_MAX_10_dBm ((int32_t) 10) 339 340 /** 341 * @} 342 */ 343 #endif /* STM32WL5Mxx */ 344 345 /** 346 * @} 347 */ 348 349 /** 350 * @} 351 */ 352 353 /* Exported macros -----------------------------------------------------------*/ 354 /** @defgroup HAL_Exported_Macros HAL Exported Macros 355 * @{ 356 */ 357 358 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 359 * @{ 360 */ 361 362 /** @brief Freeze and Unfreeze Peripherals in Debug mode 363 */ 364 365 /** @defgroup DBGMCU_APBx_GRPx_STOP_IP DBGMCU CPU1 APBx GRPx STOP IP 366 * @{ 367 */ 368 #if defined(LL_DBGMCU_APB1_GRP1_TIM2_STOP) 369 #define __HAL_DBGMCU_FREEZE_TIM2() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP) 370 #define __HAL_DBGMCU_UNFREEZE_TIM2() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP) 371 #endif 372 373 #if defined(LL_DBGMCU_APB1_GRP1_RTC_STOP) 374 #define __HAL_DBGMCU_FREEZE_RTC() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP) 375 #define __HAL_DBGMCU_UNFREEZE_RTC() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP) 376 #endif 377 378 #if defined(LL_DBGMCU_APB1_GRP1_WWDG_STOP) 379 #define __HAL_DBGMCU_FREEZE_WWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP) 380 #define __HAL_DBGMCU_UNFREEZE_WWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP) 381 #endif 382 383 #if defined(LL_DBGMCU_APB1_GRP1_IWDG_STOP) 384 #define __HAL_DBGMCU_FREEZE_IWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP) 385 #define __HAL_DBGMCU_UNFREEZE_IWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP) 386 #endif 387 388 #if defined(LL_DBGMCU_APB1_GRP1_I2C1_STOP) 389 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP) 390 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP) 391 #endif 392 393 #if defined(LL_DBGMCU_APB1_GRP1_I2C2_STOP) 394 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C2_STOP) 395 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C2_STOP) 396 #endif 397 398 #if defined(LL_DBGMCU_APB1_GRP1_I2C3_STOP) 399 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP) 400 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP) 401 #endif 402 403 #if defined(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP) 404 #define __HAL_DBGMCU_FREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP) 405 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP) 406 #endif 407 408 #if defined(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP) 409 #define __HAL_DBGMCU_FREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP) 410 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP) 411 #endif 412 413 #if defined(LL_DBGMCU_APB1_GRP2_LPTIM3_STOP) 414 #define __HAL_DBGMCU_FREEZE_LPTIM3() LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM3_STOP) 415 #define __HAL_DBGMCU_UNFREEZE_LPTIM3() LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM3_STOP) 416 #endif 417 418 #if defined(LL_DBGMCU_APB2_GRP1_TIM1_STOP) 419 #define __HAL_DBGMCU_FREEZE_TIM1() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP) 420 #define __HAL_DBGMCU_UNFREEZE_TIM1() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP) 421 #endif 422 423 #if defined(LL_DBGMCU_APB2_GRP1_TIM16_STOP) 424 #define __HAL_DBGMCU_FREEZE_TIM16() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP) 425 #define __HAL_DBGMCU_UNFREEZE_TIM16() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP) 426 #endif 427 428 #if defined(LL_DBGMCU_APB2_GRP1_TIM17_STOP) 429 #define __HAL_DBGMCU_FREEZE_TIM17() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP) 430 #define __HAL_DBGMCU_UNFREEZE_TIM17() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP) 431 #endif 432 433 /** 434 * @} 435 */ 436 437 /** @defgroup DBGMCU_C2_APBx_GRPx_STOP_IP DBGMCU CPU2 APBx GRPx STOP IP 438 * @{ 439 */ 440 #if defined(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP) 441 #define __HAL_C2_DBGMCU_FREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP) 442 #define __HAL_C2_DBGMCU_UNFREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP) 443 #endif 444 445 #if defined(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP) 446 #define __HAL_C2_DBGMCU_FREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP) 447 #define __HAL_C2_DBGMCU_UNFREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP) 448 #endif 449 450 #if defined(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP) 451 #define __HAL_C2_DBGMCU_FREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP) 452 #define __HAL_C2_DBGMCU_UNFREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP) 453 #endif 454 455 #if defined(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP) 456 #define __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP) 457 #define __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP) 458 #endif 459 460 #if defined(LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP) 461 #define __HAL_C2_DBGMCU_FREEZE_I2C2_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP) 462 #define __HAL_C2_DBGMCU_UNFREEZE_I2C2_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP) 463 #endif 464 465 #if defined(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP) 466 #define __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP) 467 #define __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP) 468 #endif 469 470 #if defined(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP) 471 #define __HAL_C2_DBGMCU_FREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP) 472 #define __HAL_C2_DBGMCU_UNFREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP) 473 #endif 474 475 #if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP) 476 #define __HAL_C2_DBGMCU_FREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP) 477 #define __HAL_C2_DBGMCU_UNFREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP) 478 #endif 479 480 #if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP) 481 #define __HAL_C2_DBGMCU_FREEZE_LPTIM3() LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP) 482 #define __HAL_C2_DBGMCU_UNFREEZE_LPTIM3() LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP) 483 #endif 484 485 #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP) 486 #define __HAL_C2_DBGMCU_FREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP) 487 #define __HAL_C2_DBGMCU_UNFREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP) 488 #endif 489 490 #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP) 491 #define __HAL_C2_DBGMCU_FREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP) 492 #define __HAL_C2_DBGMCU_UNFREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP) 493 #endif 494 495 #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP) 496 #define __HAL_C2_DBGMCU_FREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP) 497 #define __HAL_C2_DBGMCU_UNFREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP) 498 #endif 499 500 /** 501 * @} 502 */ 503 504 /** 505 * @} 506 */ 507 508 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 509 * @{ 510 */ 511 512 /** @brief Main Flash memory mapped at 0x00000000 513 */ 514 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH) 515 516 /** @brief System Flash memory mapped at 0x00000000 517 */ 518 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SYSTEMFLASH) 519 520 /** @brief Embedded SRAM mapped at 0x00000000 521 */ 522 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM) 523 524 /** 525 * @brief Return the boot mode as configured by user. 526 * @retval The boot mode as configured by user. The returned value can be one 527 * of the following values: 528 * @arg @ref SYSCFG_BOOT_MAINFLASH 529 * @arg @ref SYSCFG_BOOT_SYSTEMFLASH 530 * @arg @ref SYSCFG_BOOT_SRAM 531 */ 532 #define __HAL_SYSCFG_GET_BOOT_MODE() LL_SYSCFG_GetRemapMemory() 533 534 /** @brief SRAM2 page 0 to 31 write protection enable macro 535 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP 536 * @note Write protection can only be disabled by a system reset 537 */ 538 /* Legacy define */ 539 #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE 540 #define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 541 LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__);\ 542 }while(0) 543 544 /** @brief SRAM2 page write protection unlock prior to erase 545 * @note Writing a wrong key reactivates the write protection 546 */ 547 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() LL_SYSCFG_UnlockSRAM2WRP() 548 549 /** @brief SRAM2 erase 550 * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM_BUSY) may be used to check end of erase 551 */ 552 #define __HAL_SYSCFG_SRAM2_ERASE() LL_SYSCFG_EnableSRAM2Erase() 553 554 /** @brief SYSCFG Break ECC lock. 555 * Enable and lock the connection of Flash ECC error connection to TIM1/16/17 Break input. 556 * @note The selected configuration is locked and can be unlocked only by system reset. 557 */ 558 #define __HAL_SYSCFG_BREAK_ECC_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_ECC) 559 560 /** @brief SYSCFG Break Cortex-M4 Lockup lock. 561 * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/16/17 Break input. 562 * @note The selected configuration is locked and can be unlocked only by system reset. 563 */ 564 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP) 565 566 /** @brief SYSCFG Break PVD lock. 567 * Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. 568 * @note The selected configuration is locked and can be unlocked only by system reset. 569 */ 570 #define __HAL_SYSCFG_BREAK_PVD_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD) 571 572 /** @brief SYSCFG Break SRAM2 parity lock. 573 * Enable and lock the SRAM2 parity error signal connection to TIM1/16/17 Break input. 574 * @note The selected configuration is locked and can be unlocked by system reset. 575 */ 576 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_SRAM2_PARITY) 577 578 /** @brief Check SYSCFG flag is set or not. 579 * @param __FLAG__ specifies the flag to check. 580 * This parameter can be one of the following values: 581 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 582 * @arg @ref SYSCFG_FLAG_SRAM_BUSY SRAM2 Erase Ongoing 583 * @arg @ref SYSCFG_FLAG_PKASRAM_BUSY PKA SRAM Erase Ongoing 584 * @retval The new state of __FLAG__ (TRUE or FALSE). 585 */ 586 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_FLAG_SRAM2_PE)? SYSCFG->CFGR2 : SYSCFG->SCSR) &\ 587 (__FLAG__))!= 0) ? 1 : 0) 588 589 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 590 */ 591 #define __HAL_SYSCFG_CLEAR_FLAG() LL_SYSCFG_ClearFlag_SP() 592 593 /** @brief Fast mode Plus driving capability enable/disable macros 594 * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO 595 */ 596 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ 597 LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__); \ 598 }while(0) 599 600 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ 601 LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__); \ 602 }while(0) 603 604 /** 605 * @} 606 */ 607 608 /** 609 * @} 610 */ 611 612 /* Private macros ------------------------------------------------------------*/ 613 /** @defgroup HAL_Private_Macros HAL Private Macros 614 * @{ 615 */ 616 617 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 618 * @{ 619 */ 620 621 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU)) 622 623 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 624 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) 625 626 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 627 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 628 629 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 630 631 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 632 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 633 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 634 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 635 636 637 #if defined(DUAL_CORE) 638 #if defined(CORE_CM0PLUS) 639 #define IS_SYSCFG_IM_GRP1(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP1_RESERVED) && \ 640 ((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS) == HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS) || \ 641 (((__VALUE__) & HAL_SYSCFG_GRP1_RTCALARM ) == HAL_SYSCFG_GRP1_RTCALARM ) || \ 642 (((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU ) == HAL_SYSCFG_GRP1_RTCSSRU ) || \ 643 (((__VALUE__) & HAL_SYSCFG_GRP1_RTCWKUP ) == HAL_SYSCFG_GRP1_RTCWKUP ) || \ 644 (((__VALUE__) & HAL_SYSCFG_GRP1_RCC ) == HAL_SYSCFG_GRP1_RCC ) || \ 645 (((__VALUE__) & HAL_SYSCFG_GRP1_FLASH ) == HAL_SYSCFG_GRP1_FLASH ) || \ 646 (((__VALUE__) & HAL_SYSCFG_GRP1_PKA ) == HAL_SYSCFG_GRP1_PKA ) || \ 647 (((__VALUE__) & HAL_SYSCFG_GRP1_AES ) == HAL_SYSCFG_GRP1_AES ) || \ 648 (((__VALUE__) & HAL_SYSCFG_GRP1_COMP ) == HAL_SYSCFG_GRP1_COMP ) || \ 649 (((__VALUE__) & HAL_SYSCFG_GRP1_ADC ) == HAL_SYSCFG_GRP1_ADC ) || \ 650 (((__VALUE__) & HAL_SYSCFG_GRP1_DAC ) == HAL_SYSCFG_GRP1_DAC ) || \ 651 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI0 ) == HAL_SYSCFG_GRP1_EXTI0 ) || \ 652 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI1 ) == HAL_SYSCFG_GRP1_EXTI1 ) || \ 653 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI2 ) == HAL_SYSCFG_GRP1_EXTI2 ) || \ 654 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI3 ) == HAL_SYSCFG_GRP1_EXTI3 ) || \ 655 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI4 ) == HAL_SYSCFG_GRP1_EXTI4 ) || \ 656 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5 ) == HAL_SYSCFG_GRP1_EXTI5 ) || \ 657 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6 ) == HAL_SYSCFG_GRP1_EXTI6 ) || \ 658 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7 ) == HAL_SYSCFG_GRP1_EXTI7 ) || \ 659 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8 ) == HAL_SYSCFG_GRP1_EXTI8 ) || \ 660 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9 ) == HAL_SYSCFG_GRP1_EXTI9 ) || \ 661 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10 ) == HAL_SYSCFG_GRP1_EXTI10 ) || \ 662 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11 ) == HAL_SYSCFG_GRP1_EXTI11 ) || \ 663 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12 ) == HAL_SYSCFG_GRP1_EXTI12 ) || \ 664 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13 ) == HAL_SYSCFG_GRP1_EXTI13 ) || \ 665 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14 ) == HAL_SYSCFG_GRP1_EXTI14 ) || \ 666 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15 ) == HAL_SYSCFG_GRP1_EXTI15 ))) 667 668 #define IS_SYSCFG_IM_GRP2(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP2_RESERVED) && \ 669 ((((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH1) == HAL_SYSCFG_GRP2_DMA1CH1) || \ 670 (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH2) == HAL_SYSCFG_GRP2_DMA1CH2) || \ 671 (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH3) == HAL_SYSCFG_GRP2_DMA1CH3) || \ 672 (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH4) == HAL_SYSCFG_GRP2_DMA1CH4) || \ 673 (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH5) == HAL_SYSCFG_GRP2_DMA1CH5) || \ 674 (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH6) == HAL_SYSCFG_GRP2_DMA1CH6) || \ 675 (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH7) == HAL_SYSCFG_GRP2_DMA1CH7) || \ 676 (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH1) == HAL_SYSCFG_GRP2_DMA2CH1) || \ 677 (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH2) == HAL_SYSCFG_GRP2_DMA2CH2) || \ 678 (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH3) == HAL_SYSCFG_GRP2_DMA2CH3) || \ 679 (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH4) == HAL_SYSCFG_GRP2_DMA2CH4) || \ 680 (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH5) == HAL_SYSCFG_GRP2_DMA2CH5) || \ 681 (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH6) == HAL_SYSCFG_GRP2_DMA2CH6) || \ 682 (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH7) == HAL_SYSCFG_GRP2_DMA2CH7) || \ 683 (((__VALUE__) & HAL_SYSCFG_GRP2_DMAMUX1) == HAL_SYSCFG_GRP2_DMAMUX1) || \ 684 (((__VALUE__) & HAL_SYSCFG_GRP2_PVM3 ) == HAL_SYSCFG_GRP2_PVM3 ) || \ 685 (((__VALUE__) & HAL_SYSCFG_GRP2_PVD ) == HAL_SYSCFG_GRP2_PVD ))) 686 687 #else /* !CORE_CM0PLUS */ 688 689 #define IS_SYSCFG_IM_GRP1(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP1_RESERVED) && \ 690 ((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS) == HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS) || \ 691 (((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU ) == HAL_SYSCFG_GRP1_RTCSSRU ) || \ 692 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5 ) == HAL_SYSCFG_GRP1_EXTI5 ) || \ 693 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6 ) == HAL_SYSCFG_GRP1_EXTI6 ) || \ 694 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7 ) == HAL_SYSCFG_GRP1_EXTI7 ) || \ 695 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8 ) == HAL_SYSCFG_GRP1_EXTI8 ) || \ 696 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9 ) == HAL_SYSCFG_GRP1_EXTI9 ) || \ 697 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10 ) == HAL_SYSCFG_GRP1_EXTI10 ) || \ 698 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11 ) == HAL_SYSCFG_GRP1_EXTI11 ) || \ 699 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12 ) == HAL_SYSCFG_GRP1_EXTI12 ) || \ 700 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13 ) == HAL_SYSCFG_GRP1_EXTI13 ) || \ 701 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14 ) == HAL_SYSCFG_GRP1_EXTI14 ) || \ 702 (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15 ) == HAL_SYSCFG_GRP1_EXTI15 ))) 703 704 #define IS_SYSCFG_IM_GRP2(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP2_RESERVED) && \ 705 ((((__VALUE__) & HAL_SYSCFG_GRP2_PVM3) == HAL_SYSCFG_GRP2_PVM3) || \ 706 (((__VALUE__) & HAL_SYSCFG_GRP2_PVD ) == HAL_SYSCFG_GRP2_PVD ))) 707 708 #endif /* CORE_CM0PLUS */ 709 #endif /* DUAL_CORE */ 710 711 /** 712 * @} 713 */ 714 715 /** 716 * @} 717 */ 718 719 /** @defgroup HAL_Private_Macros HAL Private Macros 720 * @{ 721 */ 722 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 723 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 724 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 725 /** 726 * @} 727 */ 728 729 730 /* Exported functions --------------------------------------------------------*/ 731 732 /** @defgroup HAL_Exported_Functions HAL Exported Functions 733 * @{ 734 */ 735 736 /** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions 737 * @{ 738 */ 739 740 /* Initialization and Configuration functions ******************************/ 741 HAL_StatusTypeDef HAL_Init(void); 742 HAL_StatusTypeDef HAL_DeInit(void); 743 void HAL_MspInit(void); 744 void HAL_MspDeInit(void); 745 746 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 747 748 /** 749 * @} 750 */ 751 752 /* Exported variables ---------------------------------------------------------*/ 753 /** @addtogroup HAL_Exported_Variables 754 * @{ 755 */ 756 extern __IO uint32_t uwTick; 757 extern uint32_t uwTickPrio; 758 extern HAL_TickFreqTypeDef uwTickFreq; 759 /** 760 * @} 761 */ 762 763 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions 764 * @{ 765 */ 766 767 /* Peripheral Control functions ************************************************/ 768 void HAL_IncTick(void); 769 void HAL_Delay(uint32_t Delay); 770 uint32_t HAL_GetTick(void); 771 uint32_t HAL_GetTickPrio(void); 772 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 773 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 774 void HAL_SuspendTick(void); 775 void HAL_ResumeTick(void); 776 uint32_t HAL_GetHalVersion(void); 777 uint32_t HAL_GetREVID(void); 778 uint32_t HAL_GetDEVID(void); 779 uint32_t HAL_GetUIDw0(void); 780 uint32_t HAL_GetUIDw1(void); 781 uint32_t HAL_GetUIDw2(void); 782 783 /** 784 * @} 785 */ 786 787 /** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions 788 * @{ 789 */ 790 791 /* DBGMCU Peripheral Control functions *****************************************/ 792 void HAL_DBGMCU_EnableDBGSleepMode(void); 793 void HAL_DBGMCU_DisableDBGSleepMode(void); 794 void HAL_DBGMCU_EnableDBGStopMode(void); 795 void HAL_DBGMCU_DisableDBGStopMode(void); 796 void HAL_DBGMCU_EnableDBGStandbyMode(void); 797 void HAL_DBGMCU_DisableDBGStandbyMode(void); 798 /** 799 * @} 800 */ 801 802 /** @addtogroup HAL_Exported_Functions_Group4 HAL System Configuration functions 803 * @{ 804 */ 805 806 /* SYSCFG Control functions ****************************************************/ 807 void HAL_SYSCFG_SRAM2Erase(void); 808 809 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 810 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 811 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 812 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 813 void HAL_SYSCFG_DisableVREFBUF(void); 814 815 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); 816 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); 817 818 #if defined(DUAL_CORE) 819 void HAL_SYSCFG_EnableIT(SYSCFG_InterruptTypeDef *Interrupt); 820 void HAL_SYSCFG_DisableIT(SYSCFG_InterruptTypeDef *Interrupt); 821 #endif 822 /** 823 * @} 824 */ 825 826 #if defined( STM32WL5Mxx) 827 /** @addtogroup HAL_Exported_Functions_Group5 HAL Radio Configuration functions 828 * @{ 829 */ 830 831 /* RADIO Control functions ****************************************************/ 832 HAL_StatusTypeDef HAL_RADIO_Init(void); 833 HAL_StatusTypeDef HAL_RADIO_DeInit(void); 834 HAL_StatusTypeDef HAL_RADIO_SetSwitchConfig(HAL_RADIO_SwitchConfig_TypeDef Config); 835 uint8_t HAL_RADIO_IsTCXO(void); 836 uint8_t HAL_RADIO_IsDCDC(void); 837 int32_t HAL_RADIO_GetRFOMaxPowerConfig(HAL_RADIO_RFOMaxPowerConfig_TypeDef Config); 838 839 /** 840 * @} 841 */ 842 #endif /* STM32WL5Mxx */ 843 844 /** 845 * @} 846 */ 847 848 /** 849 * @} 850 */ 851 852 /** 853 * @} 854 */ 855 856 #ifdef __cplusplus 857 } 858 #endif /* __cplusplus */ 859 860 #endif /* __STM32WLxx_HAL_H */ 861
