1 /**
2   ******************************************************************************
3   * @file    stm32wb15xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS Cortex Device Peripheral Access Layer Header File.
6   *          This file contains all the peripheral register's definitions, bits
7   *          definitions and memory mapping for stm32wb15xx devices.
8   *
9   *          This file contains:
10   *           - Data structures and the address mapping for all peripherals
11   *           - Peripheral's registers declarations and bits definition
12   *           - Macros to access peripheral's registers hardware
13   *
14   ******************************************************************************
15   * @attention
16   *
17   * Copyright (c) 2019-2022 STMicroelectronics.
18   * All rights reserved.
19   *
20   * This software is licensed under terms that can be found in the LICENSE file
21   * in the root directory of this software component.
22   * If no LICENSE file comes with this software, it is provided AS-IS.
23   *
24   ******************************************************************************
25   */
26 
27 /** @addtogroup CMSIS_Device
28   * @{
29   */
30 
31 /** @addtogroup stm32wb15xx
32   * @{
33   */
34 
35 #ifndef __STM32WB15xx_H
36 #define __STM32WB15xx_H
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif /* __cplusplus */
41 
42 /** @addtogroup Configuration_section_for_CMSIS
43   * @{
44   */
45 /**
46   * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
47   */
48 #define __CM4_REV                 1U /*!< Core Revision r0p1                            */
49 #define __MPU_PRESENT             1U /*!< M4 provides an MPU                            */
50 #define __VTOR_PRESENT            1U /*!< Vector Table Register supported               */
51 #define __NVIC_PRIO_BITS          4U /*!< STM32WBxx uses 4 Bits for the Priority Levels */
52 #define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
53 #define __FPU_PRESENT             1U /*!< FPU present                                   */
54 /**
55   * @}
56   */
57 
58 /** @addtogroup Peripheral_interrupt_number_definition
59   * @{
60   */
61 
62 /**
63   * @brief stm32wb15xx Interrupt Number Definition, according to the selected device
64   *        in @ref Library_configuration_section
65   */
66 /*!< Interrupt Number Definition for M4 */
67 typedef enum
68 {
69   /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
70   NonMaskableInt_IRQn                 = -14,    /*!< Non Maskable Interrupt                                            */
71   HardFault_IRQn                      = -13,    /*!< Cortex-M4 Hard Fault Interrupt                                    */
72   MemoryManagement_IRQn               = -12,    /*!< Cortex-M4 Memory Management Interrupt                             */
73   BusFault_IRQn                       = -11,    /*!< Cortex-M4 Bus Fault Interrupt                                     */
74   UsageFault_IRQn                     = -10,    /*!< Cortex-M4 Usage Fault Interrupt                                   */
75   SVCall_IRQn                         = -5,     /*!< Cortex-M4 SV Call Interrupt                                       */
76   DebugMonitor_IRQn                   = -4,     /*!< Cortex-M4 Debug Monitor Interrupt                                 */
77   PendSV_IRQn                         = -2,     /*!< Cortex-M4 Pend SV Interrupt                                       */
78   SysTick_IRQn                        = -1,     /*!< Cortex-M4 System Tick Interrupt                                   */
79 
80   /*************  STM32WBxx specific Interrupt Numbers on M4 core ************************************************/
81   WWDG_IRQn                           = 0,      /*!< Window WatchDog Interrupt                                         */
82   PVD_PVM_IRQn                        = 1,      /*!< PVD and PVM detector                                              */
83   TAMP_STAMP_LSECSS_IRQn              = 2,      /*!< RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts         */
84   RTC_WKUP_IRQn                       = 3,      /*!< RTC Wakeup Interrupt                                              */
85   FLASH_IRQn                          = 4,      /*!< FLASH (CFI)  global Interrupt                                     */
86   RCC_IRQn                            = 5,      /*!< RCC Interrupt                                                     */
87   EXTI0_IRQn                          = 6,      /*!< EXTI Line 0 Interrupt                                             */
88   EXTI1_IRQn                          = 7,      /*!< EXTI Line 1 Interrupt                                             */
89   EXTI2_IRQn                          = 8,      /*!< EXTI Line 2 Interrupt                                             */
90   EXTI3_IRQn                          = 9,      /*!< EXTI Line 3 Interrupt                                             */
91   EXTI4_IRQn                          = 10,     /*!< EXTI Line 4 Interrupt                                             */
92   DMA1_Channel1_IRQn                  = 11,     /*!< DMA1 Channel 1 Interrupt                                          */
93   DMA1_Channel2_IRQn                  = 12,     /*!< DMA1 Channel 2 Interrupt                                          */
94   DMA1_Channel3_IRQn                  = 13,     /*!< DMA1 Channel 3 Interrupt                                          */
95   DMA1_Channel4_IRQn                  = 14,     /*!< DMA1 Channel 4 Interrupt                                          */
96   DMA1_Channel5_IRQn                  = 15,     /*!< DMA1 Channel 5 Interrupt                                          */
97   DMA1_Channel6_IRQn                  = 16,     /*!< DMA1 Channel 6 Interrupt                                          */
98   DMA1_Channel7_IRQn                  = 17,     /*!< DMA1 Channel 7 Interrupt                                          */
99   ADC1_IRQn                           = 18,     /*!< ADC1 Interrupt                                                    */
100   C2SEV_PWR_C2H_IRQn                  = 21,     /*!< CPU2 SEV Interrupt                                                */
101   COMP_IRQn                           = 22,     /*!< COMP1 Interrupt                                                   */
102   EXTI9_5_IRQn                        = 23,     /*!< EXTI Lines [9:5] Interrupt                                        */
103   TIM1_BRK_IRQn                       = 24,     /*!< TIM1 Break Interrupt                                              */
104   TIM1_UP_IRQn                        = 25,     /*!< TIM1 Update Interrupt                                             */
105   TIM1_TRG_COM_IRQn                   = 26,     /*!< TIM1 Trigger and Communication Interrupts                         */
106   TIM1_CC_IRQn                        = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
107   TIM2_IRQn                           = 28,     /*!< TIM2 Global Interrupt                                             */
108   PKA_IRQn                            = 29,     /*!< PKA Interrupt                                                     */
109   I2C1_EV_IRQn                        = 30,     /*!< I2C1 Event Interrupt                                              */
110   I2C1_ER_IRQn                        = 31,     /*!< I2C1 Error Interrupt                                              */
111   SPI1_IRQn                           = 34,     /*!< SPI1 Interrupt                                                    */
112   USART1_IRQn                         = 36,     /*!< USART1 Interrupt                                                  */
113   LPUART1_IRQn                        = 37,     /*!< LPUART1 Interrupt                                                 */
114   TSC_IRQn                            = 39,     /*!< TSC Interrupt                                                     */
115   EXTI15_10_IRQn                      = 40,     /*!< EXTI Lines1[15:10 ]Interrupts                                     */
116   RTC_Alarm_IRQn                      = 41,     /*!< RTC Alarms (A and B) Interrupt                                    */
117   PWR_SOTF_BLEACT_RFPHASE_IRQn        = 43,     /*!< PWR switching on the fly interrupt
118                                                      PWR end of BLE activity interrupt
119                                                      PWR end of critical radio phase interrupt                         */
120   IPCC_C1_RX_IRQn                     = 44,     /*!< IPCC RX Occupied Interrupt                                        */
121   IPCC_C1_TX_IRQn                     = 45,     /*!< IPCC TX Free Interrupt                                            */
122   HSEM_IRQn                           = 46,     /*!< HSEM Interrupt                                                    */
123   LPTIM1_IRQn                         = 47,     /*!< LPTIM1 Interrupt                                                  */
124   LPTIM2_IRQn                         = 48,     /*!< LPTIM2 Interrupt                                                  */
125   AES2_IRQn                           = 52,     /*!< AES2 Interrupt                                                    */
126   RNG_IRQn                            = 53,     /*!< RNG Interrupt                                                     */
127   FPU_IRQn                            = 54,     /*!< FPU Interrupt                                                     */
128   DMAMUX1_OVR_IRQn                    = 62      /*!< DMAMUX1 overrun Interrupt                                         */
129 } IRQn_Type;
130 /**
131   * @}
132   */
133 
134 #include "core_cm4.h"                /* Cortex-M4 processor and core peripherals */
135 #include "system_stm32wbxx.h"
136 #include <stdint.h>
137 
138 /** @addtogroup Peripheral_registers_structures
139   * @{
140   */
141 
142 /**
143   * @brief Analog to Digital Converter
144   */
145 typedef struct
146 {
147   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
148   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
149   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
150   __IO uint32_t CFGR1;        /*!< ADC configuration register 1,                  Address offset: 0x0C */
151   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
152   __IO uint32_t SMPR;         /*!< ADC sampling time register,                    Address offset: 0x14 */
153        uint32_t RESERVED1;    /*!< Reserved,                                                      0x18 */
154        uint32_t RESERVED2;    /*!< Reserved,                                                      0x1C */
155   __IO uint32_t TR;           /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
156   __IO uint32_t RESERVED3;    /*!< Reserved,                                                      0x24 */
157   __IO uint32_t CHSELR;       /*!< ADC group regular sequencer register,          Address offset: 0x28 */
158   __IO uint32_t RESERVED4;    /*!< Reserved,                                                      0x2C */
159        uint32_t RESERVED5[4]; /*!< Reserved,                                               0x30 - 0x3C */
160   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
161        uint32_t RESERVED6[23];/*!< Reserved,                                               0x44 - 0x9C */
162   __IO uint32_t RESERVED7;    /*!< Reserved,                                                      0xA0 */
163   __IO uint32_t RESERVED8;    /*!< Reserved,                                                      0xA4 */
164        uint32_t RESERVED9[3]; /*!< Reserved,                                               0xA8 - 0xB0 */
165   __IO uint32_t CALFACT;      /*!< ADC Calibration factor register,               Address offset: 0xB4 */
166 } ADC_TypeDef;
167 
168 /* Legacy registers naming */
169 #define TR1     TR
170 
171 
172 typedef struct
173 {
174   uint32_t      RESERVED1;    /*!< Reserved,                                      Address offset: ADC1 base address + 0x300 */
175   uint32_t      RESERVED2;    /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */
176   __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
177   uint32_t      RESERVED3;    /*!< Reserved,                                      Address offset: ADC1 base address + 0x30C */
178 } ADC_Common_TypeDef;
179 
180 /**
181   * @brief Comparator
182   */
183 typedef struct
184 {
185   __IO uint32_t CSR;         /*!< COMP control and status register,               Address offset: 0x00 */
186 } COMP_TypeDef;
187 
188 /**
189   * @brief CRC calculation unit
190   */
191 typedef struct
192 {
193   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
194   __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
195   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
196        uint32_t RESERVED2;   /*!< Reserved,                                                    0x0C */
197   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
198   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
199 } CRC_TypeDef;
200 
201 /**
202   * @brief Debug MCU
203   */
204 typedef struct
205 {
206   __IO uint32_t IDCODE;      /*!< MCU device ID code,                          Address offset: 0x00 */
207   __IO uint32_t CR;          /*!< Debug MCU configuration register,            Address offset: 0x04 */
208   uint32_t RESERVED1[13];    /*!< Reserved,                                               0x08-0x38 */
209   __IO uint32_t APB1FZR1;    /*!< Debug MCU CPU1 APB1 freeze register,         Address offset: 0x3C */
210   __IO uint32_t C2APB1FZR1;  /*!< Debug MCU CPU2 APB1 freeze register,         Address offset: 0x40 */
211   __IO uint32_t APB1FZR2;    /*!< Debug MCU CPU1 APB1 freeze register,         Address offset: 0x44 */
212   __IO uint32_t C2APB1FZR2;  /*!< Debug MCU CPU2 APB1 freeze register,         Address offset: 0x48 */
213   __IO uint32_t APB2FZR;     /*!< Debug MCU CPU1 APB2 freeze register,         Address offset: 0x4C */
214   __IO uint32_t C2APB2FZR;   /*!< Debug MCU CPU2 APB2 freeze register,         Address offset: 0x50 */
215 } DBGMCU_TypeDef;
216 
217 /**
218   * @brief DMA Controller
219   */
220 typedef struct
221 {
222   __IO uint32_t CCR;         /*!< DMA channel x configuration register        0x00 */
223   __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       0x04 */
224   __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   0x08 */
225   __IO uint32_t CMAR;        /*!< DMA channel x memory address register       0x0C */
226   uint32_t RESERVED;         /*!< Reserved,                                   0x10 */
227 } DMA_Channel_TypeDef;
228 
229 typedef struct
230 {
231   __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
232   __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
233 } DMA_TypeDef;
234 
235 /**
236   * @brief DMA Multiplexer
237   */
238 typedef struct
239 {
240   __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
241 } DMAMUX_Channel_TypeDef;
242 
243 typedef struct
244 {
245   __IO uint32_t   CSR;       /*!< DMA Channel Status Register                    Address offset: 0x0080   */
246   __IO uint32_t   CFR;       /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */
247 } DMAMUX_ChannelStatus_TypeDef;
248 
249 typedef struct
250 {
251   __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */
252 } DMAMUX_RequestGen_TypeDef;
253 
254 typedef struct
255 {
256   __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */
257   __IO uint32_t   RGCFR;       /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */
258 } DMAMUX_RequestGenStatus_TypeDef;
259 
260 /**
261   * @brief FLASH Registers
262   */
263 typedef struct
264 {
265   __IO uint32_t ACR;           /*!< FLASH Access control register,                      Address offset: 0x00      */
266   __IO uint32_t RESERVED;      /*!< Reserved,                                           Address offset: 0x04      */
267   __IO uint32_t KEYR;          /*!< FLASH Key register,                                 Address offset: 0x08      */
268   __IO uint32_t OPTKEYR;       /*!< FLASH Option Key register,                          Address offset: 0x0C      */
269   __IO uint32_t SR;            /*!< FLASH Status register,                              Address offset: 0x10      */
270   __IO uint32_t CR;            /*!< FLASH Control register,                             Address offset: 0x14      */
271   __IO uint32_t ECCR;          /*!< FLASH ECC register,                                 Address offset: 0x18      */
272   uint32_t RESERVED1;          /*!< Reserved,                                           Address offset: 0x1C      */
273   __IO uint32_t OPTR;          /*!< FLASH Option register,                              Address offset: 0x20      */
274   __IO uint32_t PCROP1ASR;     /*!< FLASH Bank 1 PCROP area A Start address register,   Address offset: 0x24      */
275   __IO uint32_t PCROP1AER;     /*!< FLASH Bank 1 PCROP area A End address register,     Address offset: 0x28      */
276   __IO uint32_t WRP1AR;        /*!< FLASH Bank 1 WRP area A address register,           Address offset: 0x2C      */
277   __IO uint32_t WRP1BR;        /*!< FLASH Bank 1 WRP area B address register,           Address offset: 0x30      */
278   __IO uint32_t PCROP1BSR;     /*!< FLASH Bank 1 PCROP area B Start address register,   Address offset: 0x34      */
279   __IO uint32_t PCROP1BER;     /*!< FLASH Bank 1 PCROP area B End address register,     Address offset: 0x38      */
280   __IO uint32_t IPCCBR;        /*!< FLASH IPCC data buffer address,                     Address offset: 0x3C      */
281   uint32_t RESERVED2[7];       /*!< Reserved,                                           Address offset: 0x40-0x58 */
282   __IO uint32_t C2ACR;         /*!< FLASH Core MO+ Access Control Register ,            Address offset: 0x5C      */
283   __IO uint32_t C2SR;          /*!< FLASH Core MO+ Status Register,                     Address offset: 0x60      */
284   __IO uint32_t C2CR;          /*!< FLASH Core MO+ Control register,                    Address offset: 0x64      */
285   uint32_t RESERVED3[6];       /*!< Reserved,                                           Address offset: 0x68-0x7C */
286   __IO uint32_t SFR;           /*!< FLASH secure start address,                         Address offset: 0x80      */
287   __IO uint32_t SRRVR;         /*!< FlASH secure SRAM2 start addr and CPU2 reset vector Address offset: 0x84      */
288 } FLASH_TypeDef;
289 
290 /**
291   * @brief General Purpose I/O
292   */
293 typedef struct
294 {
295   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
296   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
297   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
298   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
299   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
300   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
301   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
302   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
303   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
304   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
305 } GPIO_TypeDef;
306 
307 /**
308   * @brief Inter-integrated Circuit Interface
309   */
310 typedef struct
311 {
312   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
313   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
314   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
315   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
316   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
317   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
318   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
319   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
320   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
321   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
322   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
323 } I2C_TypeDef;
324 
325 /**
326   * @brief Independent WATCHDOG
327   */
328 typedef struct
329 {
330   __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
331   __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
332   __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
333   __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
334   __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
335 } IWDG_TypeDef;
336 
337 /**
338   * @brief LPTIMER
339   */
340 typedef struct
341 {
342   __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
343   __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
344   __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
345   __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
346   __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
347   __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
348   __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
349   __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
350   __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
351 } LPTIM_TypeDef;
352 
353 /**
354   * @brief Power Control
355   */
356 typedef struct
357 {
358   __IO uint32_t CR1;          /*!< PWR Power Control Register 1,                     Address offset: 0x00 */
359   __IO uint32_t CR2;          /*!< PWR Power Control Register 2,                     Address offset: 0x04 */
360   __IO uint32_t CR3;          /*!< PWR Power Control Register 3,                     Address offset: 0x08 */
361   __IO uint32_t CR4;          /*!< PWR Power Control Register 4,                     Address offset: 0x0C */
362   __IO uint32_t SR1;          /*!< PWR Power Status Register 1,                      Address offset: 0x10 */
363   __IO uint32_t SR2;          /*!< PWR Power Status Register 2,                      Address offset: 0x14 */
364   __IO uint32_t SCR;          /*!< PWR Power Status Reset Register,                  Address offset: 0x18 */
365   __IO uint32_t CR5;          /*!< PWR Power Control Register 5,                     Address offset: 0x1C */
366   __IO uint32_t PUCRA;        /*!< PWR Pull-Up Control Register of port A,           Address offset: 0x20 */
367   __IO uint32_t PDCRA;        /*!< PWR Pull-Down Control Register of port A,         Address offset: 0x24 */
368   __IO uint32_t PUCRB;        /*!< PWR Pull-Up Control Register of port B,           Address offset: 0x28 */
369   __IO uint32_t PDCRB;        /*!< PWR Pull-Down Control Register of port B,         Address offset: 0x2C */
370   __IO uint32_t PUCRC;        /*!< PWR Pull-Up Control Register of port C,           Address offset: 0x30 */
371   __IO uint32_t PDCRC;        /*!< PWR Pull-Down Control Register of port C,         Address offset: 0x34 */
372        uint32_t RESERVED2[2]; /*!< Reserved,                                         Address offset: 0x38-0x3C */
373   __IO uint32_t PUCRE;        /*!< PWR Pull-Up Control Register of port E,           Address offset: 0x40 */
374   __IO uint32_t PDCRE;        /*!< PWR Pull-Down Control Register of port E,         Address offset: 0x44 */
375        uint32_t RESERVED0[4]; /*!< Reserved,                                         Address offset: 0x48-0x54 */
376   __IO uint32_t PUCRH;        /*!< PWR Pull-Up Control Register of port H,           Address offset: 0x58 */
377   __IO uint32_t PDCRH;        /*!< PWR Pull-Down Control Register of port H,         Address offset: 0x5C */
378        uint32_t RESERVED1[8]; /*!< Reserved,                                         Address offset: 0x60-0x7C */
379   __IO uint32_t C2CR1;        /*!< PWR Power Control Register 1 for CPU2,            Address offset: 0x80 */
380   __IO uint32_t C2CR3;        /*!< PWR Power Control Register 3 for CPU2,            Address offset: 0x84 */
381   __IO uint32_t EXTSCR;       /*!< PWR Power Status Reset Register for CPU2,         Address offset: 0x88 */
382 } PWR_TypeDef;
383 
384 /**
385   * @brief Reset and Clock Control
386   */
387 typedef struct
388 {
389   __IO uint32_t CR;            /*!< RCC clock  Control Register,                                                    Address offset: 0x00 */
390   __IO uint32_t ICSCR;         /*!< RCC Internal Clock Sources Calibration Register,                                Address offset: 0x04 */
391   __IO uint32_t CFGR;          /*!< RCC Clocks Configuration Register,                                              Address offset: 0x08 */
392   __IO uint32_t PLLCFGR;       /*!< RCC System PLL configuration Register,                                          Address offset: 0x0C */
393        uint32_t RESERVED0[2];  /*!< Reserved,                                                                       Address offset: 0x10-0x14 */
394   __IO uint32_t CIER;          /*!< RCC Clock Interrupt Enable Register,                                            Address offset: 0x18 */
395   __IO uint32_t CIFR;          /*!< RCC Clock Interrupt Flag Register,                                              Address offset: 0x1C */
396   __IO uint32_t CICR;          /*!< RCC Clock Interrupt Clear Register,                                             Address offset: 0x20 */
397   __IO uint32_t SMPSCR;        /*!< RCC SMPS step-down converter control register,                                  Address offset: 0x24 */
398   __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                                             Address offset: 0x28 */
399   __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                                             Address offset: 0x2C */
400   __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 & AHB4 peripheral reset register,                                      Address offset: 0x30 */
401        uint32_t RESERVED1;     /*!< Reserved,                                                                       Address offset: 0x34 */
402   __IO uint32_t APB1RSTR1;     /*!< RCC APB1 peripheral reset register 1,                                           Address offset: 0x38 */
403   __IO uint32_t APB1RSTR2;     /*!< RCC APB1 peripheral reset register 2,                                           Address offset: 0x3C */
404   __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                                             Address offset: 0x40 */
405   __IO uint32_t APB3RSTR;      /*!< RCC APB3 peripheral reset register,                                             Address offset: 0x44 */
406   __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clocks enable register,                                     Address offset: 0x48 */
407   __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clocks enable register,                                     Address offset: 0x4C */
408   __IO uint32_t AHB3ENR;       /*!< RCC AHB3 & AHB4 peripheral clocks enable register,                              Address offset: 0x50 */
409        uint32_t RESERVED2;     /*!< Reserved,                                                                       Address offset: 0x54 */
410   __IO uint32_t APB1ENR1;      /*!< RCC APB1 peripheral clocks enable register 1,                                   Address offset: 0x58 */
411   __IO uint32_t APB1ENR2;      /*!< RCC APB1 peripheral clocks enable register 2,                                   Address offset: 0x5C */
412   __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clocks enable register,                                     Address offset: 0x60 */
413        uint32_t RESERVED3;     /*!< Reserved,                                                                       Address offset: 0x64 */
414   __IO uint32_t AHB1SMENR;     /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,             Address offset: 0x68 */
415   __IO uint32_t AHB2SMENR;     /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,             Address offset: 0x6C */
416   __IO uint32_t AHB3SMENR;     /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
417        uint32_t RESERVED4;     /*!< Reserved,                                                                       Address offset: 0x74 */
418   __IO uint32_t APB1SMENR1;    /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1,      Address offset: 0x78 */
419   __IO uint32_t APB1SMENR2;    /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2,      Address offset: 0x7C */
420   __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register,        Address offset: 0x80 */
421        uint32_t RESERVED5;     /*!< Reserved,                                                                       Address offset: 0x84 */
422   __IO uint32_t CCIPR;         /*!< RCC Peripherals Clock Configuration Independent Register,                       Address offset: 0x88 */
423        uint32_t RESERVED6;     /*!< Reserved,                                                                       Address offset: 0x8C */
424   __IO uint32_t BDCR;          /*!< RCC Backup Domain Control Register,                                             Address offset: 0x90 */
425   __IO uint32_t CSR;           /*!< RCC Control and Status Register,                                                Address offset: 0x94 */
426   __IO uint32_t CRRCR;         /*!< RCC Clock Recovery RC Register,                                                 Address offset: 0x98 */
427   __IO uint32_t HSECR;         /*!< RCC HSE Clock Register,                                                         Address offset: 0x9C */
428        uint32_t RESERVED7[26]; /*!< Reserved,                                                                       Address offset: 0xA0-0x104 */
429   __IO uint32_t EXTCFGR;       /*!< RCC Extended Clock Recovery Register,                                           Address offset: 0x108 */
430        uint32_t RESERVED8[15]; /*!< Reserved,                                                                       Address offset: 0x10C-0x144 */
431   __IO uint32_t C2AHB1ENR;     /*!< RRCC AHB1 peripheral CPU2 clocks enable register,                               Address offset: 0x148 */
432   __IO uint32_t C2AHB2ENR;     /*!< RCC AHB2 peripheral CPU2 clocks enable register,                                Address offset: 0x14C */
433   __IO uint32_t C2AHB3ENR;     /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,,                        Address offset: 0x150 */
434        uint32_t RESERVED9;     /*!< Reserved,                                                                       Address offset: 0x154 */
435   __IO uint32_t C2APB1ENR1;    /*!< RCC APB1 peripheral CPU2 clocks enable register 1,                              Address offset: 0x158 */
436   __IO uint32_t C2APB1ENR2;    /*!< RCC APB1 peripheral CPU2 clocks enable register 2,                              Address offset: 0x15C */
437   __IO uint32_t C2APB2ENR;     /*!< RCC APB2 peripheral CPU2 clocks enable register 1,                              Address offset: 0x160 */
438   __IO uint32_t C2APB3ENR;     /*!< RCC APB3 peripheral CPU2 clocks enable register 1,                              Address offset: 0x164 */
439   __IO uint32_t C2AHB1SMENR;   /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register,        Address offset: 0x168 */
440   __IO uint32_t C2AHB2SMENR;   /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register,        Address offset: 0x16C */
441   __IO uint32_t C2AHB3SMENR;   /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x170 */
442        uint32_t RESERVED10;    /*!< Reserved,                                                                                             */
443   __IO uint32_t C2APB1SMENR1;  /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1, Address offset: 0x178 */
444   __IO uint32_t C2APB1SMENR2;  /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2, Address offset: 0x17C */
445   __IO uint32_t C2APB2SMENR;   /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register,   Address offset: 0x180 */
446   __IO uint32_t C2APB3SMENR;   /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register,   Address offset: 0x184 */
447 } RCC_TypeDef;
448 
449 
450 
451 /**
452   * @brief Real-Time Clock
453   */
454 typedef struct
455 {
456   __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
457   __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
458   __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
459   __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
460   __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
461   __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
462        uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
463   __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
464   __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
465   __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
466   __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
467   __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
468   __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
469   __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
470   __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
471   __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
472   __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
473   __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
474   __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
475   __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
476   __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
477   __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
478   __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
479   __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
480   __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
481   __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
482   __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
483   __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
484   __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
485   __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
486   __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
487   __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
488   __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
489   __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
490   __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
491   __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
492   __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
493   __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
494   __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
495   __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
496 } RTC_TypeDef;
497 
498 
499 
500 
501 /**
502   * @brief Serial Peripheral Interface
503   */
504 typedef struct
505 {
506   __IO uint32_t CR1;      /*!< SPI Control register 1,       Address offset: 0x00 */
507   __IO uint32_t CR2;      /*!< SPI Control register 2,       Address offset: 0x04 */
508   __IO uint32_t SR;       /*!< SPI Status register,          Address offset: 0x08 */
509   __IO uint32_t DR;       /*!< SPI data register,            Address offset: 0x0C */
510   __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register,  Address offset: 0x10 */
511   __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register,          Address offset: 0x14 */
512   __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register,          Address offset: 0x18 */
513 } SPI_TypeDef;
514 
515 /**
516   * @brief System configuration controller
517   */
518 typedef struct
519 {
520   __IO uint32_t MEMRMP;            /*!< SYSCFG memory remap register                                            Address offset: 0x00       */
521   __IO uint32_t CFGR1;             /*!< SYSCFG configuration register 1,                                        Address offset: 0x04       */
522   __IO uint32_t EXTICR[4];         /*!< SYSCFG external interrupt configuration registers,                      Address offset: 0x08-0x14  */
523   __IO uint32_t SCSR;              /*!< SYSCFG SRAM2 control and status register,                               Address offset: 0x18       */
524   __IO uint32_t CFGR2;             /*!< SYSCFG configuration register 2,                                        Address offset: 0x1C       */
525   __IO uint32_t SWPR1;             /*!< SYSCFG SRAM2 write protection register part 1,                          Address offset: 0x20       */
526   __IO uint32_t SKR;               /*!< SYSCFG SRAM2 key register,                                              Address offset: 0x24       */
527   __IO uint32_t SWPR2;             /*!< SYSCFG write protection register part 2,                                Address offset: 0x28       */
528        uint32_t RESERVED1[53];     /*!< Reserved,                                                               Address offset: 0x2C-0xFC  */
529   __IO uint32_t IMR1;              /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 1, Address offset: 0x100      */
530   __IO uint32_t IMR2;              /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 2, Address offset: 0x104      */
531   __IO uint32_t C2IMR1;            /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 1, Address offset: 0x108      */
532   __IO uint32_t C2IMR2;            /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 2, Address offset: 0x10C      */
533   __IO uint32_t SIPCR;             /*!< SYSCFG secure IP control register,                                      Address offset: 0x110      */
534 
535 } SYSCFG_TypeDef;
536 
537 /**
538   * @brief TIM
539   */
540 typedef struct
541 {
542   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
543   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
544   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
545   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
546   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
547   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
548   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
549   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
550   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
551   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
552   __IO uint32_t PSC;         /*!< TIM prescaler register,                   Address offset: 0x28 */
553   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
554   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
555   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
556   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
557   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
558   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
559   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
560   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
561   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
562   __IO uint32_t OR;          /*!< TIM option register                       Address offset: 0x50 */
563   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
564   __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
565   __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
566   __IO uint32_t AF1;         /*!< TIM Alternate function option register 1, Address offset: 0x60 */
567   __IO uint32_t AF2;         /*!< TIM Alternate function option register 2, Address offset: 0x64 */
568 } TIM_TypeDef;
569 
570 /**
571   * @brief Universal Synchronous Asynchronous Receiver Transmitter
572   */
573 typedef struct
574 {
575   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
576   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
577   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
578   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
579   __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
580   __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
581   __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
582   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
583   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
584   __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
585   __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
586   __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C */
587 } USART_TypeDef;
588 
589 
590 /**
591   * @brief Window WATCHDOG
592   */
593 typedef struct
594 {
595   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
596   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
597   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
598 } WWDG_TypeDef;
599 
600 
601 /**
602   * @brief AES hardware accelerator
603   */
604 typedef struct
605 {
606   __IO uint32_t CR;          /*!< AES control register,                        Address offset: 0x00 */
607   __IO uint32_t SR;          /*!< AES status register,                         Address offset: 0x04 */
608   __IO uint32_t DINR;        /*!< AES data input register,                     Address offset: 0x08 */
609   __IO uint32_t DOUTR;       /*!< AES data output register,                    Address offset: 0x0C */
610   __IO uint32_t KEYR0;       /*!< AES key register 0,                          Address offset: 0x10 */
611   __IO uint32_t KEYR1;       /*!< AES key register 1,                          Address offset: 0x14 */
612   __IO uint32_t KEYR2;       /*!< AES key register 2,                          Address offset: 0x18 */
613   __IO uint32_t KEYR3;       /*!< AES key register 3,                          Address offset: 0x1C */
614   __IO uint32_t IVR0;        /*!< AES initialization vector register 0,        Address offset: 0x20 */
615   __IO uint32_t IVR1;        /*!< AES initialization vector register 1,        Address offset: 0x24 */
616   __IO uint32_t IVR2;        /*!< AES initialization vector register 2,        Address offset: 0x28 */
617   __IO uint32_t IVR3;        /*!< AES initialization vector register 3,        Address offset: 0x2C */
618   __IO uint32_t KEYR4;       /*!< AES key register 4,                          Address offset: 0x30 */
619   __IO uint32_t KEYR5;       /*!< AES key register 5,                          Address offset: 0x34 */
620   __IO uint32_t KEYR6;       /*!< AES key register 6,                          Address offset: 0x38 */
621   __IO uint32_t KEYR7;       /*!< AES key register 7,                          Address offset: 0x3C */
622   __IO uint32_t SUSP0R;      /*!< AES Suspend register 0,                      Address offset: 0x40 */
623   __IO uint32_t SUSP1R;      /*!< AES Suspend register 1,                      Address offset: 0x44 */
624   __IO uint32_t SUSP2R;      /*!< AES Suspend register 2,                      Address offset: 0x48 */
625   __IO uint32_t SUSP3R;      /*!< AES Suspend register 3,                      Address offset: 0x4C */
626   __IO uint32_t SUSP4R;      /*!< AES Suspend register 4,                      Address offset: 0x50 */
627   __IO uint32_t SUSP5R;      /*!< AES Suspend register 5,                      Address offset: 0x54 */
628   __IO uint32_t SUSP6R;      /*!< AES Suspend register 6,                      Address offset: 0x58 */
629   __IO uint32_t SUSP7R;      /*!< AES Suspend register 7,                      Address offset: 0x6C */
630 } AES_TypeDef;
631 
632 /**
633   * @brief RNG
634   */
635 typedef struct
636 {
637   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
638   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
639   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
640 } RNG_TypeDef;
641 
642 /**
643   * @brief Touch Sensing Controller (TSC)
644   */
645 typedef struct
646 {
647   __IO uint32_t CR;            /*!< TSC control register,                     Address offset: 0x00 */
648   __IO uint32_t IER;           /*!< TSC interrupt enable register,            Address offset: 0x04 */
649   __IO uint32_t ICR;           /*!< TSC interrupt clear register,             Address offset: 0x08 */
650   __IO uint32_t ISR;           /*!< TSC interrupt status register,            Address offset: 0x0C */
651   __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,      Address offset: 0x10 */
652   uint32_t      RESERVED1;     /*!< Reserved,                                 Address offset: 0x14 */
653   __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,   Address offset: 0x18 */
654   uint32_t      RESERVED2;     /*!< Reserved,                                 Address offset: 0x1C */
655   __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,        Address offset: 0x20 */
656   uint32_t      RESERVED3;     /*!< Reserved,                                 Address offset: 0x24 */
657   __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,         Address offset: 0x28 */
658   uint32_t      RESERVED4;     /*!< Reserved,                                 Address offset: 0x2C */
659   __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,    Address offset: 0x30 */
660   __IO uint32_t IOGXCR[7];     /*!< TSC I/O group x counter register,         Address offset: 0x34-4C */
661 } TSC_TypeDef;
662 
663 /**
664   * @brief Inter-Processor Communication
665   */
666 typedef struct
667 {
668   __IO uint32_t C1CR;             /*!< Inter-Processor Communication: C1 control register,                  Address offset: 0x000 */
669   __IO uint32_t C1MR ;            /*!< Inter-Processor Communication: C1 mask register,                     Address offset: 0x004 */
670   __IO uint32_t C1SCR;            /*!< Inter-Processor Communication: C1 status set clear register,         Address offset: 0x008 */
671   __IO uint32_t C1TOC2SR;         /*!< Inter-Processor Communication: C1 to processor M4  status register,  Address offset: 0x00C */
672   __IO uint32_t C2CR;             /*!< Inter-Processor Communication: C2 control register,                  Address offset: 0x010 */
673   __IO uint32_t C2MR ;            /*!< Inter-Processor Communication: C2 mask register,                     Address offset: 0x014 */
674   __IO uint32_t C2SCR;            /*!< Inter-Processor Communication: C2 status set clear register,         Address offset: 0x018 */
675   __IO uint32_t C2TOC1SR;         /*!< Inter-Processor Communication: C2 to processor M4 status register,   Address offset: 0x01C */
676 } IPCC_TypeDef;
677 
678 typedef struct
679 {
680   __IO uint32_t CR;               /*!< Control register,                                                    Address offset: 0x000 */
681   __IO uint32_t MR;               /*!< Mask register,                                                       Address offset: 0x004 */
682   __IO uint32_t SCR;              /*!< Status set clear register,                                           Address offset: 0x008 */
683   __IO uint32_t SR;               /*!< Status register,                                                     Address offset: 0x00C */
684 } IPCC_CommonTypeDef;
685 
686 /**
687   * @brief Async Interrupts and Events Controller
688   */
689 typedef struct
690 {
691   __IO uint32_t RTSR1;          /*!< EXTI rising trigger selection register [31:0],            Address offset: 0x00 */
692   __IO uint32_t FTSR1;          /*!< EXTI falling trigger selection register [31:0],           Address offset: 0x04 */
693   __IO uint32_t SWIER1;         /*!< EXTI software interrupt event register [31:0],            Address offset: 0x08 */
694   __IO uint32_t PR1;            /*!< EXTI pending register [31:0],                             Address offset: 0x0C */
695   __IO uint32_t RESERVED1[4];   /*!< Reserved,                                                 Address offset: 0x10 - 0x1C */
696   __IO uint32_t RTSR2;          /*!< EXTI rising trigger selection register [31:0],            Address offset: 0x20 */
697   __IO uint32_t FTSR2;          /*!< EXTI falling trigger selection register [31:0],           Address offset: 0x24 */
698   __IO uint32_t SWIER2;         /*!< EXTI software interrupt event register [31:0],            Address offset: 0x28 */
699   __IO uint32_t PR2;            /*!< EXTI pending register [31:0],                             Address offset: 0x2C */
700   __IO uint32_t RESERVED2[4];   /*!< Reserved,                                                 Address offset: 0x30 - 0x3C */
701   __IO uint32_t RESERVED3[8];   /*!< Reserved,                                                 Address offset: 0x40 - 0x5C */
702   __IO uint32_t RESERVED4[8];   /*!< Reserved,                                                 Address offset: 0x60 - 0x7C */
703   __IO uint32_t IMR1;           /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
704   __IO uint32_t EMR1;           /*!< EXTI wakeup with event mask register for cpu1 [31:0],     Address offset: 0x84 */
705   __IO uint32_t RESERVED5[2];   /*!< Reserved,                                                 Address offset: 0x88 - 0x8C */
706   __IO uint32_t IMR2;           /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
707   __IO uint32_t EMR2;           /*!< EXTI wakeup with event mask register for cpu1 [31:0],     Address offset: 0x94 */
708   __IO uint32_t RESERVED8[10];  /*!< Reserved,                                                 Address offset: 0x98 - 0xBC */
709   __IO uint32_t C2IMR1;         /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */
710   __IO uint32_t C2EMR1;         /*!< EXTI wakeup with event mask register for cpu2 [31:0],     Address offset: 0xC4 */
711   __IO uint32_t RESERVED9[2];   /*!< Reserved,                                                 Address offset: 0xC8 - 0xCC */
712   __IO uint32_t C2IMR2;         /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */
713   __IO uint32_t C2EMR2;         /*!< EXTI wakeup with event mask register for cpu2 [31:0],     Address offset: 0xD4 */
714 } EXTI_TypeDef;
715 
716 /**
717   * @brief Public Key Accelerator (PKA)
718   */
719 typedef struct
720 {
721   __IO uint32_t CR;          /*!< PKA control register,                 Address offset: 0x00 */
722   __IO uint32_t SR;          /*!< PKA status register,                  Address offset: 0x04 */
723   __IO uint32_t CLRFR;       /*!< PKA clear flag register,              Address offset: 0x08 */
724   uint32_t  Reserved1[253];  /*!< Reserved                              Address offset: 0x000C-0x03FC*/
725   __IO uint32_t RAM[894];    /*!< PKA RAM,                              Address offset: 0x0400-0x11F4 */
726 } PKA_TypeDef;
727 
728 /**
729   * @brief HW Semaphore HSEM
730   */
731 typedef struct
732 {
733   __IO uint32_t R[32];        /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-7Ch  */
734   __IO uint32_t RLR[32];      /*!< HSEM 1-step read lock registers,                Address offset: 80h-FCh  */
735   __IO uint32_t C1IER;        /*!< HSEM CPU1 interrupt enable register ,           Address offset: 100h     */
736   __IO uint32_t C1ICR;        /*!< HSEM CPU1 interrupt clear register ,            Address offset: 104h     */
737   __IO uint32_t C1ISR;        /*!< HSEM CPU1 interrupt status register ,           Address offset: 108h     */
738   __IO uint32_t C1MISR;       /*!< HSEM CPU1 masked interrupt status register ,    Address offset: 10Ch     */
739   __IO uint32_t C2IER;        /*!< HSEM CPU2 interrupt enable register ,           Address offset: 110h     */
740   __IO uint32_t C2ICR;        /*!< HSEM CPU2 interrupt clear register ,            Address offset: 114h     */
741   __IO uint32_t C2ISR;        /*!< HSEM CPU2 interrupt status register ,           Address offset: 118h     */
742   __IO uint32_t C2MISR;       /*!< HSEM CPU2 masked interrupt status register ,    Address offset: 11Ch     */
743        uint32_t  Reserved[8]; /*!< Reserved                                        Address offset: 120h-13Ch*/
744   __IO uint32_t CR;           /*!< HSEM Semaphore clear register ,                 Address offset: 140h     */
745   __IO uint32_t KEYR;         /*!< HSEM Semaphore clear key register ,             Address offset: 144h     */
746 } HSEM_TypeDef;
747 
748 typedef struct
749 {
750   __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */
751   __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */
752   __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */
753   __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */
754 } HSEM_Common_TypeDef;
755 
756 /**
757   * @}
758   */
759 
760 /** @addtogroup Peripheral_memory_map
761   * @{
762   */
763 
764 /*!< Boundary memory map */
765 #define FLASH_BASE             (0x08000000UL)/*!< FLASH(up to 320KB) base address */
766 #define SRAM_BASE              (0x20000000UL)/*!< SRAM(up to 12 KB) base address */
767 #define PERIPH_BASE            (0x40000000UL)/*!< Peripheral base address */
768 
769 /*!< Memory, OTP and Option bytes */
770 
771 /* Base addresses */
772 #define SYSTEM_MEMORY_BASE     (0x1FFF0000UL)  /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */
773 #define OTP_AREA_BASE          (0x1FFF7000UL)  /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF)       */
774 #define OPTION_BYTE_BASE       (0x1FFF7800UL)  /*!< Option Bytes : 128B (0x1FFF7800 - 0x1FFF787F)   */
775 #define ENGI_BYTE_BASE         (0x1FFF7400UL)  /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF)     */
776 
777 #define SRAM1_BASE             SRAM_BASE                 /*!< SRAM1(up to 12 KB) base address */
778 #define SRAM2A_BASE            (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address      */
779 #define SRAM2B_BASE            (SRAM_BASE + 0x00038000UL)/*!< SRAM2B(4 KB) base address       */
780 
781 /* Memory Size */
782 #define FLASH_SIZE              (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U)
783 #define SRAM1_SIZE              0x00003000UL   /*!< SRAM1 default size  : 12 KB */
784 #define SRAM2A_SIZE             0x00008000UL   /*!< SRAM2a default size : 32 KB */
785 #define SRAM2B_SIZE             0x00001000UL   /*!< SRAM2b default size :  4 KB */
786 
787 /* End addresses */
788 #define SRAM1_END_ADDR         (0x20002FFFUL)  /*!< SRAM1               :  12KB (0x20000000 - 0x20002FFF) */
789 #define SRAM2A_END_ADDR        (0x20037FFFUL)  /*!< SRAM2a (backup)     :  32KB (0x20030000 - 0x20037FFF) */
790 #define SRAM2B_END_ADDR        (0x20038FFFUL)  /*!< SRAM2b (backup)     :   4KB (0x20038000 - 0x20038FFF) */
791 
792 #define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL)  /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF)  */
793 #define OTP_AREA_END_ADDR      (0x1FFF73FFUL)  /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF)        */
794 #define OPTION_BYTE_END_ADDR   (0x1FFF8FFFUL)  /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF)    */
795 #define ENGI_BYTE_END_ADDR     (0x1FFF7FFFUL)  /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF)      */
796 
797 /*!< Peripheral memory map */
798 #define APB1PERIPH_BASE       PERIPH_BASE
799 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
800 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
801 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
802 #define AHB4PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)
803 #define APB3PERIPH_BASE       (PERIPH_BASE + 0x20000000UL)
804 
805 /*!< APB1 peripherals */
806 #define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
807 #define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
808 #define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
809 #define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
810 #define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
811 #define LPTIM1_BASE           (APB1PERIPH_BASE + 0x00007C00UL)
812 #define LPUART1_BASE          (APB1PERIPH_BASE + 0x00008000UL)
813 #define LPTIM2_BASE           (APB1PERIPH_BASE + 0x00009400UL)
814 
815 /*!< APB2 peripherals */
816 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
817 #define COMP1_BASE            (APB2PERIPH_BASE + 0x00000200UL)
818 #define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
819 #define ADC1_COMMON_BASE      (APB2PERIPH_BASE + 0x00002700UL)
820 
821 #define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00UL)
822 #define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
823 #define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
824 
825 /*!< AHB1 peripherals */
826 #define DMA1_BASE                (AHB1PERIPH_BASE + 0x00000000UL)
827 #define DMAMUX1_BASE             (AHB1PERIPH_BASE + 0x00000800UL)
828 #define CRC_BASE                 (AHB1PERIPH_BASE + 0x00003000UL)
829 #define TSC_BASE                 (AHB1PERIPH_BASE + 0x00004000UL)
830 
831 #define DMA1_Channel1_BASE       (DMA1_BASE + 0x00000008UL)
832 #define DMA1_Channel2_BASE       (DMA1_BASE + 0x0000001CUL)
833 #define DMA1_Channel3_BASE       (DMA1_BASE + 0x00000030UL)
834 #define DMA1_Channel4_BASE       (DMA1_BASE + 0x00000044UL)
835 #define DMA1_Channel5_BASE       (DMA1_BASE + 0x00000058UL)
836 #define DMA1_Channel6_BASE       (DMA1_BASE + 0x0000006CUL)
837 #define DMA1_Channel7_BASE       (DMA1_BASE + 0x00000080UL)
838 
839 #define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
840 #define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x00000004UL)
841 #define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x00000008UL)
842 #define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x0000000CUL)
843 #define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x00000010UL)
844 #define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x00000014UL)
845 #define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x00000018UL)
846 
847 #define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x00000100UL)
848 #define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x00000104UL)
849 #define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x00000108UL)
850 #define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x0000010CUL)
851 
852 #define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x00000080UL)
853 #define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x00000140UL)
854 
855 /*!< AHB2 peripherals */
856 #define IOPORT_BASE         (AHB2PERIPH_BASE + 0x00000000UL)
857 #define GPIOA_BASE          (IOPORT_BASE + 0x00000000UL)
858 #define GPIOB_BASE          (IOPORT_BASE + 0x00000400UL)
859 #define GPIOC_BASE          (IOPORT_BASE + 0x00000800UL)
860 #define GPIOE_BASE          (IOPORT_BASE + 0x00001000UL)
861 #define GPIOH_BASE          (IOPORT_BASE + 0x00001C00UL)
862 
863 /*!< AHB Shared peripherals */
864 #define RCC_BASE              (AHB4PERIPH_BASE + 0x00000000UL)
865 #define PWR_BASE              (AHB4PERIPH_BASE + 0x00000400UL)
866 #define EXTI_BASE             (AHB4PERIPH_BASE + 0x00000800UL)
867 #define IPCC_BASE             (AHB4PERIPH_BASE + 0x00000C00UL)
868 #define RNG_BASE              (AHB4PERIPH_BASE + 0x00001000UL)
869 #define HSEM_BASE             (AHB4PERIPH_BASE + 0x00001400UL)
870 #define AES2_BASE             (AHB4PERIPH_BASE + 0x00001800UL)
871 #define PKA_BASE              (AHB4PERIPH_BASE + 0x00002000UL)
872 #define FLASH_REG_BASE        (AHB4PERIPH_BASE + 0x00004000UL)
873 
874 /* Debug MCU registers base address */
875 #define DBGMCU_BASE           (0xE0042000UL)
876 
877 
878 /*!< AHB3 peripherals */
879 
880 /*!< Device Electronic Signature */
881 #define PACKAGE_BASE          ((uint32_t)0x1FFF7500UL)       /*!< Package data register base address     */
882 #define UID64_BASE            ((uint32_t)0x1FFF7580UL)       /*!< 64-bit Unique device Identification    */
883 #define UID_BASE              ((uint32_t)0x1FFF7590UL)       /*!< Unique device ID register base address */
884 #define FLASHSIZE_BASE        ((uint32_t)0x1FFF75E0UL)       /*!< Flash size data register base address  */
885 
886 /**
887   * @}
888   */
889 
890 /** @addtogroup Peripheral_declaration
891   * @{
892   */
893 
894 /* Peripherals available on APB1 bus */
895 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
896 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
897 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
898 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
899 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
900 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
901 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
902 #define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
903 
904 /* Peripherals available on APB2 bus */
905 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
906 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
907 #define COMP1_COMMON        ((COMP_Common_TypeDef *) COMP1_BASE)
908 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
909 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
910 #define USART1              ((USART_TypeDef *) USART1_BASE)
911 
912 /* Peripherals available on AHB1 bus */
913 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
914 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
915 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
916 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
917 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
918 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
919 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
920 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
921 
922 #define DMAMUX1             ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
923 #define DMAMUX1_Channel0    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
924 #define DMAMUX1_Channel1    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
925 #define DMAMUX1_Channel2    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
926 #define DMAMUX1_Channel3    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
927 #define DMAMUX1_Channel4    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
928 #define DMAMUX1_Channel5    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
929 #define DMAMUX1_Channel6    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
930 
931 #define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
932 #define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
933 #define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
934 #define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
935 
936 #define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
937 #define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
938 
939 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
940 #define TSC                 ((TSC_TypeDef *) TSC_BASE)
941 
942 /* Peripherals available on AHB2 bus */
943 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
944 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
945 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
946 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
947 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
948 
949 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
950 #define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
951 
952 
953 /* Peripherals available on AHB shared bus */
954 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
955 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
956 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
957 #define IPCC                ((IPCC_TypeDef *) IPCC_BASE)
958 #define IPCC_C1             ((IPCC_CommonTypeDef *) IPCC_BASE)
959 #define IPCC_C2             ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U))
960 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
961 #define HSEM                ((HSEM_TypeDef *) HSEM_BASE)
962 #define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U))
963 #define AES2                ((AES_TypeDef *) AES2_BASE)
964 #define PKA                 ((PKA_TypeDef *) PKA_BASE)
965 #define FLASH               ((FLASH_TypeDef *) FLASH_REG_BASE)
966 
967 /* Peripherals available on AHB3 bus */
968 
969 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
970 /**
971   * @}
972   */
973 
974 /** @addtogroup Exported_constants
975   * @{
976   */
977 
978 /** @addtogroup Hardware_Constant_Definition
979   * @{
980   */
981 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
982 
983 /**
984   * @}
985   */
986 
987 
988 /** @addtogroup Peripheral_Registers_Bits_Definition
989   * @{
990   */
991 
992 /******************************************************************************/
993 /*                         Peripheral Registers Bits Definition               */
994 /******************************************************************************/
995 
996 /******************************************************************************/
997 /*                                                                            */
998 /*                      Analog to Digital Converter (ADC)                     */
999 /*                                                                            */
1000 /******************************************************************************/
1001 
1002 #define ADC_SUPPORT_2_5_MSPS /* ADC sampling rate 2.5 Msamples/sec */
1003 
1004 /********************  Bit definition for ADC_ISR register  *******************/
1005 #define ADC_ISR_ADRDY_Pos              (0U)
1006 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
1007 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
1008 #define ADC_ISR_EOSMP_Pos              (1U)
1009 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
1010 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
1011 #define ADC_ISR_EOC_Pos                (2U)
1012 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
1013 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
1014 #define ADC_ISR_EOS_Pos                (3U)
1015 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
1016 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
1017 #define ADC_ISR_OVR_Pos                (4U)
1018 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
1019 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
1020 #define ADC_ISR_AWD1_Pos               (7U)
1021 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
1022 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
1023 #define ADC_ISR_AWD2_Pos               (8U)
1024 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
1025 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
1026 #define ADC_ISR_AWD3_Pos               (9U)
1027 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
1028 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
1029 #define ADC_ISR_EOCAL_Pos              (11U)
1030 #define ADC_ISR_EOCAL_Msk              (0x1UL << ADC_ISR_EOCAL_Pos)            /*!< 0x00000800 */
1031 #define ADC_ISR_EOCAL                  ADC_ISR_EOCAL_Msk                       /*!< ADC end of calibration flag */
1032 #define ADC_ISR_CCRDY_Pos              (13U)
1033 #define ADC_ISR_CCRDY_Msk              (0x1UL << ADC_ISR_CCRDY_Pos)            /*!< 0x00002000 */
1034 #define ADC_ISR_CCRDY                  ADC_ISR_CCRDY_Msk                       /*!< ADC channel configuration ready flag */
1035 
1036 /********************  Bit definition for ADC_IER register  *******************/
1037 #define ADC_IER_ADRDYIE_Pos            (0U)
1038 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
1039 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
1040 #define ADC_IER_EOSMPIE_Pos            (1U)
1041 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
1042 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
1043 #define ADC_IER_EOCIE_Pos              (2U)
1044 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
1045 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
1046 #define ADC_IER_EOSIE_Pos              (3U)
1047 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
1048 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
1049 #define ADC_IER_OVRIE_Pos              (4U)
1050 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
1051 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
1052 #define ADC_IER_AWD1IE_Pos             (7U)
1053 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
1054 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
1055 #define ADC_IER_AWD2IE_Pos             (8U)
1056 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
1057 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
1058 #define ADC_IER_AWD3IE_Pos             (9U)
1059 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
1060 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
1061 #define ADC_IER_EOCALIE_Pos            (11U)
1062 #define ADC_IER_EOCALIE_Msk            (0x1UL << ADC_IER_EOCALIE_Pos)          /*!< 0x00000800 */
1063 #define ADC_IER_EOCALIE                ADC_IER_EOCALIE_Msk                     /*!< ADC end of calibration interrupt */
1064 #define ADC_IER_CCRDYIE_Pos            (13U)
1065 #define ADC_IER_CCRDYIE_Msk            (0x1UL << ADC_IER_CCRDYIE_Pos)          /*!< 0x00002000 */
1066 #define ADC_IER_CCRDYIE                ADC_IER_CCRDYIE_Msk                     /*!< ADC channel configuration ready interrupt */
1067 
1068 /********************  Bit definition for ADC_CR register  ********************/
1069 #define ADC_CR_ADEN_Pos                (0U)
1070 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
1071 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
1072 #define ADC_CR_ADDIS_Pos               (1U)
1073 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
1074 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
1075 #define ADC_CR_ADSTART_Pos             (2U)
1076 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
1077 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
1078 #define ADC_CR_ADSTP_Pos               (4U)
1079 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
1080 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
1081 #define ADC_CR_ADVREGEN_Pos            (28U)
1082 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
1083 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
1084 #define ADC_CR_ADCAL_Pos               (31U)
1085 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
1086 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1087 
1088 /********************  Bit definition for ADC_CFGR1 register  *****************/
1089 #define ADC_CFGR1_DMAEN_Pos            (0U)
1090 #define ADC_CFGR1_DMAEN_Msk            (0x1UL << ADC_CFGR1_DMAEN_Pos)          /*!< 0x00000001 */
1091 #define ADC_CFGR1_DMAEN                ADC_CFGR1_DMAEN_Msk                     /*!< ADC DMA transfer enable */
1092 #define ADC_CFGR1_DMACFG_Pos           (1U)
1093 #define ADC_CFGR1_DMACFG_Msk           (0x1UL << ADC_CFGR1_DMACFG_Pos)         /*!< 0x00000002 */
1094 #define ADC_CFGR1_DMACFG               ADC_CFGR1_DMACFG_Msk                    /*!< ADC DMA transfer configuration */
1095 
1096 #define ADC_CFGR1_SCANDIR_Pos          (2U)
1097 #define ADC_CFGR1_SCANDIR_Msk          (0x1UL << ADC_CFGR1_SCANDIR_Pos)        /*!< 0x00000004 */
1098 #define ADC_CFGR1_SCANDIR              ADC_CFGR1_SCANDIR_Msk                   /*!< ADC group regular sequencer scan direction */
1099 
1100 #define ADC_CFGR1_RES_Pos              (3U)
1101 #define ADC_CFGR1_RES_Msk              (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000018 */
1102 #define ADC_CFGR1_RES                  ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */
1103 #define ADC_CFGR1_RES_0                (0x1UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000008 */
1104 #define ADC_CFGR1_RES_1                (0x2UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000010 */
1105 
1106 #define ADC_CFGR1_ALIGN_Pos            (5U)
1107 #define ADC_CFGR1_ALIGN_Msk            (0x1UL << ADC_CFGR1_ALIGN_Pos)          /*!< 0x00000020 */
1108 #define ADC_CFGR1_ALIGN                ADC_CFGR1_ALIGN_Msk                     /*!< ADC data alignment */
1109 
1110 #define ADC_CFGR1_EXTSEL_Pos           (6U)
1111 #define ADC_CFGR1_EXTSEL_Msk           (0x7UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x000001C0 */
1112 #define ADC_CFGR1_EXTSEL               ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */
1113 #define ADC_CFGR1_EXTSEL_0             (0x1UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000040 */
1114 #define ADC_CFGR1_EXTSEL_1             (0x2UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000080 */
1115 #define ADC_CFGR1_EXTSEL_2             (0x4UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000100 */
1116 
1117 #define ADC_CFGR1_EXTEN_Pos            (10U)
1118 #define ADC_CFGR1_EXTEN_Msk            (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */
1119 #define ADC_CFGR1_EXTEN                ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */
1120 #define ADC_CFGR1_EXTEN_0              (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */
1121 #define ADC_CFGR1_EXTEN_1              (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */
1122 
1123 #define ADC_CFGR1_OVRMOD_Pos           (12U)
1124 #define ADC_CFGR1_OVRMOD_Msk           (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */
1125 #define ADC_CFGR1_OVRMOD               ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */
1126 #define ADC_CFGR1_CONT_Pos             (13U)
1127 #define ADC_CFGR1_CONT_Msk             (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */
1128 #define ADC_CFGR1_CONT                 ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */
1129 #define ADC_CFGR1_WAIT_Pos             (14U)
1130 #define ADC_CFGR1_WAIT_Msk             (0x1UL << ADC_CFGR1_WAIT_Pos)           /*!< 0x00004000 */
1131 #define ADC_CFGR1_WAIT                 ADC_CFGR1_WAIT_Msk                      /*!< ADC low power auto wait */
1132 #define ADC_CFGR1_AUTOFF_Pos           (15U)
1133 #define ADC_CFGR1_AUTOFF_Msk           (0x1UL << ADC_CFGR1_AUTOFF_Pos)         /*!< 0x00008000 */
1134 #define ADC_CFGR1_AUTOFF               ADC_CFGR1_AUTOFF_Msk                    /*!< ADC low power auto power off */
1135 #define ADC_CFGR1_DISCEN_Pos           (16U)
1136 #define ADC_CFGR1_DISCEN_Msk           (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */
1137 #define ADC_CFGR1_DISCEN               ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */
1138 #define ADC_CFGR1_CHSELRMOD_Pos        (21U)
1139 #define ADC_CFGR1_CHSELRMOD_Msk        (0x1UL << ADC_CFGR1_CHSELRMOD_Pos)      /*!< 0x00200000 */
1140 #define ADC_CFGR1_CHSELRMOD            ADC_CFGR1_CHSELRMOD_Msk                 /*!< ADC group regular sequencer mode */
1141 
1142 #define ADC_CFGR1_AWD1SGL_Pos          (22U)
1143 #define ADC_CFGR1_AWD1SGL_Msk          (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */
1144 #define ADC_CFGR1_AWD1SGL              ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1145 #define ADC_CFGR1_AWD1EN_Pos           (23U)
1146 #define ADC_CFGR1_AWD1EN_Msk           (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */
1147 #define ADC_CFGR1_AWD1EN               ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1148 
1149 #define ADC_CFGR1_AWD1CH_Pos           (26U)
1150 #define ADC_CFGR1_AWD1CH_Msk           (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */
1151 #define ADC_CFGR1_AWD1CH               ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */
1152 #define ADC_CFGR1_AWD1CH_0             (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */
1153 #define ADC_CFGR1_AWD1CH_1             (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */
1154 #define ADC_CFGR1_AWD1CH_2             (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */
1155 #define ADC_CFGR1_AWD1CH_3             (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */
1156 #define ADC_CFGR1_AWD1CH_4             (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */
1157 
1158 /* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec across STM32WB series */
1159 #define ADC_CFGR_DMAEN_Pos             ADC_CFGR1_DMAEN_Pos
1160 #define ADC_CFGR_DMAEN_Msk             ADC_CFGR1_DMAEN_Msk
1161 #define ADC_CFGR_DMAEN                 ADC_CFGR1_DMAEN
1162 #define ADC_CFGR_DMACFG_Pos            ADC_CFGR1_DMACFG_Pos
1163 #define ADC_CFGR_DMACFG_Msk            ADC_CFGR1_DMACFG_Msk
1164 #define ADC_CFGR_DMACFG                ADC_CFGR1_DMACFG
1165 
1166 #define ADC_CFGR_SCANDIR_Pos           ADC_CFGR1_SCANDIR_Pos
1167 #define ADC_CFGR_SCANDIR_Msk           ADC_CFGR1_SCANDIR_Msk
1168 #define ADC_CFGR_SCANDIR               ADC_CFGR1_SCANDIR
1169 
1170 #define ADC_CFGR_RES_Pos               ADC_CFGR1_RES_Pos
1171 #define ADC_CFGR_RES_Msk               ADC_CFGR1_RES_Msk
1172 #define ADC_CFGR_RES                   ADC_CFGR1_RES
1173 #define ADC_CFGR_RES_0                 ADC_CFGR1_RES_0
1174 #define ADC_CFGR_RES_1                 ADC_CFGR1_RES_1
1175 
1176 #define ADC_CFGR_ALIGN_Pos             ADC_CFGR1_ALIGN_Pos
1177 #define ADC_CFGR_ALIGN_Msk             ADC_CFGR1_ALIGN_Msk
1178 #define ADC_CFGR_ALIGN                 ADC_CFGR1_ALIGN
1179 
1180 #define ADC_CFGR_EXTSEL_Pos            ADC_CFGR1_EXTSEL_Pos
1181 #define ADC_CFGR_EXTSEL_Msk            ADC_CFGR1_EXTSEL_Msk
1182 #define ADC_CFGR_EXTSEL                ADC_CFGR1_EXTSEL
1183 #define ADC_CFGR_EXTSEL_0              ADC_CFGR1_EXTSEL_0
1184 #define ADC_CFGR_EXTSEL_1              ADC_CFGR1_EXTSEL_1
1185 #define ADC_CFGR_EXTSEL_2              ADC_CFGR1_EXTSEL_2
1186 
1187 #define ADC_CFGR_EXTEN_Pos             ADC_CFGR1_EXTEN_Pos
1188 #define ADC_CFGR_EXTEN_Msk             ADC_CFGR1_EXTEN_Msk
1189 #define ADC_CFGR_EXTEN                 ADC_CFGR1_EXTEN
1190 #define ADC_CFGR_EXTEN_0               ADC_CFGR1_EXTEN_0
1191 #define ADC_CFGR_EXTEN_1               ADC_CFGR1_EXTEN_1
1192 
1193 #define ADC_CFGR_OVRMOD_Pos            ADC_CFGR1_OVRMOD_Pos
1194 #define ADC_CFGR_OVRMOD_Msk            ADC_CFGR1_OVRMOD_Msk
1195 #define ADC_CFGR_OVRMOD                ADC_CFGR1_OVRMOD
1196 #define ADC_CFGR_CONT_Pos              ADC_CFGR1_CONT_Pos
1197 #define ADC_CFGR_CONT_Msk              ADC_CFGR1_CONT_Msk
1198 #define ADC_CFGR_CONT                  ADC_CFGR1_CONT
1199 #define ADC_CFGR_AUTDLY_Pos            ADC_CFGR1_WAIT_Pos
1200 #define ADC_CFGR_AUTDLY_Msk            ADC_CFGR1_WAIT_Msk
1201 #define ADC_CFGR_AUTDLY                ADC_CFGR1_WAIT
1202 #define ADC_CFGR_AUTOFF_Pos            ADC_CFGR1_AUTOFF_Pos
1203 #define ADC_CFGR_AUTOFF_Msk            ADC_CFGR1_AUTOFF_Msk
1204 #define ADC_CFGR_AUTOFF                ADC_CFGR1_AUTOFF
1205 #define ADC_CFGR_DISCEN_Pos            ADC_CFGR1_DISCEN_Pos
1206 #define ADC_CFGR_DISCEN_Msk            ADC_CFGR1_DISCEN_Msk
1207 #define ADC_CFGR_DISCEN                ADC_CFGR1_DISCEN
1208 #define ADC_CFGR_CHSELRMOD_Pos         ADC_CFGR1_CHSELRMOD_Pos
1209 #define ADC_CFGR_CHSELRMOD_Msk         ADC_CFGR1_CHSELRMOD_Msk
1210 #define ADC_CFGR_CHSELRMOD             ADC_CFGR1_CHSELRMOD
1211 
1212 #define ADC_CFGR_AWD1SGL_Pos           ADC_CFGR1_AWD1SGL_Pos
1213 #define ADC_CFGR_AWD1SGL_Msk           ADC_CFGR1_AWD1SGL_Msk
1214 #define ADC_CFGR_AWD1SGL               ADC_CFGR1_AWD1SGL
1215 #define ADC_CFGR_AWD1EN_Pos            ADC_CFGR1_AWD1EN_Pos
1216 #define ADC_CFGR_AWD1EN_Msk            ADC_CFGR1_AWD1EN_Msk
1217 #define ADC_CFGR_AWD1EN                ADC_CFGR1_AWD1EN
1218 
1219 #define ADC_CFGR_AWD1CH_Pos            ADC_CFGR1_AWD1CH_Pos
1220 #define ADC_CFGR_AWD1CH_Msk            ADC_CFGR1_AWD1CH_Msk
1221 #define ADC_CFGR_AWD1CH                ADC_CFGR1_AWD1CH
1222 #define ADC_CFGR_AWD1CH_0              ADC_CFGR1_AWD1CH_0
1223 #define ADC_CFGR_AWD1CH_1              ADC_CFGR1_AWD1CH_1
1224 #define ADC_CFGR_AWD1CH_2              ADC_CFGR1_AWD1CH_2
1225 #define ADC_CFGR_AWD1CH_3              ADC_CFGR1_AWD1CH_3
1226 #define ADC_CFGR_AWD1CH_4              ADC_CFGR1_AWD1CH_4
1227 
1228 /********************  Bit definition for ADC_CFGR2 register  *****************/
1229 #define ADC_CFGR2_LFTRIG_Pos           (29U)
1230 #define ADC_CFGR2_LFTRIG_Msk           (0x1UL << ADC_CFGR2_LFTRIG_Pos)         /*!< 0x20000000 */
1231 #define ADC_CFGR2_LFTRIG               ADC_CFGR2_LFTRIG_Msk                    /*!< ADC low frequency trigger mode */
1232 
1233 #define ADC_CFGR2_CKMODE_Pos           (30U)
1234 #define ADC_CFGR2_CKMODE_Msk           (0x3UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0xC0000000 */
1235 #define ADC_CFGR2_CKMODE               ADC_CFGR2_CKMODE_Msk                    /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
1236 #define ADC_CFGR2_CKMODE_1             (0x2UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x80000000 */
1237 #define ADC_CFGR2_CKMODE_0             (0x1UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x40000000 */
1238 
1239 /********************  Bit definition for ADC_SMPR register  ******************/
1240 #define ADC_SMPR_SMP1_Pos              (0U)
1241 #define ADC_SMPR_SMP1_Msk              (0x7UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000007 */
1242 #define ADC_SMPR_SMP1                  ADC_SMPR_SMP1_Msk                       /*!< ADC group of channels sampling time 1 */
1243 #define ADC_SMPR_SMP1_0                (0x1UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000001 */
1244 #define ADC_SMPR_SMP1_1                (0x2UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000002 */
1245 #define ADC_SMPR_SMP1_2                (0x4UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000004 */
1246 
1247 #define ADC_SMPR_SMP2_Pos              (4U)
1248 #define ADC_SMPR_SMP2_Msk              (0x7UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000070 */
1249 #define ADC_SMPR_SMP2                  ADC_SMPR_SMP2_Msk                       /*!< ADC group of channels sampling time 2 */
1250 #define ADC_SMPR_SMP2_0                (0x1UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000010 */
1251 #define ADC_SMPR_SMP2_1                (0x2UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000020 */
1252 #define ADC_SMPR_SMP2_2                (0x4UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000040 */
1253 
1254 #define ADC_SMPR_SMPSEL_Pos            (8U)
1255 #define ADC_SMPR_SMPSEL_Msk            (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos)      /*!< 0x07FFFF00 */
1256 #define ADC_SMPR_SMPSEL                ADC_SMPR_SMPSEL_Msk                     /*!< ADC all channels sampling time selection */
1257 #define ADC_SMPR_SMPSEL0_Pos           (8U)
1258 #define ADC_SMPR_SMPSEL0_Msk           (0x1UL << ADC_SMPR_SMPSEL0_Pos)         /*!< 0x00000100 */
1259 #define ADC_SMPR_SMPSEL0               ADC_SMPR_SMPSEL0_Msk                    /*!< ADC channel 0 sampling time selection */
1260 #define ADC_SMPR_SMPSEL1_Pos           (9U)
1261 #define ADC_SMPR_SMPSEL1_Msk           (0x1UL << ADC_SMPR_SMPSEL1_Pos)         /*!< 0x00000200 */
1262 #define ADC_SMPR_SMPSEL1               ADC_SMPR_SMPSEL1_Msk                    /*!< ADC channel 1 sampling time selection */
1263 #define ADC_SMPR_SMPSEL2_Pos           (10U)
1264 #define ADC_SMPR_SMPSEL2_Msk           (0x1UL << ADC_SMPR_SMPSEL2_Pos)         /*!< 0x00000400 */
1265 #define ADC_SMPR_SMPSEL2               ADC_SMPR_SMPSEL2_Msk                    /*!< ADC channel 2 sampling time selection */
1266 #define ADC_SMPR_SMPSEL3_Pos           (11U)
1267 #define ADC_SMPR_SMPSEL3_Msk           (0x1UL << ADC_SMPR_SMPSEL3_Pos)         /*!< 0x00000800 */
1268 #define ADC_SMPR_SMPSEL3               ADC_SMPR_SMPSEL3_Msk                    /*!< ADC channel 3 sampling time selection */
1269 #define ADC_SMPR_SMPSEL4_Pos           (12U)
1270 #define ADC_SMPR_SMPSEL4_Msk           (0x1UL << ADC_SMPR_SMPSEL4_Pos)         /*!< 0x00001000 */
1271 #define ADC_SMPR_SMPSEL4               ADC_SMPR_SMPSEL4_Msk                    /*!< ADC channel 4 sampling time selection */
1272 #define ADC_SMPR_SMPSEL5_Pos           (13U)
1273 #define ADC_SMPR_SMPSEL5_Msk           (0x1UL << ADC_SMPR_SMPSEL5_Pos)         /*!< 0x00002000 */
1274 #define ADC_SMPR_SMPSEL5               ADC_SMPR_SMPSEL5_Msk                    /*!< ADC channel 5 sampling time selection */
1275 #define ADC_SMPR_SMPSEL6_Pos           (14U)
1276 #define ADC_SMPR_SMPSEL6_Msk           (0x1UL << ADC_SMPR_SMPSEL6_Pos)         /*!< 0x00004000 */
1277 #define ADC_SMPR_SMPSEL6               ADC_SMPR_SMPSEL6_Msk                    /*!< ADC channel 6 sampling time selection */
1278 #define ADC_SMPR_SMPSEL7_Pos           (15U)
1279 #define ADC_SMPR_SMPSEL7_Msk           (0x1UL << ADC_SMPR_SMPSEL7_Pos)         /*!< 0x00008000 */
1280 #define ADC_SMPR_SMPSEL7               ADC_SMPR_SMPSEL7_Msk                    /*!< ADC channel 7 sampling time selection */
1281 #define ADC_SMPR_SMPSEL8_Pos           (16U)
1282 #define ADC_SMPR_SMPSEL8_Msk           (0x1UL << ADC_SMPR_SMPSEL8_Pos)         /*!< 0x00010000 */
1283 #define ADC_SMPR_SMPSEL8               ADC_SMPR_SMPSEL8_Msk                    /*!< ADC channel 8 sampling time selection */
1284 #define ADC_SMPR_SMPSEL9_Pos           (17U)
1285 #define ADC_SMPR_SMPSEL9_Msk           (0x1UL << ADC_SMPR_SMPSEL9_Pos)         /*!< 0x00020000 */
1286 #define ADC_SMPR_SMPSEL9               ADC_SMPR_SMPSEL9_Msk                    /*!< ADC channel 9 sampling time selection */
1287 #define ADC_SMPR_SMPSEL10_Pos          (18U)
1288 #define ADC_SMPR_SMPSEL10_Msk          (0x1UL << ADC_SMPR_SMPSEL10_Pos)        /*!< 0x00040000 */
1289 #define ADC_SMPR_SMPSEL10              ADC_SMPR_SMPSEL10_Msk                   /*!< ADC channel 10 sampling time selection */
1290 #define ADC_SMPR_SMPSEL11_Pos          (19U)
1291 #define ADC_SMPR_SMPSEL11_Msk          (0x1UL << ADC_SMPR_SMPSEL11_Pos)        /*!< 0x00080000 */
1292 #define ADC_SMPR_SMPSEL11              ADC_SMPR_SMPSEL11_Msk                   /*!< ADC channel 11 sampling time selection */
1293 #define ADC_SMPR_SMPSEL12_Pos          (20U)
1294 #define ADC_SMPR_SMPSEL12_Msk          (0x1UL << ADC_SMPR_SMPSEL12_Pos)        /*!< 0x00100000 */
1295 #define ADC_SMPR_SMPSEL12              ADC_SMPR_SMPSEL12_Msk                   /*!< ADC channel 12 sampling time selection */
1296 #define ADC_SMPR_SMPSEL13_Pos          (21U)
1297 #define ADC_SMPR_SMPSEL13_Msk          (0x1UL << ADC_SMPR_SMPSEL13_Pos)        /*!< 0x00200000 */
1298 #define ADC_SMPR_SMPSEL13              ADC_SMPR_SMPSEL13_Msk                   /*!< ADC channel 13 sampling time selection */
1299 #define ADC_SMPR_SMPSEL14_Pos          (22U)
1300 #define ADC_SMPR_SMPSEL14_Msk          (0x1UL << ADC_SMPR_SMPSEL14_Pos)        /*!< 0x00400000 */
1301 #define ADC_SMPR_SMPSEL14              ADC_SMPR_SMPSEL14_Msk                   /*!< ADC channel 14 sampling time selection */
1302 #define ADC_SMPR_SMPSEL15_Pos          (23U)
1303 #define ADC_SMPR_SMPSEL15_Msk          (0x1UL << ADC_SMPR_SMPSEL15_Pos)        /*!< 0x00800000 */
1304 #define ADC_SMPR_SMPSEL15              ADC_SMPR_SMPSEL15_Msk                   /*!< ADC channel 15 sampling time selection */
1305 #define ADC_SMPR_SMPSEL16_Pos          (24U)
1306 #define ADC_SMPR_SMPSEL16_Msk          (0x1UL << ADC_SMPR_SMPSEL16_Pos)        /*!< 0x01000000 */
1307 #define ADC_SMPR_SMPSEL16              ADC_SMPR_SMPSEL16_Msk                   /*!< ADC channel 16 sampling time selection */
1308 #define ADC_SMPR_SMPSEL17_Pos          (25U)
1309 #define ADC_SMPR_SMPSEL17_Msk          (0x1UL << ADC_SMPR_SMPSEL17_Pos)        /*!< 0x02000000 */
1310 #define ADC_SMPR_SMPSEL17              ADC_SMPR_SMPSEL17_Msk                   /*!< ADC channel 17 sampling time selection */
1311 #define ADC_SMPR_SMPSEL18_Pos          (25U)
1312 #define ADC_SMPR_SMPSEL18_Msk          (0x1UL << ADC_SMPR_SMPSEL18_Pos)        /*!< 0x04000000 */
1313 #define ADC_SMPR_SMPSEL18              ADC_SMPR_SMPSEL18_Msk                   /*!< ADC channel 18 sampling time selection */
1314 
1315 /********************  Bit definition for ADC_TR register  *******************/
1316 #define ADC_TR_LT_Pos             (0U)
1317 #define ADC_TR_LT_Msk             (0xFFFUL << ADC_TR_LT_Pos)         /*!< 0x00000FFF */
1318 #define ADC_TR_LT                 ADC_TR_LT_Msk                      /*!< ADC analog watchdog 1 threshold low */
1319 #define ADC_TR_LT_0               (0x001UL << ADC_TR_LT_Pos)         /*!< 0x00000001 */
1320 #define ADC_TR_LT_1               (0x002UL << ADC_TR_LT_Pos)         /*!< 0x00000002 */
1321 #define ADC_TR_LT_2               (0x004UL << ADC_TR_LT_Pos)         /*!< 0x00000004 */
1322 #define ADC_TR_LT_3               (0x008UL << ADC_TR_LT_Pos)         /*!< 0x00000008 */
1323 #define ADC_TR_LT_4               (0x010UL << ADC_TR_LT_Pos)         /*!< 0x00000010 */
1324 #define ADC_TR_LT_5               (0x020UL << ADC_TR_LT_Pos)         /*!< 0x00000020 */
1325 #define ADC_TR_LT_6               (0x040UL << ADC_TR_LT_Pos)         /*!< 0x00000040 */
1326 #define ADC_TR_LT_7               (0x080UL << ADC_TR_LT_Pos)         /*!< 0x00000080 */
1327 #define ADC_TR_LT_8               (0x100UL << ADC_TR_LT_Pos)         /*!< 0x00000100 */
1328 #define ADC_TR_LT_9               (0x200UL << ADC_TR_LT_Pos)         /*!< 0x00000200 */
1329 #define ADC_TR_LT_10              (0x400UL << ADC_TR_LT_Pos)         /*!< 0x00000400 */
1330 #define ADC_TR_LT_11              (0x800UL << ADC_TR_LT_Pos)         /*!< 0x00000800 */
1331 
1332 #define ADC_TR_HT_Pos             (16U)
1333 #define ADC_TR_HT_Msk             (0xFFFUL << ADC_TR_HT_Pos)         /*!< 0x0FFF0000 */
1334 #define ADC_TR_HT                 ADC_TR_HT_Msk                      /*!< ADC Analog watchdog 1 threshold high */
1335 #define ADC_TR_HT_0               (0x001UL << ADC_TR_HT_Pos)         /*!< 0x00010000 */
1336 #define ADC_TR_HT_1               (0x002UL << ADC_TR_HT_Pos)         /*!< 0x00020000 */
1337 #define ADC_TR_HT_2               (0x004UL << ADC_TR_HT_Pos)         /*!< 0x00040000 */
1338 #define ADC_TR_HT_3               (0x008UL << ADC_TR_HT_Pos)         /*!< 0x00080000 */
1339 #define ADC_TR_HT_4               (0x010UL << ADC_TR_HT_Pos)         /*!< 0x00100000 */
1340 #define ADC_TR_HT_5               (0x020UL << ADC_TR_HT_Pos)         /*!< 0x00200000 */
1341 #define ADC_TR_HT_6               (0x040UL << ADC_TR_HT_Pos)         /*!< 0x00400000 */
1342 #define ADC_TR_HT_7               (0x080UL << ADC_TR_HT_Pos)         /*!< 0x00800000 */
1343 #define ADC_TR_HT_8               (0x100UL << ADC_TR_HT_Pos)         /*!< 0x01000000 */
1344 #define ADC_TR_HT_9               (0x200UL << ADC_TR_HT_Pos)         /*!< 0x02000000 */
1345 #define ADC_TR_HT_10              (0x400UL << ADC_TR_HT_Pos)         /*!< 0x04000000 */
1346 #define ADC_TR_HT_11              (0x800UL << ADC_TR_HT_Pos)         /*!< 0x08000000 */
1347 
1348 /* Legacy definitions */
1349 #define ADC_TR1_LT1             ADC_TR_LT
1350 #define ADC_TR1_LT1_0           ADC_TR_LT_0
1351 #define ADC_TR1_LT1_1           ADC_TR_LT_1
1352 #define ADC_TR1_LT1_2           ADC_TR_LT_2
1353 #define ADC_TR1_LT1_3           ADC_TR_LT_3
1354 #define ADC_TR1_LT1_4           ADC_TR_LT_4
1355 #define ADC_TR1_LT1_5           ADC_TR_LT_5
1356 #define ADC_TR1_LT1_6           ADC_TR_LT_6
1357 #define ADC_TR1_LT1_7           ADC_TR_LT_7
1358 #define ADC_TR1_LT1_8           ADC_TR_LT_8
1359 #define ADC_TR1_LT1_9           ADC_TR_LT_9
1360 #define ADC_TR1_LT1_10          ADC_TR_LT_10
1361 #define ADC_TR1_LT1_11          ADC_TR_LT_11
1362 
1363 #define ADC_TR1_HT1             ADC_TR_HT
1364 #define ADC_TR1_HT1_0           ADC_TR_HT_0
1365 #define ADC_TR1_HT1_1           ADC_TR_HT_1
1366 #define ADC_TR1_HT1_2           ADC_TR_HT_2
1367 #define ADC_TR1_HT1_3           ADC_TR_HT_3
1368 #define ADC_TR1_HT1_4           ADC_TR_HT_4
1369 #define ADC_TR1_HT1_5           ADC_TR_HT_5
1370 #define ADC_TR1_HT1_6           ADC_TR_HT_6
1371 #define ADC_TR1_HT1_7           ADC_TR_HT_7
1372 #define ADC_TR1_HT1_8           ADC_TR_HT_8
1373 #define ADC_TR1_HT1_9           ADC_TR_HT_9
1374 #define ADC_TR1_HT1_10          ADC_TR_HT_10
1375 #define ADC_TR1_HT1_11          ADC_TR_HT_11
1376 
1377 /********************  Bit definition for ADC_CHSELR register  ****************/
1378 #define ADC_CHSELR_CHSEL_Pos           (0U)
1379 #define ADC_CHSELR_CHSEL_Msk           (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)     /*!< 0x0007FFFF */
1380 #define ADC_CHSELR_CHSEL               ADC_CHSELR_CHSEL_Msk                    /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
1381 #define ADC_CHSELR_CHSEL18_Pos         (18U)
1382 #define ADC_CHSELR_CHSEL18_Msk         (0x1UL << ADC_CHSELR_CHSEL18_Pos)       /*!< 0x00040000 */
1383 #define ADC_CHSELR_CHSEL18             ADC_CHSELR_CHSEL18_Msk                  /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
1384 #define ADC_CHSELR_CHSEL17_Pos         (17U)
1385 #define ADC_CHSELR_CHSEL17_Msk         (0x1UL << ADC_CHSELR_CHSEL17_Pos)       /*!< 0x00020000 */
1386 #define ADC_CHSELR_CHSEL17             ADC_CHSELR_CHSEL17_Msk                  /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
1387 #define ADC_CHSELR_CHSEL16_Pos         (16U)
1388 #define ADC_CHSELR_CHSEL16_Msk         (0x1UL << ADC_CHSELR_CHSEL16_Pos)       /*!< 0x00010000 */
1389 #define ADC_CHSELR_CHSEL16             ADC_CHSELR_CHSEL16_Msk                  /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
1390 #define ADC_CHSELR_CHSEL15_Pos         (15U)
1391 #define ADC_CHSELR_CHSEL15_Msk         (0x1UL << ADC_CHSELR_CHSEL15_Pos)       /*!< 0x00008000 */
1392 #define ADC_CHSELR_CHSEL15             ADC_CHSELR_CHSEL15_Msk                  /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
1393 #define ADC_CHSELR_CHSEL14_Pos         (14U)
1394 #define ADC_CHSELR_CHSEL14_Msk         (0x1UL << ADC_CHSELR_CHSEL14_Pos)       /*!< 0x00004000 */
1395 #define ADC_CHSELR_CHSEL14             ADC_CHSELR_CHSEL14_Msk                  /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
1396 #define ADC_CHSELR_CHSEL13_Pos         (13U)
1397 #define ADC_CHSELR_CHSEL13_Msk         (0x1UL << ADC_CHSELR_CHSEL13_Pos)       /*!< 0x00002000 */
1398 #define ADC_CHSELR_CHSEL13             ADC_CHSELR_CHSEL13_Msk                  /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
1399 #define ADC_CHSELR_CHSEL12_Pos         (12U)
1400 #define ADC_CHSELR_CHSEL12_Msk         (0x1UL << ADC_CHSELR_CHSEL12_Pos)       /*!< 0x00001000 */
1401 #define ADC_CHSELR_CHSEL12             ADC_CHSELR_CHSEL12_Msk                  /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
1402 #define ADC_CHSELR_CHSEL11_Pos         (11U)
1403 #define ADC_CHSELR_CHSEL11_Msk         (0x1UL << ADC_CHSELR_CHSEL11_Pos)       /*!< 0x00000800 */
1404 #define ADC_CHSELR_CHSEL11             ADC_CHSELR_CHSEL11_Msk                  /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
1405 #define ADC_CHSELR_CHSEL10_Pos         (10U)
1406 #define ADC_CHSELR_CHSEL10_Msk         (0x1UL << ADC_CHSELR_CHSEL10_Pos)       /*!< 0x00000400 */
1407 #define ADC_CHSELR_CHSEL10             ADC_CHSELR_CHSEL10_Msk                  /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
1408 #define ADC_CHSELR_CHSEL9_Pos          (9U)
1409 #define ADC_CHSELR_CHSEL9_Msk          (0x1UL << ADC_CHSELR_CHSEL9_Pos)        /*!< 0x00000200 */
1410 #define ADC_CHSELR_CHSEL9              ADC_CHSELR_CHSEL9_Msk                   /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
1411 #define ADC_CHSELR_CHSEL8_Pos          (8U)
1412 #define ADC_CHSELR_CHSEL8_Msk          (0x1UL << ADC_CHSELR_CHSEL8_Pos)        /*!< 0x00000100 */
1413 #define ADC_CHSELR_CHSEL8              ADC_CHSELR_CHSEL8_Msk                   /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
1414 #define ADC_CHSELR_CHSEL7_Pos          (7U)
1415 #define ADC_CHSELR_CHSEL7_Msk          (0x1UL << ADC_CHSELR_CHSEL7_Pos)        /*!< 0x00000080 */
1416 #define ADC_CHSELR_CHSEL7              ADC_CHSELR_CHSEL7_Msk                   /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
1417 #define ADC_CHSELR_CHSEL6_Pos          (6U)
1418 #define ADC_CHSELR_CHSEL6_Msk          (0x1UL << ADC_CHSELR_CHSEL6_Pos)        /*!< 0x00000040 */
1419 #define ADC_CHSELR_CHSEL6              ADC_CHSELR_CHSEL6_Msk                   /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
1420 #define ADC_CHSELR_CHSEL5_Pos          (5U)
1421 #define ADC_CHSELR_CHSEL5_Msk          (0x1UL << ADC_CHSELR_CHSEL5_Pos)        /*!< 0x00000020 */
1422 #define ADC_CHSELR_CHSEL5              ADC_CHSELR_CHSEL5_Msk                   /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
1423 #define ADC_CHSELR_CHSEL4_Pos          (4U)
1424 #define ADC_CHSELR_CHSEL4_Msk          (0x1UL << ADC_CHSELR_CHSEL4_Pos)        /*!< 0x00000010 */
1425 #define ADC_CHSELR_CHSEL4              ADC_CHSELR_CHSEL4_Msk                   /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
1426 #define ADC_CHSELR_CHSEL3_Pos          (3U)
1427 #define ADC_CHSELR_CHSEL3_Msk          (0x1UL << ADC_CHSELR_CHSEL3_Pos)        /*!< 0x00000008 */
1428 #define ADC_CHSELR_CHSEL3              ADC_CHSELR_CHSEL3_Msk                   /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
1429 #define ADC_CHSELR_CHSEL2_Pos          (2U)
1430 #define ADC_CHSELR_CHSEL2_Msk          (0x1UL << ADC_CHSELR_CHSEL2_Pos)        /*!< 0x00000004 */
1431 #define ADC_CHSELR_CHSEL2              ADC_CHSELR_CHSEL2_Msk                   /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
1432 #define ADC_CHSELR_CHSEL1_Pos          (1U)
1433 #define ADC_CHSELR_CHSEL1_Msk          (0x1UL << ADC_CHSELR_CHSEL1_Pos)        /*!< 0x00000002 */
1434 #define ADC_CHSELR_CHSEL1              ADC_CHSELR_CHSEL1_Msk                   /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
1435 #define ADC_CHSELR_CHSEL0_Pos          (0U)
1436 #define ADC_CHSELR_CHSEL0_Msk          (0x1UL << ADC_CHSELR_CHSEL0_Pos)        /*!< 0x00000001 */
1437 #define ADC_CHSELR_CHSEL0              ADC_CHSELR_CHSEL0_Msk                   /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
1438 
1439 #define ADC_CHSELR_SQ_ALL_Pos          (0U)
1440 #define ADC_CHSELR_SQ_ALL_Msk          (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
1441 #define ADC_CHSELR_SQ_ALL              ADC_CHSELR_SQ_ALL_Msk                   /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
1442 
1443 #define ADC_CHSELR_SQ8_Pos             (28U)
1444 #define ADC_CHSELR_SQ8_Msk             (0xFUL << ADC_CHSELR_SQ8_Pos)           /*!< 0xF0000000 */
1445 #define ADC_CHSELR_SQ8                 ADC_CHSELR_SQ8_Msk                      /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
1446 #define ADC_CHSELR_SQ8_0               (0x1UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x10000000 */
1447 #define ADC_CHSELR_SQ8_1               (0x2UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x20000000 */
1448 #define ADC_CHSELR_SQ8_2               (0x4UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x40000000 */
1449 #define ADC_CHSELR_SQ8_3               (0x8UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x80000000 */
1450 
1451 #define ADC_CHSELR_SQ7_Pos             (24U)
1452 #define ADC_CHSELR_SQ7_Msk             (0xFUL << ADC_CHSELR_SQ7_Pos)           /*!< 0x0F000000 */
1453 #define ADC_CHSELR_SQ7                 ADC_CHSELR_SQ7_Msk                      /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
1454 #define ADC_CHSELR_SQ7_0               (0x1UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x01000000 */
1455 #define ADC_CHSELR_SQ7_1               (0x2UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x02000000 */
1456 #define ADC_CHSELR_SQ7_2               (0x4UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x04000000 */
1457 #define ADC_CHSELR_SQ7_3               (0x8UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x08000000 */
1458 
1459 #define ADC_CHSELR_SQ6_Pos             (20U)
1460 #define ADC_CHSELR_SQ6_Msk             (0xFUL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00F00000 */
1461 #define ADC_CHSELR_SQ6                 ADC_CHSELR_SQ6_Msk                      /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
1462 #define ADC_CHSELR_SQ6_0               (0x1UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00100000 */
1463 #define ADC_CHSELR_SQ6_1               (0x2UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00200000 */
1464 #define ADC_CHSELR_SQ6_2               (0x4UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00400000 */
1465 #define ADC_CHSELR_SQ6_3               (0x8UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00800000 */
1466 
1467 #define ADC_CHSELR_SQ5_Pos             (16U)
1468 #define ADC_CHSELR_SQ5_Msk             (0xFUL << ADC_CHSELR_SQ5_Pos)           /*!< 0x000F0000 */
1469 #define ADC_CHSELR_SQ5                 ADC_CHSELR_SQ5_Msk                      /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
1470 #define ADC_CHSELR_SQ5_0               (0x1UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00010000 */
1471 #define ADC_CHSELR_SQ5_1               (0x2UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00020000 */
1472 #define ADC_CHSELR_SQ5_2               (0x4UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00040000 */
1473 #define ADC_CHSELR_SQ5_3               (0x8UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00080000 */
1474 
1475 #define ADC_CHSELR_SQ4_Pos             (12U)
1476 #define ADC_CHSELR_SQ4_Msk             (0xFUL << ADC_CHSELR_SQ4_Pos)           /*!< 0x0000F000 */
1477 #define ADC_CHSELR_SQ4                 ADC_CHSELR_SQ4_Msk                      /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
1478 #define ADC_CHSELR_SQ4_0               (0x1UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00001000 */
1479 #define ADC_CHSELR_SQ4_1               (0x2UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00002000 */
1480 #define ADC_CHSELR_SQ4_2               (0x4UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00004000 */
1481 #define ADC_CHSELR_SQ4_3               (0x8UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00008000 */
1482 
1483 #define ADC_CHSELR_SQ3_Pos             (8U)
1484 #define ADC_CHSELR_SQ3_Msk             (0xFUL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000F00 */
1485 #define ADC_CHSELR_SQ3                 ADC_CHSELR_SQ3_Msk                      /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
1486 #define ADC_CHSELR_SQ3_0               (0x1UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000100 */
1487 #define ADC_CHSELR_SQ3_1               (0x2UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000200 */
1488 #define ADC_CHSELR_SQ3_2               (0x4UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000400 */
1489 #define ADC_CHSELR_SQ3_3               (0x8UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000800 */
1490 
1491 #define ADC_CHSELR_SQ2_Pos             (4U)
1492 #define ADC_CHSELR_SQ2_Msk             (0xFUL << ADC_CHSELR_SQ2_Pos)           /*!< 0x000000F0 */
1493 #define ADC_CHSELR_SQ2                 ADC_CHSELR_SQ2_Msk                      /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
1494 #define ADC_CHSELR_SQ2_0               (0x1UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000010 */
1495 #define ADC_CHSELR_SQ2_1               (0x2UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000020 */
1496 #define ADC_CHSELR_SQ2_2               (0x4UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000040 */
1497 #define ADC_CHSELR_SQ2_3               (0x8UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000080 */
1498 
1499 #define ADC_CHSELR_SQ1_Pos             (0U)
1500 #define ADC_CHSELR_SQ1_Msk             (0xFUL << ADC_CHSELR_SQ1_Pos)           /*!< 0x0000000F */
1501 #define ADC_CHSELR_SQ1                 ADC_CHSELR_SQ1_Msk                      /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
1502 #define ADC_CHSELR_SQ1_0               (0x1UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000001 */
1503 #define ADC_CHSELR_SQ1_1               (0x2UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000002 */
1504 #define ADC_CHSELR_SQ1_2               (0x4UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000004 */
1505 #define ADC_CHSELR_SQ1_3               (0x8UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000008 */
1506 
1507 /********************  Bit definition for ADC_DR register  ********************/
1508 #define ADC_DR_DATA_Pos                (0U)
1509 #define ADC_DR_DATA_Msk                (0xFFFFUL << ADC_DR_DATA_Pos)           /*!< 0x0000FFFF */
1510 #define ADC_DR_DATA                    ADC_DR_DATA_Msk                         /*!< ADC group regular conversion data */
1511 #define ADC_DR_DATA_0                  (0x0001UL << ADC_DR_DATA_Pos)           /*!< 0x00000001 */
1512 #define ADC_DR_DATA_1                  (0x0002UL << ADC_DR_DATA_Pos)           /*!< 0x00000002 */
1513 #define ADC_DR_DATA_2                  (0x0004UL << ADC_DR_DATA_Pos)           /*!< 0x00000004 */
1514 #define ADC_DR_DATA_3                  (0x0008UL << ADC_DR_DATA_Pos)           /*!< 0x00000008 */
1515 #define ADC_DR_DATA_4                  (0x0010UL << ADC_DR_DATA_Pos)           /*!< 0x00000010 */
1516 #define ADC_DR_DATA_5                  (0x0020UL << ADC_DR_DATA_Pos)           /*!< 0x00000020 */
1517 #define ADC_DR_DATA_6                  (0x0040UL << ADC_DR_DATA_Pos)           /*!< 0x00000040 */
1518 #define ADC_DR_DATA_7                  (0x0080UL << ADC_DR_DATA_Pos)           /*!< 0x00000080 */
1519 #define ADC_DR_DATA_8                  (0x0100UL << ADC_DR_DATA_Pos)           /*!< 0x00000100 */
1520 #define ADC_DR_DATA_9                  (0x0200UL << ADC_DR_DATA_Pos)           /*!< 0x00000200 */
1521 #define ADC_DR_DATA_10                 (0x0400UL << ADC_DR_DATA_Pos)           /*!< 0x00000400 */
1522 #define ADC_DR_DATA_11                 (0x0800UL << ADC_DR_DATA_Pos)           /*!< 0x00000800 */
1523 #define ADC_DR_DATA_12                 (0x1000UL << ADC_DR_DATA_Pos)           /*!< 0x00001000 */
1524 #define ADC_DR_DATA_13                 (0x2000UL << ADC_DR_DATA_Pos)           /*!< 0x00002000 */
1525 #define ADC_DR_DATA_14                 (0x4000UL << ADC_DR_DATA_Pos)           /*!< 0x00004000 */
1526 #define ADC_DR_DATA_15                 (0x8000UL << ADC_DR_DATA_Pos)           /*!< 0x00008000 */
1527 
1528 /* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec across STM32WB series */
1529 #define ADC_DR_RDATA_Pos               ADC_DR_DATA_Pos
1530 #define ADC_DR_RDATA_Msk               ADC_DR_DATA_Msk
1531 #define ADC_DR_RDATA                   ADC_DR_DATA
1532 
1533 /********************  Bit definition for ADC_CALFACT register  ***************/
1534 #define ADC_CALFACT_CALFACT_Pos        (0U)
1535 #define ADC_CALFACT_CALFACT_Msk        (0x7FUL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x0000007F */
1536 #define ADC_CALFACT_CALFACT            ADC_CALFACT_CALFACT_Msk                 /*!< ADC calibration factor in single-ended mode */
1537 #define ADC_CALFACT_CALFACT_0          (0x01UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000001 */
1538 #define ADC_CALFACT_CALFACT_1          (0x02UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000002 */
1539 #define ADC_CALFACT_CALFACT_2          (0x04UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000004 */
1540 #define ADC_CALFACT_CALFACT_3          (0x08UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000008 */
1541 #define ADC_CALFACT_CALFACT_4          (0x10UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000010 */
1542 #define ADC_CALFACT_CALFACT_5          (0x20UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000020 */
1543 #define ADC_CALFACT_CALFACT_6          (0x40UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000040 */
1544 
1545 /*************************  ADC Common registers  *****************************/
1546 /********************  Bit definition for ADC_CCR register  *******************/
1547 #define ADC_CCR_PRESC_Pos              (18U)
1548 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
1549 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
1550 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
1551 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
1552 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
1553 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
1554 
1555 #define ADC_CCR_VREFEN_Pos             (22U)
1556 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
1557 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
1558 #define ADC_CCR_TSEN_Pos               (23U)
1559 #define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
1560 #define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
1561 #define ADC_CCR_VBATEN_Pos             (24U)
1562 #define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
1563 #define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
1564 
1565 /******************************************************************************/
1566 /*                                                                            */
1567 /*                      Analog Comparators (COMP)                             */
1568 /*                                                                            */
1569 /******************************************************************************/
1570 /**********************  Bit definition for COMP_CSR register  ***************/
1571 #define COMP_CSR_EN_Pos            (0U)
1572 #define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
1573 #define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
1574 #define COMP_CSR_PWRMODE_Pos       (2U)
1575 #define COMP_CSR_PWRMODE_Msk       (0x3UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x0000000C */
1576 #define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
1577 #define COMP_CSR_PWRMODE_0         (0x1UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000004 */
1578 #define COMP_CSR_PWRMODE_1         (0x2UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000008 */
1579 #define COMP_CSR_INMSEL_Pos        (4U)
1580 #define COMP_CSR_INMSEL_Msk        (0x7UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */
1581 #define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
1582 #define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */
1583 #define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */
1584 #define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */
1585 #define COMP_CSR_INPSEL_Pos        (7U)
1586 #define COMP_CSR_INPSEL_Msk        (0x3UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000180 */
1587 #define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
1588 #define COMP_CSR_INPSEL_0          (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000080 */
1589 #define COMP_CSR_INPSEL_1          (0x2UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
1590 #define COMP_CSR_POLARITY_Pos      (15U)
1591 #define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
1592 #define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
1593 #define COMP_CSR_HYST_Pos          (16U)
1594 #define COMP_CSR_HYST_Msk          (0x3UL << COMP_CSR_HYST_Pos)                /*!< 0x00030000 */
1595 #define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
1596 #define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
1597 #define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */
1598 #define COMP_CSR_BLANKING_Pos      (18U)
1599 #define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x001C0000 */
1600 #define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
1601 #define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00040000 */
1602 #define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */
1603 #define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */
1604 #define COMP_CSR_BRGEN_Pos         (22U)
1605 #define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */
1606 #define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */
1607 #define COMP_CSR_SCALEN_Pos        (23U)
1608 #define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */
1609 #define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */
1610 #define COMP_CSR_INMESEL_Pos       (25U)
1611 #define COMP_CSR_INMESEL_Msk       (0x3UL << COMP_CSR_INMESEL_Pos)             /*!< 0x06000000 */
1612 #define COMP_CSR_INMESEL           COMP_CSR_INMESEL_Msk                        /*!< Comparator input minus extended selection */
1613 #define COMP_CSR_INMESEL_0         (0x1UL << COMP_CSR_INMESEL_Pos)             /*!< 0x02000000 */
1614 #define COMP_CSR_INMESEL_1         (0x2UL << COMP_CSR_INMESEL_Pos)             /*!< 0x04000000 */
1615 #define COMP_CSR_VALUE_Pos         (30U)
1616 #define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */
1617 #define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
1618 #define COMP_CSR_LOCK_Pos          (31U)
1619 #define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */
1620 #define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
1621 
1622 /******************************************************************************/
1623 /*                                                                            */
1624 /*                          CRC calculation unit                              */
1625 /*                                                                            */
1626 /******************************************************************************/
1627 /*******************  Bit definition for CRC_DR register  *********************/
1628 #define CRC_DR_DR_Pos            (0U)
1629 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
1630 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
1631 
1632 /*******************  Bit definition for CRC_IDR register  ********************/
1633 #define CRC_IDR_IDR_Pos          (0U)
1634 #define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)                   /*!< 0x000000FF */
1635 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bits data register bits */
1636 
1637 /********************  Bit definition for CRC_CR register  ********************/
1638 #define CRC_CR_RESET_Pos         (0U)
1639 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
1640 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
1641 #define CRC_CR_POLYSIZE_Pos      (3U)
1642 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
1643 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
1644 #define CRC_CR_POLYSIZE_0        (0x1U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
1645 #define CRC_CR_POLYSIZE_1        (0x2U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
1646 #define CRC_CR_REV_IN_Pos        (5U)
1647 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
1648 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
1649 #define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
1650 #define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
1651 #define CRC_CR_REV_OUT_Pos       (7U)
1652 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
1653 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
1654 
1655 /*******************  Bit definition for CRC_INIT register  *******************/
1656 #define CRC_INIT_INIT_Pos        (0U)
1657 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
1658 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
1659 
1660 /*******************  Bit definition for CRC_POL register  ********************/
1661 #define CRC_POL_POL_Pos          (0U)
1662 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
1663 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
1664 
1665 /******************************************************************************/
1666 /*                                                                            */
1667 /*                       Advanced Encryption Standard (AES)                   */
1668 /*                                                                            */
1669 /******************************************************************************/
1670 /*******************  Bit definition for AES_CR register  *********************/
1671 #define AES_CR_EN_Pos            (0U)
1672 #define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                      /*!< 0x00000001 */
1673 #define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
1674 #define AES_CR_DATATYPE_Pos      (1U)
1675 #define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000006 */
1676 #define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
1677 #define AES_CR_DATATYPE_0        (0x1U << AES_CR_DATATYPE_Pos)                 /*!< 0x00000002 */
1678 #define AES_CR_DATATYPE_1        (0x2U << AES_CR_DATATYPE_Pos)                 /*!< 0x00000004 */
1679 
1680 #define AES_CR_MODE_Pos          (3U)
1681 #define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                    /*!< 0x00000018 */
1682 #define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
1683 #define AES_CR_MODE_0            (0x1U << AES_CR_MODE_Pos)                     /*!< 0x00000008 */
1684 #define AES_CR_MODE_1            (0x2U << AES_CR_MODE_Pos)                     /*!< 0x00000010 */
1685 
1686 #define AES_CR_CHMOD_Pos         (5U)
1687 #define AES_CR_CHMOD_Msk         (0x803UL << AES_CR_CHMOD_Pos)                 /*!< 0x00010060 */
1688 #define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
1689 #define AES_CR_CHMOD_0           (0x001U << AES_CR_CHMOD_Pos)                  /*!< 0x00000020 */
1690 #define AES_CR_CHMOD_1           (0x002U << AES_CR_CHMOD_Pos)                  /*!< 0x00000040 */
1691 #define AES_CR_CHMOD_2           (0x800U << AES_CR_CHMOD_Pos)                  /*!< 0x00010000 */
1692 
1693 #define AES_CR_CCFC_Pos          (7U)
1694 #define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                    /*!< 0x00000080 */
1695 #define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
1696 #define AES_CR_ERRC_Pos          (8U)
1697 #define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                    /*!< 0x00000100 */
1698 #define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
1699 #define AES_CR_CCFIE_Pos         (9U)
1700 #define AES_CR_CCFIE_Msk         (0x1UL << AES_CR_CCFIE_Pos)                   /*!< 0x00000200 */
1701 #define AES_CR_CCFIE             AES_CR_CCFIE_Msk                              /*!< Computation Complete Flag Interrupt Enable */
1702 #define AES_CR_ERRIE_Pos         (10U)
1703 #define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                   /*!< 0x00000400 */
1704 #define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
1705 #define AES_CR_DMAINEN_Pos       (11U)
1706 #define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                 /*!< 0x00000800 */
1707 #define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< Enable data input phase DMA management  */
1708 #define AES_CR_DMAOUTEN_Pos      (12U)
1709 #define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                /*!< 0x00001000 */
1710 #define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< Enable data output phase DMA management */
1711 
1712 #define AES_CR_GCMPH_Pos         (13U)
1713 #define AES_CR_GCMPH_Msk         (0x3UL << AES_CR_GCMPH_Pos)                   /*!< 0x00006000 */
1714 #define AES_CR_GCMPH             AES_CR_GCMPH_Msk                              /*!< GCM Phase */
1715 #define AES_CR_GCMPH_0           (0x1U << AES_CR_GCMPH_Pos)                    /*!< 0x00002000 */
1716 #define AES_CR_GCMPH_1           (0x2U << AES_CR_GCMPH_Pos)                    /*!< 0x00004000 */
1717 
1718 #define AES_CR_KEYSIZE_Pos       (18U)
1719 #define AES_CR_KEYSIZE_Msk       (0x1UL << AES_CR_KEYSIZE_Pos)                 /*!< 0x00040000 */
1720 #define AES_CR_KEYSIZE           AES_CR_KEYSIZE_Msk                            /*!< Key size selection */
1721 
1722 #define AES_CR_NPBLB_Pos         (20U)
1723 #define AES_CR_NPBLB_Msk         (0xFUL << AES_CR_NPBLB_Pos)                   /*!< 0x00F00000 */
1724 #define AES_CR_NPBLB             AES_CR_NPBLB_Msk                              /*!< Number of padding bytes in last payload block */
1725 #define AES_CR_NPBLB_0           (0x1U << AES_CR_NPBLB_Pos)                    /*!< 0x00100000 */
1726 #define AES_CR_NPBLB_1           (0x2U << AES_CR_NPBLB_Pos)                    /*!< 0x00200000 */
1727 #define AES_CR_NPBLB_2           (0x4U << AES_CR_NPBLB_Pos)                    /*!< 0x00400000 */
1728 #define AES_CR_NPBLB_3           (0x8U << AES_CR_NPBLB_Pos)                    /*!< 0x00800000 */
1729 
1730 /*******************  Bit definition for AES_SR register  *********************/
1731 #define AES_SR_CCF_Pos           (0U)
1732 #define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                     /*!< 0x00000001 */
1733 #define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
1734 #define AES_SR_RDERR_Pos         (1U)
1735 #define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                   /*!< 0x00000002 */
1736 #define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
1737 #define AES_SR_WRERR_Pos         (2U)
1738 #define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                   /*!< 0x00000004 */
1739 #define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
1740 #define AES_SR_BUSY_Pos          (3U)
1741 #define AES_SR_BUSY_Msk          (0x1UL << AES_SR_BUSY_Pos)                    /*!< 0x00000008 */
1742 #define AES_SR_BUSY              AES_SR_BUSY_Msk                               /*!< Busy Flag */
1743 
1744 /*******************  Bit definition for AES_DINR register  *******************/
1745 #define AES_DINR_Pos             (0U)
1746 #define AES_DINR_Msk             (0xFFFFFFFFUL << AES_DINR_Pos)                /*!< 0xFFFFFFFF */
1747 #define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
1748 
1749 /*******************  Bit definition for AES_DOUTR register  ******************/
1750 #define AES_DOUTR_Pos            (0U)
1751 #define AES_DOUTR_Msk            (0xFFFFFFFFUL << AES_DOUTR_Pos)               /*!< 0xFFFFFFFF */
1752 #define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
1753 
1754 /*******************  Bit definition for AES_KEYR0 register  ******************/
1755 #define AES_KEYR0_Pos            (0U)
1756 #define AES_KEYR0_Msk            (0xFFFFFFFFUL << AES_KEYR0_Pos)               /*!< 0xFFFFFFFF */
1757 #define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
1758 
1759 /*******************  Bit definition for AES_KEYR1 register  ******************/
1760 #define AES_KEYR1_Pos            (0U)
1761 #define AES_KEYR1_Msk            (0xFFFFFFFFUL << AES_KEYR1_Pos)               /*!< 0xFFFFFFFF */
1762 #define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
1763 
1764 /*******************  Bit definition for AES_KEYR2 register  ******************/
1765 #define AES_KEYR2_Pos            (0U)
1766 #define AES_KEYR2_Msk            (0xFFFFFFFFUL << AES_KEYR2_Pos)               /*!< 0xFFFFFFFF */
1767 #define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
1768 
1769 /*******************  Bit definition for AES_KEYR3 register  ******************/
1770 #define AES_KEYR3_Pos            (0U)
1771 #define AES_KEYR3_Msk            (0xFFFFFFFFUL << AES_KEYR3_Pos)               /*!< 0xFFFFFFFF */
1772 #define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
1773 
1774 /*******************  Bit definition for AES_KEYR4 register  ******************/
1775 #define AES_KEYR4_Pos            (0U)
1776 #define AES_KEYR4_Msk            (0xFFFFFFFFUL << AES_KEYR4_Pos)               /*!< 0xFFFFFFFF */
1777 #define AES_KEYR4                AES_KEYR4_Msk                                 /*!< AES Key Register 4 */
1778 
1779 /*******************  Bit definition for AES_KEYR5 register  ******************/
1780 #define AES_KEYR5_Pos            (0U)
1781 #define AES_KEYR5_Msk            (0xFFFFFFFFUL << AES_KEYR5_Pos)               /*!< 0xFFFFFFFF */
1782 #define AES_KEYR5                AES_KEYR5_Msk                                 /*!< AES Key Register 5 */
1783 
1784 /*******************  Bit definition for AES_KEYR6 register  ******************/
1785 #define AES_KEYR6_Pos            (0U)
1786 #define AES_KEYR6_Msk            (0xFFFFFFFFUL << AES_KEYR6_Pos)               /*!< 0xFFFFFFFF */
1787 #define AES_KEYR6                AES_KEYR6_Msk                                 /*!< AES Key Register 6 */
1788 
1789 /*******************  Bit definition for AES_KEYR7 register  ******************/
1790 #define AES_KEYR7_Pos            (0U)
1791 #define AES_KEYR7_Msk            (0xFFFFFFFFUL << AES_KEYR7_Pos)               /*!< 0xFFFFFFFF */
1792 #define AES_KEYR7                AES_KEYR7_Msk                                 /*!< AES Key Register 7 */
1793 
1794 /*******************  Bit definition for AES_IVR0 register   ******************/
1795 #define AES_IVR0_Pos             (0U)
1796 #define AES_IVR0_Msk             (0xFFFFFFFFUL << AES_IVR0_Pos)                /*!< 0xFFFFFFFF */
1797 #define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
1798 
1799 /*******************  Bit definition for AES_IVR1 register   ******************/
1800 #define AES_IVR1_Pos             (0U)
1801 #define AES_IVR1_Msk             (0xFFFFFFFFUL << AES_IVR1_Pos)                /*!< 0xFFFFFFFF */
1802 #define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
1803 
1804 /*******************  Bit definition for AES_IVR2 register   ******************/
1805 #define AES_IVR2_Pos             (0U)
1806 #define AES_IVR2_Msk             (0xFFFFFFFFUL << AES_IVR2_Pos)                /*!< 0xFFFFFFFF */
1807 #define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
1808 
1809 /*******************  Bit definition for AES_IVR3 register   ******************/
1810 #define AES_IVR3_Pos             (0U)
1811 #define AES_IVR3_Msk             (0xFFFFFFFFUL << AES_IVR3_Pos)                /*!< 0xFFFFFFFF */
1812 #define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
1813 
1814 /*******************  Bit definition for AES_SUSP0R register  ******************/
1815 #define AES_SUSP0R_Pos           (0U)
1816 #define AES_SUSP0R_Msk           (0xFFFFFFFFUL << AES_SUSP0R_Pos)              /*!< 0xFFFFFFFF */
1817 #define AES_SUSP0R               AES_SUSP0R_Msk                                /*!< AES Suspend registers 0 */
1818 
1819 /*******************  Bit definition for AES_SUSP1R register  ******************/
1820 #define AES_SUSP1R_Pos           (0U)
1821 #define AES_SUSP1R_Msk           (0xFFFFFFFFUL << AES_SUSP1R_Pos)              /*!< 0xFFFFFFFF */
1822 #define AES_SUSP1R               AES_SUSP1R_Msk                                /*!< AES Suspend registers 1 */
1823 
1824 /*******************  Bit definition for AES_SUSP2R register  ******************/
1825 #define AES_SUSP2R_Pos           (0U)
1826 #define AES_SUSP2R_Msk           (0xFFFFFFFFUL << AES_SUSP2R_Pos)              /*!< 0xFFFFFFFF */
1827 #define AES_SUSP2R               AES_SUSP2R_Msk                                /*!< AES Suspend registers 2 */
1828 
1829 /*******************  Bit definition for AES_SUSP3R register  ******************/
1830 #define AES_SUSP3R_Pos           (0U)
1831 #define AES_SUSP3R_Msk           (0xFFFFFFFFUL << AES_SUSP3R_Pos)              /*!< 0xFFFFFFFF */
1832 #define AES_SUSP3R               AES_SUSP3R_Msk                                /*!< AES Suspend registers 3 */
1833 
1834 /*******************  Bit definition for AES_SUSP4R register  ******************/
1835 #define AES_SUSP4R_Pos           (0U)
1836 #define AES_SUSP4R_Msk           (0xFFFFFFFFUL << AES_SUSP4R_Pos)              /*!< 0xFFFFFFFF */
1837 #define AES_SUSP4R               AES_SUSP4R_Msk                                /*!< AES Suspend registers 4 */
1838 
1839 /*******************  Bit definition for AES_SUSP5R register  ******************/
1840 #define AES_SUSP5R_Pos           (0U)
1841 #define AES_SUSP5R_Msk           (0xFFFFFFFFUL << AES_SUSP5R_Pos)              /*!< 0xFFFFFFFF */
1842 #define AES_SUSP5R               AES_SUSP5R_Msk                                /*!< AES Suspend registers 5 */
1843 
1844 /*******************  Bit definition for AES_SUSP6R register  ******************/
1845 #define AES_SUSP6R_Pos           (0U)
1846 #define AES_SUSP6R_Msk           (0xFFFFFFFFUL << AES_SUSP6R_Pos)              /*!< 0xFFFFFFFF */
1847 #define AES_SUSP6R               AES_SUSP6R_Msk                                /*!< AES Suspend registers 6 */
1848 
1849 /*******************  Bit definition for AES_SUSP7R register  ******************/
1850 #define AES_SUSP7R_Pos           (0U)
1851 #define AES_SUSP7R_Msk           (0xFFFFFFFFUL << AES_SUSP7R_Pos)              /*!< 0xFFFFFFFF */
1852 #define AES_SUSP7R               AES_SUSP7R_Msk                                /*!< AES Suspend registers 7 */
1853 
1854 /******************************************************************************/
1855 /*                                                                            */
1856 /*                           DMA Controller (DMA)                             */
1857 /*                                                                            */
1858 /******************************************************************************/
1859 
1860 /*******************  Bit definition for DMA_ISR register  ********************/
1861 #define DMA_ISR_GIF1_Pos       (0U)
1862 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
1863 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
1864 #define DMA_ISR_TCIF1_Pos      (1U)
1865 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
1866 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
1867 #define DMA_ISR_HTIF1_Pos      (2U)
1868 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
1869 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
1870 #define DMA_ISR_TEIF1_Pos      (3U)
1871 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
1872 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
1873 #define DMA_ISR_GIF2_Pos       (4U)
1874 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
1875 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
1876 #define DMA_ISR_TCIF2_Pos      (5U)
1877 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
1878 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
1879 #define DMA_ISR_HTIF2_Pos      (6U)
1880 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
1881 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
1882 #define DMA_ISR_TEIF2_Pos      (7U)
1883 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
1884 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
1885 #define DMA_ISR_GIF3_Pos       (8U)
1886 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
1887 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
1888 #define DMA_ISR_TCIF3_Pos      (9U)
1889 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
1890 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
1891 #define DMA_ISR_HTIF3_Pos      (10U)
1892 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
1893 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
1894 #define DMA_ISR_TEIF3_Pos      (11U)
1895 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
1896 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
1897 #define DMA_ISR_GIF4_Pos       (12U)
1898 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
1899 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
1900 #define DMA_ISR_TCIF4_Pos      (13U)
1901 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
1902 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
1903 #define DMA_ISR_HTIF4_Pos      (14U)
1904 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
1905 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
1906 #define DMA_ISR_TEIF4_Pos      (15U)
1907 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
1908 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
1909 #define DMA_ISR_GIF5_Pos       (16U)
1910 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
1911 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
1912 #define DMA_ISR_TCIF5_Pos      (17U)
1913 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
1914 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
1915 #define DMA_ISR_HTIF5_Pos      (18U)
1916 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
1917 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
1918 #define DMA_ISR_TEIF5_Pos      (19U)
1919 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
1920 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
1921 #define DMA_ISR_GIF6_Pos       (20U)
1922 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
1923 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
1924 #define DMA_ISR_TCIF6_Pos      (21U)
1925 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
1926 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
1927 #define DMA_ISR_HTIF6_Pos      (22U)
1928 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
1929 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
1930 #define DMA_ISR_TEIF6_Pos      (23U)
1931 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
1932 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
1933 #define DMA_ISR_GIF7_Pos       (24U)
1934 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
1935 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
1936 #define DMA_ISR_TCIF7_Pos      (25U)
1937 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
1938 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
1939 #define DMA_ISR_HTIF7_Pos      (26U)
1940 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
1941 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
1942 #define DMA_ISR_TEIF7_Pos      (27U)
1943 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
1944 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
1945 
1946 /*******************  Bit definition for DMA_IFCR register  *******************/
1947 #define DMA_IFCR_CGIF1_Pos     (0U)
1948 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
1949 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear */
1950 #define DMA_IFCR_CTCIF1_Pos    (1U)
1951 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
1952 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
1953 #define DMA_IFCR_CHTIF1_Pos    (2U)
1954 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
1955 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
1956 #define DMA_IFCR_CTEIF1_Pos    (3U)
1957 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
1958 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
1959 #define DMA_IFCR_CGIF2_Pos     (4U)
1960 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
1961 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
1962 #define DMA_IFCR_CTCIF2_Pos    (5U)
1963 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
1964 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
1965 #define DMA_IFCR_CHTIF2_Pos    (6U)
1966 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
1967 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
1968 #define DMA_IFCR_CTEIF2_Pos    (7U)
1969 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
1970 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
1971 #define DMA_IFCR_CGIF3_Pos     (8U)
1972 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
1973 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
1974 #define DMA_IFCR_CTCIF3_Pos    (9U)
1975 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
1976 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
1977 #define DMA_IFCR_CHTIF3_Pos    (10U)
1978 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
1979 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
1980 #define DMA_IFCR_CTEIF3_Pos    (11U)
1981 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
1982 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
1983 #define DMA_IFCR_CGIF4_Pos     (12U)
1984 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
1985 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
1986 #define DMA_IFCR_CTCIF4_Pos    (13U)
1987 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
1988 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
1989 #define DMA_IFCR_CHTIF4_Pos    (14U)
1990 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
1991 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
1992 #define DMA_IFCR_CTEIF4_Pos    (15U)
1993 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
1994 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
1995 #define DMA_IFCR_CGIF5_Pos     (16U)
1996 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
1997 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
1998 #define DMA_IFCR_CTCIF5_Pos    (17U)
1999 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
2000 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
2001 #define DMA_IFCR_CHTIF5_Pos    (18U)
2002 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
2003 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
2004 #define DMA_IFCR_CTEIF5_Pos    (19U)
2005 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
2006 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
2007 #define DMA_IFCR_CGIF6_Pos     (20U)
2008 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
2009 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
2010 #define DMA_IFCR_CTCIF6_Pos    (21U)
2011 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
2012 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
2013 #define DMA_IFCR_CHTIF6_Pos    (22U)
2014 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
2015 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
2016 #define DMA_IFCR_CTEIF6_Pos    (23U)
2017 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
2018 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
2019 #define DMA_IFCR_CGIF7_Pos     (24U)
2020 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
2021 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
2022 #define DMA_IFCR_CTCIF7_Pos    (25U)
2023 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
2024 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
2025 #define DMA_IFCR_CHTIF7_Pos    (26U)
2026 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
2027 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
2028 #define DMA_IFCR_CTEIF7_Pos    (27U)
2029 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
2030 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
2031 
2032 /*******************  Bit definition for DMA_CCR register  ********************/
2033 #define DMA_CCR_EN_Pos         (0U)
2034 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
2035 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
2036 #define DMA_CCR_TCIE_Pos       (1U)
2037 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
2038 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
2039 #define DMA_CCR_HTIE_Pos       (2U)
2040 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
2041 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
2042 #define DMA_CCR_TEIE_Pos       (3U)
2043 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
2044 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
2045 #define DMA_CCR_DIR_Pos        (4U)
2046 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
2047 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
2048 #define DMA_CCR_CIRC_Pos       (5U)
2049 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
2050 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
2051 #define DMA_CCR_PINC_Pos       (6U)
2052 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
2053 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
2054 #define DMA_CCR_MINC_Pos       (7U)
2055 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
2056 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
2057 
2058 #define DMA_CCR_PSIZE_Pos      (8U)
2059 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
2060 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
2061 #define DMA_CCR_PSIZE_0        (0x1U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
2062 #define DMA_CCR_PSIZE_1        (0x2U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
2063 
2064 #define DMA_CCR_MSIZE_Pos      (10U)
2065 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
2066 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
2067 #define DMA_CCR_MSIZE_0        (0x1U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
2068 #define DMA_CCR_MSIZE_1        (0x2U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
2069 
2070 #define DMA_CCR_PL_Pos         (12U)
2071 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
2072 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
2073 #define DMA_CCR_PL_0           (0x1U << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
2074 #define DMA_CCR_PL_1           (0x2U << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
2075 
2076 #define DMA_CCR_MEM2MEM_Pos    (14U)
2077 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
2078 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
2079 
2080 /******************  Bit definition for DMA_CNDTR register  *******************/
2081 #define DMA_CNDTR_NDT_Pos      (0U)
2082 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */
2083 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
2084 
2085 /******************  Bit definition for DMA_CPAR register  ********************/
2086 #define DMA_CPAR_PA_Pos        (0U)
2087 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
2088 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
2089 
2090 /******************  Bit definition for DMA_CMAR register  ********************/
2091 #define DMA_CMAR_MA_Pos        (0U)
2092 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
2093 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
2094 
2095 /******************************************************************************/
2096 /*                                                                            */
2097 /*                             DMAMUX Controller                              */
2098 /*                                                                            */
2099 /******************************************************************************/
2100 /********************  Bits definition for DMAMUX_CxCR register  **************/
2101 #define DMAMUX_CxCR_DMAREQ_ID_Pos              (0U)
2102 #define DMAMUX_CxCR_DMAREQ_ID_Msk              (0x3FUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x0000003F */
2103 #define DMAMUX_CxCR_DMAREQ_ID                  DMAMUX_CxCR_DMAREQ_ID_Msk       /*!< DMA Request ID                       */
2104 #define DMAMUX_CxCR_DMAREQ_ID_0                (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
2105 #define DMAMUX_CxCR_DMAREQ_ID_1                (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
2106 #define DMAMUX_CxCR_DMAREQ_ID_2                (0x04U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
2107 #define DMAMUX_CxCR_DMAREQ_ID_3                (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
2108 #define DMAMUX_CxCR_DMAREQ_ID_4                (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
2109 #define DMAMUX_CxCR_DMAREQ_ID_5                (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
2110 #define DMAMUX_CxCR_SOIE_Pos                   (8U)
2111 #define DMAMUX_CxCR_SOIE_Msk                   (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
2112 #define DMAMUX_CxCR_SOIE                       DMAMUX_CxCR_SOIE_Msk            /*!< Synchro overrun interrupt enable     */
2113 #define DMAMUX_CxCR_EGE_Pos                    (9U)
2114 #define DMAMUX_CxCR_EGE_Msk                    (0x1UL << DMAMUX_CxCR_EGE_Pos)  /*!< 0x00000200 */
2115 #define DMAMUX_CxCR_EGE                        DMAMUX_CxCR_EGE_Msk             /*!< Event generation interrupt enable    */
2116 #define DMAMUX_CxCR_SE_Pos                     (16U)
2117 #define DMAMUX_CxCR_SE_Msk                     (0x1UL << DMAMUX_CxCR_SE_Pos)   /*!< 0x00010000 */
2118 #define DMAMUX_CxCR_SE                         DMAMUX_CxCR_SE_Msk              /*!< Synchronization enable               */
2119 #define DMAMUX_CxCR_SPOL_Pos                   (17U)
2120 #define DMAMUX_CxCR_SPOL_Msk                   (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
2121 #define DMAMUX_CxCR_SPOL                       DMAMUX_CxCR_SPOL_Msk            /*!< Synchronization polarity             */
2122 #define DMAMUX_CxCR_SPOL_0                     (0x1U << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00020000 */
2123 #define DMAMUX_CxCR_SPOL_1                     (0x2U << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00040000 */
2124 #define DMAMUX_CxCR_NBREQ_Pos                  (19U)
2125 #define DMAMUX_CxCR_NBREQ_Msk                  (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
2126 #define DMAMUX_CxCR_NBREQ                      DMAMUX_CxCR_NBREQ_Msk           /*!< Number of request                    */
2127 #define DMAMUX_CxCR_NBREQ_0                    (0x01U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
2128 #define DMAMUX_CxCR_NBREQ_1                    (0x02U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
2129 #define DMAMUX_CxCR_NBREQ_2                    (0x04U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
2130 #define DMAMUX_CxCR_NBREQ_3                    (0x08U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
2131 #define DMAMUX_CxCR_NBREQ_4                    (0x10U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
2132 #define DMAMUX_CxCR_SYNC_ID_Pos                (24U)
2133 #define DMAMUX_CxCR_SYNC_ID_Msk                (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
2134 #define DMAMUX_CxCR_SYNC_ID                    DMAMUX_CxCR_SYNC_ID_Msk         /*!< Synchronization ID                   */
2135 #define DMAMUX_CxCR_SYNC_ID_0                  (0x01U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
2136 #define DMAMUX_CxCR_SYNC_ID_1                  (0x02U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
2137 #define DMAMUX_CxCR_SYNC_ID_2                  (0x04U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
2138 #define DMAMUX_CxCR_SYNC_ID_3                  (0x08U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
2139 #define DMAMUX_CxCR_SYNC_ID_4                  (0x10U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
2140 
2141 /*******************  Bits definition for DMAMUX_CSR register  **************/
2142 #define DMAMUX_CSR_SOF0_Pos                    (0U)
2143 #define DMAMUX_CSR_SOF0_Msk                    (0x1UL << DMAMUX_CSR_SOF0_Pos)  /*!< 0x00000001 */
2144 #define DMAMUX_CSR_SOF0                        DMAMUX_CSR_SOF0_Msk             /*!< Synchronization Overrun Flag 0       */
2145 #define DMAMUX_CSR_SOF1_Pos                    (1U)
2146 #define DMAMUX_CSR_SOF1_Msk                    (0x1UL << DMAMUX_CSR_SOF1_Pos)  /*!< 0x00000002 */
2147 #define DMAMUX_CSR_SOF1                        DMAMUX_CSR_SOF1_Msk             /*!< Synchronization Overrun Flag 1       */
2148 #define DMAMUX_CSR_SOF2_Pos                    (2U)
2149 #define DMAMUX_CSR_SOF2_Msk                    (0x1UL << DMAMUX_CSR_SOF2_Pos)  /*!< 0x00000004 */
2150 #define DMAMUX_CSR_SOF2                        DMAMUX_CSR_SOF2_Msk             /*!< Synchronization Overrun Flag 2       */
2151 #define DMAMUX_CSR_SOF3_Pos                    (3U)
2152 #define DMAMUX_CSR_SOF3_Msk                    (0x1UL << DMAMUX_CSR_SOF3_Pos)  /*!< 0x00000008 */
2153 #define DMAMUX_CSR_SOF3                        DMAMUX_CSR_SOF3_Msk             /*!< Synchronization Overrun Flag 3       */
2154 #define DMAMUX_CSR_SOF4_Pos                    (4U)
2155 #define DMAMUX_CSR_SOF4_Msk                    (0x1UL << DMAMUX_CSR_SOF4_Pos)  /*!< 0x00000010 */
2156 #define DMAMUX_CSR_SOF4                        DMAMUX_CSR_SOF4_Msk             /*!< Synchronization Overrun Flag 4       */
2157 #define DMAMUX_CSR_SOF5_Pos                    (5U)
2158 #define DMAMUX_CSR_SOF5_Msk                    (0x1UL << DMAMUX_CSR_SOF5_Pos)  /*!< 0x00000020 */
2159 #define DMAMUX_CSR_SOF5                        DMAMUX_CSR_SOF5_Msk             /*!< Synchronization Overrun Flag 5       */
2160 #define DMAMUX_CSR_SOF6_Pos                    (6U)
2161 #define DMAMUX_CSR_SOF6_Msk                    (0x1UL << DMAMUX_CSR_SOF6_Pos)  /*!< 0x00000040 */
2162 #define DMAMUX_CSR_SOF6                        DMAMUX_CSR_SOF6_Msk             /*!< Synchronization Overrun Flag 6       */
2163 
2164 /********************  Bits definition for DMAMUX_CFR register  **************/
2165 #define DMAMUX_CFR_CSOF0_Pos                   (0U)
2166 #define DMAMUX_CFR_CSOF0_Msk                   (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
2167 #define DMAMUX_CFR_CSOF0                       DMAMUX_CFR_CSOF0_Msk            /*!< Clear Overrun Flag 0                 */
2168 #define DMAMUX_CFR_CSOF1_Pos                   (1U)
2169 #define DMAMUX_CFR_CSOF1_Msk                   (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
2170 #define DMAMUX_CFR_CSOF1                       DMAMUX_CFR_CSOF1_Msk            /*!< Clear Overrun Flag 1                 */
2171 #define DMAMUX_CFR_CSOF2_Pos                   (2U)
2172 #define DMAMUX_CFR_CSOF2_Msk                   (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
2173 #define DMAMUX_CFR_CSOF2                       DMAMUX_CFR_CSOF2_Msk            /*!< Clear Overrun Flag 2                 */
2174 #define DMAMUX_CFR_CSOF3_Pos                   (3U)
2175 #define DMAMUX_CFR_CSOF3_Msk                   (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
2176 #define DMAMUX_CFR_CSOF3                       DMAMUX_CFR_CSOF3_Msk            /*!< Clear Overrun Flag 3                 */
2177 #define DMAMUX_CFR_CSOF4_Pos                   (4U)
2178 #define DMAMUX_CFR_CSOF4_Msk                   (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
2179 #define DMAMUX_CFR_CSOF4                       DMAMUX_CFR_CSOF4_Msk            /*!< Clear Overrun Flag 4                 */
2180 #define DMAMUX_CFR_CSOF5_Pos                   (5U)
2181 #define DMAMUX_CFR_CSOF5_Msk                   (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
2182 #define DMAMUX_CFR_CSOF5                       DMAMUX_CFR_CSOF5_Msk            /*!< Clear Overrun Flag 5                 */
2183 #define DMAMUX_CFR_CSOF6_Pos                   (6U)
2184 #define DMAMUX_CFR_CSOF6_Msk                   (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
2185 #define DMAMUX_CFR_CSOF6                       DMAMUX_CFR_CSOF6_Msk            /*!< Clear Overrun Flag 6                 */
2186 
2187 /********************  Bits definition for DMAMUX_RGxCR register  ************/
2188 #define DMAMUX_RGxCR_SIG_ID_Pos                (0U)
2189 #define DMAMUX_RGxCR_SIG_ID_Msk                (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
2190 #define DMAMUX_RGxCR_SIG_ID                    DMAMUX_RGxCR_SIG_ID_Msk         /*!< Signal ID                            */
2191 #define DMAMUX_RGxCR_SIG_ID_0                  (0x01U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
2192 #define DMAMUX_RGxCR_SIG_ID_1                  (0x02U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
2193 #define DMAMUX_RGxCR_SIG_ID_2                  (0x04U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
2194 #define DMAMUX_RGxCR_SIG_ID_3                  (0x08U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
2195 #define DMAMUX_RGxCR_SIG_ID_4                  (0x10U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
2196 #define DMAMUX_RGxCR_OIE_Pos                   (8U)
2197 #define DMAMUX_RGxCR_OIE_Msk                   (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
2198 #define DMAMUX_RGxCR_OIE                       DMAMUX_RGxCR_OIE_Msk            /*!< Overrun interrupt enable             */
2199 #define DMAMUX_RGxCR_GE_Pos                    (16U)
2200 #define DMAMUX_RGxCR_GE_Msk                    (0x1UL << DMAMUX_RGxCR_GE_Pos)  /*!< 0x00010000 */
2201 #define DMAMUX_RGxCR_GE                        DMAMUX_RGxCR_GE_Msk             /*!< Generation enable                    */
2202 #define DMAMUX_RGxCR_GPOL_Pos                  (17U)
2203 #define DMAMUX_RGxCR_GPOL_Msk                  (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
2204 #define DMAMUX_RGxCR_GPOL                      DMAMUX_RGxCR_GPOL_Msk           /*!< Generation polarity                  */
2205 #define DMAMUX_RGxCR_GPOL_0                    (0x1U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
2206 #define DMAMUX_RGxCR_GPOL_1                    (0x2U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
2207 #define DMAMUX_RGxCR_GNBREQ_Pos                (19U)
2208 #define DMAMUX_RGxCR_GNBREQ_Msk                (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
2209 #define DMAMUX_RGxCR_GNBREQ                    DMAMUX_RGxCR_GNBREQ_Msk          /*!< Number of request                    */
2210 #define DMAMUX_RGxCR_GNBREQ_0                  (0x01U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
2211 #define DMAMUX_RGxCR_GNBREQ_1                  (0x02U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
2212 #define DMAMUX_RGxCR_GNBREQ_2                  (0x04U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
2213 #define DMAMUX_RGxCR_GNBREQ_3                  (0x08U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
2214 #define DMAMUX_RGxCR_GNBREQ_4                  (0x10U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
2215 
2216 /********************  Bits definition for DMAMUX_RGSR register  **************/
2217 #define DMAMUX_RGSR_OF0_Pos                    (0U)
2218 #define DMAMUX_RGSR_OF0_Msk                    (0x1UL << DMAMUX_RGSR_OF0_Pos)  /*!< 0x00000001 */
2219 #define DMAMUX_RGSR_OF0                        DMAMUX_RGSR_OF0_Msk             /*!< Overrun flag 0                       */
2220 #define DMAMUX_RGSR_OF1_Pos                    (1U)
2221 #define DMAMUX_RGSR_OF1_Msk                    (0x1UL << DMAMUX_RGSR_OF1_Pos)  /*!< 0x00000002 */
2222 #define DMAMUX_RGSR_OF1                        DMAMUX_RGSR_OF1_Msk             /*!< Overrun flag 1                       */
2223 #define DMAMUX_RGSR_OF2_Pos                    (2U)
2224 #define DMAMUX_RGSR_OF2_Msk                    (0x1UL << DMAMUX_RGSR_OF2_Pos)  /*!< 0x00000004 */
2225 #define DMAMUX_RGSR_OF2                        DMAMUX_RGSR_OF2_Msk             /*!< Overrun flag 2                       */
2226 #define DMAMUX_RGSR_OF3_Pos                    (3U)
2227 #define DMAMUX_RGSR_OF3_Msk                    (0x1UL << DMAMUX_RGSR_OF3_Pos)  /*!< 0x00000008 */
2228 #define DMAMUX_RGSR_OF3                        DMAMUX_RGSR_OF3_Msk             /*!< Overrun flag 3                       */
2229 
2230 /********************  Bits definition for DMAMUX_RGCFR register  **************/
2231 #define DMAMUX_RGCFR_COF0_Pos                  (0U)
2232 #define DMAMUX_RGCFR_COF0_Msk                  (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
2233 #define DMAMUX_RGCFR_COF0                      DMAMUX_RGCFR_COF0_Msk           /*!< Clear Overrun flag 0                 */
2234 #define DMAMUX_RGCFR_COF1_Pos                  (1U)
2235 #define DMAMUX_RGCFR_COF1_Msk                  (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
2236 #define DMAMUX_RGCFR_COF1                      DMAMUX_RGCFR_COF1_Msk           /*!< Clear Overrun flag 1                 */
2237 #define DMAMUX_RGCFR_COF2_Pos                  (2U)
2238 #define DMAMUX_RGCFR_COF2_Msk                  (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
2239 #define DMAMUX_RGCFR_COF2                      DMAMUX_RGCFR_COF2_Msk           /*!< Clear Overrun flag 2                 */
2240 #define DMAMUX_RGCFR_COF3_Pos                  (3U)
2241 #define DMAMUX_RGCFR_COF3_Msk                  (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
2242 #define DMAMUX_RGCFR_COF3                      DMAMUX_RGCFR_COF3_Msk           /*!< Clear Overrun flag 3                 */
2243 
2244 /******************************************************************************/
2245 /*                                                                            */
2246 /*                    External Interrupt/Event Controller                     */
2247 /*                                                                            */
2248 /******************************************************************************/
2249 
2250 /******************  Bit definition for EXTI_RTSR1 register  ******************/
2251 #define EXTI_RTSR1_RT_Pos        (0U)
2252 #define EXTI_RTSR1_RT_Msk        (0x803FFFFFUL << EXTI_RTSR1_RT_Pos)           /*!< 0x803FFFFF */
2253 #define EXTI_RTSR1_RT            EXTI_RTSR1_RT_Msk                             /*!< Rising trigger event configuration bit */
2254 #define EXTI_RTSR1_RT0_Pos       (0U)
2255 #define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */
2256 #define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
2257 #define EXTI_RTSR1_RT1_Pos       (1U)
2258 #define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */
2259 #define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
2260 #define EXTI_RTSR1_RT2_Pos       (2U)
2261 #define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */
2262 #define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
2263 #define EXTI_RTSR1_RT3_Pos       (3U)
2264 #define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */
2265 #define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
2266 #define EXTI_RTSR1_RT4_Pos       (4U)
2267 #define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */
2268 #define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
2269 #define EXTI_RTSR1_RT5_Pos       (5U)
2270 #define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */
2271 #define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
2272 #define EXTI_RTSR1_RT6_Pos       (6U)
2273 #define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */
2274 #define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
2275 #define EXTI_RTSR1_RT7_Pos       (7U)
2276 #define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */
2277 #define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
2278 #define EXTI_RTSR1_RT8_Pos       (8U)
2279 #define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */
2280 #define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
2281 #define EXTI_RTSR1_RT9_Pos       (9U)
2282 #define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */
2283 #define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
2284 #define EXTI_RTSR1_RT10_Pos      (10U)
2285 #define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */
2286 #define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
2287 #define EXTI_RTSR1_RT11_Pos      (11U)
2288 #define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */
2289 #define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
2290 #define EXTI_RTSR1_RT12_Pos      (12U)
2291 #define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */
2292 #define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
2293 #define EXTI_RTSR1_RT13_Pos      (13U)
2294 #define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */
2295 #define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
2296 #define EXTI_RTSR1_RT14_Pos      (14U)
2297 #define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */
2298 #define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
2299 #define EXTI_RTSR1_RT15_Pos      (15U)
2300 #define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */
2301 #define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
2302 #define EXTI_RTSR1_RT16_Pos      (16U)
2303 #define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */
2304 #define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
2305 #define EXTI_RTSR1_RT17_Pos      (17U)
2306 #define EXTI_RTSR1_RT17_Msk      (0x1UL << EXTI_RTSR1_RT17_Pos)                /*!< 0x00020000 */
2307 #define EXTI_RTSR1_RT17          EXTI_RTSR1_RT17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
2308 #define EXTI_RTSR1_RT18_Pos      (18U)
2309 #define EXTI_RTSR1_RT18_Msk      (0x1UL << EXTI_RTSR1_RT18_Pos)                /*!< 0x00040000 */
2310 #define EXTI_RTSR1_RT18          EXTI_RTSR1_RT18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
2311 #define EXTI_RTSR1_RT19_Pos      (19U)
2312 #define EXTI_RTSR1_RT19_Msk      (0x1UL << EXTI_RTSR1_RT19_Pos)                /*!< 0x00080000 */
2313 #define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
2314 #define EXTI_RTSR1_RT20_Pos      (20U)
2315 #define EXTI_RTSR1_RT20_Msk      (0x1UL << EXTI_RTSR1_RT20_Pos)                /*!< 0x00100000 */
2316 #define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
2317 #define EXTI_RTSR1_RT31_Pos      (31U)
2318 #define EXTI_RTSR1_RT31_Msk      (0x1UL << EXTI_RTSR1_RT31_Pos)                /*!< 0x80000000 */
2319 #define EXTI_RTSR1_RT31          EXTI_RTSR1_RT31_Msk                           /*!< Rising trigger event configuration bit of line 31 */
2320 
2321 /******************  Bit definition for EXTI_FTSR1 register  ******************/
2322 #define EXTI_FTSR1_FT_Pos        (0U)
2323 #define EXTI_FTSR1_FT_Msk        (0x803FFFFFUL << EXTI_FTSR1_FT_Pos)           /*!< 0x803FFFFF */
2324 #define EXTI_FTSR1_FT            EXTI_FTSR1_FT_Msk                             /*!< Falling trigger event configuration bit */
2325 #define EXTI_FTSR1_FT0_Pos       (0U)
2326 #define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */
2327 #define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
2328 #define EXTI_FTSR1_FT1_Pos       (1U)
2329 #define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */
2330 #define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
2331 #define EXTI_FTSR1_FT2_Pos       (2U)
2332 #define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */
2333 #define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
2334 #define EXTI_FTSR1_FT3_Pos       (3U)
2335 #define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */
2336 #define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
2337 #define EXTI_FTSR1_FT4_Pos       (4U)
2338 #define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */
2339 #define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
2340 #define EXTI_FTSR1_FT5_Pos       (5U)
2341 #define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */
2342 #define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
2343 #define EXTI_FTSR1_FT6_Pos       (6U)
2344 #define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */
2345 #define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
2346 #define EXTI_FTSR1_FT7_Pos       (7U)
2347 #define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */
2348 #define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
2349 #define EXTI_FTSR1_FT8_Pos       (8U)
2350 #define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */
2351 #define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
2352 #define EXTI_FTSR1_FT9_Pos       (9U)
2353 #define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */
2354 #define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
2355 #define EXTI_FTSR1_FT10_Pos      (10U)
2356 #define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */
2357 #define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
2358 #define EXTI_FTSR1_FT11_Pos      (11U)
2359 #define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */
2360 #define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
2361 #define EXTI_FTSR1_FT12_Pos      (12U)
2362 #define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */
2363 #define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
2364 #define EXTI_FTSR1_FT13_Pos      (13U)
2365 #define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */
2366 #define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
2367 #define EXTI_FTSR1_FT14_Pos      (14U)
2368 #define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */
2369 #define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
2370 #define EXTI_FTSR1_FT15_Pos      (15U)
2371 #define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */
2372 #define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
2373 #define EXTI_FTSR1_FT16_Pos      (16U)
2374 #define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */
2375 #define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
2376 #define EXTI_FTSR1_FT17_Pos      (17U)
2377 #define EXTI_FTSR1_FT17_Msk      (0x1UL << EXTI_FTSR1_FT17_Pos)                /*!< 0x00020000 */
2378 #define EXTI_FTSR1_FT17          EXTI_FTSR1_FT17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
2379 #define EXTI_FTSR1_FT18_Pos      (18U)
2380 #define EXTI_FTSR1_FT18_Msk      (0x1UL << EXTI_FTSR1_FT18_Pos)                /*!< 0x00040000 */
2381 #define EXTI_FTSR1_FT18          EXTI_FTSR1_FT18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
2382 #define EXTI_FTSR1_FT19_Pos      (19U)
2383 #define EXTI_FTSR1_FT19_Msk      (0x1UL << EXTI_FTSR1_FT19_Pos)                /*!< 0x00080000 */
2384 #define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
2385 #define EXTI_FTSR1_FT20_Pos      (20U)
2386 #define EXTI_FTSR1_FT20_Msk      (0x1UL << EXTI_FTSR1_FT20_Pos)                /*!< 0x00100000 */
2387 #define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
2388 #define EXTI_FTSR1_FT31_Pos      (31U)
2389 #define EXTI_FTSR1_FT31_Msk      (0x1UL << EXTI_FTSR1_FT31_Pos)                /*!< 0x80000000 */
2390 #define EXTI_FTSR1_FT31          EXTI_FTSR1_FT31_Msk                           /*!< Falling trigger event configuration bit of line 31 */
2391 
2392 /******************  Bit definition for EXTI_SWIER1 register  *****************/
2393 #define EXTI_SWIER1_SWI_Pos      (0U)
2394 #define EXTI_SWIER1_SWI_Msk      (0x803FFFFFUL << EXTI_SWIER1_SWI_Pos)         /*!< 0x803FFFFF */
2395 #define EXTI_SWIER1_SWI          EXTI_SWIER1_SWI_Msk                           /*!< Software interrupt */
2396 #define EXTI_SWIER1_SWI0_Pos     (0U)
2397 #define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */
2398 #define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
2399 #define EXTI_SWIER1_SWI1_Pos     (1U)
2400 #define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */
2401 #define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
2402 #define EXTI_SWIER1_SWI2_Pos     (2U)
2403 #define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */
2404 #define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
2405 #define EXTI_SWIER1_SWI3_Pos     (3U)
2406 #define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */
2407 #define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
2408 #define EXTI_SWIER1_SWI4_Pos     (4U)
2409 #define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */
2410 #define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
2411 #define EXTI_SWIER1_SWI5_Pos     (5U)
2412 #define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */
2413 #define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
2414 #define EXTI_SWIER1_SWI6_Pos     (6U)
2415 #define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */
2416 #define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
2417 #define EXTI_SWIER1_SWI7_Pos     (7U)
2418 #define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */
2419 #define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
2420 #define EXTI_SWIER1_SWI8_Pos     (8U)
2421 #define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */
2422 #define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
2423 #define EXTI_SWIER1_SWI9_Pos     (9U)
2424 #define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */
2425 #define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
2426 #define EXTI_SWIER1_SWI10_Pos    (10U)
2427 #define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */
2428 #define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
2429 #define EXTI_SWIER1_SWI11_Pos    (11U)
2430 #define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */
2431 #define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
2432 #define EXTI_SWIER1_SWI12_Pos    (12U)
2433 #define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */
2434 #define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
2435 #define EXTI_SWIER1_SWI13_Pos    (13U)
2436 #define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */
2437 #define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
2438 #define EXTI_SWIER1_SWI14_Pos    (14U)
2439 #define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */
2440 #define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
2441 #define EXTI_SWIER1_SWI15_Pos    (15U)
2442 #define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */
2443 #define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
2444 #define EXTI_SWIER1_SWI16_Pos    (16U)
2445 #define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */
2446 #define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
2447 #define EXTI_SWIER1_SWI17_Pos    (17U)
2448 #define EXTI_SWIER1_SWI17_Msk    (0x1UL << EXTI_SWIER1_SWI17_Pos)              /*!< 0x00020000 */
2449 #define EXTI_SWIER1_SWI17        EXTI_SWIER1_SWI17_Msk                         /*!< Software Interrupt on line 17 */
2450 #define EXTI_SWIER1_SWI18_Pos    (18U)
2451 #define EXTI_SWIER1_SWI18_Msk    (0x1UL << EXTI_SWIER1_SWI18_Pos)              /*!< 0x00040000 */
2452 #define EXTI_SWIER1_SWI18        EXTI_SWIER1_SWI18_Msk                         /*!< Software Interrupt on line 18 */
2453 #define EXTI_SWIER1_SWI19_Pos    (19U)
2454 #define EXTI_SWIER1_SWI19_Msk    (0x1UL << EXTI_SWIER1_SWI19_Pos)              /*!< 0x00080000 */
2455 #define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
2456 #define EXTI_SWIER1_SWI20_Pos    (20U)
2457 #define EXTI_SWIER1_SWI20_Msk    (0x1UL << EXTI_SWIER1_SWI20_Pos)              /*!< 0x00100000 */
2458 #define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
2459 #define EXTI_SWIER1_SWI31_Pos    (31U)
2460 #define EXTI_SWIER1_SWI31_Msk    (0x1UL << EXTI_SWIER1_SWI31_Pos)              /*!< 0x80000000 */
2461 #define EXTI_SWIER1_SWI31         EXTI_SWIER1_SWI31_Msk                        /*!< Software Interrupt on line 31 */
2462 
2463 /*******************  Bit definition for EXTI_PR1 register  *******************/
2464 #define EXTI_PR1_PIF_Pos         (0U)
2465 #define EXTI_PR1_PIF_Msk         (0x803FFFFFUL << EXTI_PR1_PIF_Pos)            /*!< 0x803FFFFF */
2466 #define EXTI_PR1_PIF             EXTI_PR1_PIF_Msk                              /*!< Pending bit */
2467 #define EXTI_PR1_PIF0_Pos        (0U)
2468 #define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */
2469 #define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
2470 #define EXTI_PR1_PIF1_Pos        (1U)
2471 #define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */
2472 #define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
2473 #define EXTI_PR1_PIF2_Pos        (2U)
2474 #define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */
2475 #define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
2476 #define EXTI_PR1_PIF3_Pos        (3U)
2477 #define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */
2478 #define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
2479 #define EXTI_PR1_PIF4_Pos        (4U)
2480 #define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */
2481 #define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
2482 #define EXTI_PR1_PIF5_Pos        (5U)
2483 #define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */
2484 #define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
2485 #define EXTI_PR1_PIF6_Pos        (6U)
2486 #define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */
2487 #define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
2488 #define EXTI_PR1_PIF7_Pos        (7U)
2489 #define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */
2490 #define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
2491 #define EXTI_PR1_PIF8_Pos        (8U)
2492 #define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */
2493 #define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
2494 #define EXTI_PR1_PIF9_Pos        (9U)
2495 #define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */
2496 #define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
2497 #define EXTI_PR1_PIF10_Pos       (10U)
2498 #define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */
2499 #define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
2500 #define EXTI_PR1_PIF11_Pos       (11U)
2501 #define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */
2502 #define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
2503 #define EXTI_PR1_PIF12_Pos       (12U)
2504 #define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */
2505 #define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
2506 #define EXTI_PR1_PIF13_Pos       (13U)
2507 #define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */
2508 #define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
2509 #define EXTI_PR1_PIF14_Pos       (14U)
2510 #define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */
2511 #define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
2512 #define EXTI_PR1_PIF15_Pos       (15U)
2513 #define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */
2514 #define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
2515 #define EXTI_PR1_PIF16_Pos       (16U)
2516 #define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */
2517 #define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
2518 #define EXTI_PR1_PIF17_Pos       (17U)
2519 #define EXTI_PR1_PIF17_Msk       (0x1UL << EXTI_PR1_PIF17_Pos)                 /*!< 0x00020000 */
2520 #define EXTI_PR1_PIF17           EXTI_PR1_PIF17_Msk                            /*!< Pending bit for line 17 */
2521 #define EXTI_PR1_PIF18_Pos       (18U)
2522 #define EXTI_PR1_PIF18_Msk       (0x1UL << EXTI_PR1_PIF18_Pos)                 /*!< 0x00040000 */
2523 #define EXTI_PR1_PIF18           EXTI_PR1_PIF18_Msk                            /*!< Pending bit for line 18 */
2524 #define EXTI_PR1_PIF19_Pos       (19U)
2525 #define EXTI_PR1_PIF19_Msk       (0x1UL << EXTI_PR1_PIF19_Pos)                 /*!< 0x00080000 */
2526 #define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
2527 #define EXTI_PR1_PIF20_Pos       (20U)
2528 #define EXTI_PR1_PIF20_Msk       (0x1UL << EXTI_PR1_PIF20_Pos)                 /*!< 0x00100000 */
2529 #define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
2530 #define EXTI_PR1_PIF31_Pos       (31U)
2531 #define EXTI_PR1_PIF31_Msk       (0x1UL << EXTI_PR1_PIF31_Pos)                 /*!< 0x80000000 */
2532 #define EXTI_PR1_PIF31           EXTI_PR1_PIF31_Msk                            /*!< Pending bit for line 31 */
2533 
2534 /******************  Bit definition for EXTI_RTSR2 register  ******************/
2535 #define EXTI_RTSR2_RT_Pos        (0U)
2536 #define EXTI_RTSR2_RT_Msk        (0x302UL << EXTI_RTSR2_RT_Pos)                /*!< 0x00000302 */
2537 #define EXTI_RTSR2_RT            EXTI_RTSR2_RT_Msk                             /*!< Rising trigger event configuration bit */
2538 #define EXTI_RTSR2_RT33_Pos      (1U)
2539 #define EXTI_RTSR2_RT33_Msk      (0x1UL << EXTI_RTSR2_RT33_Pos)                /*!< 0x00000002 */
2540 #define EXTI_RTSR2_RT33          EXTI_RTSR2_RT33_Msk                           /*!< Rising trigger event configuration bit of line 33 */
2541 #define EXTI_RTSR2_RT40_Pos      (8U)
2542 #define EXTI_RTSR2_RT40_Msk      (0x1UL << EXTI_RTSR2_RT40_Pos)                /*!< 0x00000100 */
2543 #define EXTI_RTSR2_RT40          EXTI_RTSR2_RT40_Msk                           /*!< Rising trigger event configuration bit of line 40 */
2544 #define EXTI_RTSR2_RT41_Pos      (9U)
2545 #define EXTI_RTSR2_RT41_Msk      (0x1UL << EXTI_RTSR2_RT41_Pos)                /*!< 0x00000200 */
2546 #define EXTI_RTSR2_RT41          EXTI_RTSR2_RT41_Msk                           /*!< Rising trigger event configuration bit of line 41 */
2547 
2548 /******************  Bit definition for EXTI_FTSR2 register  ******************/
2549 #define EXTI_FTSR2_FT_Pos        (0U)
2550 #define EXTI_FTSR2_FT_Msk        (0x302UL << EXTI_FTSR2_FT_Pos)                /*!< 0x00000302 */
2551 #define EXTI_FTSR2_FT            EXTI_FTSR2_FT_Msk                             /*!< Falling trigger event configuration bit */
2552 #define EXTI_FTSR2_FT33_Pos      (1U)
2553 #define EXTI_FTSR2_FT33_Msk      (0x1UL << EXTI_FTSR2_FT33_Pos)                /*!< 0x00000002 */
2554 #define EXTI_FTSR2_FT33          EXTI_FTSR2_FT33_Msk                           /*!< Falling trigger event configuration bit of line 33 */
2555 #define EXTI_FTSR2_FT40_Pos      (8U)
2556 #define EXTI_FTSR2_FT40_Msk      (0x1UL << EXTI_FTSR2_FT40_Pos)                /*!< 0x00000100 */
2557 #define EXTI_FTSR2_FT40          EXTI_FTSR2_FT40_Msk                           /*!< Falling trigger event configuration bit of line 40 */
2558 #define EXTI_FTSR2_FT41_Pos      (9U)
2559 #define EXTI_FTSR2_FT41_Msk      (0x1UL << EXTI_FTSR2_FT41_Pos)                /*!< 0x00000200 */
2560 #define EXTI_FTSR2_FT41          EXTI_FTSR2_FT41_Msk                           /*!< Falling trigger event configuration bit of line 41 */
2561 
2562 /******************  Bit definition for EXTI_SWIER2 register  *****************/
2563 #define EXTI_SWIER2_SWI_Pos      (0U)
2564 #define EXTI_SWIER2_SWI_Msk      (0x302UL << EXTI_SWIER2_SWI_Pos)              /*!< 0x00000302 */
2565 #define EXTI_SWIER2_SWI          EXTI_SWIER2_SWI_Msk                           /*!< Falling trigger event configuration bit */
2566 #define EXTI_SWIER2_SWI33_Pos    (1U)
2567 #define EXTI_SWIER2_SWI33_Msk    (0x1UL << EXTI_SWIER2_SWI33_Pos)                /*!< 0x00000002 */
2568 #define EXTI_SWIER2_SWI33        EXTI_SWIER2_SWI33_Msk                           /*!< Software Interrupt on line 33 */
2569 #define EXTI_SWIER2_SWI40_Pos    (8U)
2570 #define EXTI_SWIER2_SWI40_Msk    (0x1UL << EXTI_SWIER2_SWI40_Pos)                /*!< 0x00000100 */
2571 #define EXTI_SWIER2_SWI40        EXTI_SWIER2_SWI40_Msk                           /*!< Software Interrupt on line 40 */
2572 #define EXTI_SWIER2_SWI41_Pos    (9U)
2573 #define EXTI_SWIER2_SWI41_Msk    (0x1UL << EXTI_SWIER2_SWI41_Pos)                /*!< 0x00000200 */
2574 #define EXTI_SWIER2_SWI41        EXTI_SWIER2_SWI41_Msk                           /*!< Software Interrupt on line 41 */
2575 
2576 /*******************  Bit definition for EXTI_PR2 register  *******************/
2577 #define EXTI_PR2_PIF_Pos         (0U)
2578 #define EXTI_PR2_PIF_Msk         (0x302UL << EXTI_PR2_PIF_Pos)                 /*!< 0x00000302 */
2579 #define EXTI_PR2_PIF             EXTI_PR2_PIF_Msk                              /*!< Pending bit */
2580 #define EXTI_PR2_PIF33_Pos       (1U)
2581 #define EXTI_PR2_PIF33_Msk       (0x1UL << EXTI_PR2_PIF33_Pos)                 /*!< 0x00000002 */
2582 #define EXTI_PR2_PIF33           EXTI_PR2_PIF33_Msk                            /*!< Pending bit for line 33 */
2583 #define EXTI_PR2_PIF40_Pos       (8U)
2584 #define EXTI_PR2_PIF40_Msk       (0x1UL << EXTI_PR2_PIF40_Pos)                 /*!< 0x00000100 */
2585 #define EXTI_PR2_PIF40           EXTI_PR2_PIF40_Msk                            /*!< Pending bit for line 40 */
2586 #define EXTI_PR2_PIF41_Pos       (9U)
2587 #define EXTI_PR2_PIF41_Msk       (0x1UL << EXTI_PR2_PIF41_Pos)                 /*!< 0x00000200 */
2588 #define EXTI_PR2_PIF41           EXTI_PR2_PIF41_Msk                            /*!< Pending bit for line 41 */
2589 
2590 /********************  Bits definition for EXTI_IMR1 register  ****************/
2591 #define EXTI_IMR1_Pos            (0U)
2592 #define EXTI_IMR1_Msk            (0xFFFFFFFFUL << EXTI_IMR1_Pos)               /*!< 0xFFFFFFFF */
2593 #define EXTI_IMR1_IM             EXTI_IMR1_Msk                                 /*!< CPU1 wakeup with interrupt Mask on Event */
2594 #define EXTI_IMR1_IM0_Pos        (0U)
2595 #define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */
2596 #define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< CPU1 Interrupt Mask on line 0 */
2597 #define EXTI_IMR1_IM1_Pos        (1U)
2598 #define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */
2599 #define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< CPU1 Interrupt Mask on line 1 */
2600 #define EXTI_IMR1_IM2_Pos        (2U)
2601 #define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */
2602 #define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< CPU1 Interrupt Mask on line 2 */
2603 #define EXTI_IMR1_IM3_Pos        (3U)
2604 #define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */
2605 #define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< CPU1 Interrupt Mask on line 3 */
2606 #define EXTI_IMR1_IM4_Pos        (4U)
2607 #define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */
2608 #define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< CPU1 Interrupt Mask on line 4 */
2609 #define EXTI_IMR1_IM5_Pos        (5U)
2610 #define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */
2611 #define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< CPU1 Interrupt Mask on line 5 */
2612 #define EXTI_IMR1_IM6_Pos        (6U)
2613 #define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */
2614 #define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< CPU1 Interrupt Mask on line 6 */
2615 #define EXTI_IMR1_IM7_Pos        (7U)
2616 #define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */
2617 #define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< CPU1 Interrupt Mask on line 7 */
2618 #define EXTI_IMR1_IM8_Pos        (8U)
2619 #define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */
2620 #define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< CPU1 Interrupt Mask on line 8 */
2621 #define EXTI_IMR1_IM9_Pos        (9U)
2622 #define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */
2623 #define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< CPU1 Interrupt Mask on line 9 */
2624 #define EXTI_IMR1_IM10_Pos       (10U)
2625 #define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */
2626 #define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< CPU1 Interrupt Mask on line 10 */
2627 #define EXTI_IMR1_IM11_Pos       (11U)
2628 #define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */
2629 #define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< CPU1 Interrupt Mask on line 11 */
2630 #define EXTI_IMR1_IM12_Pos       (12U)
2631 #define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */
2632 #define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< CPU1 Interrupt Mask on line 12 */
2633 #define EXTI_IMR1_IM13_Pos       (13U)
2634 #define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */
2635 #define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< CPU1 Interrupt Mask on line 13 */
2636 #define EXTI_IMR1_IM14_Pos       (14U)
2637 #define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */
2638 #define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< CPU1 Interrupt Mask on line 14 */
2639 #define EXTI_IMR1_IM15_Pos       (15U)
2640 #define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */
2641 #define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< CPU1 Interrupt Mask on line 15 */
2642 #define EXTI_IMR1_IM16_Pos       (16U)
2643 #define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */
2644 #define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< CPU1 Interrupt Mask on line 16 */
2645 #define EXTI_IMR1_IM17_Pos       (17U)
2646 #define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */
2647 #define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< CPU1 Interrupt Mask on line 17 */
2648 #define EXTI_IMR1_IM18_Pos       (18U)
2649 #define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */
2650 #define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< CPU1 Interrupt Mask on line 18 */
2651 #define EXTI_IMR1_IM19_Pos       (19U)
2652 #define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */
2653 #define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< CPU1 Interrupt Mask on line 19 */
2654 #define EXTI_IMR1_IM20_Pos       (20U)
2655 #define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */
2656 #define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< CPU1 Interrupt Mask on line 20 */
2657 #define EXTI_IMR1_IM22_Pos       (22U)
2658 #define EXTI_IMR1_IM22_Msk       (0x1UL << EXTI_IMR1_IM22_Pos)                 /*!< 0x00400000 */
2659 #define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< CPU1 Interrupt Mask on line 22 */
2660 #define EXTI_IMR1_IM24_Pos       (24U)
2661 #define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */
2662 #define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< CPU1 Interrupt Mask on line 24 */
2663 #define EXTI_IMR1_IM25_Pos       (25U)
2664 #define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */
2665 #define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< CPU1 Interrupt Mask on line 25 */
2666 #define EXTI_IMR1_IM29_Pos       (29U)
2667 #define EXTI_IMR1_IM29_Msk       (0x1UL << EXTI_IMR1_IM29_Pos)                 /*!< 0x20000000 */
2668 #define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< CPU1 Interrupt Mask on line 29 */
2669 #define EXTI_IMR1_IM30_Pos       (30U)
2670 #define EXTI_IMR1_IM30_Msk       (0x1UL << EXTI_IMR1_IM30_Pos)                 /*!< 0x40000000 */
2671 #define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< CPU1 Interrupt Mask on line 30 */
2672 #define EXTI_IMR1_IM31_Pos       (31U)
2673 #define EXTI_IMR1_IM31_Msk       (0x1UL << EXTI_IMR1_IM31_Pos)                 /*!< 0x80000000 */
2674 #define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< CPU1 Interrupt Mask on line 31 */
2675 
2676 /********************  Bits definition for EXTI_EMR1 register  ****************/
2677 #define EXTI_EMR1_Pos            (0U)
2678 #define EXTI_EMR1_Msk            (0x003EFFFFUL << EXTI_EMR1_Pos)               /*!< 0xFFFFFFFF */
2679 #define EXTI_EMR1_EM             EXTI_EMR1_Msk                                 /*!< CPU1 Event Mask */
2680 #define EXTI_EMR1_EM0_Pos        (0U)
2681 #define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */
2682 #define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< CPU1 Event Mask on line 0 */
2683 #define EXTI_EMR1_EM1_Pos        (1U)
2684 #define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */
2685 #define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< CPU1 Event Mask on line 1 */
2686 #define EXTI_EMR1_EM2_Pos        (2U)
2687 #define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */
2688 #define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< CPU1 Event Mask on line 2 */
2689 #define EXTI_EMR1_EM3_Pos        (3U)
2690 #define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */
2691 #define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< CPU1 Event Mask on line 3 */
2692 #define EXTI_EMR1_EM4_Pos        (4U)
2693 #define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */
2694 #define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< CPU1 Event Mask on line 4 */
2695 #define EXTI_EMR1_EM5_Pos        (5U)
2696 #define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */
2697 #define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< CPU1 Event Mask on line 5 */
2698 #define EXTI_EMR1_EM6_Pos        (6U)
2699 #define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */
2700 #define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< CPU1 Event Mask on line 6 */
2701 #define EXTI_EMR1_EM7_Pos        (7U)
2702 #define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */
2703 #define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< CPU1 Event Mask on line 7 */
2704 #define EXTI_EMR1_EM8_Pos        (8U)
2705 #define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */
2706 #define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< CPU1 Event Mask on line 8 */
2707 #define EXTI_EMR1_EM9_Pos        (9U)
2708 #define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */
2709 #define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< CPU1 Event Mask on line 9 */
2710 #define EXTI_EMR1_EM10_Pos       (10U)
2711 #define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */
2712 #define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< CPU1 Event Mask on line 10 */
2713 #define EXTI_EMR1_EM11_Pos       (11U)
2714 #define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */
2715 #define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< CPU1 Event Mask on line 11 */
2716 #define EXTI_EMR1_EM12_Pos       (12U)
2717 #define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */
2718 #define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< CPU1 Event Mask on line 12 */
2719 #define EXTI_EMR1_EM13_Pos       (13U)
2720 #define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */
2721 #define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< CPU1 Event Mask on line 13 */
2722 #define EXTI_EMR1_EM14_Pos       (14U)
2723 #define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */
2724 #define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< CPU1 Event Mask on line 14 */
2725 #define EXTI_EMR1_EM15_Pos       (15U)
2726 #define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */
2727 #define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< CPU1 Event Mask on line 15 */
2728 #define EXTI_EMR1_EM17_Pos       (17U)
2729 #define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */
2730 #define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< CPU1 Event Mask on line 17 */
2731 #define EXTI_EMR1_EM18_Pos       (18U)
2732 #define EXTI_EMR1_EM18_Msk       (0x1UL << EXTI_EMR1_EM18_Pos)                 /*!< 0x00040000 */
2733 #define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< CPU1 Event Mask on line 18 */
2734 #define EXTI_EMR1_EM19_Pos       (19U)
2735 #define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */
2736 #define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< CPU1 Event Mask on line 19 */
2737 #define EXTI_EMR1_EM20_Pos       (20U)
2738 #define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */
2739 #define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< CPU1 Event Mask on line 20 */
2740 
2741 /********************  Bits definition for EXTI_IMR2 register  ****************/
2742 #define EXTI_IMR2_Pos            (0U)
2743 #define EXTI_IMR2_Msk            (0x0001FFFFUL << EXTI_IMR2_Pos)               /*!< 0x0001FFFF */
2744 #define EXTI_IMR2_IM             EXTI_IMR2_Msk                                 /*!< CPU1 Interrupt Mask  */
2745 #define EXTI_IMR2_IM33_Pos       (1U)
2746 #define EXTI_IMR2_IM33_Msk       (0x1UL << EXTI_IMR2_IM33_Pos)                 /*!< 0x00000002 */
2747 #define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< CPU1 Interrupt Mask on line 33 */
2748 #define EXTI_IMR2_IM36_Pos       (4U)
2749 #define EXTI_IMR2_IM36_Msk       (0x1UL << EXTI_IMR2_IM36_Pos)                 /*!< 0x00000010 */
2750 #define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< CPU1 Interrupt Mask on line 36 */
2751 #define EXTI_IMR2_IM37_Pos       (5U)
2752 #define EXTI_IMR2_IM37_Msk       (0x1UL << EXTI_IMR2_IM37_Pos)                 /*!< 0x00000020 */
2753 #define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< CPU1 Interrupt Mask on line 37 */
2754 #define EXTI_IMR2_IM38_Pos       (6U)
2755 #define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */
2756 #define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< CPU1 Interrupt Mask on line 38 */
2757 #define EXTI_IMR2_IM39_Pos       (7U)
2758 #define EXTI_IMR2_IM39_Msk       (0x1UL << EXTI_IMR2_IM39_Pos)                 /*!< 0x00000080 */
2759 #define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< CPU1 Interrupt Mask on line 39 */
2760 #define EXTI_IMR2_IM40_Pos       (8U)
2761 #define EXTI_IMR2_IM40_Msk       (0x1UL << EXTI_IMR2_IM40_Pos)                 /*!< 0x00000100 */
2762 #define EXTI_IMR2_IM40           EXTI_IMR2_IM40_Msk                            /*!< CPU1 Interrupt Mask on line 40 */
2763 #define EXTI_IMR2_IM41_Pos       (9U)
2764 #define EXTI_IMR2_IM41_Msk       (0x1UL << EXTI_IMR2_IM41_Pos)                 /*!< 0x00000200 */
2765 #define EXTI_IMR2_IM41           EXTI_IMR2_IM41_Msk                            /*!< CPU1 Interrupt Mask on line 41 */
2766 #define EXTI_IMR2_IM42_Pos       (10U)
2767 #define EXTI_IMR2_IM42_Msk       (0x1UL << EXTI_IMR2_IM42_Pos)                 /*!< 0x00000400 */
2768 #define EXTI_IMR2_IM42           EXTI_IMR2_IM42_Msk                            /*!< CPU1 Interrupt Mask on line 42 */
2769 #define EXTI_IMR2_IM44_Pos       (12U)
2770 #define EXTI_IMR2_IM44_Msk       (0x1UL << EXTI_IMR2_IM44_Pos)                 /*!< 0x00001000 */
2771 #define EXTI_IMR2_IM44           EXTI_IMR2_IM44_Msk                            /*!< CPU1 Interrupt Mask on line 44 */
2772 #define EXTI_IMR2_IM45_Pos       (13U)
2773 #define EXTI_IMR2_IM45_Msk       (0x1UL << EXTI_IMR2_IM45_Pos)                 /*!< 0x00002000 */
2774 #define EXTI_IMR2_IM45           EXTI_IMR2_IM45_Msk                            /*!< CPU1 Interrupt Mask on line 45 */
2775 #define EXTI_IMR2_IM48_Pos       (16U)
2776 #define EXTI_IMR2_IM48_Msk       (0x1UL << EXTI_IMR2_IM48_Pos)                 /*!< 0x00010000 */
2777 #define EXTI_IMR2_IM48           EXTI_IMR2_IM48_Msk                            /*!< CPU1 Interrupt Mask on line 48 */
2778 
2779 /********************  Bits definition for EXTI_EMR2 register  ****************/
2780 #define EXTI_EMR2_Pos            (0U)
2781 #define EXTI_EMR2_Msk            (0x00000300UL << EXTI_EMR2_Pos)               /*!< 0x000003000 */
2782 #define EXTI_EMR2_EM             EXTI_EMR2_Msk                                 /*!< CPU1 Interrupt Mask  */
2783 #define EXTI_EMR2_EM40_Pos       (8U)
2784 #define EXTI_EMR2_EM40_Msk       (0x1UL << EXTI_EMR2_EM40_Pos)                 /*!< 0x00000100 */
2785 #define EXTI_EMR2_EM40           EXTI_EMR2_EM40_Msk                            /*!< CPU1 Event Mask on line 40 */
2786 #define EXTI_EMR2_EM41_Pos       (9U)
2787 #define EXTI_EMR2_EM41_Msk       (0x1UL << EXTI_EMR2_EM41_Pos)                 /*!< 0x00000200 */
2788 #define EXTI_EMR2_EM41           EXTI_EMR2_EM41_Msk                            /*!< CPU1 Event Mask on line 41 */
2789 
2790 /********************  Bits definition for EXTI_C2IMR1 register  **************/
2791 #define EXTI_C2IMR1_Pos          (0U)
2792 #define EXTI_C2IMR1_Msk          (0xFFFFFFFFUL << EXTI_C2IMR1_Pos)             /*!< 0xFFFFFFFF */
2793 #define EXTI_C2IMR1_IM           EXTI_C2IMR1_Msk                               /*!< CPU2 wakeup with interrupt Mask on Event */
2794 #define EXTI_C2IMR1_IM0_Pos      (0U)
2795 #define EXTI_C2IMR1_IM0_Msk      (0x1UL << EXTI_C2IMR1_IM0_Pos)                /*!< 0x00000001 */
2796 #define EXTI_C2IMR1_IM0          EXTI_C2IMR1_IM0_Msk                           /*!< CPU2 Interrupt Mask on line 0 */
2797 #define EXTI_C2IMR1_IM1_Pos      (1U)
2798 #define EXTI_C2IMR1_IM1_Msk      (0x1UL << EXTI_C2IMR1_IM1_Pos)                /*!< 0x00000002 */
2799 #define EXTI_C2IMR1_IM1          EXTI_C2IMR1_IM1_Msk                           /*!< CPU2 Interrupt Mask on line 1 */
2800 #define EXTI_C2IMR1_IM2_Pos      (2U)
2801 #define EXTI_C2IMR1_IM2_Msk      (0x1UL << EXTI_C2IMR1_IM2_Pos)                /*!< 0x00000004 */
2802 #define EXTI_C2IMR1_IM2          EXTI_C2IMR1_IM2_Msk                           /*!< CPU2 Interrupt Mask on line 2 */
2803 #define EXTI_C2IMR1_IM3_Pos      (3U)
2804 #define EXTI_C2IMR1_IM3_Msk      (0x1UL << EXTI_C2IMR1_IM3_Pos)                /*!< 0x00000008 */
2805 #define EXTI_C2IMR1_IM3          EXTI_C2IMR1_IM3_Msk                           /*!< CPU2 Interrupt Mask on line 3 */
2806 #define EXTI_C2IMR1_IM4_Pos      (4U)
2807 #define EXTI_C2IMR1_IM4_Msk      (0x1UL << EXTI_C2IMR1_IM4_Pos)                /*!< 0x00000010 */
2808 #define EXTI_C2IMR1_IM4          EXTI_C2IMR1_IM4_Msk                           /*!< CPU2 Interrupt Mask on line 4 */
2809 #define EXTI_C2IMR1_IM5_Pos      (5U)
2810 #define EXTI_C2IMR1_IM5_Msk      (0x1UL << EXTI_C2IMR1_IM5_Pos)                /*!< 0x00000020 */
2811 #define EXTI_C2IMR1_IM5          EXTI_C2IMR1_IM5_Msk                           /*!< CPU2 Interrupt Mask on line 5 */
2812 #define EXTI_C2IMR1_IM6_Pos      (6U)
2813 #define EXTI_C2IMR1_IM6_Msk      (0x1UL << EXTI_C2IMR1_IM6_Pos)                /*!< 0x00000040 */
2814 #define EXTI_C2IMR1_IM6          EXTI_C2IMR1_IM6_Msk                           /*!< CPU2 Interrupt Mask on line 6 */
2815 #define EXTI_C2IMR1_IM7_Pos      (7U)
2816 #define EXTI_C2IMR1_IM7_Msk      (0x1UL << EXTI_C2IMR1_IM7_Pos)                /*!< 0x00000080 */
2817 #define EXTI_C2IMR1_IM7          EXTI_C2IMR1_IM7_Msk                           /*!< CPU2 Interrupt Mask on line 7 */
2818 #define EXTI_C2IMR1_IM8_Pos      (8U)
2819 #define EXTI_C2IMR1_IM8_Msk      (0x1UL << EXTI_C2IMR1_IM8_Pos)                /*!< 0x00000100 */
2820 #define EXTI_C2IMR1_IM8          EXTI_C2IMR1_IM8_Msk                           /*!< CPU2 Interrupt Mask on line 8 */
2821 #define EXTI_C2IMR1_IM9_Pos      (9U)
2822 #define EXTI_C2IMR1_IM9_Msk      (0x1UL << EXTI_C2IMR1_IM9_Pos)                /*!< 0x00000200 */
2823 #define EXTI_C2IMR1_IM9          EXTI_C2IMR1_IM9_Msk                           /*!< CPU2 Interrupt Mask on line 9 */
2824 #define EXTI_C2IMR1_IM10_Pos     (10U)
2825 #define EXTI_C2IMR1_IM10_Msk     (0x1UL << EXTI_C2IMR1_IM10_Pos)               /*!< 0x00000400 */
2826 #define EXTI_C2IMR1_IM10         EXTI_C2IMR1_IM10_Msk                          /*!< CPU2 Interrupt Mask on line 10 */
2827 #define EXTI_C2IMR1_IM11_Pos     (11U)
2828 #define EXTI_C2IMR1_IM11_Msk     (0x1UL << EXTI_C2IMR1_IM11_Pos)               /*!< 0x00000800 */
2829 #define EXTI_C2IMR1_IM11         EXTI_C2IMR1_IM11_Msk                          /*!< CPU2 Interrupt Mask on line 11 */
2830 #define EXTI_C2IMR1_IM12_Pos     (12U)
2831 #define EXTI_C2IMR1_IM12_Msk     (0x1UL << EXTI_C2IMR1_IM12_Pos)               /*!< 0x00001000 */
2832 #define EXTI_C2IMR1_IM12         EXTI_C2IMR1_IM12_Msk                          /*!< CPU2 Interrupt Mask on line 12 */
2833 #define EXTI_C2IMR1_IM13_Pos     (13U)
2834 #define EXTI_C2IMR1_IM13_Msk     (0x1UL << EXTI_C2IMR1_IM13_Pos)               /*!< 0x00002000 */
2835 #define EXTI_C2IMR1_IM13         EXTI_C2IMR1_IM13_Msk                          /*!< CPU2 Interrupt Mask on line 13 */
2836 #define EXTI_C2IMR1_IM14_Pos     (14U)
2837 #define EXTI_C2IMR1_IM14_Msk     (0x1UL << EXTI_C2IMR1_IM14_Pos)               /*!< 0x00004000 */
2838 #define EXTI_C2IMR1_IM14         EXTI_C2IMR1_IM14_Msk                          /*!< CPU2 Interrupt Mask on line 14 */
2839 #define EXTI_C2IMR1_IM15_Pos     (15U)
2840 #define EXTI_C2IMR1_IM15_Msk     (0x1UL << EXTI_C2IMR1_IM15_Pos)               /*!< 0x00008000 */
2841 #define EXTI_C2IMR1_IM15         EXTI_C2IMR1_IM15_Msk                          /*!< CPU2 Interrupt Mask on line 15 */
2842 #define EXTI_C2IMR1_IM16_Pos     (16U)
2843 #define EXTI_C2IMR1_IM16_Msk     (0x1UL << EXTI_C2IMR1_IM16_Pos)               /*!< 0x00010000 */
2844 #define EXTI_C2IMR1_IM16         EXTI_C2IMR1_IM16_Msk                          /*!< CPU2 Interrupt Mask on line 16 */
2845 #define EXTI_C2IMR1_IM17_Pos     (17U)
2846 #define EXTI_C2IMR1_IM17_Msk     (0x1UL << EXTI_C2IMR1_IM17_Pos)               /*!< 0x00020000 */
2847 #define EXTI_C2IMR1_IM17         EXTI_C2IMR1_IM17_Msk                          /*!< CPU2 Interrupt Mask on line 17 */
2848 #define EXTI_C2IMR1_IM18_Pos     (18U)
2849 #define EXTI_C2IMR1_IM18_Msk     (0x1UL << EXTI_C2IMR1_IM18_Pos)               /*!< 0x00040000 */
2850 #define EXTI_C2IMR1_IM18         EXTI_C2IMR1_IM18_Msk                          /*!< CPU2 Interrupt Mask on line 18 */
2851 #define EXTI_C2IMR1_IM19_Pos     (19U)
2852 #define EXTI_C2IMR1_IM19_Msk     (0x1UL << EXTI_C2IMR1_IM19_Pos)               /*!< 0x00080000 */
2853 #define EXTI_C2IMR1_IM19         EXTI_C2IMR1_IM19_Msk                          /*!< CPU2 Interrupt Mask on line 19 */
2854 #define EXTI_C2IMR1_IM20_Pos     (20U)
2855 #define EXTI_C2IMR1_IM20_Msk     (0x1UL << EXTI_C2IMR1_IM20_Pos)               /*!< 0x00100000 */
2856 #define EXTI_C2IMR1_IM20         EXTI_C2IMR1_IM20_Msk                          /*!< CPU2 Interrupt Mask on line 20 */
2857 #define EXTI_C2IMR1_IM22_Pos     (22U)
2858 #define EXTI_C2IMR1_IM22_Msk     (0x1UL << EXTI_C2IMR1_IM22_Pos)               /*!< 0x00400000 */
2859 #define EXTI_C2IMR1_IM22         EXTI_C2IMR1_IM22_Msk                          /*!< CPU2 Interrupt Mask on line 22 */
2860 #define EXTI_C2IMR1_IM24_Pos     (24U)
2861 #define EXTI_C2IMR1_IM24_Msk     (0x1UL << EXTI_C2IMR1_IM24_Pos)               /*!< 0x01000000 */
2862 #define EXTI_C2IMR1_IM24         EXTI_C2IMR1_IM24_Msk                          /*!< CPU2 Interrupt Mask on line 24 */
2863 #define EXTI_C2IMR1_IM25_Pos     (25U)
2864 #define EXTI_C2IMR1_IM25_Msk     (0x1UL << EXTI_C2IMR1_IM25_Pos)               /*!< 0x02000000 */
2865 #define EXTI_C2IMR1_IM25         EXTI_C2IMR1_IM25_Msk                          /*!< CPU2 Interrupt Mask on line 25 */
2866 #define EXTI_C2IMR1_IM29_Pos     (29U)
2867 #define EXTI_C2IMR1_IM29_Msk     (0x1UL << EXTI_C2IMR1_IM29_Pos)               /*!< 0x20000000 */
2868 #define EXTI_C2IMR1_IM29         EXTI_C2IMR1_IM29_Msk                          /*!< CPU2 Interrupt Mask on line 29 */
2869 #define EXTI_C2IMR1_IM30_Pos     (30U)
2870 #define EXTI_C2IMR1_IM30_Msk     (0x1UL << EXTI_C2IMR1_IM30_Pos)               /*!< 0x40000000 */
2871 #define EXTI_C2IMR1_IM30         EXTI_C2IMR1_IM30_Msk                          /*!< CPU2 Interrupt Mask on line 30 */
2872 #define EXTI_C2IMR1_IM31_Pos     (31U)
2873 #define EXTI_C2IMR1_IM31_Msk     (0x1UL << EXTI_C2IMR1_IM31_Pos)               /*!< 0x80000000 */
2874 #define EXTI_C2IMR1_IM31         EXTI_C2IMR1_IM31_Msk                          /*!< CPU2 Interrupt Mask on line 31 */
2875 
2876 /********************  Bits definition for EXTI_C2EMR1 register  **************/
2877 #define EXTI_C2EMR1_Pos          (0U)
2878 #define EXTI_C2EMR1_Msk          (0x003EFFFFUL << EXTI_C2EMR1_Pos)             /*!< 0xFFFFFFFF */
2879 #define EXTI_C2EMR1_EM           EXTI_C2EMR1_Msk                               /*!< CPU2 Event Mask */
2880 #define EXTI_C2EMR1_EM0_Pos      (0U)
2881 #define EXTI_C2EMR1_EM0_Msk      (0x1UL << EXTI_C2EMR1_EM0_Pos)                /*!< 0x00000001 */
2882 #define EXTI_C2EMR1_EM0          EXTI_C2EMR1_EM0_Msk                           /*!< CPU2 Event Mask on line 0 */
2883 #define EXTI_C2EMR1_EM1_Pos      (1U)
2884 #define EXTI_C2EMR1_EM1_Msk      (0x1UL << EXTI_C2EMR1_EM1_Pos)                /*!< 0x00000002 */
2885 #define EXTI_C2EMR1_EM1          EXTI_C2EMR1_EM1_Msk                           /*!< CPU2 Event Mask on line 1 */
2886 #define EXTI_C2EMR1_EM2_Pos      (2U)
2887 #define EXTI_C2EMR1_EM2_Msk      (0x1UL << EXTI_C2EMR1_EM2_Pos)                /*!< 0x00000004 */
2888 #define EXTI_C2EMR1_EM2          EXTI_C2EMR1_EM2_Msk                           /*!< CPU2 Event Mask on line 2 */
2889 #define EXTI_C2EMR1_EM3_Pos      (3U)
2890 #define EXTI_C2EMR1_EM3_Msk      (0x1UL << EXTI_C2EMR1_EM3_Pos)                /*!< 0x00000008 */
2891 #define EXTI_C2EMR1_EM3          EXTI_C2EMR1_EM3_Msk                           /*!< CPU2 Event Mask on line 3 */
2892 #define EXTI_C2EMR1_EM4_Pos      (4U)
2893 #define EXTI_C2EMR1_EM4_Msk      (0x1UL << EXTI_C2EMR1_EM4_Pos)                /*!< 0x00000010 */
2894 #define EXTI_C2EMR1_EM4          EXTI_C2EMR1_EM4_Msk                           /*!< CPU2 Event Mask on line 4 */
2895 #define EXTI_C2EMR1_EM5_Pos      (5U)
2896 #define EXTI_C2EMR1_EM5_Msk      (0x1UL << EXTI_C2EMR1_EM5_Pos)                /*!< 0x00000020 */
2897 #define EXTI_C2EMR1_EM5          EXTI_C2EMR1_EM5_Msk                           /*!< CPU2 Event Mask on line 5 */
2898 #define EXTI_C2EMR1_EM6_Pos      (6U)
2899 #define EXTI_C2EMR1_EM6_Msk      (0x1UL << EXTI_C2EMR1_EM6_Pos)                /*!< 0x00000040 */
2900 #define EXTI_C2EMR1_EM6          EXTI_C2EMR1_EM6_Msk                           /*!< CPU2 Event Mask on line 6 */
2901 #define EXTI_C2EMR1_EM7_Pos      (7U)
2902 #define EXTI_C2EMR1_EM7_Msk      (0x1UL << EXTI_C2EMR1_EM7_Pos)                /*!< 0x00000080 */
2903 #define EXTI_C2EMR1_EM7          EXTI_C2EMR1_EM7_Msk                           /*!< CPU2 Event Mask on line 7 */
2904 #define EXTI_C2EMR1_EM8_Pos      (8U)
2905 #define EXTI_C2EMR1_EM8_Msk      (0x1UL << EXTI_C2EMR1_EM8_Pos)                /*!< 0x00000100 */
2906 #define EXTI_C2EMR1_EM8          EXTI_C2EMR1_EM8_Msk                           /*!< CPU2 Event Mask on line 8 */
2907 #define EXTI_C2EMR1_EM9_Pos      (9U)
2908 #define EXTI_C2EMR1_EM9_Msk      (0x1UL << EXTI_C2EMR1_EM9_Pos)                /*!< 0x00000200 */
2909 #define EXTI_C2EMR1_EM9          EXTI_C2EMR1_EM9_Msk                           /*!< CPU2 Event Mask on line 9 */
2910 #define EXTI_C2EMR1_EM10_Pos     (10U)
2911 #define EXTI_C2EMR1_EM10_Msk     (0x1UL << EXTI_C2EMR1_EM10_Pos)               /*!< 0x00000400 */
2912 #define EXTI_C2EMR1_EM10         EXTI_C2EMR1_EM10_Msk                          /*!< CPU2 Event Mask on line 10 */
2913 #define EXTI_C2EMR1_EM11_Pos     (11U)
2914 #define EXTI_C2EMR1_EM11_Msk     (0x1UL << EXTI_C2EMR1_EM11_Pos)               /*!< 0x00000800 */
2915 #define EXTI_C2EMR1_EM11         EXTI_C2EMR1_EM11_Msk                          /*!< CPU2 Event Mask on line 11 */
2916 #define EXTI_C2EMR1_EM12_Pos     (12U)
2917 #define EXTI_C2EMR1_EM12_Msk     (0x1UL << EXTI_C2EMR1_EM12_Pos)               /*!< 0x00001000 */
2918 #define EXTI_C2EMR1_EM12         EXTI_C2EMR1_EM12_Msk                          /*!< CPU2 Event Mask on line 12 */
2919 #define EXTI_C2EMR1_EM13_Pos     (13U)
2920 #define EXTI_C2EMR1_EM13_Msk     (0x1UL << EXTI_C2EMR1_EM13_Pos)               /*!< 0x00002000 */
2921 #define EXTI_C2EMR1_EM13         EXTI_C2EMR1_EM13_Msk                          /*!< CPU2 Event Mask on line 13 */
2922 #define EXTI_C2EMR1_EM14_Pos     (14U)
2923 #define EXTI_C2EMR1_EM14_Msk     (0x1UL << EXTI_C2EMR1_EM14_Pos)               /*!< 0x00004000 */
2924 #define EXTI_C2EMR1_EM14         EXTI_C2EMR1_EM14_Msk                          /*!< CPU2 Event Mask on line 14 */
2925 #define EXTI_C2EMR1_EM15_Pos     (15U)
2926 #define EXTI_C2EMR1_EM15_Msk     (0x1UL << EXTI_C2EMR1_EM15_Pos)               /*!< 0x00008000 */
2927 #define EXTI_C2EMR1_EM15         EXTI_C2EMR1_EM15_Msk                          /*!< CPU2 Event Mask on line 15 */
2928 #define EXTI_C2EMR1_EM17_Pos     (17U)
2929 #define EXTI_C2EMR1_EM17_Msk     (0x1UL << EXTI_C2EMR1_EM17_Pos)               /*!< 0x00020000 */
2930 #define EXTI_C2EMR1_EM17         EXTI_C2EMR1_EM17_Msk                          /*!< CPU2 Event Mask on line 17 */
2931 #define EXTI_C2EMR1_EM18_Pos     (18U)
2932 #define EXTI_C2EMR1_EM18_Msk     (0x1UL << EXTI_C2EMR1_EM18_Pos)               /*!< 0x00040000 */
2933 #define EXTI_C2EMR1_EM18         EXTI_C2EMR1_EM18_Msk                          /*!< CPU2 Event Mask on line 18 */
2934 #define EXTI_C2EMR1_EM19_Pos     (19U)
2935 #define EXTI_C2EMR1_EM19_Msk     (0x1UL << EXTI_C2EMR1_EM19_Pos)               /*!< 0x00080000 */
2936 #define EXTI_C2EMR1_EM19         EXTI_C2EMR1_EM19_Msk                          /*!< CPU2 Event Mask on line 19 */
2937 #define EXTI_C2EMR1_EM20_Pos     (20U)
2938 #define EXTI_C2EMR1_EM20_Msk     (0x1UL << EXTI_C2EMR1_EM20_Pos)               /*!< 0x00100000 */
2939 #define EXTI_C2EMR1_EM20         EXTI_C2EMR1_EM20_Msk                          /*!< CPU2 Event Mask on line 20 */
2940 
2941 /********************  Bits definition for EXTI_C2IMR2 register  **************/
2942 #define EXTI_C2IMR2_Pos          (0U)
2943 #define EXTI_C2IMR2_Msk          (0x0001FFFFUL << EXTI_C2IMR2_Pos)             /*!< 0x0001FFFF */
2944 #define EXTI_C2IMR2_IM           EXTI_C2IMR2_Msk                               /*!< CPU2 Interrupt Mask  */
2945 #define EXTI_C2IMR2_IM33_Pos     (1U)
2946 #define EXTI_C2IMR2_IM33_Msk     (0x1UL << EXTI_C2IMR2_IM33_Pos)               /*!< 0x00000002 */
2947 #define EXTI_C2IMR2_IM33         EXTI_C2IMR2_IM33_Msk                          /*!< CPU2 Interrupt Mask on line 33 */
2948 #define EXTI_C2IMR2_IM36_Pos     (4U)
2949 #define EXTI_C2IMR2_IM36_Msk     (0x1UL << EXTI_C2IMR2_IM36_Pos)               /*!< 0x00000010 */
2950 #define EXTI_C2IMR2_IM36         EXTI_C2IMR2_IM36_Msk                          /*!< CPU2 Interrupt Mask on line 36 */
2951 #define EXTI_C2IMR2_IM37_Pos     (5U)
2952 #define EXTI_C2IMR2_IM37_Msk     (0x1UL << EXTI_C2IMR2_IM37_Pos)               /*!< 0x00000020 */
2953 #define EXTI_C2IMR2_IM37         EXTI_C2IMR2_IM37_Msk                          /*!< CPU2 Interrupt Mask on line 37 */
2954 #define EXTI_C2IMR2_IM38_Pos     (6U)
2955 #define EXTI_C2IMR2_IM38_Msk     (0x1UL << EXTI_C2IMR2_IM38_Pos)               /*!< 0x00000040 */
2956 #define EXTI_C2IMR2_IM38         EXTI_C2IMR2_IM38_Msk                          /*!< CPU2 Interrupt Mask on line 38 */
2957 #define EXTI_C2IMR2_IM39_Pos     (7U)
2958 #define EXTI_C2IMR2_IM39_Msk     (0x1UL << EXTI_C2IMR2_IM39_Pos)               /*!< 0x00000080 */
2959 #define EXTI_C2IMR2_IM39         EXTI_C2IMR2_IM39_Msk                          /*!< CPU2 Interrupt Mask on line 39 */
2960 #define EXTI_C2IMR2_IM40_Pos     (8U)
2961 #define EXTI_C2IMR2_IM40_Msk     (0x1UL << EXTI_C2IMR2_IM40_Pos)               /*!< 0x00000100 */
2962 #define EXTI_C2IMR2_IM40         EXTI_C2IMR2_IM40_Msk                          /*!< CPU2 Interrupt Mask on line 40 */
2963 #define EXTI_C2IMR2_IM41_Pos     (9U)
2964 #define EXTI_C2IMR2_IM41_Msk     (0x1UL << EXTI_C2IMR2_IM41_Pos)               /*!< 0x00000200 */
2965 #define EXTI_C2IMR2_IM41         EXTI_C2IMR2_IM41_Msk                          /*!< CPU2 Interrupt Mask on line 41 */
2966 #define EXTI_C2IMR2_IM42_Pos     (10U)
2967 #define EXTI_C2IMR2_IM42_Msk     (0x1UL << EXTI_C2IMR2_IM42_Pos)               /*!< 0x00000400 */
2968 #define EXTI_C2IMR2_IM42         EXTI_C2IMR2_IM42_Msk                          /*!< CPU2 Interrupt Mask on line 42 */
2969 #define EXTI_C2IMR2_IM44_Pos     (12U)
2970 #define EXTI_C2IMR2_IM44_Msk     (0x1UL << EXTI_C2IMR2_IM44_Pos)               /*!< 0x00001000 */
2971 #define EXTI_C2IMR2_IM44         EXTI_C2IMR2_IM44_Msk                          /*!< CPU2 Interrupt Mask on line 44 */
2972 #define EXTI_C2IMR2_IM45_Pos     (13U)
2973 #define EXTI_C2IMR2_IM45_Msk     (0x1UL << EXTI_C2IMR2_IM45_Pos)               /*!< 0x00002000 */
2974 #define EXTI_C2IMR2_IM45         EXTI_C2IMR2_IM45_Msk                          /*!< CPU2 Interrupt Mask on line 45 */
2975 #define EXTI_C2IMR2_IM48_Pos     (16U)
2976 #define EXTI_C2IMR2_IM48_Msk     (0x1UL << EXTI_C2IMR2_IM48_Pos)               /*!< 0x00010000 */
2977 #define EXTI_C2IMR2_IM48         EXTI_C2IMR2_IM48_Msk                          /*!< CPU2 Interrupt Mask on line 48 */
2978 
2979 /********************  Bits definition for EXTI_C2EMR2 register  **************/
2980 #define EXTI_C2EMR2_Pos          (8U)
2981 #define EXTI_C2EMR2_Msk          (0x00000300UL << EXTI_C2EMR2_Pos)             /*!< 0x000003000 */
2982 #define EXTI_C2EMR2_EM           EXTI_C2EMR2_Msk                               /*!< CPU2 Interrupt Mask  */
2983 #define EXTI_C2EMR2_EM40_Pos     (8U)
2984 #define EXTI_C2EMR2_EM40_Msk     (0x1UL << EXTI_C2EMR2_EM40_Pos)               /*!< 0x00000100 */
2985 #define EXTI_C2EMR2_EM40         EXTI_C2EMR2_EM40_Msk                          /*!< CPU2 Event Mask on line 40 */
2986 #define EXTI_C2EMR2_EM41_Pos     (9U)
2987 #define EXTI_C2EMR2_EM41_Msk     (0x1UL << EXTI_C2EMR2_EM41_Pos)               /*!< 0x00000200 */
2988 #define EXTI_C2EMR2_EM41         EXTI_C2EMR2_EM41_Msk                          /*!< CPU2 Event Mask on line 41 */
2989 
2990 /******************************************************************************/
2991 /*                                                                            */
2992 /*                       Public Key Accelerator (PKA)                         */
2993 /*                                                                            */
2994 /******************************************************************************/
2995 
2996 /*******************  Bits definition for PKA_CR register  **************/
2997 #define PKA_CR_EN_Pos              (0U)
2998 #define PKA_CR_EN_Msk              (0x1UL << PKA_CR_EN_Pos)                /*!< 0x00000001 */
2999 #define PKA_CR_EN                  PKA_CR_EN_Msk                           /*!< PKA enable */
3000 #define PKA_CR_START_Pos           (1U)
3001 #define PKA_CR_START_Msk           (0x1UL << PKA_CR_START_Pos)             /*!< 0x00000002 */
3002 #define PKA_CR_START               PKA_CR_START_Msk                        /*!< Start operation */
3003 #define PKA_CR_MODE_Pos            (8U)
3004 #define PKA_CR_MODE_Msk            (0x3FUL << PKA_CR_MODE_Pos)             /*!< 0x00003F00 */
3005 #define PKA_CR_MODE                PKA_CR_MODE_Msk                         /*!< MODE[5:0] PKA operation code */
3006 #define PKA_CR_MODE_0              (0x01U << PKA_CR_MODE_Pos)              /*!< 0x00000100 */
3007 #define PKA_CR_MODE_1              (0x02U << PKA_CR_MODE_Pos)              /*!< 0x00000200 */
3008 #define PKA_CR_MODE_2              (0x04U << PKA_CR_MODE_Pos)              /*!< 0x00000400 */
3009 #define PKA_CR_MODE_3              (0x08U << PKA_CR_MODE_Pos)              /*!< 0x00000800 */
3010 #define PKA_CR_MODE_4              (0x10U << PKA_CR_MODE_Pos)              /*!< 0x00001000 */
3011 #define PKA_CR_MODE_5              (0x20U << PKA_CR_MODE_Pos)              /*!< 0x00002000 */
3012 #define PKA_CR_PROCENDIE_Pos       (17U)
3013 #define PKA_CR_PROCENDIE_Msk       (0x1UL << PKA_CR_PROCENDIE_Pos)         /*!< 0x00020000 */
3014 #define PKA_CR_PROCENDIE           PKA_CR_PROCENDIE_Msk                    /*!< End of operation interrupt enable */
3015 #define PKA_CR_RAMERRIE_Pos        (19U)
3016 #define PKA_CR_RAMERRIE_Msk        (0x1UL << PKA_CR_RAMERRIE_Pos)          /*!< 0x00080000 */
3017 #define PKA_CR_RAMERRIE            PKA_CR_RAMERRIE_Msk                     /*!< RAM error interrupt enable */
3018 #define PKA_CR_ADDRERRIE_Pos       (20U)
3019 #define PKA_CR_ADDRERRIE_Msk       (0x1UL << PKA_CR_ADDRERRIE_Pos)         /*!< 0x00100000 */
3020 #define PKA_CR_ADDRERRIE           PKA_CR_ADDRERRIE_Msk                    /*!< RAM error interrupt enable */
3021 
3022 /*******************  Bits definition for PKA_SR register  **************/
3023 #define PKA_SR_BUSY_Pos            (16U)
3024 #define PKA_SR_BUSY_Msk            (0x1UL << PKA_SR_BUSY_Pos)              /*!< 0x00010000 */
3025 #define PKA_SR_BUSY                PKA_SR_BUSY_Msk                         /*!< PKA operation is in progress */
3026 #define PKA_SR_PROCENDF_Pos        (17U)
3027 #define PKA_SR_PROCENDF_Msk        (0x1UL << PKA_SR_PROCENDF_Pos)          /*!< 0x00020000 */
3028 #define PKA_SR_PROCENDF            PKA_SR_PROCENDF_Msk                     /*!< PKA end of operation flag */
3029 #define PKA_SR_RAMERRF_Pos         (19U)
3030 #define PKA_SR_RAMERRF_Msk         (0x1UL << PKA_SR_RAMERRF_Pos)           /*!< 0x00080000 */
3031 #define PKA_SR_RAMERRF             PKA_SR_RAMERRF_Msk                      /*!< PKA RAM error flag */
3032 #define PKA_SR_ADDRERRF_Pos        (20U)
3033 #define PKA_SR_ADDRERRF_Msk        (0x1UL << PKA_SR_ADDRERRF_Pos)          /*!< 0x00100000 */
3034 #define PKA_SR_ADDRERRF            PKA_SR_ADDRERRF_Msk                     /*!< Address error flag */
3035 
3036 /*******************  Bits definition for PKA_CLRFR register  **************/
3037 #define PKA_CLRFR_PROCENDFC_Pos    (17U)
3038 #define PKA_CLRFR_PROCENDFC_Msk    (0x1UL << PKA_CLRFR_PROCENDFC_Pos)      /*!< 0x00020000 */
3039 #define PKA_CLRFR_PROCENDFC        PKA_CLRFR_PROCENDFC_Msk                 /*!< Clear PKA end of operation flag */
3040 #define PKA_CLRFR_RAMERRFC_Pos     (19U)
3041 #define PKA_CLRFR_RAMERRFC_Msk     (0x1UL << PKA_CLRFR_RAMERRFC_Pos)       /*!< 0x00080000 */
3042 #define PKA_CLRFR_RAMERRFC         PKA_CLRFR_RAMERRFC_Msk                  /*!< Clear PKA RAM error flag */
3043 #define PKA_CLRFR_ADDRERRFC_Pos    (20U)
3044 #define PKA_CLRFR_ADDRERRFC_Msk    (0x1UL << PKA_CLRFR_ADDRERRFC_Pos)      /*!< 0x00100000 */
3045 #define PKA_CLRFR_ADDRERRFC        PKA_CLRFR_ADDRERRFC_Msk                 /*!< Clear address error flag */
3046 
3047 /*******************  Bits definition for PKA RAM  *************************/
3048 #define PKA_RAM_OFFSET                            0x400U                           /*!< PKA RAM address offset */
3049 
3050 /* Compute Montgomery parameter input data */
3051 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS       ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
3052 #define PKA_MONTGOMERY_PARAM_IN_MODULUS           ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
3053 
3054 /* Compute Montgomery parameter output data */
3055 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER        ((0x594U - PKA_RAM_OFFSET)>>2)   /*!< Output Montgomery parameter */
3056 
3057 /* Compute modular exponentiation input data */
3058 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS            ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input exponent number of bits */
3059 #define PKA_MODULAR_EXP_IN_OP_NB_BITS             ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
3060 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM       ((0x594U - PKA_RAM_OFFSET)>>2)   /*!< Input storage area for Montgomery parameter */
3061 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE          ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input base of the exponentiation */
3062 #define PKA_MODULAR_EXP_IN_EXPONENT               ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Input exponent to process */
3063 #define PKA_MODULAR_EXP_IN_MODULUS                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
3064 
3065 /* Compute modular exponentiation output data */
3066 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM      ((0x594U - PKA_RAM_OFFSET)>>2)   /*!< Output storage area for Montgomery parameter */
3067 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1          ((0x724U - PKA_RAM_OFFSET)>>2)   /*!< Output SM algorithm accumulator 1 */
3068 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2          ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Output SM algorithm accumulator 2 */
3069 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE         ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Output base of the exponentiation */
3070 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3          ((0xE3CU - PKA_RAM_OFFSET)>>2)   /*!< Output SM algorithm accumulator 3 */
3071 
3072 /* Compute ECC scalar multiplication input data */
3073 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS         ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input exponent number of bits */
3074 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS          ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
3075 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN        ((0x408U - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
3076 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF             ((0x40CU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
3077 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF              ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
3078 #define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM    ((0x4B4U - PKA_RAM_OFFSET)>>2)   /*!< Input storage area for Montgomery parameter */
3079 #define PKA_ECC_SCALAR_MUL_IN_K                   ((0x508U - PKA_RAM_OFFSET)>>2)   /*!< Input 'k' of KP */
3080 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X     ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
3081 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y     ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
3082 
3083 /* Compute ECC scalar multiplication output data */
3084 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X           ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Output result X coordinate */
3085 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y           ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Output result Y coordinate */
3086 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1     ((0xDE8U - PKA_RAM_OFFSET)>>2)   /*!< Output last double X1 coordinate */
3087 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1     ((0xE3CU - PKA_RAM_OFFSET)>>2)   /*!< Output last double Y1 coordinate */
3088 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1     ((0xE90U - PKA_RAM_OFFSET)>>2)   /*!< Output last double Z1 coordinate */
3089 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2     ((0xEE4U - PKA_RAM_OFFSET)>>2)   /*!< Output check point X2 coordinate */
3090 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2     ((0xF38U - PKA_RAM_OFFSET)>>2)   /*!< Output check point Y2 coordinate */
3091 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2     ((0xF8CU - PKA_RAM_OFFSET)>>2)   /*!< Output check point Z2 coordinate */
3092 
3093 /* Point check input data */
3094 #define PKA_POINT_CHECK_IN_MOD_NB_BITS            ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
3095 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN           ((0x408U - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
3096 #define PKA_POINT_CHECK_IN_A_COEFF                ((0x40CU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
3097 #define PKA_POINT_CHECK_IN_B_COEFF                ((0x7FCU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'b' coefficient */
3098 #define PKA_POINT_CHECK_IN_MOD_GF                 ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
3099 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X        ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
3100 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y        ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
3101 
3102 /* Point check output data */
3103 #define PKA_POINT_CHECK_OUT_ERROR                 ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Output error */
3104 
3105 /* ECDSA signature input data */
3106 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS           ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input order number of bits */
3107 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS             ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
3108 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN            ((0x408U - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
3109 #define PKA_ECDSA_SIGN_IN_A_COEFF                 ((0x40CU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
3110 #define PKA_ECDSA_SIGN_IN_MOD_GF                  ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
3111 #define PKA_ECDSA_SIGN_IN_K                       ((0x508U - PKA_RAM_OFFSET)>>2)   /*!< Input k value of the ECDSA */
3112 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X         ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
3113 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y         ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
3114 #define PKA_ECDSA_SIGN_IN_HASH_E                  ((0xDE8U - PKA_RAM_OFFSET)>>2)   /*!< Input e, hash of the message */
3115 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D           ((0xE3CU - PKA_RAM_OFFSET)>>2)   /*!< Input d, private key */
3116 #define PKA_ECDSA_SIGN_IN_ORDER_N                 ((0xE94U - PKA_RAM_OFFSET)>>2)   /*!< Input n, order of the curve */
3117 
3118 /* ECDSA signature output data */
3119 #define PKA_ECDSA_SIGN_OUT_ERROR                  ((0xEE8U - PKA_RAM_OFFSET)>>2)   /*!< Output error */
3120 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R            ((0x700U - PKA_RAM_OFFSET)>>2)   /*!< Output signature r */
3121 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S            ((0x754U - PKA_RAM_OFFSET)>>2)   /*!< Output signature s */
3122 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X          ((0x103CU - PKA_RAM_OFFSET)>>2)  /*!< Output final point kP X coordinate */
3123 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y          ((0x1090U - PKA_RAM_OFFSET)>>2)  /*!< Output final point kP Y coordinate */
3124 
3125 /* ECDSA verification input data */
3126 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS          ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input order number of bits */
3127 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS            ((0x4B4U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
3128 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN           ((0x45CU - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
3129 #define PKA_ECDSA_VERIF_IN_A_COEFF                ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
3130 #define PKA_ECDSA_VERIF_IN_MOD_GF                 ((0x4B8U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
3131 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X        ((0x5E8U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
3132 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y        ((0x63CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
3133 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X     ((0xF40U - PKA_RAM_OFFSET)>>2)   /*!< Input public key point X coordinate */
3134 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y     ((0xF94U - PKA_RAM_OFFSET)>>2)   /*!< Input public key point Y coordinate */
3135 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R            ((0x1098U - PKA_RAM_OFFSET)>>2)  /*!< Input r, part of the signature */
3136 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S            ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input s, part of the signature */
3137 #define PKA_ECDSA_VERIF_IN_HASH_E                 ((0xFE8U - PKA_RAM_OFFSET)>>2)   /*!< Input e, hash of the message */
3138 #define PKA_ECDSA_VERIF_IN_ORDER_N                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input n, order of the curve */
3139 
3140 /* ECDSA verification output data */
3141 #define PKA_ECDSA_VERIF_OUT_RESULT                ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
3142 
3143 /* RSA CRT exponentiation input data */
3144 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS            ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operands number of bits */
3145 #define PKA_RSA_CRT_EXP_IN_DP_CRT                 ((0x65CU - PKA_RAM_OFFSET)>>2)   /*!< Input Dp CRT parameter */
3146 #define PKA_RSA_CRT_EXP_IN_DQ_CRT                 ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Input Dq CRT parameter */
3147 #define PKA_RSA_CRT_EXP_IN_QINV_CRT               ((0x7ECU - PKA_RAM_OFFSET)>>2)   /*!< Input qInv CRT parameter */
3148 #define PKA_RSA_CRT_EXP_IN_PRIME_P                ((0x97CU - PKA_RAM_OFFSET)>>2)   /*!< Input Prime p */
3149 #define PKA_RSA_CRT_EXP_IN_PRIME_Q                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input Prime q */
3150 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE          ((0xEECU - PKA_RAM_OFFSET)>>2)   /*!< Input base of the exponentiation */
3151 
3152 /* RSA CRT exponentiation output data */
3153 #define PKA_RSA_CRT_EXP_OUT_RESULT                ((0x724U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
3154 
3155 /* Modular reduction input data */
3156 #define PKA_MODULAR_REDUC_IN_OP_LENGTH            ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input operand length */
3157 #define PKA_MODULAR_REDUC_IN_OPERAND              ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand */
3158 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH           ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus length */
3159 #define PKA_MODULAR_REDUC_IN_MODULUS              ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
3160 
3161 /* Modular reduction output data */
3162 #define PKA_MODULAR_REDUC_OUT_RESULT              ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
3163 
3164 /* Arithmetic addition input data */
3165 #define PKA_ARITHMETIC_ADD_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
3166 #define PKA_ARITHMETIC_ADD_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
3167 #define PKA_ARITHMETIC_ADD_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
3168 
3169 /* Arithmetic addition output data */
3170 #define PKA_ARITHMETIC_ADD_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
3171 
3172 /* Arithmetic subtraction input data */
3173 #define PKA_ARITHMETIC_SUB_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
3174 #define PKA_ARITHMETIC_SUB_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
3175 #define PKA_ARITHMETIC_SUB_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
3176 
3177 /* Arithmetic subtraction output data */
3178 #define PKA_ARITHMETIC_SUB_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
3179 
3180 /* Arithmetic multiplication input data */
3181 #define PKA_ARITHMETIC_MUL_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
3182 #define PKA_ARITHMETIC_MUL_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
3183 #define PKA_ARITHMETIC_MUL_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
3184 
3185 /* Arithmetic multiplication output data */
3186 #define PKA_ARITHMETIC_MUL_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
3187 
3188 /* Comparison input data */
3189 #define PKA_COMPARISON_NB_BITS                    ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
3190 #define PKA_COMPARISON_IN_OP1                     ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
3191 #define PKA_COMPARISON_IN_OP2                     ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
3192 
3193 /* Comparison output data */
3194 #define PKA_COMPARISON_OUT_RESULT                 ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
3195 
3196 /* Modular addition input data */
3197 #define PKA_MODULAR_ADD_NB_BITS                   ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
3198 #define PKA_MODULAR_ADD_IN_OP1                    ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
3199 #define PKA_MODULAR_ADD_IN_OP2                    ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
3200 #define PKA_MODULAR_ADD_IN_OP3_MOD                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 (modulus) */
3201 
3202 /* Modular addition output data */
3203 #define PKA_MODULAR_ADD_OUT_RESULT                ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
3204 
3205 /* Modular inversion input data */
3206 #define PKA_MODULAR_INV_NB_BITS                   ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
3207 #define PKA_MODULAR_INV_IN_OP1                    ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
3208 #define PKA_MODULAR_INV_IN_OP2_MOD                ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 (modulus) */
3209 
3210 /* Modular inversion output data */
3211 #define PKA_MODULAR_INV_OUT_RESULT                ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
3212 
3213 /* Modular subtraction input data */
3214 #define PKA_MODULAR_SUB_NB_BITS                   ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
3215 #define PKA_MODULAR_SUB_IN_OP1                    ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
3216 #define PKA_MODULAR_SUB_IN_OP2                    ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
3217 #define PKA_MODULAR_SUB_IN_OP3_MOD                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 */
3218 
3219 /* Modular subtraction output data */
3220 #define PKA_MODULAR_SUB_OUT_RESULT                ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
3221 
3222 /* Montgomery multiplication input data */
3223 #define PKA_MONTGOMERY_MUL_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
3224 #define PKA_MONTGOMERY_MUL_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
3225 #define PKA_MONTGOMERY_MUL_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
3226 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD             ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
3227 
3228 /* Montgomery multiplication output data */
3229 #define PKA_MONTGOMERY_MUL_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
3230 
3231 /* Generic Arithmetic input data */
3232 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS            ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
3233 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1             ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
3234 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2             ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
3235 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3             ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
3236 
3237 /* Generic Arithmetic output data */
3238 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT         ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
3239 
3240 /******************************************************************************/
3241 /*                                                                            */
3242 /*                                    FLASH                                   */
3243 /*                                                                            */
3244 /******************************************************************************/
3245 /*******************  Bits definition for FLASH_ACR register  *****************/
3246 #define FLASH_ACR_LATENCY_Pos               (0U)
3247 #define FLASH_ACR_LATENCY_Msk               (0x7UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000007 */
3248 #define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk              /*!< Latency                                             */
3249 #define FLASH_ACR_LATENCY_0                 (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
3250 #define FLASH_ACR_LATENCY_1                 (0x2UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000002 */
3251 #define FLASH_ACR_LATENCY_2                 (0x4UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000004 */
3252 #define FLASH_ACR_PRFTEN_Pos                (8U)
3253 #define FLASH_ACR_PRFTEN_Msk                (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000100 */
3254 #define FLASH_ACR_PRFTEN                    FLASH_ACR_PRFTEN_Msk               /*!< Prefetch enable                                     */
3255 #define FLASH_ACR_ICEN_Pos                  (9U)
3256 #define FLASH_ACR_ICEN_Msk                  (0x1UL << FLASH_ACR_ICEN_Pos)      /*!< 0x00000200 */
3257 #define FLASH_ACR_ICEN                      FLASH_ACR_ICEN_Msk                 /*!< Instruction cache enable                            */
3258 #define FLASH_ACR_DCEN_Pos                  (10U)
3259 #define FLASH_ACR_DCEN_Msk                  (0x1UL << FLASH_ACR_DCEN_Pos)      /*!< 0x00000400 */
3260 #define FLASH_ACR_DCEN                      FLASH_ACR_DCEN_Msk                 /*!< Data cache enable                                   */
3261 #define FLASH_ACR_ICRST_Pos                 (11U)
3262 #define FLASH_ACR_ICRST_Msk                 (0x1UL << FLASH_ACR_ICRST_Pos)     /*!< 0x00000800 */
3263 #define FLASH_ACR_ICRST                     FLASH_ACR_ICRST_Msk                /*!< Instruction cache reset                             */
3264 #define FLASH_ACR_DCRST_Pos                 (12U)
3265 #define FLASH_ACR_DCRST_Msk                 (0x1UL << FLASH_ACR_DCRST_Pos)     /*!< 0x00001000 */
3266 #define FLASH_ACR_DCRST                     FLASH_ACR_DCRST_Msk                /*!< Data cache reset                                    */
3267 #define FLASH_ACR_PES_Pos                   (15U)
3268 #define FLASH_ACR_PES_Msk                   (0x1UL << FLASH_ACR_PES_Pos)       /*!< 0x00008000 */
3269 #define FLASH_ACR_PES                       FLASH_ACR_PES_Msk                  /*!< Program/erase suspend request                       */
3270 #define FLASH_ACR_EMPTY_Pos                 (16U)
3271 #define FLASH_ACR_EMPTY_Msk                 (0x1UL << FLASH_ACR_EMPTY_Pos)     /*!< 0x00010000 */
3272 #define FLASH_ACR_EMPTY                     FLASH_ACR_EMPTY_Msk                /*!< Flash use area empty                                */
3273 
3274 #define FLASH_ACR_LATENCY_0WS               (0x0UL << FLASH_ACR_LATENCY_Pos)            /*!< FLASH Zero wait state   */
3275 #define FLASH_ACR_LATENCY_1WS               FLASH_ACR_LATENCY_0                         /*!< FLASH One wait state    */
3276 #define FLASH_ACR_LATENCY_2WS               FLASH_ACR_LATENCY_1                         /*!< FLASH Two wait states   */
3277 #define FLASH_ACR_LATENCY_3WS               (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Three wait states */
3278 
3279 /*******************  Bits definition for FLASH_SR register  ******************/
3280 #define FLASH_SR_EOP_Pos                    (0U)
3281 #define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000001 */
3282 #define FLASH_SR_EOP                        FLASH_SR_EOP_Msk                   /*!< End of Operation                                    */
3283 #define FLASH_SR_OPERR_Pos                  (1U)
3284 #define FLASH_SR_OPERR_Msk                  (0x1UL << FLASH_SR_OPERR_Pos)      /*!< 0x00000002 */
3285 #define FLASH_SR_OPERR                      FLASH_SR_OPERR_Msk                 /*!< Operation error                                     */
3286 #define FLASH_SR_PROGERR_Pos                (3U)
3287 #define FLASH_SR_PROGERR_Msk                (0x1UL << FLASH_SR_PROGERR_Pos)    /*!< 0x00000008 */
3288 #define FLASH_SR_PROGERR                    FLASH_SR_PROGERR_Msk               /*!< Programming error                                   */
3289 #define FLASH_SR_WRPERR_Pos                 (4U)
3290 #define FLASH_SR_WRPERR_Msk                 (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000010 */
3291 #define FLASH_SR_WRPERR                     FLASH_SR_WRPERR_Msk                /*!< Write protection error                              */
3292 #define FLASH_SR_PGAERR_Pos                 (5U)
3293 #define FLASH_SR_PGAERR_Msk                 (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000020 */
3294 #define FLASH_SR_PGAERR                     FLASH_SR_PGAERR_Msk                /*!< Programming alignment error                         */
3295 #define FLASH_SR_SIZERR_Pos                 (6U)
3296 #define FLASH_SR_SIZERR_Msk                 (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000040 */
3297 #define FLASH_SR_SIZERR                     FLASH_SR_SIZERR_Msk                /*!< Size error                                          */
3298 #define FLASH_SR_PGSERR_Pos                 (7U)
3299 #define FLASH_SR_PGSERR_Msk                 (0x1UL << FLASH_SR_PGSERR_Pos)     /*!< 0x00000080 */
3300 #define FLASH_SR_PGSERR                     FLASH_SR_PGSERR_Msk                /*!< Programming sequence error                          */
3301 #define FLASH_SR_MISERR_Pos                 (8U)
3302 #define FLASH_SR_MISERR_Msk                 (0x1UL << FLASH_SR_MISERR_Pos)     /*!< 0x00000100 */
3303 #define FLASH_SR_MISERR                     FLASH_SR_MISERR_Msk                /*!< Fast programming data miss error                    */
3304 #define FLASH_SR_FASTERR_Pos                (9U)
3305 #define FLASH_SR_FASTERR_Msk                (0x1UL << FLASH_SR_FASTERR_Pos)    /*!< 0x00000200 */
3306 #define FLASH_SR_FASTERR                    FLASH_SR_FASTERR_Msk               /*!< Fast programming error                              */
3307 #define FLASH_SR_OPTNV_Pos                  (13U)
3308 #define FLASH_SR_OPTNV_Msk                  (0x1UL << FLASH_SR_OPTNV_Pos)     /*!< 0x00002000 */
3309 #define FLASH_SR_OPTNV                      FLASH_SR_OPTNV_Msk                /*!< User option OPTVAL indication                       */
3310 #define FLASH_SR_RDERR_Pos                  (14U)
3311 #define FLASH_SR_RDERR_Msk                  (0x1UL << FLASH_SR_RDERR_Pos)      /*!< 0x00004000 */
3312 #define FLASH_SR_RDERR                      FLASH_SR_RDERR_Msk                 /*!< PCROP read error                                    */
3313 #define FLASH_SR_OPTVERR_Pos                (15U)
3314 #define FLASH_SR_OPTVERR_Msk                (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00008000 */
3315 #define FLASH_SR_OPTVERR                    FLASH_SR_OPTVERR_Msk               /*!< Option validity error                               */
3316 #define FLASH_SR_BSY_Pos                    (16U)
3317 #define FLASH_SR_BSY_Msk                    (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00010000 */
3318 #define FLASH_SR_BSY                        FLASH_SR_BSY_Msk                   /*!< Flash Busy                                          */
3319 #define FLASH_SR_CFGBSY_Pos                 (18U)
3320 #define FLASH_SR_CFGBSY_Msk                 (0x1UL << FLASH_SR_CFGBSY_Pos)     /*!< 0x00040000 */
3321 #define FLASH_SR_CFGBSY                     FLASH_SR_CFGBSY_Msk                /*!< Programming or erase configuration busy             */
3322 #define FLASH_SR_PESD_Pos                   (19U)
3323 #define FLASH_SR_PESD_Msk                   (0x1UL << FLASH_SR_PESD_Pos)       /*!< 0x00080000 */
3324 #define FLASH_SR_PESD                       FLASH_SR_PESD_Msk                  /*!< Programming/erase operation suspended               */
3325 
3326 /*******************  Bits definition for FLASH_CR register  ******************/
3327 #define FLASH_CR_PG_Pos                     (0U)
3328 #define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)         /*!< 0x00000001 */
3329 #define FLASH_CR_PG                         FLASH_CR_PG_Msk                    /*!< Flash programming                                   */
3330 #define FLASH_CR_PER_Pos                    (1U)
3331 #define FLASH_CR_PER_Msk                    (0x1UL << FLASH_CR_PER_Pos)        /*!< 0x00000002 */
3332 #define FLASH_CR_PER                        FLASH_CR_PER_Msk                   /*!< Page erase                                          */
3333 #define FLASH_CR_MER_Pos                    (2U)
3334 #define FLASH_CR_MER_Msk                    (0x1UL << FLASH_CR_MER_Pos)        /*!< 0x00000004 */
3335 #define FLASH_CR_MER                        FLASH_CR_MER_Msk                   /*!< Mass erase                                          */
3336 #define FLASH_CR_PNB_Pos                    (3U)
3337 #define FLASH_CR_PNB_Msk                    (0xFFUL << FLASH_CR_PNB_Pos)       /*!< 0x000007F8 */
3338 #define FLASH_CR_PNB                        FLASH_CR_PNB_Msk                   /*!< Page number selection mask                          */
3339 #define FLASH_CR_STRT_Pos                   (16U)
3340 #define FLASH_CR_STRT_Msk                   (0x1UL << FLASH_CR_STRT_Pos)       /*!< 0x00010000 */
3341 #define FLASH_CR_STRT                       FLASH_CR_STRT_Msk                  /*!< Start an erase operation                            */
3342 #define FLASH_CR_OPTSTRT_Pos                (17U)
3343 #define FLASH_CR_OPTSTRT_Msk                (0x1UL << FLASH_CR_OPTSTRT_Pos)    /*!< 0x00020000 */
3344 #define FLASH_CR_OPTSTRT                    FLASH_CR_OPTSTRT_Msk               /*!< Options modification start                          */
3345 #define FLASH_CR_FSTPG_Pos                  (18U)
3346 #define FLASH_CR_FSTPG_Msk                  (0x1UL << FLASH_CR_FSTPG_Pos)      /*!< 0x00040000 */
3347 #define FLASH_CR_FSTPG                      FLASH_CR_FSTPG_Msk                 /*!< Fast programming                                    */
3348 #define FLASH_CR_EOPIE_Pos                  (24U)
3349 #define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)      /*!< 0x01000000 */
3350 #define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk                 /*!< End of operation interrupt enable                   */
3351 #define FLASH_CR_ERRIE_Pos                  (25U)
3352 #define FLASH_CR_ERRIE_Msk                  (0x1UL << FLASH_CR_ERRIE_Pos)      /*!< 0x02000000 */
3353 #define FLASH_CR_ERRIE                      FLASH_CR_ERRIE_Msk                 /*!< Error interrupt enable                              */
3354 #define FLASH_CR_RDERRIE_Pos                (26U)
3355 #define FLASH_CR_RDERRIE_Msk                (0x1UL << FLASH_CR_RDERRIE_Pos)    /*!< 0x04000000 */
3356 #define FLASH_CR_RDERRIE                    FLASH_CR_RDERRIE_Msk               /*!< PCROP read error interrupt enable                   */
3357 #define FLASH_CR_OBL_LAUNCH_Pos             (27U)
3358 #define FLASH_CR_OBL_LAUNCH_Msk             (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
3359 #define FLASH_CR_OBL_LAUNCH                 FLASH_CR_OBL_LAUNCH_Msk            /*!< Force the option byte loading                       */
3360 #define FLASH_CR_OPTLOCK_Pos                (30U)
3361 #define FLASH_CR_OPTLOCK_Msk                (0x1UL << FLASH_CR_OPTLOCK_Pos)    /*!< 0x40000000 */
3362 #define FLASH_CR_OPTLOCK                    FLASH_CR_OPTLOCK_Msk               /*!< Options lock                                        */
3363 #define FLASH_CR_LOCK_Pos                   (31U)
3364 #define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)       /*!< 0x80000000 */
3365 #define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk                  /*!< Flash control register lock                         */
3366 
3367 /*******************  Bits definition for FLASH_ECCR register  ****************/
3368 #define FLASH_ECCR_ADDR_ECC_Pos             (0U)
3369 #define FLASH_ECCR_ADDR_ECC_Msk             (0x1FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0001FFFF */
3370 #define FLASH_ECCR_ADDR_ECC                 FLASH_ECCR_ADDR_ECC_Msk            /*!< double-word address ECC fail                        */
3371 #define FLASH_ECCR_SYSF_ECC_Pos             (20U)
3372 #define FLASH_ECCR_SYSF_ECC_Msk             (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
3373 #define FLASH_ECCR_SYSF_ECC                 FLASH_ECCR_SYSF_ECC_Msk            /*!< System flash ECC fail                               */
3374 #define FLASH_ECCR_ECCCIE_Pos               (24U)
3375 #define FLASH_ECCR_ECCCIE_Msk               (0x1UL << FLASH_ECCR_ECCCIE_Pos)   /*!< 0x01000000 */
3376 #define FLASH_ECCR_ECCCIE                   FLASH_ECCR_ECCCIE_Msk              /*!< ECC correction interrupt enable                     */
3377 #define FLASH_ECCR_CPUID_Pos                (26U)
3378 #define FLASH_ECCR_CPUID_Msk                (0x7UL << FLASH_ECCR_CPUID_Pos)    /*!< 0x1C000000 */
3379 #define FLASH_ECCR_CPUID                    FLASH_ECCR_CPUID_Msk               /*!< CPU identification                                  */
3380 #define FLASH_ECCR_CPUID_0                  (0x1U << FLASH_ECCR_CPUID_Pos)     /*!< 0x04000000 */
3381 #define FLASH_ECCR_CPUID_1                  (0x2U << FLASH_ECCR_CPUID_Pos)     /*!< 0x08000000 */
3382 #define FLASH_ECCR_CPUID_2                  (0x4U << FLASH_ECCR_CPUID_Pos)     /*!< 0x10000000 */
3383 #define FLASH_ECCR_ECCC_Pos                 (30U)
3384 #define FLASH_ECCR_ECCC_Msk                 (0x1UL << FLASH_ECCR_ECCC_Pos)     /*!< 0x40000000 */
3385 #define FLASH_ECCR_ECCC                     FLASH_ECCR_ECCC_Msk                /*!< ECC correction                                      */
3386 #define FLASH_ECCR_ECCD_Pos                 (31U)
3387 #define FLASH_ECCR_ECCD_Msk                 (0x1UL << FLASH_ECCR_ECCD_Pos)     /*!< 0x80000000 */
3388 #define FLASH_ECCR_ECCD                     FLASH_ECCR_ECCD_Msk                /*!< ECC detection                                       */
3389 
3390 /*******************  Bits definition for FLASH_OPTR register  ****************/
3391 #define FLASH_OPTR_RDP_Pos                  (0U)
3392 #define FLASH_OPTR_RDP_Msk                  (0xFFUL << FLASH_OPTR_RDP_Pos)     /*!< 0x000000FF */
3393 #define FLASH_OPTR_RDP                      FLASH_OPTR_RDP_Msk                 /*!< Read protection level                               */
3394 #define FLASH_OPTR_ESE_Pos                  (8U)
3395 #define FLASH_OPTR_ESE_Msk                  (0x1UL << FLASH_OPTR_ESE_Pos)      /*!< 0x00000100 */
3396 #define FLASH_OPTR_ESE                      FLASH_OPTR_ESE_Msk                 /*!< Security enable                                     */
3397 #define FLASH_OPTR_BOR_LEV_Pos              (9U)
3398 #define FLASH_OPTR_BOR_LEV_Msk              (0x7UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000E00 */
3399 #define FLASH_OPTR_BOR_LEV                  FLASH_OPTR_BOR_LEV_Msk             /*!< BOR reset level mask                                */
3400 #define FLASH_OPTR_BOR_LEV_0                (0x1U << FLASH_OPTR_BOR_LEV_Pos)   /*!< 0x00000200 */
3401 #define FLASH_OPTR_BOR_LEV_1                (0x2U << FLASH_OPTR_BOR_LEV_Pos)   /*!< 0x00000400 */
3402 #define FLASH_OPTR_BOR_LEV_2                (0x4U << FLASH_OPTR_BOR_LEV_Pos)   /*!< 0x00000800 */
3403 #define FLASH_OPTR_nRST_STOP_Pos            (12U)
3404 #define FLASH_OPTR_nRST_STOP_Msk            (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
3405 #define FLASH_OPTR_nRST_STOP                FLASH_OPTR_nRST_STOP_Msk           /*!< Reset option in Stop mode                           */
3406 #define FLASH_OPTR_nRST_STDBY_Pos           (13U)
3407 #define FLASH_OPTR_nRST_STDBY_Msk           (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
3408 #define FLASH_OPTR_nRST_STDBY               FLASH_OPTR_nRST_STDBY_Msk          /*!< Reset option in Standby mode                        */
3409 #define FLASH_OPTR_nRST_SHDW_Pos            (14U)
3410 #define FLASH_OPTR_nRST_SHDW_Msk            (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
3411 #define FLASH_OPTR_nRST_SHDW                FLASH_OPTR_nRST_SHDW_Msk           /*!< Reset option in Shutdown mode                       */
3412 #define FLASH_OPTR_IRHEN_Pos                (15U)
3413 #define FLASH_OPTR_IRHEN_Msk                (0x1UL << FLASH_OPTR_IRHEN_Pos)    /*!< 0x00008000 */
3414 #define FLASH_OPTR_IRHEN                    FLASH_OPTR_IRHEN_Msk               /*!< Internal reset holder enable bit                    */
3415 #define FLASH_OPTR_IWDG_SW_Pos              (16U)
3416 #define FLASH_OPTR_IWDG_SW_Msk              (0x1UL << FLASH_OPTR_IWDG_SW_Pos)  /*!< 0x00010000 */
3417 #define FLASH_OPTR_IWDG_SW                  FLASH_OPTR_IWDG_SW_Msk             /*!< Independent watchdog selection                      */
3418 #define FLASH_OPTR_IWDG_STOP_Pos            (17U)
3419 #define FLASH_OPTR_IWDG_STOP_Msk            (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
3420 #define FLASH_OPTR_IWDG_STOP                FLASH_OPTR_IWDG_STOP_Msk           /*!< Independent watchdog counter option in Stop mode    */
3421 #define FLASH_OPTR_IWDG_STDBY_Pos           (18U)
3422 #define FLASH_OPTR_IWDG_STDBY_Msk           (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
3423 #define FLASH_OPTR_IWDG_STDBY               FLASH_OPTR_IWDG_STDBY_Msk          /*!< Independent watchdog counter option in Standby mode */
3424 #define FLASH_OPTR_WWDG_SW_Pos              (19U)
3425 #define FLASH_OPTR_WWDG_SW_Msk              (0x1UL << FLASH_OPTR_WWDG_SW_Pos)  /*!< 0x00080000 */
3426 #define FLASH_OPTR_WWDG_SW                  FLASH_OPTR_WWDG_SW_Msk             /*!< Window watchdog selection                           */
3427 #define FLASH_OPTR_nRST_MODE_1_Pos          (22U)
3428 #define FLASH_OPTR_nRST_MODE_1_Msk          (0x1UL << FLASH_OPTR_nRST_MODE_1_Pos)  /*!< 0x04000000 */
3429 #define FLASH_OPTR_nRST_MODE_1              FLASH_OPTR_nRST_MODE_1_Msk         /*!< PB11 GPIO normal mode                               */
3430 #define FLASH_OPTR_nBOOT1_Pos               (23U)
3431 #define FLASH_OPTR_nBOOT1_Msk               (0x1UL << FLASH_OPTR_nBOOT1_Pos)   /*!< 0x00800000 */
3432 #define FLASH_OPTR_nBOOT1                   FLASH_OPTR_nBOOT1_Msk              /*!< Boot Configuration                                  */
3433 #define FLASH_OPTR_SRAM2PE_Pos              (24U)
3434 #define FLASH_OPTR_SRAM2PE_Msk              (0x1UL << FLASH_OPTR_SRAM2PE_Pos)  /*!< 0x01000000 */
3435 #define FLASH_OPTR_SRAM2PE                  FLASH_OPTR_SRAM2PE_Msk             /*!< SRAM2 parity check enable                           */
3436 #define FLASH_OPTR_SRAM2RST_Pos             (25U)
3437 #define FLASH_OPTR_SRAM2RST_Msk             (0x1UL << FLASH_OPTR_SRAM2RST_Pos) /*!< 0x02000000 */
3438 #define FLASH_OPTR_SRAM2RST                 FLASH_OPTR_SRAM2RST_Msk            /*!< SRAM2 erase option when system reset                */
3439 #define FLASH_OPTR_nSWBOOT0_Pos             (26U)
3440 #define FLASH_OPTR_nSWBOOT0_Msk             (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
3441 #define FLASH_OPTR_nSWBOOT0                 FLASH_OPTR_nSWBOOT0_Msk            /*!< Software BOOT0                                      */
3442 #define FLASH_OPTR_nBOOT0_Pos               (27U)
3443 #define FLASH_OPTR_nBOOT0_Msk               (0x1UL << FLASH_OPTR_nBOOT0_Pos)   /*!< 0x08000000 */
3444 #define FLASH_OPTR_nBOOT0                   FLASH_OPTR_nBOOT0_Msk              /*!< BOOT0 option bit                                    */
3445 #define FLASH_OPTR_nRST_MODE_0_Pos          (28U)
3446 #define FLASH_OPTR_nRST_MODE_0_Msk          (0x1UL << FLASH_OPTR_nRST_MODE_0_Pos)  /*!< 0x10000000 */
3447 #define FLASH_OPTR_nRST_MODE_0              FLASH_OPTR_nRST_MODE_0_Msk         /*!< PB11 reset input mode                               */
3448 #define FLASH_OPTR_nRST_MODE_Pos            (22U)
3449 #define FLASH_OPTR_nRST_MODE_Msk            (0x41UL << FLASH_OPTR_nRST_MODE_Pos)  /*!< 0x10400000 */
3450 #define FLASH_OPTR_nRST_MODE                FLASH_OPTR_nRST_MODE_Msk
3451 #define FLASH_OPTR_AGC_TRIM_Pos             (29U)
3452 #define FLASH_OPTR_AGC_TRIM_Msk             (0x7UL << FLASH_OPTR_AGC_TRIM_Pos)  /*!< 0xE0000000 */
3453 #define FLASH_OPTR_AGC_TRIM                 FLASH_OPTR_AGC_TRIM_Msk             /*!< Automatic Gain Control trimming mask               */
3454 #define FLASH_OPTR_AGC_TRIM_0               (0x1U << FLASH_OPTR_AGC_TRIM_Pos)   /*!< 0x20000000 */
3455 #define FLASH_OPTR_AGC_TRIM_1               (0x2U << FLASH_OPTR_AGC_TRIM_Pos)   /*!< 0x40000000 */
3456 #define FLASH_OPTR_AGC_TRIM_2               (0x4U << FLASH_OPTR_AGC_TRIM_Pos)   /*!< 0x80000000 */
3457 
3458 /******************  Bits definition for FLASH_PCROP1ASR register  ************/
3459 #define FLASH_PCROP1ASR_PCROP1A_STRT_Pos    (0U)
3460 #define FLASH_PCROP1ASR_PCROP1A_STRT_Msk    (0x1FFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x000001FF */
3461 #define FLASH_PCROP1ASR_PCROP1A_STRT        FLASH_PCROP1ASR_PCROP1A_STRT_Msk   /*!< PCROP area A start offset                           */
3462 
3463 /******************  Bits definition for FLASH_PCROP1AER register  ************/
3464 #define FLASH_PCROP1AER_PCROP1A_END_Pos     (0U)
3465 #define FLASH_PCROP1AER_PCROP1A_END_Msk     (0x1FFUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x000001FF */
3466 #define FLASH_PCROP1AER_PCROP1A_END         FLASH_PCROP1AER_PCROP1A_END_Msk    /*!< PCROP area A end offset                             */
3467 #define FLASH_PCROP1AER_PCROP_RDP_Pos       (31U)
3468 #define FLASH_PCROP1AER_PCROP_RDP_Msk       (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */
3469 #define FLASH_PCROP1AER_PCROP_RDP           FLASH_PCROP1AER_PCROP_RDP_Msk      /*!< PCROP area   preserved when RDP level decreased     */
3470 
3471 /******************  Bits definition for FLASH_WRP1AR register  ***************/
3472 #define FLASH_WRP1AR_WRP1A_STRT_Pos         (0U)
3473 #define FLASH_WRP1AR_WRP1A_STRT_Msk         (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
3474 #define FLASH_WRP1AR_WRP1A_STRT             FLASH_WRP1AR_WRP1A_STRT_Msk        /*!< WRP area A start offset                             */
3475 #define FLASH_WRP1AR_WRP1A_END_Pos          (16U)
3476 #define FLASH_WRP1AR_WRP1A_END_Msk          (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
3477 #define FLASH_WRP1AR_WRP1A_END              FLASH_WRP1AR_WRP1A_END_Msk         /*!< WRP area A end offset                               */
3478 
3479 /******************  Bits definition for FLASH_WRP1BR register  ***************/
3480 #define FLASH_WRP1BR_WRP1B_STRT_Pos         (0U)
3481 #define FLASH_WRP1BR_WRP1B_STRT_Msk         (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
3482 #define FLASH_WRP1BR_WRP1B_STRT             FLASH_WRP1BR_WRP1B_STRT_Msk        /*!< WRP area B start offset                             */
3483 #define FLASH_WRP1BR_WRP1B_END_Pos          (16U)
3484 #define FLASH_WRP1BR_WRP1B_END_Msk          (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
3485 #define FLASH_WRP1BR_WRP1B_END              FLASH_WRP1BR_WRP1B_END_Msk         /*!< WRP area B end offset                               */
3486 
3487 /******************  Bits definition for FLASH_PCROP1BSR register  ************/
3488 #define FLASH_PCROP1BSR_PCROP1B_STRT_Pos    (0U)
3489 #define FLASH_PCROP1BSR_PCROP1B_STRT_Msk    (0x1FFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x000001FF */
3490 #define FLASH_PCROP1BSR_PCROP1B_STRT        FLASH_PCROP1BSR_PCROP1B_STRT_Msk   /*!< PCROP area B start offset                           */
3491 
3492 /******************  Bits definition for FLASH_PCROP1BER register  ************/
3493 #define FLASH_PCROP1BER_PCROP1B_END_Pos     (0U)
3494 #define FLASH_PCROP1BER_PCROP1B_END_Msk     (0x1FFUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x000001FF */
3495 #define FLASH_PCROP1BER_PCROP1B_END         FLASH_PCROP1BER_PCROP1B_END_Msk    /*!< PCROP area B end offset                             */
3496 
3497 /******************  Bits definition for FLASH_IPCCBR register  ************/
3498 #define FLASH_IPCCBR_IPCCDBA_Pos            (0U)
3499 #define FLASH_IPCCBR_IPCCDBA_Msk            (0x3FFFUL << FLASH_IPCCBR_IPCCDBA_Pos) /*!< 0x00003FFF */
3500 #define FLASH_IPCCBR_IPCCDBA                FLASH_IPCCBR_IPCCDBA_Msk           /*!< IPCC data buffer base address                       */
3501 
3502 /******************  Bits definition for FLASH_SFR register  ************/
3503 #define FLASH_SFR_SFSA_Pos                  (0U)
3504 #define FLASH_SFR_SFSA_Msk                  (0xFFUL << FLASH_SFR_SFSA_Pos)     /*!< 0x000000FF */
3505 #define FLASH_SFR_SFSA                      FLASH_SFR_SFSA_Msk                 /* Secure flash start address                             */
3506 #define FLASH_SFR_FSD_Pos                   (8U)
3507 #define FLASH_SFR_FSD_Msk                   (0x1UL << FLASH_SFR_FSD_Pos)       /*!< 0x00000100 */
3508 #define FLASH_SFR_FSD                       FLASH_SFR_FSD_Msk                  /* Flash mode secure                                      */
3509 #define FLASH_SFR_DDS_Pos                   (12U)
3510 #define FLASH_SFR_DDS_Msk                   (0x1UL << FLASH_SFR_DDS_Pos)       /*!< 0x00001000 */
3511 #define FLASH_SFR_DDS                       FLASH_SFR_DDS_Msk                  /* Enabling and disabling CPU2 Debug access               */
3512 
3513 /******************  Bits definition for FLASH_SRRVR register  ************/
3514 #define FLASH_SRRVR_SBRV_Pos                (0U)
3515 #define FLASH_SRRVR_SBRV_Msk                (0x1FFFFUL << FLASH_SRRVR_SBRV_Pos) /*!< 0x0001FFFF */
3516 #define FLASH_SRRVR_SBRV                    FLASH_SRRVR_SBRV_Msk                /* CPU2 boot reset vector memory offset                  */
3517 
3518 #define FLASH_SRRVR_SBRSA_A_Pos             (18U)
3519 #define FLASH_SRRVR_SBRSA_A_Msk             (0x1FUL << FLASH_SRRVR_SBRSA_A_Pos) /*!< 0x007C0000 */
3520 #define FLASH_SRRVR_SBRSA_A                 FLASH_SRRVR_SBRSA_A_Msk             /* Secure backup SRAM2a start address                    */
3521 #define FLASH_SRRVR_BRSD_A_Pos              (23U)
3522 #define FLASH_SRRVR_BRSD_A_Msk              (0x1UL << FLASH_SRRVR_BRSD_A_Pos)   /*!< 0x00800000 */
3523 #define FLASH_SRRVR_BRSD_A                  FLASH_SRRVR_BRSD_A_Msk              /* Backup SRAM2A secure mode                             */
3524 
3525 #define FLASH_SRRVR_SBRSA_B_Pos             (25U)
3526 #define FLASH_SRRVR_SBRSA_B_Msk             (0x3UL << FLASH_SRRVR_SBRSA_B_Pos)  /*!< 0x06000000 */
3527 #define FLASH_SRRVR_SBRSA_B                 FLASH_SRRVR_SBRSA_B_Msk             /* Secure backup SRAM2b start address                    */
3528 #define FLASH_SRRVR_BRSD_B_Pos              (30U)
3529 #define FLASH_SRRVR_BRSD_B_Msk              (0x1UL << FLASH_SRRVR_BRSD_B_Pos)   /*!< 0x40000000 */
3530 #define FLASH_SRRVR_BRSD_B                  FLASH_SRRVR_BRSD_B_Msk              /* Backup SRAM2B secure mode                             */
3531 #define FLASH_SRRVR_C2OPT_Pos               (31U)
3532 #define FLASH_SRRVR_C2OPT_Msk               (0x1UL << FLASH_SRRVR_C2OPT_Pos)    /*!< 0x80000000 */
3533 #define FLASH_SRRVR_C2OPT                   FLASH_SRRVR_C2OPT_Msk               /* CPU2 boot reset vector memory selection                */
3534 
3535 /******************  Bits definition for FLASH_C2ACR register  ************/
3536 #define FLASH_C2ACR_PRFTEN_Pos              (8U)
3537 #define FLASH_C2ACR_PRFTEN_Msk              (0x1UL << FLASH_C2ACR_PRFTEN_Pos) /*!< 0x00000100 */
3538 #define FLASH_C2ACR_PRFTEN                  FLASH_C2ACR_PRFTEN_Msk            /*!< CPU2 Prefetch enable                                */
3539 #define FLASH_C2ACR_ICEN_Pos                (9U)
3540 #define FLASH_C2ACR_ICEN_Msk                (0x1UL << FLASH_C2ACR_ICEN_Pos)   /*!< 0x00000200 */
3541 #define FLASH_C2ACR_ICEN                    FLASH_C2ACR_ICEN_Msk              /*!< CPU2 Instruction cache enable                       */
3542 #define FLASH_C2ACR_ICRST_Pos               (11U)
3543 #define FLASH_C2ACR_ICRST_Msk               (0x1UL << FLASH_C2ACR_ICRST_Pos)  /*!< 0x00000800 */
3544 #define FLASH_C2ACR_ICRST                   FLASH_C2ACR_ICRST_Msk             /*!< CPU2 Instruction cache reset                        */
3545 #define FLASH_C2ACR_PES_Pos                 (15U)
3546 #define FLASH_C2ACR_PES_Msk                 (0x1UL << FLASH_C2ACR_PES_Pos)    /*!< 0x00008000 */
3547 #define FLASH_C2ACR_PES                     FLASH_C2ACR_PES_Msk               /*!< CPU2 Program/erase suspend request                  */
3548 
3549 /******************  Bits definition for FLASH_C2SR register  ************/
3550 #define FLASH_C2SR_EOP_Pos                  (0U)
3551 #define FLASH_C2SR_EOP_Msk                  (0x1UL << FLASH_C2SR_EOP_Pos)     /*!< 0x00000001 */
3552 #define FLASH_C2SR_EOP                      FLASH_C2SR_EOP_Msk                /*!< CPU2 End of operation                            */
3553 #define FLASH_C2SR_OPERR_Pos                (1U)
3554 #define FLASH_C2SR_OPERR_Msk                (0x1UL << FLASH_C2SR_OPERR_Pos)   /*!< 0x00000002 */
3555 #define FLASH_C2SR_OPERR                    FLASH_C2SR_OPERR_Msk              /*!< CPU2 Operation error                             */
3556 #define FLASH_C2SR_PROGERR_Pos              (3U)
3557 #define FLASH_C2SR_PROGERR_Msk              (0x1UL << FLASH_C2SR_PROGERR_Pos) /*!< 0x00000008 */
3558 #define FLASH_C2SR_PROGERR                  FLASH_C2SR_PROGERR_Msk            /*!< CPU2 Programming error                           */
3559 #define FLASH_C2SR_WRPERR_Pos               (4U)
3560 #define FLASH_C2SR_WRPERR_Msk               (0x1UL << FLASH_C2SR_WRPERR_Pos)  /*!< 0x00000010 */
3561 #define FLASH_C2SR_WRPERR                   FLASH_C2SR_WRPERR_Msk             /*!< CPU2 Write protection error                      */
3562 #define FLASH_C2SR_PGAERR_Pos               (5U)
3563 #define FLASH_C2SR_PGAERR_Msk               (0x1UL << FLASH_C2SR_PGAERR_Pos)  /*!< 0x00000020 */
3564 #define FLASH_C2SR_PGAERR                   FLASH_C2SR_PGAERR_Msk             /*!< CPU2 Programming alignment error                 */
3565 #define FLASH_C2SR_SIZERR_Pos               (6U)
3566 #define FLASH_C2SR_SIZERR_Msk               (0x1UL << FLASH_C2SR_SIZERR_Pos)  /*!< 0x00000040 */
3567 #define FLASH_C2SR_SIZERR                   FLASH_C2SR_SIZERR_Msk             /*!< CPU2 Size error                                  */
3568 #define FLASH_C2SR_PGSERR_Pos               (7U)
3569 #define FLASH_C2SR_PGSERR_Msk               (0x1UL << FLASH_C2SR_PGSERR_Pos)  /*!< 0x00000080 */
3570 #define FLASH_C2SR_PGSERR                   FLASH_C2SR_PGSERR_Msk             /*!< CPU2 Programming sequence error                  */
3571 #define FLASH_C2SR_MISERR_Pos               (8U)
3572 #define FLASH_C2SR_MISERR_Msk               (0x1UL << FLASH_C2SR_MISERR_Pos)  /*!< 0x00000100 */
3573 #define FLASH_C2SR_MISERR                   FLASH_C2SR_MISERR_Msk             /*!< CPU2 Fast programming data miss error            */
3574 #define FLASH_C2SR_FASTERR_Pos              (9U)
3575 #define FLASH_C2SR_FASTERR_Msk              (0x1UL << FLASH_C2SR_FASTERR_Pos) /*!< 0x00000200 */
3576 #define FLASH_C2SR_FASTERR                  FLASH_C2SR_FASTERR_Msk            /*!< CPU2 Fast programming error                      */
3577 #define FLASH_C2SR_RDERR_Pos                (14U)
3578 #define FLASH_C2SR_RDERR_Msk                (0x1UL << FLASH_C2SR_RDERR_Pos)   /*!< 0x00004000 */
3579 #define FLASH_C2SR_RDERR                    FLASH_C2SR_RDERR_Msk              /*!< CPU2 PCROP read error                            */
3580 #define FLASH_C2SR_BSY_Pos                  (16U)
3581 #define FLASH_C2SR_BSY_Msk                  (0x1UL << FLASH_C2SR_BSY_Pos)     /*!< 0x00010000 */
3582 #define FLASH_C2SR_BSY                      FLASH_C2SR_BSY_Msk                /*!< CPU2 Flash busy                                  */
3583 #define FLASH_C2SR_CFGBSY_Pos               (18U)
3584 #define FLASH_C2SR_CFGBSY_Msk               (0x1UL << FLASH_C2SR_CFGBSY_Pos)  /*!< 0x00040000 */
3585 #define FLASH_C2SR_CFGBSY                   FLASH_C2SR_CFGBSY_Msk             /*!< CPU2 Programming or erase configuration busy     */
3586 #define FLASH_C2SR_PESD_Pos                 (19U)
3587 #define FLASH_C2SR_PESD_Msk                 (0x1UL << FLASH_C2SR_PESD_Pos)   /*!< 0x00080000 */
3588 #define FLASH_C2SR_PESD                     FLASH_C2SR_PESD_Msk              /*!< CPU2 Programming/erase operation suspended       */
3589 
3590 /******************  Bits definition for FLASH_C2CR register  ************/
3591 #define FLASH_C2CR_PG_Pos                   (0U)
3592 #define FLASH_C2CR_PG_Msk                   (0x1UL << FLASH_C2CR_PG_Pos)      /*!< 0x00000001 */
3593 #define FLASH_C2CR_PG                       FLASH_C2CR_PG_Msk                 /*!< CPU2 Flash programming                                   */
3594 #define FLASH_C2CR_PER_Pos                  (1U)
3595 #define FLASH_C2CR_PER_Msk                  (0x1UL << FLASH_C2CR_PER_Pos)     /*!< 0x00000002 */
3596 #define FLASH_C2CR_PER                      FLASH_C2CR_PER_Msk                /*!< CPU2 Page erase                                          */
3597 #define FLASH_C2CR_MER_Pos                  (2U)
3598 #define FLASH_C2CR_MER_Msk                  (0x1UL << FLASH_C2CR_MER_Pos)     /*!< 0x00000004 */
3599 #define FLASH_C2CR_MER                      FLASH_C2CR_MER_Msk                /*!< CPU2 Mass erase                                          */
3600 #define FLASH_C2CR_PNB_Pos                  (3U)
3601 #define FLASH_C2CR_PNB_Msk                  (0xFFUL << FLASH_C2CR_PNB_Pos)    /*!< 0x000007F8 */
3602 #define FLASH_C2CR_PNB                      FLASH_C2CR_PNB_Msk                /*!< CPU2 Page number selection mask                          */
3603 #define FLASH_C2CR_STRT_Pos                 (16U)
3604 #define FLASH_C2CR_STRT_Msk                 (0x1UL << FLASH_C2CR_STRT_Pos)    /*!< 0x00010000 */
3605 #define FLASH_C2CR_STRT                     FLASH_C2CR_STRT_Msk               /*!< CPU2 Start an erase operation                            */
3606 #define FLASH_C2CR_FSTPG_Pos                (18U)
3607 #define FLASH_C2CR_FSTPG_Msk                (0x1UL << FLASH_C2CR_FSTPG_Pos)   /*!< 0x00040000 */
3608 #define FLASH_C2CR_FSTPG                    FLASH_C2CR_FSTPG_Msk              /*!< CPU2 Fast programming                                    */
3609 #define FLASH_C2CR_EOPIE_Pos                (24U)
3610 #define FLASH_C2CR_EOPIE_Msk                (0x1UL << FLASH_C2CR_EOPIE_Pos)   /*!< 0x01000000 */
3611 #define FLASH_C2CR_EOPIE                    FLASH_C2CR_EOPIE_Msk              /*!< CPU2 End of operation interrupt enable                   */
3612 #define FLASH_C2CR_ERRIE_Pos                (25U)
3613 #define FLASH_C2CR_ERRIE_Msk                (0x1UL << FLASH_C2CR_ERRIE_Pos)   /*!< 0x02000000 */
3614 #define FLASH_C2CR_ERRIE                    FLASH_C2CR_ERRIE_Msk              /*!< CPU2 Error interrupt enable                              */
3615 #define FLASH_C2CR_RDERRIE_Pos              (26U)
3616 #define FLASH_C2CR_RDERRIE_Msk              (0x1UL << FLASH_C2CR_RDERRIE_Pos) /*!< 0x04000000 */
3617 #define FLASH_C2CR_RDERRIE                  FLASH_C2CR_RDERRIE_Msk            /*!< CPU2 PCROP read error interrupt enable                   */
3618 
3619 /******************************************************************************/
3620 /*                                                                            */
3621 /*                            General Purpose I/O                             */
3622 /*                                                                            */
3623 /******************************************************************************/
3624 /******************  Bits definition for GPIO_MODER register  *****************/
3625 #define GPIO_MODER_MODE0_Pos           (0U)
3626 #define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
3627 #define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
3628 #define GPIO_MODER_MODE0_0             (0x1U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
3629 #define GPIO_MODER_MODE0_1             (0x2U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
3630 #define GPIO_MODER_MODE1_Pos           (2U)
3631 #define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
3632 #define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
3633 #define GPIO_MODER_MODE1_0             (0x1U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
3634 #define GPIO_MODER_MODE1_1             (0x2U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
3635 #define GPIO_MODER_MODE2_Pos           (4U)
3636 #define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
3637 #define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
3638 #define GPIO_MODER_MODE2_0             (0x1U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
3639 #define GPIO_MODER_MODE2_1             (0x2U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
3640 #define GPIO_MODER_MODE3_Pos           (6U)
3641 #define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
3642 #define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
3643 #define GPIO_MODER_MODE3_0             (0x1U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
3644 #define GPIO_MODER_MODE3_1             (0x2U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
3645 #define GPIO_MODER_MODE4_Pos           (8U)
3646 #define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
3647 #define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
3648 #define GPIO_MODER_MODE4_0             (0x1U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
3649 #define GPIO_MODER_MODE4_1             (0x2U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
3650 #define GPIO_MODER_MODE5_Pos           (10U)
3651 #define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
3652 #define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
3653 #define GPIO_MODER_MODE5_0             (0x1U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
3654 #define GPIO_MODER_MODE5_1             (0x2U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
3655 #define GPIO_MODER_MODE6_Pos           (12U)
3656 #define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
3657 #define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
3658 #define GPIO_MODER_MODE6_0             (0x1U << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
3659 #define GPIO_MODER_MODE6_1             (0x2U << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
3660 #define GPIO_MODER_MODE7_Pos           (14U)
3661 #define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
3662 #define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
3663 #define GPIO_MODER_MODE7_0             (0x1U << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
3664 #define GPIO_MODER_MODE7_1             (0x2U << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
3665 #define GPIO_MODER_MODE8_Pos           (16U)
3666 #define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
3667 #define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
3668 #define GPIO_MODER_MODE8_0             (0x1U << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
3669 #define GPIO_MODER_MODE8_1             (0x2U << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
3670 #define GPIO_MODER_MODE9_Pos           (18U)
3671 #define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
3672 #define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
3673 #define GPIO_MODER_MODE9_0             (0x1U << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
3674 #define GPIO_MODER_MODE9_1             (0x2U << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
3675 #define GPIO_MODER_MODE10_Pos          (20U)
3676 #define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
3677 #define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
3678 #define GPIO_MODER_MODE10_0            (0x1U << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
3679 #define GPIO_MODER_MODE10_1            (0x2U << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
3680 #define GPIO_MODER_MODE11_Pos          (22U)
3681 #define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
3682 #define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
3683 #define GPIO_MODER_MODE11_0            (0x1U << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
3684 #define GPIO_MODER_MODE11_1            (0x2U << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
3685 #define GPIO_MODER_MODE12_Pos          (24U)
3686 #define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
3687 #define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
3688 #define GPIO_MODER_MODE12_0            (0x1U << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
3689 #define GPIO_MODER_MODE12_1            (0x2U << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
3690 #define GPIO_MODER_MODE13_Pos          (26U)
3691 #define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
3692 #define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
3693 #define GPIO_MODER_MODE13_0            (0x1U << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
3694 #define GPIO_MODER_MODE13_1            (0x2U << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
3695 #define GPIO_MODER_MODE14_Pos          (28U)
3696 #define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
3697 #define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
3698 #define GPIO_MODER_MODE14_0            (0x1U << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
3699 #define GPIO_MODER_MODE14_1            (0x2U << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
3700 #define GPIO_MODER_MODE15_Pos          (30U)
3701 #define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
3702 #define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
3703 #define GPIO_MODER_MODE15_0            (0x1U << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
3704 #define GPIO_MODER_MODE15_1            (0x2U << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
3705 
3706 /******************  Bits definition for GPIO_OTYPER register  ****************/
3707 #define GPIO_OTYPER_OT0_Pos            (0U)
3708 #define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
3709 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
3710 #define GPIO_OTYPER_OT1_Pos            (1U)
3711 #define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
3712 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
3713 #define GPIO_OTYPER_OT2_Pos            (2U)
3714 #define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
3715 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
3716 #define GPIO_OTYPER_OT3_Pos            (3U)
3717 #define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
3718 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
3719 #define GPIO_OTYPER_OT4_Pos            (4U)
3720 #define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
3721 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
3722 #define GPIO_OTYPER_OT5_Pos            (5U)
3723 #define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
3724 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
3725 #define GPIO_OTYPER_OT6_Pos            (6U)
3726 #define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
3727 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
3728 #define GPIO_OTYPER_OT7_Pos            (7U)
3729 #define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
3730 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
3731 #define GPIO_OTYPER_OT8_Pos            (8U)
3732 #define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
3733 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
3734 #define GPIO_OTYPER_OT9_Pos            (9U)
3735 #define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
3736 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
3737 #define GPIO_OTYPER_OT10_Pos           (10U)
3738 #define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
3739 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
3740 #define GPIO_OTYPER_OT11_Pos           (11U)
3741 #define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
3742 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
3743 #define GPIO_OTYPER_OT12_Pos           (12U)
3744 #define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
3745 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
3746 #define GPIO_OTYPER_OT13_Pos           (13U)
3747 #define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
3748 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
3749 #define GPIO_OTYPER_OT14_Pos           (14U)
3750 #define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
3751 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
3752 #define GPIO_OTYPER_OT15_Pos           (15U)
3753 #define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
3754 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
3755 
3756 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
3757 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
3758 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
3759 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
3760 #define GPIO_OSPEEDR_OSPEED0_0         (0x1U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
3761 #define GPIO_OSPEEDR_OSPEED0_1         (0x2U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
3762 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
3763 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
3764 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
3765 #define GPIO_OSPEEDR_OSPEED1_0         (0x1U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
3766 #define GPIO_OSPEEDR_OSPEED1_1         (0x2U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
3767 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
3768 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
3769 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
3770 #define GPIO_OSPEEDR_OSPEED2_0         (0x1U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
3771 #define GPIO_OSPEEDR_OSPEED2_1         (0x2U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
3772 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
3773 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
3774 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
3775 #define GPIO_OSPEEDR_OSPEED3_0         (0x1U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
3776 #define GPIO_OSPEEDR_OSPEED3_1         (0x2U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
3777 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
3778 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
3779 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
3780 #define GPIO_OSPEEDR_OSPEED4_0         (0x1U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
3781 #define GPIO_OSPEEDR_OSPEED4_1         (0x2U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
3782 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
3783 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
3784 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
3785 #define GPIO_OSPEEDR_OSPEED5_0         (0x1U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
3786 #define GPIO_OSPEEDR_OSPEED5_1         (0x2U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
3787 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
3788 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
3789 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
3790 #define GPIO_OSPEEDR_OSPEED6_0         (0x1U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
3791 #define GPIO_OSPEEDR_OSPEED6_1         (0x2U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
3792 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
3793 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
3794 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
3795 #define GPIO_OSPEEDR_OSPEED7_0         (0x1U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
3796 #define GPIO_OSPEEDR_OSPEED7_1         (0x2U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
3797 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
3798 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
3799 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
3800 #define GPIO_OSPEEDR_OSPEED8_0         (0x1U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
3801 #define GPIO_OSPEEDR_OSPEED8_1         (0x2U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
3802 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
3803 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
3804 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
3805 #define GPIO_OSPEEDR_OSPEED9_0         (0x1U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
3806 #define GPIO_OSPEEDR_OSPEED9_1         (0x2U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
3807 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
3808 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
3809 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
3810 #define GPIO_OSPEEDR_OSPEED10_0        (0x1U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
3811 #define GPIO_OSPEEDR_OSPEED10_1        (0x2U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
3812 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
3813 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
3814 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
3815 #define GPIO_OSPEEDR_OSPEED11_0        (0x1U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
3816 #define GPIO_OSPEEDR_OSPEED11_1        (0x2U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
3817 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
3818 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
3819 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
3820 #define GPIO_OSPEEDR_OSPEED12_0        (0x1U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
3821 #define GPIO_OSPEEDR_OSPEED12_1        (0x2U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
3822 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
3823 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
3824 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
3825 #define GPIO_OSPEEDR_OSPEED13_0        (0x1U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
3826 #define GPIO_OSPEEDR_OSPEED13_1        (0x2U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
3827 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
3828 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
3829 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
3830 #define GPIO_OSPEEDR_OSPEED14_0        (0x1U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
3831 #define GPIO_OSPEEDR_OSPEED14_1        (0x2U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
3832 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
3833 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
3834 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
3835 #define GPIO_OSPEEDR_OSPEED15_0        (0x1U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
3836 #define GPIO_OSPEEDR_OSPEED15_1        (0x2U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
3837 
3838 /******************  Bits definition for GPIO_PUPDR register  *****************/
3839 #define GPIO_PUPDR_PUPD0_Pos           (0U)
3840 #define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
3841 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
3842 #define GPIO_PUPDR_PUPD0_0             (0x1U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
3843 #define GPIO_PUPDR_PUPD0_1             (0x2U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
3844 #define GPIO_PUPDR_PUPD1_Pos           (2U)
3845 #define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
3846 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
3847 #define GPIO_PUPDR_PUPD1_0             (0x1U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
3848 #define GPIO_PUPDR_PUPD1_1             (0x2U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
3849 #define GPIO_PUPDR_PUPD2_Pos           (4U)
3850 #define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
3851 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
3852 #define GPIO_PUPDR_PUPD2_0             (0x1U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
3853 #define GPIO_PUPDR_PUPD2_1             (0x2U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
3854 #define GPIO_PUPDR_PUPD3_Pos           (6U)
3855 #define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
3856 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
3857 #define GPIO_PUPDR_PUPD3_0             (0x1U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
3858 #define GPIO_PUPDR_PUPD3_1             (0x2U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
3859 #define GPIO_PUPDR_PUPD4_Pos           (8U)
3860 #define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
3861 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
3862 #define GPIO_PUPDR_PUPD4_0             (0x1U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
3863 #define GPIO_PUPDR_PUPD4_1             (0x2U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
3864 #define GPIO_PUPDR_PUPD5_Pos           (10U)
3865 #define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
3866 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
3867 #define GPIO_PUPDR_PUPD5_0             (0x1U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
3868 #define GPIO_PUPDR_PUPD5_1             (0x2U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
3869 #define GPIO_PUPDR_PUPD6_Pos           (12U)
3870 #define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
3871 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
3872 #define GPIO_PUPDR_PUPD6_0             (0x1U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
3873 #define GPIO_PUPDR_PUPD6_1             (0x2U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
3874 #define GPIO_PUPDR_PUPD7_Pos           (14U)
3875 #define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
3876 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
3877 #define GPIO_PUPDR_PUPD7_0             (0x1U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
3878 #define GPIO_PUPDR_PUPD7_1             (0x2U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
3879 #define GPIO_PUPDR_PUPD8_Pos           (16U)
3880 #define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
3881 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
3882 #define GPIO_PUPDR_PUPD8_0             (0x1U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
3883 #define GPIO_PUPDR_PUPD8_1             (0x2U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
3884 #define GPIO_PUPDR_PUPD9_Pos           (18U)
3885 #define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
3886 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
3887 #define GPIO_PUPDR_PUPD9_0             (0x1U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
3888 #define GPIO_PUPDR_PUPD9_1             (0x2U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
3889 #define GPIO_PUPDR_PUPD10_Pos          (20U)
3890 #define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
3891 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
3892 #define GPIO_PUPDR_PUPD10_0            (0x1U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
3893 #define GPIO_PUPDR_PUPD10_1            (0x2U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
3894 #define GPIO_PUPDR_PUPD11_Pos          (22U)
3895 #define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
3896 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
3897 #define GPIO_PUPDR_PUPD11_0            (0x1U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
3898 #define GPIO_PUPDR_PUPD11_1            (0x2U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
3899 #define GPIO_PUPDR_PUPD12_Pos          (24U)
3900 #define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
3901 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
3902 #define GPIO_PUPDR_PUPD12_0            (0x1U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
3903 #define GPIO_PUPDR_PUPD12_1            (0x2U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
3904 #define GPIO_PUPDR_PUPD13_Pos          (26U)
3905 #define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
3906 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
3907 #define GPIO_PUPDR_PUPD13_0            (0x1U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
3908 #define GPIO_PUPDR_PUPD13_1            (0x2U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
3909 #define GPIO_PUPDR_PUPD14_Pos          (28U)
3910 #define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
3911 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
3912 #define GPIO_PUPDR_PUPD14_0            (0x1U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
3913 #define GPIO_PUPDR_PUPD14_1            (0x2U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
3914 #define GPIO_PUPDR_PUPD15_Pos          (30U)
3915 #define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
3916 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
3917 #define GPIO_PUPDR_PUPD15_0            (0x1U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
3918 #define GPIO_PUPDR_PUPD15_1            (0x2U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
3919 
3920 /******************  Bits definition for GPIO_IDR register  *******************/
3921 #define GPIO_IDR_ID0_Pos               (0U)
3922 #define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
3923 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
3924 #define GPIO_IDR_ID1_Pos               (1U)
3925 #define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
3926 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
3927 #define GPIO_IDR_ID2_Pos               (2U)
3928 #define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
3929 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
3930 #define GPIO_IDR_ID3_Pos               (3U)
3931 #define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
3932 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
3933 #define GPIO_IDR_ID4_Pos               (4U)
3934 #define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
3935 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
3936 #define GPIO_IDR_ID5_Pos               (5U)
3937 #define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
3938 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
3939 #define GPIO_IDR_ID6_Pos               (6U)
3940 #define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
3941 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
3942 #define GPIO_IDR_ID7_Pos               (7U)
3943 #define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
3944 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
3945 #define GPIO_IDR_ID8_Pos               (8U)
3946 #define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
3947 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
3948 #define GPIO_IDR_ID9_Pos               (9U)
3949 #define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
3950 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
3951 #define GPIO_IDR_ID10_Pos              (10U)
3952 #define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
3953 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
3954 #define GPIO_IDR_ID11_Pos              (11U)
3955 #define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
3956 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
3957 #define GPIO_IDR_ID12_Pos              (12U)
3958 #define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
3959 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
3960 #define GPIO_IDR_ID13_Pos              (13U)
3961 #define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
3962 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
3963 #define GPIO_IDR_ID14_Pos              (14U)
3964 #define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
3965 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
3966 #define GPIO_IDR_ID15_Pos              (15U)
3967 #define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
3968 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
3969 
3970 /******************  Bits definition for GPIO_ODR register  *******************/
3971 #define GPIO_ODR_OD0_Pos               (0U)
3972 #define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
3973 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
3974 #define GPIO_ODR_OD1_Pos               (1U)
3975 #define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
3976 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
3977 #define GPIO_ODR_OD2_Pos               (2U)
3978 #define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
3979 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
3980 #define GPIO_ODR_OD3_Pos               (3U)
3981 #define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
3982 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
3983 #define GPIO_ODR_OD4_Pos               (4U)
3984 #define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
3985 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
3986 #define GPIO_ODR_OD5_Pos               (5U)
3987 #define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
3988 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
3989 #define GPIO_ODR_OD6_Pos               (6U)
3990 #define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
3991 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
3992 #define GPIO_ODR_OD7_Pos               (7U)
3993 #define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
3994 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
3995 #define GPIO_ODR_OD8_Pos               (8U)
3996 #define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
3997 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
3998 #define GPIO_ODR_OD9_Pos               (9U)
3999 #define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
4000 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
4001 #define GPIO_ODR_OD10_Pos              (10U)
4002 #define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
4003 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
4004 #define GPIO_ODR_OD11_Pos              (11U)
4005 #define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
4006 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
4007 #define GPIO_ODR_OD12_Pos              (12U)
4008 #define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
4009 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
4010 #define GPIO_ODR_OD13_Pos              (13U)
4011 #define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
4012 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
4013 #define GPIO_ODR_OD14_Pos              (14U)
4014 #define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
4015 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
4016 #define GPIO_ODR_OD15_Pos              (15U)
4017 #define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
4018 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
4019 
4020 /******************  Bits definition for GPIO_BSRR register  ******************/
4021 #define GPIO_BSRR_BS0_Pos              (0U)
4022 #define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
4023 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
4024 #define GPIO_BSRR_BS1_Pos              (1U)
4025 #define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
4026 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
4027 #define GPIO_BSRR_BS2_Pos              (2U)
4028 #define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
4029 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
4030 #define GPIO_BSRR_BS3_Pos              (3U)
4031 #define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
4032 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
4033 #define GPIO_BSRR_BS4_Pos              (4U)
4034 #define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
4035 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
4036 #define GPIO_BSRR_BS5_Pos              (5U)
4037 #define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
4038 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
4039 #define GPIO_BSRR_BS6_Pos              (6U)
4040 #define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
4041 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
4042 #define GPIO_BSRR_BS7_Pos              (7U)
4043 #define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
4044 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
4045 #define GPIO_BSRR_BS8_Pos              (8U)
4046 #define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
4047 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
4048 #define GPIO_BSRR_BS9_Pos              (9U)
4049 #define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
4050 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
4051 #define GPIO_BSRR_BS10_Pos             (10U)
4052 #define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
4053 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
4054 #define GPIO_BSRR_BS11_Pos             (11U)
4055 #define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
4056 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
4057 #define GPIO_BSRR_BS12_Pos             (12U)
4058 #define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
4059 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
4060 #define GPIO_BSRR_BS13_Pos             (13U)
4061 #define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
4062 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
4063 #define GPIO_BSRR_BS14_Pos             (14U)
4064 #define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
4065 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
4066 #define GPIO_BSRR_BS15_Pos             (15U)
4067 #define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
4068 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
4069 #define GPIO_BSRR_BR0_Pos              (16U)
4070 #define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
4071 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
4072 #define GPIO_BSRR_BR1_Pos              (17U)
4073 #define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
4074 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
4075 #define GPIO_BSRR_BR2_Pos              (18U)
4076 #define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
4077 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
4078 #define GPIO_BSRR_BR3_Pos              (19U)
4079 #define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
4080 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
4081 #define GPIO_BSRR_BR4_Pos              (20U)
4082 #define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
4083 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
4084 #define GPIO_BSRR_BR5_Pos              (21U)
4085 #define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
4086 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
4087 #define GPIO_BSRR_BR6_Pos              (22U)
4088 #define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
4089 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
4090 #define GPIO_BSRR_BR7_Pos              (23U)
4091 #define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
4092 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
4093 #define GPIO_BSRR_BR8_Pos              (24U)
4094 #define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
4095 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
4096 #define GPIO_BSRR_BR9_Pos              (25U)
4097 #define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
4098 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
4099 #define GPIO_BSRR_BR10_Pos             (26U)
4100 #define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
4101 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
4102 #define GPIO_BSRR_BR11_Pos             (27U)
4103 #define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
4104 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
4105 #define GPIO_BSRR_BR12_Pos             (28U)
4106 #define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
4107 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
4108 #define GPIO_BSRR_BR13_Pos             (29U)
4109 #define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
4110 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
4111 #define GPIO_BSRR_BR14_Pos             (30U)
4112 #define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
4113 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
4114 #define GPIO_BSRR_BR15_Pos             (31U)
4115 #define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
4116 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
4117 
4118 /****************** Bit definition for GPIO_LCKR register *********************/
4119 #define GPIO_LCKR_LCK0_Pos             (0U)
4120 #define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
4121 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
4122 #define GPIO_LCKR_LCK1_Pos             (1U)
4123 #define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
4124 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
4125 #define GPIO_LCKR_LCK2_Pos             (2U)
4126 #define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
4127 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
4128 #define GPIO_LCKR_LCK3_Pos             (3U)
4129 #define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
4130 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
4131 #define GPIO_LCKR_LCK4_Pos             (4U)
4132 #define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
4133 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
4134 #define GPIO_LCKR_LCK5_Pos             (5U)
4135 #define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
4136 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
4137 #define GPIO_LCKR_LCK6_Pos             (6U)
4138 #define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
4139 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
4140 #define GPIO_LCKR_LCK7_Pos             (7U)
4141 #define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
4142 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
4143 #define GPIO_LCKR_LCK8_Pos             (8U)
4144 #define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
4145 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
4146 #define GPIO_LCKR_LCK9_Pos             (9U)
4147 #define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
4148 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
4149 #define GPIO_LCKR_LCK10_Pos            (10U)
4150 #define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
4151 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
4152 #define GPIO_LCKR_LCK11_Pos            (11U)
4153 #define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
4154 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
4155 #define GPIO_LCKR_LCK12_Pos            (12U)
4156 #define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
4157 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
4158 #define GPIO_LCKR_LCK13_Pos            (13U)
4159 #define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
4160 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
4161 #define GPIO_LCKR_LCK14_Pos            (14U)
4162 #define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
4163 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
4164 #define GPIO_LCKR_LCK15_Pos            (15U)
4165 #define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
4166 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
4167 #define GPIO_LCKR_LCKK_Pos             (16U)
4168 #define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
4169 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
4170 
4171 /****************** Bit definition for GPIO_AFRL register *********************/
4172 #define GPIO_AFRL_AFSEL0_Pos           (0U)
4173 #define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
4174 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
4175 #define GPIO_AFRL_AFSEL0_0             (0x1U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
4176 #define GPIO_AFRL_AFSEL0_1             (0x2U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
4177 #define GPIO_AFRL_AFSEL0_2             (0x4U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
4178 #define GPIO_AFRL_AFSEL0_3             (0x8U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
4179 #define GPIO_AFRL_AFSEL1_Pos           (4U)
4180 #define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
4181 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
4182 #define GPIO_AFRL_AFSEL1_0             (0x1U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
4183 #define GPIO_AFRL_AFSEL1_1             (0x2U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
4184 #define GPIO_AFRL_AFSEL1_2             (0x4U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
4185 #define GPIO_AFRL_AFSEL1_3             (0x8U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
4186 #define GPIO_AFRL_AFSEL2_Pos           (8U)
4187 #define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
4188 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
4189 #define GPIO_AFRL_AFSEL2_0             (0x1U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
4190 #define GPIO_AFRL_AFSEL2_1             (0x2U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
4191 #define GPIO_AFRL_AFSEL2_2             (0x4U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
4192 #define GPIO_AFRL_AFSEL2_3             (0x8U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
4193 #define GPIO_AFRL_AFSEL3_Pos           (12U)
4194 #define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
4195 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
4196 #define GPIO_AFRL_AFSEL3_0             (0x1U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
4197 #define GPIO_AFRL_AFSEL3_1             (0x2U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
4198 #define GPIO_AFRL_AFSEL3_2             (0x4U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
4199 #define GPIO_AFRL_AFSEL3_3             (0x8U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
4200 #define GPIO_AFRL_AFSEL4_Pos           (16U)
4201 #define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
4202 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
4203 #define GPIO_AFRL_AFSEL4_0             (0x1U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
4204 #define GPIO_AFRL_AFSEL4_1             (0x2U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
4205 #define GPIO_AFRL_AFSEL4_2             (0x4U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
4206 #define GPIO_AFRL_AFSEL4_3             (0x8U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
4207 #define GPIO_AFRL_AFSEL5_Pos           (20U)
4208 #define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
4209 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
4210 #define GPIO_AFRL_AFSEL5_0             (0x1U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
4211 #define GPIO_AFRL_AFSEL5_1             (0x2U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
4212 #define GPIO_AFRL_AFSEL5_2             (0x4U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
4213 #define GPIO_AFRL_AFSEL5_3             (0x8U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
4214 #define GPIO_AFRL_AFSEL6_Pos           (24U)
4215 #define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
4216 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
4217 #define GPIO_AFRL_AFSEL6_0             (0x1U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
4218 #define GPIO_AFRL_AFSEL6_1             (0x2U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
4219 #define GPIO_AFRL_AFSEL6_2             (0x4U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
4220 #define GPIO_AFRL_AFSEL6_3             (0x8U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
4221 #define GPIO_AFRL_AFSEL7_Pos           (28U)
4222 #define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
4223 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
4224 #define GPIO_AFRL_AFSEL7_0             (0x1U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
4225 #define GPIO_AFRL_AFSEL7_1             (0x2U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
4226 #define GPIO_AFRL_AFSEL7_2             (0x4U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
4227 #define GPIO_AFRL_AFSEL7_3             (0x8U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
4228 
4229 /****************** Bit definition for GPIO_AFRH register *********************/
4230 #define GPIO_AFRH_AFSEL8_Pos           (0U)
4231 #define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
4232 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
4233 #define GPIO_AFRH_AFSEL8_0             (0x1U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
4234 #define GPIO_AFRH_AFSEL8_1             (0x2U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
4235 #define GPIO_AFRH_AFSEL8_2             (0x4U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
4236 #define GPIO_AFRH_AFSEL8_3             (0x8U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
4237 #define GPIO_AFRH_AFSEL9_Pos           (4U)
4238 #define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
4239 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
4240 #define GPIO_AFRH_AFSEL9_0             (0x1U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
4241 #define GPIO_AFRH_AFSEL9_1             (0x2U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
4242 #define GPIO_AFRH_AFSEL9_2             (0x4U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
4243 #define GPIO_AFRH_AFSEL9_3             (0x8U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
4244 #define GPIO_AFRH_AFSEL10_Pos          (8U)
4245 #define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
4246 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
4247 #define GPIO_AFRH_AFSEL10_0            (0x1U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
4248 #define GPIO_AFRH_AFSEL10_1            (0x2U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
4249 #define GPIO_AFRH_AFSEL10_2            (0x4U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
4250 #define GPIO_AFRH_AFSEL10_3            (0x8U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
4251 #define GPIO_AFRH_AFSEL11_Pos          (12U)
4252 #define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
4253 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
4254 #define GPIO_AFRH_AFSEL11_0            (0x1U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
4255 #define GPIO_AFRH_AFSEL11_1            (0x2U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
4256 #define GPIO_AFRH_AFSEL11_2            (0x4U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
4257 #define GPIO_AFRH_AFSEL11_3            (0x8U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
4258 #define GPIO_AFRH_AFSEL12_Pos          (16U)
4259 #define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
4260 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
4261 #define GPIO_AFRH_AFSEL12_0            (0x1U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
4262 #define GPIO_AFRH_AFSEL12_1            (0x2U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
4263 #define GPIO_AFRH_AFSEL12_2            (0x4U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
4264 #define GPIO_AFRH_AFSEL12_3            (0x8U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
4265 #define GPIO_AFRH_AFSEL13_Pos          (20U)
4266 #define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
4267 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
4268 #define GPIO_AFRH_AFSEL13_0            (0x1U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
4269 #define GPIO_AFRH_AFSEL13_1            (0x2U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
4270 #define GPIO_AFRH_AFSEL13_2            (0x4U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
4271 #define GPIO_AFRH_AFSEL13_3            (0x8U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
4272 #define GPIO_AFRH_AFSEL14_Pos          (24U)
4273 #define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
4274 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
4275 #define GPIO_AFRH_AFSEL14_0            (0x1U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
4276 #define GPIO_AFRH_AFSEL14_1            (0x2U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
4277 #define GPIO_AFRH_AFSEL14_2            (0x4U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
4278 #define GPIO_AFRH_AFSEL14_3            (0x8U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
4279 #define GPIO_AFRH_AFSEL15_Pos          (28U)
4280 #define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
4281 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
4282 #define GPIO_AFRH_AFSEL15_0            (0x1U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
4283 #define GPIO_AFRH_AFSEL15_1            (0x2U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
4284 #define GPIO_AFRH_AFSEL15_2            (0x4U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
4285 #define GPIO_AFRH_AFSEL15_3            (0x8U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
4286 
4287 /******************  Bits definition for GPIO_BRR register  ******************/
4288 #define GPIO_BRR_BR0_Pos               (0U)
4289 #define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
4290 #define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
4291 #define GPIO_BRR_BR1_Pos               (1U)
4292 #define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
4293 #define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
4294 #define GPIO_BRR_BR2_Pos               (2U)
4295 #define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
4296 #define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
4297 #define GPIO_BRR_BR3_Pos               (3U)
4298 #define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
4299 #define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
4300 #define GPIO_BRR_BR4_Pos               (4U)
4301 #define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
4302 #define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
4303 #define GPIO_BRR_BR5_Pos               (5U)
4304 #define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
4305 #define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
4306 #define GPIO_BRR_BR6_Pos               (6U)
4307 #define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
4308 #define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
4309 #define GPIO_BRR_BR7_Pos               (7U)
4310 #define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
4311 #define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
4312 #define GPIO_BRR_BR8_Pos               (8U)
4313 #define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
4314 #define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
4315 #define GPIO_BRR_BR9_Pos               (9U)
4316 #define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
4317 #define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
4318 #define GPIO_BRR_BR10_Pos              (10U)
4319 #define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
4320 #define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
4321 #define GPIO_BRR_BR11_Pos              (11U)
4322 #define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
4323 #define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
4324 #define GPIO_BRR_BR12_Pos              (12U)
4325 #define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
4326 #define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
4327 #define GPIO_BRR_BR13_Pos              (13U)
4328 #define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
4329 #define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
4330 #define GPIO_BRR_BR14_Pos              (14U)
4331 #define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
4332 #define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
4333 #define GPIO_BRR_BR15_Pos              (15U)
4334 #define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
4335 #define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
4336 
4337 /******************************************************************************/
4338 /*                                                                            */
4339 /*                        HSEM HW Semaphore                                   */
4340 /*                                                                            */
4341 /******************************************************************************/
4342 /********************  Bit definition for HSEM_R register  ********************/
4343 #define HSEM_R_PROCID_Pos        (0U)
4344 #define HSEM_R_PROCID_Msk        (0xFFUL << HSEM_R_PROCID_Pos)                 /*!< 0x000000FF */
4345 #define HSEM_R_PROCID            HSEM_R_PROCID_Msk                             /*!<Semaphore ProcessID */
4346 #define HSEM_R_COREID_Pos        (8U)
4347 #define HSEM_R_COREID_Msk        (0xFUL << HSEM_R_COREID_Pos)                  /*!< 0x00000F00 */
4348 #define HSEM_R_COREID            HSEM_R_COREID_Msk                             /*!<Semaphore CoreID. */
4349 #define HSEM_R_LOCK_Pos          (31U)
4350 #define HSEM_R_LOCK_Msk          (0x1UL << HSEM_R_LOCK_Pos)                    /*!< 0x80000000 */
4351 #define HSEM_R_LOCK              HSEM_R_LOCK_Msk                               /*!<Lock indication. */
4352 
4353 /********************  Bit definition for HSEM_RLR register  ******************/
4354 #define HSEM_RLR_PROCID_Pos      (0U)
4355 #define HSEM_RLR_PROCID_Msk      (0xFFUL << HSEM_RLR_PROCID_Pos)               /*!< 0x000000FF */
4356 #define HSEM_RLR_PROCID          HSEM_RLR_PROCID_Msk                           /*!<Semaphore ProcessID */
4357 #define HSEM_RLR_COREID_Pos      (8U)
4358 #define HSEM_RLR_COREID_Msk      (0xFUL << HSEM_RLR_COREID_Pos)                /*!< 0x00000F00 */
4359 #define HSEM_RLR_COREID          HSEM_RLR_COREID_Msk                           /*!<Semaphore CoreID. */
4360 #define HSEM_RLR_LOCK_Pos        (31U)
4361 #define HSEM_RLR_LOCK_Msk        (0x1UL << HSEM_RLR_LOCK_Pos)                  /*!< 0x80000000 */
4362 #define HSEM_RLR_LOCK            HSEM_RLR_LOCK_Msk                             /*!<Lock indication. */
4363 
4364 /********************  Bit definition for HSEM_C1IER register  ****************/
4365 #define HSEM_C1IER_ISE0_Pos      (0U)
4366 #define HSEM_C1IER_ISE0_Msk      (0x1UL << HSEM_C1IER_ISE0_Pos)                /*!< 0x00000001 */
4367 #define HSEM_C1IER_ISE0          HSEM_C1IER_ISE0_Msk                           /*!<semaphore 0 CPU1 interrupt enable bit.  */
4368 #define HSEM_C1IER_ISE1_Pos      (1U)
4369 #define HSEM_C1IER_ISE1_Msk      (0x1UL << HSEM_C1IER_ISE1_Pos)                /*!< 0x00000002 */
4370 #define HSEM_C1IER_ISE1          HSEM_C1IER_ISE1_Msk                           /*!<semaphore 1 CPU1 interrupt enable bit.  */
4371 #define HSEM_C1IER_ISE2_Pos      (2U)
4372 #define HSEM_C1IER_ISE2_Msk      (0x1UL << HSEM_C1IER_ISE2_Pos)                /*!< 0x00000004 */
4373 #define HSEM_C1IER_ISE2          HSEM_C1IER_ISE2_Msk                           /*!<semaphore 2 CPU1 interrupt enable bit.  */
4374 #define HSEM_C1IER_ISE3_Pos      (3U)
4375 #define HSEM_C1IER_ISE3_Msk      (0x1UL << HSEM_C1IER_ISE3_Pos)                /*!< 0x00000008 */
4376 #define HSEM_C1IER_ISE3          HSEM_C1IER_ISE3_Msk                           /*!<semaphore 3 CPU1 interrupt enable bit.  */
4377 #define HSEM_C1IER_ISE4_Pos      (4U)
4378 #define HSEM_C1IER_ISE4_Msk      (0x1UL << HSEM_C1IER_ISE4_Pos)                /*!< 0x00000010 */
4379 #define HSEM_C1IER_ISE4          HSEM_C1IER_ISE4_Msk                           /*!<semaphore 4 CPU1 interrupt enable bit.  */
4380 #define HSEM_C1IER_ISE5_Pos      (5U)
4381 #define HSEM_C1IER_ISE5_Msk      (0x1UL << HSEM_C1IER_ISE5_Pos)                /*!< 0x00000020 */
4382 #define HSEM_C1IER_ISE5          HSEM_C1IER_ISE5_Msk                           /*!<semaphore 5 CPU1 interrupt enable bit.  */
4383 #define HSEM_C1IER_ISE6_Pos      (6U)
4384 #define HSEM_C1IER_ISE6_Msk      (0x1UL << HSEM_C1IER_ISE6_Pos)                /*!< 0x00000040 */
4385 #define HSEM_C1IER_ISE6          HSEM_C1IER_ISE6_Msk                           /*!<semaphore 6 CPU1 interrupt enable bit.  */
4386 #define HSEM_C1IER_ISE7_Pos      (7U)
4387 #define HSEM_C1IER_ISE7_Msk      (0x1UL << HSEM_C1IER_ISE7_Pos)                /*!< 0x00000080 */
4388 #define HSEM_C1IER_ISE7          HSEM_C1IER_ISE7_Msk                           /*!<semaphore 7 CPU1 interrupt enable bit.  */
4389 #define HSEM_C1IER_ISE8_Pos      (8U)
4390 #define HSEM_C1IER_ISE8_Msk      (0x1UL << HSEM_C1IER_ISE8_Pos)                /*!< 0x00000100 */
4391 #define HSEM_C1IER_ISE8          HSEM_C1IER_ISE8_Msk                           /*!<semaphore 8 CPU1 interrupt enable bit.  */
4392 #define HSEM_C1IER_ISE9_Pos      (9U)
4393 #define HSEM_C1IER_ISE9_Msk      (0x1UL << HSEM_C1IER_ISE9_Pos)                /*!< 0x00000200 */
4394 #define HSEM_C1IER_ISE9          HSEM_C1IER_ISE9_Msk                           /*!<semaphore 9 CPU1 interrupt enable bit.  */
4395 #define HSEM_C1IER_ISE10_Pos     (10U)
4396 #define HSEM_C1IER_ISE10_Msk     (0x1UL << HSEM_C1IER_ISE10_Pos)               /*!< 0x00000400 */
4397 #define HSEM_C1IER_ISE10         HSEM_C1IER_ISE10_Msk                          /*!<semaphore 10 CPU1 interrupt enable bit. */
4398 #define HSEM_C1IER_ISE11_Pos     (11U)
4399 #define HSEM_C1IER_ISE11_Msk     (0x1UL << HSEM_C1IER_ISE11_Pos)               /*!< 0x00000800 */
4400 #define HSEM_C1IER_ISE11         HSEM_C1IER_ISE11_Msk                          /*!<semaphore 11 CPU1 interrupt enable bit. */
4401 #define HSEM_C1IER_ISE12_Pos     (12U)
4402 #define HSEM_C1IER_ISE12_Msk     (0x1UL << HSEM_C1IER_ISE12_Pos)               /*!< 0x00001000 */
4403 #define HSEM_C1IER_ISE12         HSEM_C1IER_ISE12_Msk                          /*!<semaphore 12 CPU1 interrupt enable bit. */
4404 #define HSEM_C1IER_ISE13_Pos     (13U)
4405 #define HSEM_C1IER_ISE13_Msk     (0x1UL << HSEM_C1IER_ISE13_Pos)               /*!< 0x00002000 */
4406 #define HSEM_C1IER_ISE13         HSEM_C1IER_ISE13_Msk                          /*!<semaphore 13 CPU1 interrupt enable bit. */
4407 #define HSEM_C1IER_ISE14_Pos     (14U)
4408 #define HSEM_C1IER_ISE14_Msk     (0x1UL << HSEM_C1IER_ISE14_Pos)               /*!< 0x00004000 */
4409 #define HSEM_C1IER_ISE14         HSEM_C1IER_ISE14_Msk                          /*!<semaphore 14 CPU1 interrupt enable bit. */
4410 #define HSEM_C1IER_ISE15_Pos     (15U)
4411 #define HSEM_C1IER_ISE15_Msk     (0x1UL << HSEM_C1IER_ISE15_Pos)               /*!< 0x00008000 */
4412 #define HSEM_C1IER_ISE15         HSEM_C1IER_ISE15_Msk                          /*!<semaphore 15 CPU1 interrupt enable bit. */
4413 #define HSEM_C1IER_ISE16_Pos     (16U)
4414 #define HSEM_C1IER_ISE16_Msk     (0x1UL << HSEM_C1IER_ISE16_Pos)               /*!< 0x00010000 */
4415 #define HSEM_C1IER_ISE16         HSEM_C1IER_ISE16_Msk                          /*!<semaphore 16 CPU1 interrupt enable bit. */
4416 #define HSEM_C1IER_ISE17_Pos     (17U)
4417 #define HSEM_C1IER_ISE17_Msk     (0x1UL << HSEM_C1IER_ISE17_Pos)               /*!< 0x00020000 */
4418 #define HSEM_C1IER_ISE17         HSEM_C1IER_ISE17_Msk                          /*!<semaphore 17 CPU1 interrupt enable bit. */
4419 #define HSEM_C1IER_ISE18_Pos     (18U)
4420 #define HSEM_C1IER_ISE18_Msk     (0x1UL << HSEM_C1IER_ISE18_Pos)               /*!< 0x00040000 */
4421 #define HSEM_C1IER_ISE18         HSEM_C1IER_ISE18_Msk                          /*!<semaphore 18 CPU1 interrupt enable bit. */
4422 #define HSEM_C1IER_ISE19_Pos     (19U)
4423 #define HSEM_C1IER_ISE19_Msk     (0x1UL << HSEM_C1IER_ISE19_Pos)               /*!< 0x00080000 */
4424 #define HSEM_C1IER_ISE19         HSEM_C1IER_ISE19_Msk                          /*!<semaphore 19 CPU1 interrupt enable bit. */
4425 #define HSEM_C1IER_ISE20_Pos     (20U)
4426 #define HSEM_C1IER_ISE20_Msk     (0x1UL << HSEM_C1IER_ISE20_Pos)               /*!< 0x00100000 */
4427 #define HSEM_C1IER_ISE20         HSEM_C1IER_ISE20_Msk                          /*!<semaphore 20 CPU1 interrupt enable bit. */
4428 #define HSEM_C1IER_ISE21_Pos     (21U)
4429 #define HSEM_C1IER_ISE21_Msk     (0x1UL << HSEM_C1IER_ISE21_Pos)               /*!< 0x00200000 */
4430 #define HSEM_C1IER_ISE21         HSEM_C1IER_ISE21_Msk                          /*!<semaphore 21 CPU1 interrupt enable bit. */
4431 #define HSEM_C1IER_ISE22_Pos     (22U)
4432 #define HSEM_C1IER_ISE22_Msk     (0x1UL << HSEM_C1IER_ISE22_Pos)               /*!< 0x00400000 */
4433 #define HSEM_C1IER_ISE22         HSEM_C1IER_ISE22_Msk                          /*!<semaphore 22 CPU1 interrupt enable bit. */
4434 #define HSEM_C1IER_ISE23_Pos     (23U)
4435 #define HSEM_C1IER_ISE23_Msk     (0x1UL << HSEM_C1IER_ISE23_Pos)               /*!< 0x00800000 */
4436 #define HSEM_C1IER_ISE23         HSEM_C1IER_ISE23_Msk                          /*!<semaphore 23 CPU1 interrupt enable bit. */
4437 #define HSEM_C1IER_ISE24_Pos     (24U)
4438 #define HSEM_C1IER_ISE24_Msk     (0x1UL << HSEM_C1IER_ISE24_Pos)               /*!< 0x01000000 */
4439 #define HSEM_C1IER_ISE24         HSEM_C1IER_ISE24_Msk                          /*!<semaphore 24 CPU1 interrupt enable bit. */
4440 #define HSEM_C1IER_ISE25_Pos     (25U)
4441 #define HSEM_C1IER_ISE25_Msk     (0x1UL << HSEM_C1IER_ISE25_Pos)               /*!< 0x02000000 */
4442 #define HSEM_C1IER_ISE25         HSEM_C1IER_ISE25_Msk                          /*!<semaphore 25 CPU1 interrupt enable bit. */
4443 #define HSEM_C1IER_ISE26_Pos     (26U)
4444 #define HSEM_C1IER_ISE26_Msk     (0x1UL << HSEM_C1IER_ISE26_Pos)               /*!< 0x04000000 */
4445 #define HSEM_C1IER_ISE26         HSEM_C1IER_ISE26_Msk                          /*!<semaphore 26 CPU1 interrupt enable bit. */
4446 #define HSEM_C1IER_ISE27_Pos     (27U)
4447 #define HSEM_C1IER_ISE27_Msk     (0x1UL << HSEM_C1IER_ISE27_Pos)               /*!< 0x08000000 */
4448 #define HSEM_C1IER_ISE27         HSEM_C1IER_ISE27_Msk                          /*!<semaphore 27 CPU1 interrupt enable bit. */
4449 #define HSEM_C1IER_ISE28_Pos     (28U)
4450 #define HSEM_C1IER_ISE28_Msk     (0x1UL << HSEM_C1IER_ISE28_Pos)               /*!< 0x10000000 */
4451 #define HSEM_C1IER_ISE28         HSEM_C1IER_ISE28_Msk                          /*!<semaphore 28 CPU1 interrupt enable bit. */
4452 #define HSEM_C1IER_ISE29_Pos     (29U)
4453 #define HSEM_C1IER_ISE29_Msk     (0x1UL << HSEM_C1IER_ISE29_Pos)               /*!< 0x20000000 */
4454 #define HSEM_C1IER_ISE29         HSEM_C1IER_ISE29_Msk                          /*!<semaphore 29 CPU1 interrupt enable bit. */
4455 #define HSEM_C1IER_ISE30_Pos     (30U)
4456 #define HSEM_C1IER_ISE30_Msk     (0x1UL << HSEM_C1IER_ISE30_Pos)               /*!< 0x40000000 */
4457 #define HSEM_C1IER_ISE30         HSEM_C1IER_ISE30_Msk                          /*!<semaphore 30 CPU1 interrupt enable bit. */
4458 #define HSEM_C1IER_ISE31_Pos     (31U)
4459 #define HSEM_C1IER_ISE31_Msk     (0x1UL << HSEM_C1IER_ISE31_Pos)               /*!< 0x80000000 */
4460 #define HSEM_C1IER_ISE31         HSEM_C1IER_ISE31_Msk                          /*!<semaphore 31 CPU1 interrupt enable bit. */
4461 
4462 /********************  Bit definition for HSEM_C1ICR register  *****************/
4463 #define HSEM_C1ICR_ISC0_Pos      (0U)
4464 #define HSEM_C1ICR_ISC0_Msk      (0x1UL << HSEM_C1ICR_ISC0_Pos)                /*!< 0x00000001 */
4465 #define HSEM_C1ICR_ISC0          HSEM_C1ICR_ISC0_Msk                           /*!<semaphore 0 CPU1 interrupt clear bit.  */
4466 #define HSEM_C1ICR_ISC1_Pos      (1U)
4467 #define HSEM_C1ICR_ISC1_Msk      (0x1UL << HSEM_C1ICR_ISC1_Pos)                /*!< 0x00000002 */
4468 #define HSEM_C1ICR_ISC1          HSEM_C1ICR_ISC1_Msk                           /*!<semaphore 1 CPU1 interrupt clear bit.  */
4469 #define HSEM_C1ICR_ISC2_Pos      (2U)
4470 #define HSEM_C1ICR_ISC2_Msk      (0x1UL << HSEM_C1ICR_ISC2_Pos)                /*!< 0x00000004 */
4471 #define HSEM_C1ICR_ISC2          HSEM_C1ICR_ISC2_Msk                           /*!<semaphore 2 CPU1 interrupt clear bit.  */
4472 #define HSEM_C1ICR_ISC3_Pos      (3U)
4473 #define HSEM_C1ICR_ISC3_Msk      (0x1UL << HSEM_C1ICR_ISC3_Pos)                /*!< 0x00000008 */
4474 #define HSEM_C1ICR_ISC3          HSEM_C1ICR_ISC3_Msk                           /*!<semaphore 3 CPU1 interrupt clear bit.  */
4475 #define HSEM_C1ICR_ISC4_Pos      (4U)
4476 #define HSEM_C1ICR_ISC4_Msk      (0x1UL << HSEM_C1ICR_ISC4_Pos)                /*!< 0x00000010 */
4477 #define HSEM_C1ICR_ISC4          HSEM_C1ICR_ISC4_Msk                           /*!<semaphore 4 CPU1 interrupt clear bit.  */
4478 #define HSEM_C1ICR_ISC5_Pos      (5U)
4479 #define HSEM_C1ICR_ISC5_Msk      (0x1UL << HSEM_C1ICR_ISC5_Pos)                /*!< 0x00000020 */
4480 #define HSEM_C1ICR_ISC5          HSEM_C1ICR_ISC5_Msk                           /*!<semaphore 5 CPU1 interrupt clear bit.  */
4481 #define HSEM_C1ICR_ISC6_Pos      (6U)
4482 #define HSEM_C1ICR_ISC6_Msk      (0x1UL << HSEM_C1ICR_ISC6_Pos)                /*!< 0x00000040 */
4483 #define HSEM_C1ICR_ISC6          HSEM_C1ICR_ISC6_Msk                           /*!<semaphore 6 CPU1 interrupt clear bit.  */
4484 #define HSEM_C1ICR_ISC7_Pos      (7U)
4485 #define HSEM_C1ICR_ISC7_Msk      (0x1UL << HSEM_C1ICR_ISC7_Pos)                /*!< 0x00000080 */
4486 #define HSEM_C1ICR_ISC7          HSEM_C1ICR_ISC7_Msk                           /*!<semaphore 7 CPU1 interrupt clear bit.  */
4487 #define HSEM_C1ICR_ISC8_Pos      (8U)
4488 #define HSEM_C1ICR_ISC8_Msk      (0x1UL << HSEM_C1ICR_ISC8_Pos)                /*!< 0x00000100 */
4489 #define HSEM_C1ICR_ISC8          HSEM_C1ICR_ISC8_Msk                           /*!<semaphore 8 CPU1 interrupt clear bit.  */
4490 #define HSEM_C1ICR_ISC9_Pos      (9U)
4491 #define HSEM_C1ICR_ISC9_Msk      (0x1UL << HSEM_C1ICR_ISC9_Pos)                /*!< 0x00000200 */
4492 #define HSEM_C1ICR_ISC9          HSEM_C1ICR_ISC9_Msk                           /*!<semaphore 9 CPU1 interrupt clear bit.  */
4493 #define HSEM_C1ICR_ISC10_Pos     (10U)
4494 #define HSEM_C1ICR_ISC10_Msk     (0x1UL << HSEM_C1ICR_ISC10_Pos)               /*!< 0x00000400 */
4495 #define HSEM_C1ICR_ISC10         HSEM_C1ICR_ISC10_Msk                          /*!<semaphore 10 CPU1 interrupt clear bit. */
4496 #define HSEM_C1ICR_ISC11_Pos     (11U)
4497 #define HSEM_C1ICR_ISC11_Msk     (0x1UL << HSEM_C1ICR_ISC11_Pos)               /*!< 0x00000800 */
4498 #define HSEM_C1ICR_ISC11         HSEM_C1ICR_ISC11_Msk                          /*!<semaphore 11 CPU1 interrupt clear bit. */
4499 #define HSEM_C1ICR_ISC12_Pos     (12U)
4500 #define HSEM_C1ICR_ISC12_Msk     (0x1UL << HSEM_C1ICR_ISC12_Pos)               /*!< 0x00001000 */
4501 #define HSEM_C1ICR_ISC12         HSEM_C1ICR_ISC12_Msk                          /*!<semaphore 12 CPU1 interrupt clear bit. */
4502 #define HSEM_C1ICR_ISC13_Pos     (13U)
4503 #define HSEM_C1ICR_ISC13_Msk     (0x1UL << HSEM_C1ICR_ISC13_Pos)               /*!< 0x00002000 */
4504 #define HSEM_C1ICR_ISC13         HSEM_C1ICR_ISC13_Msk                          /*!<semaphore 13 CPU1 interrupt clear bit. */
4505 #define HSEM_C1ICR_ISC14_Pos     (14U)
4506 #define HSEM_C1ICR_ISC14_Msk     (0x1UL << HSEM_C1ICR_ISC14_Pos)               /*!< 0x00004000 */
4507 #define HSEM_C1ICR_ISC14         HSEM_C1ICR_ISC14_Msk                          /*!<semaphore 14 CPU1 interrupt clear bit. */
4508 #define HSEM_C1ICR_ISC15_Pos     (15U)
4509 #define HSEM_C1ICR_ISC15_Msk     (0x1UL << HSEM_C1ICR_ISC15_Pos)               /*!< 0x00008000 */
4510 #define HSEM_C1ICR_ISC15         HSEM_C1ICR_ISC15_Msk                          /*!<semaphore 15 CPU1 interrupt clear bit. */
4511 #define HSEM_C1ICR_ISC16_Pos     (16U)
4512 #define HSEM_C1ICR_ISC16_Msk     (0x1UL << HSEM_C1ICR_ISC16_Pos)               /*!< 0x00010000 */
4513 #define HSEM_C1ICR_ISC16         HSEM_C1ICR_ISC16_Msk                          /*!<semaphore 16 CPU1 interrupt clear bit. */
4514 #define HSEM_C1ICR_ISC17_Pos     (17U)
4515 #define HSEM_C1ICR_ISC17_Msk     (0x1UL << HSEM_C1ICR_ISC17_Pos)               /*!< 0x00020000 */
4516 #define HSEM_C1ICR_ISC17         HSEM_C1ICR_ISC17_Msk                          /*!<semaphore 17 CPU1 interrupt clear bit. */
4517 #define HSEM_C1ICR_ISC18_Pos     (18U)
4518 #define HSEM_C1ICR_ISC18_Msk     (0x1UL << HSEM_C1ICR_ISC18_Pos)               /*!< 0x00040000 */
4519 #define HSEM_C1ICR_ISC18         HSEM_C1ICR_ISC18_Msk                          /*!<semaphore 18 CPU1 interrupt clear bit. */
4520 #define HSEM_C1ICR_ISC19_Pos     (19U)
4521 #define HSEM_C1ICR_ISC19_Msk     (0x1UL << HSEM_C1ICR_ISC19_Pos)               /*!< 0x00080000 */
4522 #define HSEM_C1ICR_ISC19         HSEM_C1ICR_ISC19_Msk                          /*!<semaphore 19 CPU1 interrupt clear bit. */
4523 #define HSEM_C1ICR_ISC20_Pos     (20U)
4524 #define HSEM_C1ICR_ISC20_Msk     (0x1UL << HSEM_C1ICR_ISC20_Pos)               /*!< 0x00100000 */
4525 #define HSEM_C1ICR_ISC20         HSEM_C1ICR_ISC20_Msk                          /*!<semaphore 20 CPU1 interrupt clear bit. */
4526 #define HSEM_C1ICR_ISC21_Pos     (21U)
4527 #define HSEM_C1ICR_ISC21_Msk     (0x1UL << HSEM_C1ICR_ISC21_Pos)               /*!< 0x00200000 */
4528 #define HSEM_C1ICR_ISC21         HSEM_C1ICR_ISC21_Msk                          /*!<semaphore 21 CPU1 interrupt clear bit. */
4529 #define HSEM_C1ICR_ISC22_Pos     (22U)
4530 #define HSEM_C1ICR_ISC22_Msk     (0x1UL << HSEM_C1ICR_ISC22_Pos)               /*!< 0x00400000 */
4531 #define HSEM_C1ICR_ISC22         HSEM_C1ICR_ISC22_Msk                          /*!<semaphore 22 CPU1 interrupt clear bit. */
4532 #define HSEM_C1ICR_ISC23_Pos     (23U)
4533 #define HSEM_C1ICR_ISC23_Msk     (0x1UL << HSEM_C1ICR_ISC23_Pos)               /*!< 0x00800000 */
4534 #define HSEM_C1ICR_ISC23         HSEM_C1ICR_ISC23_Msk                          /*!<semaphore 23 CPU1 interrupt clear bit. */
4535 #define HSEM_C1ICR_ISC24_Pos     (24U)
4536 #define HSEM_C1ICR_ISC24_Msk     (0x1UL << HSEM_C1ICR_ISC24_Pos)               /*!< 0x01000000 */
4537 #define HSEM_C1ICR_ISC24         HSEM_C1ICR_ISC24_Msk                          /*!<semaphore 24 CPU1 interrupt clear bit. */
4538 #define HSEM_C1ICR_ISC25_Pos     (25U)
4539 #define HSEM_C1ICR_ISC25_Msk     (0x1UL << HSEM_C1ICR_ISC25_Pos)               /*!< 0x02000000 */
4540 #define HSEM_C1ICR_ISC25         HSEM_C1ICR_ISC25_Msk                          /*!<semaphore 25 CPU1 interrupt clear bit. */
4541 #define HSEM_C1ICR_ISC26_Pos     (26U)
4542 #define HSEM_C1ICR_ISC26_Msk     (0x1UL << HSEM_C1ICR_ISC26_Pos)               /*!< 0x04000000 */
4543 #define HSEM_C1ICR_ISC26         HSEM_C1ICR_ISC26_Msk                          /*!<semaphore 26 CPU1 interrupt clear bit. */
4544 #define HSEM_C1ICR_ISC27_Pos     (27U)
4545 #define HSEM_C1ICR_ISC27_Msk     (0x1UL << HSEM_C1ICR_ISC27_Pos)               /*!< 0x08000000 */
4546 #define HSEM_C1ICR_ISC27         HSEM_C1ICR_ISC27_Msk                          /*!<semaphore 27 CPU1 interrupt clear bit. */
4547 #define HSEM_C1ICR_ISC28_Pos     (28U)
4548 #define HSEM_C1ICR_ISC28_Msk     (0x1UL << HSEM_C1ICR_ISC28_Pos)               /*!< 0x10000000 */
4549 #define HSEM_C1ICR_ISC28         HSEM_C1ICR_ISC28_Msk                          /*!<semaphore 28 CPU1 interrupt clear bit. */
4550 #define HSEM_C1ICR_ISC29_Pos     (29U)
4551 #define HSEM_C1ICR_ISC29_Msk     (0x1UL << HSEM_C1ICR_ISC29_Pos)               /*!< 0x20000000 */
4552 #define HSEM_C1ICR_ISC29         HSEM_C1ICR_ISC29_Msk                          /*!<semaphore 29 CPU1 interrupt clear bit. */
4553 #define HSEM_C1ICR_ISC30_Pos     (30U)
4554 #define HSEM_C1ICR_ISC30_Msk     (0x1UL << HSEM_C1ICR_ISC30_Pos)               /*!< 0x40000000 */
4555 #define HSEM_C1ICR_ISC30         HSEM_C1ICR_ISC30_Msk                          /*!<semaphore 30 CPU1 interrupt clear bit. */
4556 #define HSEM_C1ICR_ISC31_Pos     (31U)
4557 #define HSEM_C1ICR_ISC31_Msk     (0x1UL << HSEM_C1ICR_ISC31_Pos)               /*!< 0x80000000 */
4558 #define HSEM_C1ICR_ISC31         HSEM_C1ICR_ISC31_Msk                          /*!<semaphore 31 CPU1 interrupt clear bit. */
4559 
4560 /********************  Bit definition for HSEM_C1ISR register  *****************/
4561 #define HSEM_C1ISR_ISF0_Pos      (0U)
4562 #define HSEM_C1ISR_ISF0_Msk      (0x1UL << HSEM_C1ISR_ISF0_Pos)                /*!< 0x00000001 */
4563 #define HSEM_C1ISR_ISF0          HSEM_C1ISR_ISF0_Msk                           /*!<semaphore 0 CPU1 interrupt status bit.  */
4564 #define HSEM_C1ISR_ISF1_Pos      (1U)
4565 #define HSEM_C1ISR_ISF1_Msk      (0x1UL << HSEM_C1ISR_ISF1_Pos)                /*!< 0x00000002 */
4566 #define HSEM_C1ISR_ISF1          HSEM_C1ISR_ISF1_Msk                           /*!<semaphore 1 CPU1 interrupt status bit.  */
4567 #define HSEM_C1ISR_ISF2_Pos      (2U)
4568 #define HSEM_C1ISR_ISF2_Msk      (0x1UL << HSEM_C1ISR_ISF2_Pos)                /*!< 0x00000004 */
4569 #define HSEM_C1ISR_ISF2          HSEM_C1ISR_ISF2_Msk                           /*!<semaphore 2 CPU1 interrupt status bit.  */
4570 #define HSEM_C1ISR_ISF3_Pos      (3U)
4571 #define HSEM_C1ISR_ISF3_Msk      (0x1UL << HSEM_C1ISR_ISF3_Pos)                /*!< 0x00000008 */
4572 #define HSEM_C1ISR_ISF3          HSEM_C1ISR_ISF3_Msk                           /*!<semaphore 3 CPU1 interrupt status bit.  */
4573 #define HSEM_C1ISR_ISF4_Pos      (4U)
4574 #define HSEM_C1ISR_ISF4_Msk      (0x1UL << HSEM_C1ISR_ISF4_Pos)                /*!< 0x00000010 */
4575 #define HSEM_C1ISR_ISF4          HSEM_C1ISR_ISF4_Msk                           /*!<semaphore 4 CPU1 interrupt status bit.  */
4576 #define HSEM_C1ISR_ISF5_Pos      (5U)
4577 #define HSEM_C1ISR_ISF5_Msk      (0x1UL << HSEM_C1ISR_ISF5_Pos)                /*!< 0x00000020 */
4578 #define HSEM_C1ISR_ISF5          HSEM_C1ISR_ISF5_Msk                           /*!<semaphore 5 CPU1 interrupt status bit.  */
4579 #define HSEM_C1ISR_ISF6_Pos      (6U)
4580 #define HSEM_C1ISR_ISF6_Msk      (0x1UL << HSEM_C1ISR_ISF6_Pos)                /*!< 0x00000040 */
4581 #define HSEM_C1ISR_ISF6          HSEM_C1ISR_ISF6_Msk                           /*!<semaphore 6 CPU1 interrupt status bit.  */
4582 #define HSEM_C1ISR_ISF7_Pos      (7U)
4583 #define HSEM_C1ISR_ISF7_Msk      (0x1UL << HSEM_C1ISR_ISF7_Pos)                /*!< 0x00000080 */
4584 #define HSEM_C1ISR_ISF7          HSEM_C1ISR_ISF7_Msk                           /*!<semaphore 7 CPU1 interrupt status bit.  */
4585 #define HSEM_C1ISR_ISF8_Pos      (8U)
4586 #define HSEM_C1ISR_ISF8_Msk      (0x1UL << HSEM_C1ISR_ISF8_Pos)                /*!< 0x00000100 */
4587 #define HSEM_C1ISR_ISF8          HSEM_C1ISR_ISF8_Msk                           /*!<semaphore 8 CPU1 interrupt status bit.  */
4588 #define HSEM_C1ISR_ISF9_Pos      (9U)
4589 #define HSEM_C1ISR_ISF9_Msk      (0x1UL << HSEM_C1ISR_ISF9_Pos)                /*!< 0x00000200 */
4590 #define HSEM_C1ISR_ISF9          HSEM_C1ISR_ISF9_Msk                           /*!<semaphore 9 CPU1 interrupt status bit.  */
4591 #define HSEM_C1ISR_ISF10_Pos     (10U)
4592 #define HSEM_C1ISR_ISF10_Msk     (0x1UL << HSEM_C1ISR_ISF10_Pos)               /*!< 0x00000400 */
4593 #define HSEM_C1ISR_ISF10         HSEM_C1ISR_ISF10_Msk                          /*!<semaphore 10 CPU1 interrupt status bit. */
4594 #define HSEM_C1ISR_ISF11_Pos     (11U)
4595 #define HSEM_C1ISR_ISF11_Msk     (0x1UL << HSEM_C1ISR_ISF11_Pos)               /*!< 0x00000800 */
4596 #define HSEM_C1ISR_ISF11         HSEM_C1ISR_ISF11_Msk                          /*!<semaphore 11 CPU1 interrupt status bit. */
4597 #define HSEM_C1ISR_ISF12_Pos     (12U)
4598 #define HSEM_C1ISR_ISF12_Msk     (0x1UL << HSEM_C1ISR_ISF12_Pos)               /*!< 0x00001000 */
4599 #define HSEM_C1ISR_ISF12         HSEM_C1ISR_ISF12_Msk                          /*!<semaphore 12 CPU1 interrupt status bit. */
4600 #define HSEM_C1ISR_ISF13_Pos     (13U)
4601 #define HSEM_C1ISR_ISF13_Msk     (0x1UL << HSEM_C1ISR_ISF13_Pos)               /*!< 0x00002000 */
4602 #define HSEM_C1ISR_ISF13         HSEM_C1ISR_ISF13_Msk                          /*!<semaphore 13 CPU1 interrupt status bit. */
4603 #define HSEM_C1ISR_ISF14_Pos     (14U)
4604 #define HSEM_C1ISR_ISF14_Msk     (0x1UL << HSEM_C1ISR_ISF14_Pos)               /*!< 0x00004000 */
4605 #define HSEM_C1ISR_ISF14         HSEM_C1ISR_ISF14_Msk                          /*!<semaphore 14 CPU1 interrupt status bit. */
4606 #define HSEM_C1ISR_ISF15_Pos     (15U)
4607 #define HSEM_C1ISR_ISF15_Msk     (0x1UL << HSEM_C1ISR_ISF15_Pos)               /*!< 0x00008000 */
4608 #define HSEM_C1ISR_ISF15         HSEM_C1ISR_ISF15_Msk                          /*!<semaphore 15 CPU1 interrupt status bit. */
4609 #define HSEM_C1ISR_ISF16_Pos     (16U)
4610 #define HSEM_C1ISR_ISF16_Msk     (0x1UL << HSEM_C1ISR_ISF16_Pos)               /*!< 0x00010000 */
4611 #define HSEM_C1ISR_ISF16         HSEM_C1ISR_ISF16_Msk                          /*!<semaphore 16 CPU1 interrupt status bit. */
4612 #define HSEM_C1ISR_ISF17_Pos     (17U)
4613 #define HSEM_C1ISR_ISF17_Msk     (0x1UL << HSEM_C1ISR_ISF17_Pos)               /*!< 0x00020000 */
4614 #define HSEM_C1ISR_ISF17         HSEM_C1ISR_ISF17_Msk                          /*!<semaphore 17 CPU1 interrupt status bit. */
4615 #define HSEM_C1ISR_ISF18_Pos     (18U)
4616 #define HSEM_C1ISR_ISF18_Msk     (0x1UL << HSEM_C1ISR_ISF18_Pos)               /*!< 0x00040000 */
4617 #define HSEM_C1ISR_ISF18         HSEM_C1ISR_ISF18_Msk                          /*!<semaphore 18 CPU1 interrupt status bit. */
4618 #define HSEM_C1ISR_ISF19_Pos     (19U)
4619 #define HSEM_C1ISR_ISF19_Msk     (0x1UL << HSEM_C1ISR_ISF19_Pos)               /*!< 0x00080000 */
4620 #define HSEM_C1ISR_ISF19         HSEM_C1ISR_ISF19_Msk                          /*!<semaphore 19 CPU1 interrupt status bit. */
4621 #define HSEM_C1ISR_ISF20_Pos     (20U)
4622 #define HSEM_C1ISR_ISF20_Msk     (0x1UL << HSEM_C1ISR_ISF20_Pos)               /*!< 0x00100000 */
4623 #define HSEM_C1ISR_ISF20         HSEM_C1ISR_ISF20_Msk                          /*!<semaphore 20 CPU1 interrupt status bit. */
4624 #define HSEM_C1ISR_ISF21_Pos     (21U)
4625 #define HSEM_C1ISR_ISF21_Msk     (0x1UL << HSEM_C1ISR_ISF21_Pos)               /*!< 0x00200000 */
4626 #define HSEM_C1ISR_ISF21         HSEM_C1ISR_ISF21_Msk                          /*!<semaphore 21 CPU1 interrupt status bit. */
4627 #define HSEM_C1ISR_ISF22_Pos     (22U)
4628 #define HSEM_C1ISR_ISF22_Msk     (0x1UL << HSEM_C1ISR_ISF22_Pos)               /*!< 0x00400000 */
4629 #define HSEM_C1ISR_ISF22         HSEM_C1ISR_ISF22_Msk                          /*!<semaphore 22 CPU1 interrupt status bit. */
4630 #define HSEM_C1ISR_ISF23_Pos     (23U)
4631 #define HSEM_C1ISR_ISF23_Msk     (0x1UL << HSEM_C1ISR_ISF23_Pos)               /*!< 0x00800000 */
4632 #define HSEM_C1ISR_ISF23         HSEM_C1ISR_ISF23_Msk                          /*!<semaphore 23 CPU1 interrupt status bit. */
4633 #define HSEM_C1ISR_ISF24_Pos     (24U)
4634 #define HSEM_C1ISR_ISF24_Msk     (0x1UL << HSEM_C1ISR_ISF24_Pos)               /*!< 0x01000000 */
4635 #define HSEM_C1ISR_ISF24         HSEM_C1ISR_ISF24_Msk                          /*!<semaphore 24 CPU1 interrupt status bit. */
4636 #define HSEM_C1ISR_ISF25_Pos     (25U)
4637 #define HSEM_C1ISR_ISF25_Msk     (0x1UL << HSEM_C1ISR_ISF25_Pos)               /*!< 0x02000000 */
4638 #define HSEM_C1ISR_ISF25         HSEM_C1ISR_ISF25_Msk                          /*!<semaphore 25 CPU1 interrupt status bit. */
4639 #define HSEM_C1ISR_ISF26_Pos     (26U)
4640 #define HSEM_C1ISR_ISF26_Msk     (0x1UL << HSEM_C1ISR_ISF26_Pos)               /*!< 0x04000000 */
4641 #define HSEM_C1ISR_ISF26         HSEM_C1ISR_ISF26_Msk                          /*!<semaphore 26 CPU1 interrupt status bit. */
4642 #define HSEM_C1ISR_ISF27_Pos     (27U)
4643 #define HSEM_C1ISR_ISF27_Msk     (0x1UL << HSEM_C1ISR_ISF27_Pos)               /*!< 0x08000000 */
4644 #define HSEM_C1ISR_ISF27         HSEM_C1ISR_ISF27_Msk                          /*!<semaphore 27 CPU1 interrupt status bit. */
4645 #define HSEM_C1ISR_ISF28_Pos     (28U)
4646 #define HSEM_C1ISR_ISF28_Msk     (0x1UL << HSEM_C1ISR_ISF28_Pos)               /*!< 0x10000000 */
4647 #define HSEM_C1ISR_ISF28         HSEM_C1ISR_ISF28_Msk                          /*!<semaphore 28 CPU1 interrupt status bit. */
4648 #define HSEM_C1ISR_ISF29_Pos     (29U)
4649 #define HSEM_C1ISR_ISF29_Msk     (0x1UL << HSEM_C1ISR_ISF29_Pos)               /*!< 0x20000000 */
4650 #define HSEM_C1ISR_ISF29         HSEM_C1ISR_ISF29_Msk                          /*!<semaphore 29 CPU1 interrupt status bit. */
4651 #define HSEM_C1ISR_ISF30_Pos     (30U)
4652 #define HSEM_C1ISR_ISF30_Msk     (0x1UL << HSEM_C1ISR_ISF30_Pos)               /*!< 0x40000000 */
4653 #define HSEM_C1ISR_ISF30         HSEM_C1ISR_ISF30_Msk                          /*!<semaphore 30 CPU1 interrupt status bit. */
4654 #define HSEM_C1ISR_ISF31_Pos     (31U)
4655 #define HSEM_C1ISR_ISF31_Msk     (0x1UL << HSEM_C1ISR_ISF31_Pos)               /*!< 0x80000000 */
4656 #define HSEM_C1ISR_ISF31         HSEM_C1ISR_ISF31_Msk                          /*!<semaphore 31 CPU1 interrupt status bit. */
4657 
4658 /********************  Bit definition for HSEM_C1MISR register  *****************/
4659 #define HSEM_C1MISR_MISF0_Pos     (0U)
4660 #define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)               /*!< 0x00000001 */
4661 #define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                          /*!<semaphore 0 CPU1 interrupt masked status bit.  */
4662 #define HSEM_C1MISR_MISF1_Pos     (1U)
4663 #define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)               /*!< 0x00000002 */
4664 #define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                          /*!<semaphore 1 CPU1 interrupt masked status bit.  */
4665 #define HSEM_C1MISR_MISF2_Pos     (2U)
4666 #define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)               /*!< 0x00000004 */
4667 #define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                          /*!<semaphore 2 CPU1 interrupt masked status bit.  */
4668 #define HSEM_C1MISR_MISF3_Pos     (3U)
4669 #define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)               /*!< 0x00000008 */
4670 #define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                          /*!<semaphore 3 CPU1 interrupt masked status bit.  */
4671 #define HSEM_C1MISR_MISF4_Pos     (4U)
4672 #define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)               /*!< 0x00000010 */
4673 #define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                          /*!<semaphore 4 CPU1 interrupt masked status bit.  */
4674 #define HSEM_C1MISR_MISF5_Pos     (5U)
4675 #define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)               /*!< 0x00000020 */
4676 #define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                          /*!<semaphore 5 CPU1 interrupt masked status bit.  */
4677 #define HSEM_C1MISR_MISF6_Pos     (6U)
4678 #define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)               /*!< 0x00000040 */
4679 #define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                          /*!<semaphore 6 CPU1 interrupt masked status bit.  */
4680 #define HSEM_C1MISR_MISF7_Pos     (7U)
4681 #define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)               /*!< 0x00000080 */
4682 #define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                          /*!<semaphore 7 CPU1 interrupt masked status bit.  */
4683 #define HSEM_C1MISR_MISF8_Pos     (8U)
4684 #define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)               /*!< 0x00000100 */
4685 #define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                          /*!<semaphore 8 CPU1 interrupt masked status bit.  */
4686 #define HSEM_C1MISR_MISF9_Pos     (9U)
4687 #define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)               /*!< 0x00000200 */
4688 #define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                          /*!<semaphore 9 CPU1 interrupt masked status bit.  */
4689 #define HSEM_C1MISR_MISF10_Pos    (10U)
4690 #define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)              /*!< 0x00000400 */
4691 #define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                         /*!<semaphore 10 CPU1 interrupt masked status bit. */
4692 #define HSEM_C1MISR_MISF11_Pos    (11U)
4693 #define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)              /*!< 0x00000800 */
4694 #define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                         /*!<semaphore 11 CPU1 interrupt masked status bit. */
4695 #define HSEM_C1MISR_MISF12_Pos    (12U)
4696 #define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)              /*!< 0x00001000 */
4697 #define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                         /*!<semaphore 12 CPU1 interrupt masked status bit. */
4698 #define HSEM_C1MISR_MISF13_Pos    (13U)
4699 #define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)              /*!< 0x00002000 */
4700 #define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                         /*!<semaphore 13 CPU1 interrupt masked status bit. */
4701 #define HSEM_C1MISR_MISF14_Pos    (14U)
4702 #define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)              /*!< 0x00004000 */
4703 #define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                         /*!<semaphore 14 CPU1 interrupt masked status bit. */
4704 #define HSEM_C1MISR_MISF15_Pos    (15U)
4705 #define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)              /*!< 0x00008000 */
4706 #define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                         /*!<semaphore 15 CPU1 interrupt masked status bit. */
4707 #define HSEM_C1MISR_MISF16_Pos    (16U)
4708 #define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)              /*!< 0x00010000 */
4709 #define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                         /*!<semaphore 16 CPU1 interrupt masked status bit. */
4710 #define HSEM_C1MISR_MISF17_Pos    (17U)
4711 #define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)              /*!< 0x00020000 */
4712 #define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                         /*!<semaphore 17 CPU1 interrupt masked status bit. */
4713 #define HSEM_C1MISR_MISF18_Pos    (18U)
4714 #define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)              /*!< 0x00040000 */
4715 #define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                         /*!<semaphore 18 CPU1 interrupt masked status bit. */
4716 #define HSEM_C1MISR_MISF19_Pos    (19U)
4717 #define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)              /*!< 0x00080000 */
4718 #define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                         /*!<semaphore 19 CPU1 interrupt masked status bit. */
4719 #define HSEM_C1MISR_MISF20_Pos    (20U)
4720 #define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)              /*!< 0x00100000 */
4721 #define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                         /*!<semaphore 20 CPU1 interrupt masked status bit. */
4722 #define HSEM_C1MISR_MISF21_Pos    (21U)
4723 #define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)              /*!< 0x00200000 */
4724 #define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                         /*!<semaphore 21 CPU1 interrupt masked status bit. */
4725 #define HSEM_C1MISR_MISF22_Pos    (22U)
4726 #define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)              /*!< 0x00400000 */
4727 #define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                         /*!<semaphore 22 CPU1 interrupt masked status bit. */
4728 #define HSEM_C1MISR_MISF23_Pos    (23U)
4729 #define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)              /*!< 0x00800000 */
4730 #define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                         /*!<semaphore 23 CPU1 interrupt masked status bit. */
4731 #define HSEM_C1MISR_MISF24_Pos    (24U)
4732 #define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)              /*!< 0x01000000 */
4733 #define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                         /*!<semaphore 24 CPU1 interrupt masked status bit. */
4734 #define HSEM_C1MISR_MISF25_Pos    (25U)
4735 #define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)              /*!< 0x02000000 */
4736 #define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                         /*!<semaphore 25 CPU1 interrupt masked status bit. */
4737 #define HSEM_C1MISR_MISF26_Pos    (26U)
4738 #define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)              /*!< 0x04000000 */
4739 #define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                         /*!<semaphore 26 CPU1 interrupt masked status bit. */
4740 #define HSEM_C1MISR_MISF27_Pos    (27U)
4741 #define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)              /*!< 0x08000000 */
4742 #define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                         /*!<semaphore 27 CPU1 interrupt masked status bit. */
4743 #define HSEM_C1MISR_MISF28_Pos    (28U)
4744 #define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)              /*!< 0x10000000 */
4745 #define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                         /*!<semaphore 28 CPU1 interrupt masked status bit. */
4746 #define HSEM_C1MISR_MISF29_Pos    (29U)
4747 #define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)              /*!< 0x20000000 */
4748 #define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                         /*!<semaphore 29 CPU1 interrupt masked status bit. */
4749 #define HSEM_C1MISR_MISF30_Pos    (30U)
4750 #define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)              /*!< 0x40000000 */
4751 #define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                         /*!<semaphore 30 CPU1 interrupt masked status bit. */
4752 #define HSEM_C1MISR_MISF31_Pos    (31U)
4753 #define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)              /*!< 0x80000000 */
4754 #define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                         /*!<semaphore 31 CPU1 interrupt masked status bit. */
4755 
4756 /********************  Bit definition for HSEM_C2IER register  *****************/
4757 #define HSEM_C2IER_ISE0_Pos      (0U)
4758 #define HSEM_C2IER_ISE0_Msk      (0x1UL << HSEM_C2IER_ISE0_Pos)                /*!< 0x00000001 */
4759 #define HSEM_C2IER_ISE0          HSEM_C2IER_ISE0_Msk                           /*!<semaphore 0 CPU2 interrupt enable bit.  */
4760 #define HSEM_C2IER_ISE1_Pos      (1U)
4761 #define HSEM_C2IER_ISE1_Msk      (0x1UL << HSEM_C2IER_ISE1_Pos)                /*!< 0x00000002 */
4762 #define HSEM_C2IER_ISE1          HSEM_C2IER_ISE1_Msk                           /*!<semaphore 1 CPU2 interrupt enable bit.  */
4763 #define HSEM_C2IER_ISE2_Pos      (2U)
4764 #define HSEM_C2IER_ISE2_Msk      (0x1UL << HSEM_C2IER_ISE2_Pos)                /*!< 0x00000004 */
4765 #define HSEM_C2IER_ISE2          HSEM_C2IER_ISE2_Msk                           /*!<semaphore 2 CPU2 interrupt enable bit.  */
4766 #define HSEM_C2IER_ISE3_Pos      (3U)
4767 #define HSEM_C2IER_ISE3_Msk      (0x1UL << HSEM_C2IER_ISE3_Pos)                /*!< 0x00000008 */
4768 #define HSEM_C2IER_ISE3          HSEM_C2IER_ISE3_Msk                           /*!<semaphore 3 CPU2 interrupt enable bit.  */
4769 #define HSEM_C2IER_ISE4_Pos      (4U)
4770 #define HSEM_C2IER_ISE4_Msk      (0x1UL << HSEM_C2IER_ISE4_Pos)                /*!< 0x00000010 */
4771 #define HSEM_C2IER_ISE4          HSEM_C2IER_ISE4_Msk                           /*!<semaphore 4 CPU2 interrupt enable bit.  */
4772 #define HSEM_C2IER_ISE5_Pos      (5U)
4773 #define HSEM_C2IER_ISE5_Msk      (0x1UL << HSEM_C2IER_ISE5_Pos)                /*!< 0x00000020 */
4774 #define HSEM_C2IER_ISE5          HSEM_C2IER_ISE5_Msk                           /*!<semaphore 5 CPU2 interrupt enable bit.  */
4775 #define HSEM_C2IER_ISE6_Pos      (6U)
4776 #define HSEM_C2IER_ISE6_Msk      (0x1UL << HSEM_C2IER_ISE6_Pos)                /*!< 0x00000040 */
4777 #define HSEM_C2IER_ISE6          HSEM_C2IER_ISE6_Msk                           /*!<semaphore 6 CPU2 interrupt enable bit.  */
4778 #define HSEM_C2IER_ISE7_Pos      (7U)
4779 #define HSEM_C2IER_ISE7_Msk      (0x1UL << HSEM_C2IER_ISE7_Pos)                /*!< 0x00000080 */
4780 #define HSEM_C2IER_ISE7          HSEM_C2IER_ISE7_Msk                           /*!<semaphore 7 CPU2 interrupt enable bit.  */
4781 #define HSEM_C2IER_ISE8_Pos      (8U)
4782 #define HSEM_C2IER_ISE8_Msk      (0x1UL << HSEM_C2IER_ISE8_Pos)                /*!< 0x00000100 */
4783 #define HSEM_C2IER_ISE8          HSEM_C2IER_ISE8_Msk                           /*!<semaphore 8 CPU2 interrupt enable bit.  */
4784 #define HSEM_C2IER_ISE9_Pos      (9U)
4785 #define HSEM_C2IER_ISE9_Msk      (0x1UL << HSEM_C2IER_ISE9_Pos)                /*!< 0x00000200 */
4786 #define HSEM_C2IER_ISE9          HSEM_C2IER_ISE9_Msk                           /*!<semaphore 9 CPU2 interrupt enable bit.  */
4787 #define HSEM_C2IER_ISE10_Pos     (10U)
4788 #define HSEM_C2IER_ISE10_Msk     (0x1UL << HSEM_C2IER_ISE10_Pos)               /*!< 0x00000400 */
4789 #define HSEM_C2IER_ISE10         HSEM_C2IER_ISE10_Msk                          /*!<semaphore 10 CPU2 interrupt enable bit. */
4790 #define HSEM_C2IER_ISE11_Pos     (11U)
4791 #define HSEM_C2IER_ISE11_Msk     (0x1UL << HSEM_C2IER_ISE11_Pos)               /*!< 0x00000800 */
4792 #define HSEM_C2IER_ISE11         HSEM_C2IER_ISE11_Msk                          /*!<semaphore 11 CPU2 interrupt enable bit. */
4793 #define HSEM_C2IER_ISE12_Pos     (12U)
4794 #define HSEM_C2IER_ISE12_Msk     (0x1UL << HSEM_C2IER_ISE12_Pos)               /*!< 0x00001000 */
4795 #define HSEM_C2IER_ISE12         HSEM_C2IER_ISE12_Msk                          /*!<semaphore 12 CPU2 interrupt enable bit. */
4796 #define HSEM_C2IER_ISE13_Pos     (13U)
4797 #define HSEM_C2IER_ISE13_Msk     (0x1UL << HSEM_C2IER_ISE13_Pos)               /*!< 0x00002000 */
4798 #define HSEM_C2IER_ISE13         HSEM_C2IER_ISE13_Msk                          /*!<semaphore 13 CPU2 interrupt enable bit. */
4799 #define HSEM_C2IER_ISE14_Pos     (14U)
4800 #define HSEM_C2IER_ISE14_Msk     (0x1UL << HSEM_C2IER_ISE14_Pos)               /*!< 0x00004000 */
4801 #define HSEM_C2IER_ISE14         HSEM_C2IER_ISE14_Msk                          /*!<semaphore 14 CPU2 interrupt enable bit. */
4802 #define HSEM_C2IER_ISE15_Pos     (15U)
4803 #define HSEM_C2IER_ISE15_Msk     (0x1UL << HSEM_C2IER_ISE15_Pos)               /*!< 0x00008000 */
4804 #define HSEM_C2IER_ISE15         HSEM_C2IER_ISE15_Msk                          /*!<semaphore 15 CPU2 interrupt enable bit. */
4805 #define HSEM_C2IER_ISE16_Pos     (16U)
4806 #define HSEM_C2IER_ISE16_Msk     (0x1UL << HSEM_C2IER_ISE16_Pos)               /*!< 0x00010000 */
4807 #define HSEM_C2IER_ISE16         HSEM_C2IER_ISE16_Msk                          /*!<semaphore 16 CPU2 interrupt enable bit. */
4808 #define HSEM_C2IER_ISE17_Pos     (17U)
4809 #define HSEM_C2IER_ISE17_Msk     (0x1UL << HSEM_C2IER_ISE17_Pos)               /*!< 0x00020000 */
4810 #define HSEM_C2IER_ISE17         HSEM_C2IER_ISE17_Msk                          /*!<semaphore 17 CPU2 interrupt enable bit. */
4811 #define HSEM_C2IER_ISE18_Pos     (18U)
4812 #define HSEM_C2IER_ISE18_Msk     (0x1UL << HSEM_C2IER_ISE18_Pos)               /*!< 0x00040000 */
4813 #define HSEM_C2IER_ISE18         HSEM_C2IER_ISE18_Msk                          /*!<semaphore 18 CPU2 interrupt enable bit. */
4814 #define HSEM_C2IER_ISE19_Pos     (19U)
4815 #define HSEM_C2IER_ISE19_Msk     (0x1UL << HSEM_C2IER_ISE19_Pos)               /*!< 0x00080000 */
4816 #define HSEM_C2IER_ISE19         HSEM_C2IER_ISE19_Msk                          /*!<semaphore 19 CPU2 interrupt enable bit. */
4817 #define HSEM_C2IER_ISE20_Pos     (20U)
4818 #define HSEM_C2IER_ISE20_Msk     (0x1UL << HSEM_C2IER_ISE20_Pos)               /*!< 0x00100000 */
4819 #define HSEM_C2IER_ISE20         HSEM_C2IER_ISE20_Msk                          /*!<semaphore 20 CPU2 interrupt enable bit. */
4820 #define HSEM_C2IER_ISE21_Pos     (21U)
4821 #define HSEM_C2IER_ISE21_Msk     (0x1UL << HSEM_C2IER_ISE21_Pos)               /*!< 0x00200000 */
4822 #define HSEM_C2IER_ISE21         HSEM_C2IER_ISE21_Msk                          /*!<semaphore 21 CPU2 interrupt enable bit. */
4823 #define HSEM_C2IER_ISE22_Pos     (22U)
4824 #define HSEM_C2IER_ISE22_Msk     (0x1UL << HSEM_C2IER_ISE22_Pos)               /*!< 0x00400000 */
4825 #define HSEM_C2IER_ISE22         HSEM_C2IER_ISE22_Msk                          /*!<semaphore 22 CPU2 interrupt enable bit. */
4826 #define HSEM_C2IER_ISE23_Pos     (23U)
4827 #define HSEM_C2IER_ISE23_Msk     (0x1UL << HSEM_C2IER_ISE23_Pos)               /*!< 0x00800000 */
4828 #define HSEM_C2IER_ISE23         HSEM_C2IER_ISE23_Msk                          /*!<semaphore 23 CPU2 interrupt enable bit. */
4829 #define HSEM_C2IER_ISE24_Pos     (24U)
4830 #define HSEM_C2IER_ISE24_Msk     (0x1UL << HSEM_C2IER_ISE24_Pos)               /*!< 0x01000000 */
4831 #define HSEM_C2IER_ISE24         HSEM_C2IER_ISE24_Msk                          /*!<semaphore 24 CPU2 interrupt enable bit. */
4832 #define HSEM_C2IER_ISE25_Pos     (25U)
4833 #define HSEM_C2IER_ISE25_Msk     (0x1UL << HSEM_C2IER_ISE25_Pos)               /*!< 0x02000000 */
4834 #define HSEM_C2IER_ISE25         HSEM_C2IER_ISE25_Msk                          /*!<semaphore 25 CPU2 interrupt enable bit. */
4835 #define HSEM_C2IER_ISE26_Pos     (26U)
4836 #define HSEM_C2IER_ISE26_Msk     (0x1UL << HSEM_C2IER_ISE26_Pos)               /*!< 0x04000000 */
4837 #define HSEM_C2IER_ISE26         HSEM_C2IER_ISE26_Msk                          /*!<semaphore 26 CPU2 interrupt enable bit. */
4838 #define HSEM_C2IER_ISE27_Pos     (27U)
4839 #define HSEM_C2IER_ISE27_Msk     (0x1UL << HSEM_C2IER_ISE27_Pos)               /*!< 0x08000000 */
4840 #define HSEM_C2IER_ISE27         HSEM_C2IER_ISE27_Msk                          /*!<semaphore 27 CPU2 interrupt enable bit. */
4841 #define HSEM_C2IER_ISE28_Pos     (28U)
4842 #define HSEM_C2IER_ISE28_Msk     (0x1UL << HSEM_C2IER_ISE28_Pos)               /*!< 0x10000000 */
4843 #define HSEM_C2IER_ISE28         HSEM_C2IER_ISE28_Msk                          /*!<semaphore 28 CPU2 interrupt enable bit. */
4844 #define HSEM_C2IER_ISE29_Pos     (29U)
4845 #define HSEM_C2IER_ISE29_Msk     (0x1UL << HSEM_C2IER_ISE29_Pos)               /*!< 0x20000000 */
4846 #define HSEM_C2IER_ISE29         HSEM_C2IER_ISE29_Msk                          /*!<semaphore 29 CPU2 interrupt enable bit. */
4847 #define HSEM_C2IER_ISE30_Pos     (30U)
4848 #define HSEM_C2IER_ISE30_Msk     (0x1UL << HSEM_C2IER_ISE30_Pos)               /*!< 0x40000000 */
4849 #define HSEM_C2IER_ISE30         HSEM_C2IER_ISE30_Msk                          /*!<semaphore 30 CPU2 interrupt enable bit. */
4850 #define HSEM_C2IER_ISE31_Pos     (31U)
4851 #define HSEM_C2IER_ISE31_Msk     (0x1UL << HSEM_C2IER_ISE31_Pos)               /*!< 0x80000000 */
4852 #define HSEM_C2IER_ISE31         HSEM_C2IER_ISE31_Msk                          /*!<semaphore 31 CPU2 interrupt enable bit. */
4853 
4854 /********************  Bit definition for HSEM_C2ICR register  *****************/
4855 #define HSEM_C2ICR_ISC0_Pos      (0U)
4856 #define HSEM_C2ICR_ISC0_Msk      (0x1UL << HSEM_C2ICR_ISC0_Pos)                /*!< 0x00000001 */
4857 #define HSEM_C2ICR_ISC0          HSEM_C2ICR_ISC0_Msk                           /*!<semaphore 0 CPU2 interrupt clear bit.  */
4858 #define HSEM_C2ICR_ISC1_Pos      (1U)
4859 #define HSEM_C2ICR_ISC1_Msk      (0x1UL << HSEM_C2ICR_ISC1_Pos)                /*!< 0x00000002 */
4860 #define HSEM_C2ICR_ISC1          HSEM_C2ICR_ISC1_Msk                           /*!<semaphore 1 CPU2 interrupt clear bit.  */
4861 #define HSEM_C2ICR_ISC2_Pos      (2U)
4862 #define HSEM_C2ICR_ISC2_Msk      (0x1UL << HSEM_C2ICR_ISC2_Pos)                /*!< 0x00000004 */
4863 #define HSEM_C2ICR_ISC2          HSEM_C2ICR_ISC2_Msk                           /*!<semaphore 2 CPU2 interrupt clear bit.  */
4864 #define HSEM_C2ICR_ISC3_Pos      (3U)
4865 #define HSEM_C2ICR_ISC3_Msk      (0x1UL << HSEM_C2ICR_ISC3_Pos)                /*!< 0x00000008 */
4866 #define HSEM_C2ICR_ISC3          HSEM_C2ICR_ISC3_Msk                           /*!<semaphore 3 CPU2 interrupt clear bit.  */
4867 #define HSEM_C2ICR_ISC4_Pos      (4U)
4868 #define HSEM_C2ICR_ISC4_Msk      (0x1UL << HSEM_C2ICR_ISC4_Pos)                /*!< 0x00000010 */
4869 #define HSEM_C2ICR_ISC4          HSEM_C2ICR_ISC4_Msk                           /*!<semaphore 4 CPU2 interrupt clear bit.  */
4870 #define HSEM_C2ICR_ISC5_Pos      (5U)
4871 #define HSEM_C2ICR_ISC5_Msk      (0x1UL << HSEM_C2ICR_ISC5_Pos)                /*!< 0x00000020 */
4872 #define HSEM_C2ICR_ISC5          HSEM_C2ICR_ISC5_Msk                           /*!<semaphore 5 CPU2 interrupt clear bit.  */
4873 #define HSEM_C2ICR_ISC6_Pos      (6U)
4874 #define HSEM_C2ICR_ISC6_Msk      (0x1UL << HSEM_C2ICR_ISC6_Pos)                /*!< 0x00000040 */
4875 #define HSEM_C2ICR_ISC6          HSEM_C2ICR_ISC6_Msk                           /*!<semaphore 6 CPU2 interrupt clear bit.  */
4876 #define HSEM_C2ICR_ISC7_Pos      (7U)
4877 #define HSEM_C2ICR_ISC7_Msk      (0x1UL << HSEM_C2ICR_ISC7_Pos)                /*!< 0x00000080 */
4878 #define HSEM_C2ICR_ISC7          HSEM_C2ICR_ISC7_Msk                           /*!<semaphore 7 CPU2 interrupt clear bit.  */
4879 #define HSEM_C2ICR_ISC8_Pos      (8U)
4880 #define HSEM_C2ICR_ISC8_Msk      (0x1UL << HSEM_C2ICR_ISC8_Pos)                /*!< 0x00000100 */
4881 #define HSEM_C2ICR_ISC8          HSEM_C2ICR_ISC8_Msk                           /*!<semaphore 8 CPU2 interrupt clear bit.  */
4882 #define HSEM_C2ICR_ISC9_Pos      (9U)
4883 #define HSEM_C2ICR_ISC9_Msk      (0x1UL << HSEM_C2ICR_ISC9_Pos)                /*!< 0x00000200 */
4884 #define HSEM_C2ICR_ISC9          HSEM_C2ICR_ISC9_Msk                           /*!<semaphore 9 CPU2 interrupt clear bit.  */
4885 #define HSEM_C2ICR_ISC10_Pos     (10U)
4886 #define HSEM_C2ICR_ISC10_Msk     (0x1UL << HSEM_C2ICR_ISC10_Pos)               /*!< 0x00000400 */
4887 #define HSEM_C2ICR_ISC10         HSEM_C2ICR_ISC10_Msk                          /*!<semaphore 10 CPU2 interrupt clear bit. */
4888 #define HSEM_C2ICR_ISC11_Pos     (11U)
4889 #define HSEM_C2ICR_ISC11_Msk     (0x1UL << HSEM_C2ICR_ISC11_Pos)               /*!< 0x00000800 */
4890 #define HSEM_C2ICR_ISC11         HSEM_C2ICR_ISC11_Msk                          /*!<semaphore 11 CPU2 interrupt clear bit. */
4891 #define HSEM_C2ICR_ISC12_Pos     (12U)
4892 #define HSEM_C2ICR_ISC12_Msk     (0x1UL << HSEM_C2ICR_ISC12_Pos)               /*!< 0x00001000 */
4893 #define HSEM_C2ICR_ISC12         HSEM_C2ICR_ISC12_Msk                          /*!<semaphore 12 CPU2 interrupt clear bit. */
4894 #define HSEM_C2ICR_ISC13_Pos     (13U)
4895 #define HSEM_C2ICR_ISC13_Msk     (0x1UL << HSEM_C2ICR_ISC13_Pos)               /*!< 0x00002000 */
4896 #define HSEM_C2ICR_ISC13         HSEM_C2ICR_ISC13_Msk                          /*!<semaphore 13 CPU2 interrupt clear bit. */
4897 #define HSEM_C2ICR_ISC14_Pos     (14U)
4898 #define HSEM_C2ICR_ISC14_Msk     (0x1UL << HSEM_C2ICR_ISC14_Pos)               /*!< 0x00004000 */
4899 #define HSEM_C2ICR_ISC14         HSEM_C2ICR_ISC14_Msk                          /*!<semaphore 14 CPU2 interrupt clear bit. */
4900 #define HSEM_C2ICR_ISC15_Pos     (15U)
4901 #define HSEM_C2ICR_ISC15_Msk     (0x1UL << HSEM_C2ICR_ISC15_Pos)               /*!< 0x00008000 */
4902 #define HSEM_C2ICR_ISC15         HSEM_C2ICR_ISC15_Msk                          /*!<semaphore 15 CPU2 interrupt clear bit. */
4903 #define HSEM_C2ICR_ISC16_Pos     (16U)
4904 #define HSEM_C2ICR_ISC16_Msk     (0x1UL << HSEM_C2ICR_ISC16_Pos)               /*!< 0x00010000 */
4905 #define HSEM_C2ICR_ISC16         HSEM_C2ICR_ISC16_Msk                          /*!<semaphore 16 CPU2 interrupt clear bit. */
4906 #define HSEM_C2ICR_ISC17_Pos     (17U)
4907 #define HSEM_C2ICR_ISC17_Msk     (0x1UL << HSEM_C2ICR_ISC17_Pos)               /*!< 0x00020000 */
4908 #define HSEM_C2ICR_ISC17         HSEM_C2ICR_ISC17_Msk                          /*!<semaphore 17 CPU2 interrupt clear bit. */
4909 #define HSEM_C2ICR_ISC18_Pos     (18U)
4910 #define HSEM_C2ICR_ISC18_Msk     (0x1UL << HSEM_C2ICR_ISC18_Pos)               /*!< 0x00040000 */
4911 #define HSEM_C2ICR_ISC18         HSEM_C2ICR_ISC18_Msk                          /*!<semaphore 18 CPU2 interrupt clear bit. */
4912 #define HSEM_C2ICR_ISC19_Pos     (19U)
4913 #define HSEM_C2ICR_ISC19_Msk     (0x1UL << HSEM_C2ICR_ISC19_Pos)               /*!< 0x00080000 */
4914 #define HSEM_C2ICR_ISC19         HSEM_C2ICR_ISC19_Msk                          /*!<semaphore 19 CPU2 interrupt clear bit. */
4915 #define HSEM_C2ICR_ISC20_Pos     (20U)
4916 #define HSEM_C2ICR_ISC20_Msk     (0x1UL << HSEM_C2ICR_ISC20_Pos)               /*!< 0x00100000 */
4917 #define HSEM_C2ICR_ISC20         HSEM_C2ICR_ISC20_Msk                          /*!<semaphore 20 CPU2 interrupt clear bit. */
4918 #define HSEM_C2ICR_ISC21_Pos     (21U)
4919 #define HSEM_C2ICR_ISC21_Msk     (0x1UL << HSEM_C2ICR_ISC21_Pos)               /*!< 0x00200000 */
4920 #define HSEM_C2ICR_ISC21         HSEM_C2ICR_ISC21_Msk                          /*!<semaphore 21 CPU2 interrupt clear bit. */
4921 #define HSEM_C2ICR_ISC22_Pos     (22U)
4922 #define HSEM_C2ICR_ISC22_Msk     (0x1UL << HSEM_C2ICR_ISC22_Pos)               /*!< 0x00400000 */
4923 #define HSEM_C2ICR_ISC22         HSEM_C2ICR_ISC22_Msk                          /*!<semaphore 22 CPU2 interrupt clear bit. */
4924 #define HSEM_C2ICR_ISC23_Pos     (23U)
4925 #define HSEM_C2ICR_ISC23_Msk     (0x1UL << HSEM_C2ICR_ISC23_Pos)               /*!< 0x00800000 */
4926 #define HSEM_C2ICR_ISC23         HSEM_C2ICR_ISC23_Msk                          /*!<semaphore 23 CPU2 interrupt clear bit. */
4927 #define HSEM_C2ICR_ISC24_Pos     (24U)
4928 #define HSEM_C2ICR_ISC24_Msk     (0x1UL << HSEM_C2ICR_ISC24_Pos)               /*!< 0x01000000 */
4929 #define HSEM_C2ICR_ISC24         HSEM_C2ICR_ISC24_Msk                          /*!<semaphore 24 CPU2 interrupt clear bit. */
4930 #define HSEM_C2ICR_ISC25_Pos     (25U)
4931 #define HSEM_C2ICR_ISC25_Msk     (0x1UL << HSEM_C2ICR_ISC25_Pos)               /*!< 0x02000000 */
4932 #define HSEM_C2ICR_ISC25         HSEM_C2ICR_ISC25_Msk                          /*!<semaphore 25 CPU2 interrupt clear bit. */
4933 #define HSEM_C2ICR_ISC26_Pos     (26U)
4934 #define HSEM_C2ICR_ISC26_Msk     (0x1UL << HSEM_C2ICR_ISC26_Pos)               /*!< 0x04000000 */
4935 #define HSEM_C2ICR_ISC26         HSEM_C2ICR_ISC26_Msk                          /*!<semaphore 26 CPU2 interrupt clear bit. */
4936 #define HSEM_C2ICR_ISC27_Pos     (27U)
4937 #define HSEM_C2ICR_ISC27_Msk     (0x1UL << HSEM_C2ICR_ISC27_Pos)               /*!< 0x08000000 */
4938 #define HSEM_C2ICR_ISC27         HSEM_C2ICR_ISC27_Msk                          /*!<semaphore 27 CPU2 interrupt clear bit. */
4939 #define HSEM_C2ICR_ISC28_Pos     (28U)
4940 #define HSEM_C2ICR_ISC28_Msk     (0x1UL << HSEM_C2ICR_ISC28_Pos)               /*!< 0x10000000 */
4941 #define HSEM_C2ICR_ISC28         HSEM_C2ICR_ISC28_Msk                          /*!<semaphore 28 CPU2 interrupt clear bit. */
4942 #define HSEM_C2ICR_ISC29_Pos     (29U)
4943 #define HSEM_C2ICR_ISC29_Msk     (0x1UL << HSEM_C2ICR_ISC29_Pos)               /*!< 0x20000000 */
4944 #define HSEM_C2ICR_ISC29         HSEM_C2ICR_ISC29_Msk                          /*!<semaphore 29 CPU2 interrupt clear bit. */
4945 #define HSEM_C2ICR_ISC30_Pos     (30U)
4946 #define HSEM_C2ICR_ISC30_Msk     (0x1UL << HSEM_C2ICR_ISC30_Pos)               /*!< 0x40000000 */
4947 #define HSEM_C2ICR_ISC30         HSEM_C2ICR_ISC30_Msk                          /*!<semaphore 30 CPU2 interrupt clear bit. */
4948 #define HSEM_C2ICR_ISC31_Pos     (31U)
4949 #define HSEM_C2ICR_ISC31_Msk     (0x1UL << HSEM_C2ICR_ISC31_Pos)               /*!< 0x80000000 */
4950 #define HSEM_C2ICR_ISC31         HSEM_C2ICR_ISC31_Msk                          /*!<semaphore 31 CPU2 interrupt clear bit. */
4951 
4952 /********************  Bit definition for HSEM_C2ISR register  *****************/
4953 #define HSEM_C2ISR_ISF0_Pos      (0U)
4954 #define HSEM_C2ISR_ISF0_Msk      (0x1UL << HSEM_C2ISR_ISF0_Pos)                /*!< 0x00000001 */
4955 #define HSEM_C2ISR_ISF0          HSEM_C2ISR_ISF0_Msk                           /*!<semaphore 0 CPU2 interrupt status bit.  */
4956 #define HSEM_C2ISR_ISF1_Pos      (1U)
4957 #define HSEM_C2ISR_ISF1_Msk      (0x1UL << HSEM_C2ISR_ISF1_Pos)                /*!< 0x00000002 */
4958 #define HSEM_C2ISR_ISF1          HSEM_C2ISR_ISF1_Msk                           /*!<semaphore 1 CPU2 interrupt status bit.  */
4959 #define HSEM_C2ISR_ISF2_Pos      (2U)
4960 #define HSEM_C2ISR_ISF2_Msk      (0x1UL << HSEM_C2ISR_ISF2_Pos)                /*!< 0x00000004 */
4961 #define HSEM_C2ISR_ISF2          HSEM_C2ISR_ISF2_Msk                           /*!<semaphore 2 CPU2 interrupt status bit.  */
4962 #define HSEM_C2ISR_ISF3_Pos      (3U)
4963 #define HSEM_C2ISR_ISF3_Msk      (0x1UL << HSEM_C2ISR_ISF3_Pos)                /*!< 0x00000008 */
4964 #define HSEM_C2ISR_ISF3          HSEM_C2ISR_ISF3_Msk                           /*!<semaphore 3 CPU2 interrupt status bit.  */
4965 #define HSEM_C2ISR_ISF4_Pos      (4U)
4966 #define HSEM_C2ISR_ISF4_Msk      (0x1UL << HSEM_C2ISR_ISF4_Pos)                /*!< 0x00000010 */
4967 #define HSEM_C2ISR_ISF4          HSEM_C2ISR_ISF4_Msk                           /*!<semaphore 4 CPU2 interrupt status bit.  */
4968 #define HSEM_C2ISR_ISF5_Pos      (5U)
4969 #define HSEM_C2ISR_ISF5_Msk      (0x1UL << HSEM_C2ISR_ISF5_Pos)                /*!< 0x00000020 */
4970 #define HSEM_C2ISR_ISF5          HSEM_C2ISR_ISF5_Msk                           /*!<semaphore 5 CPU2 interrupt status bit.  */
4971 #define HSEM_C2ISR_ISF6_Pos      (6U)
4972 #define HSEM_C2ISR_ISF6_Msk      (0x1UL << HSEM_C2ISR_ISF6_Pos)                /*!< 0x00000040 */
4973 #define HSEM_C2ISR_ISF6          HSEM_C2ISR_ISF6_Msk                           /*!<semaphore 6 CPU2 interrupt status bit.  */
4974 #define HSEM_C2ISR_ISF7_Pos      (7U)
4975 #define HSEM_C2ISR_ISF7_Msk      (0x1UL << HSEM_C2ISR_ISF7_Pos)                /*!< 0x00000080 */
4976 #define HSEM_C2ISR_ISF7          HSEM_C2ISR_ISF7_Msk                           /*!<semaphore 7 CPU2 interrupt status bit.  */
4977 #define HSEM_C2ISR_ISF8_Pos      (8U)
4978 #define HSEM_C2ISR_ISF8_Msk      (0x1UL << HSEM_C2ISR_ISF8_Pos)                /*!< 0x00000100 */
4979 #define HSEM_C2ISR_ISF8          HSEM_C2ISR_ISF8_Msk                           /*!<semaphore 8 CPU2 interrupt status bit.  */
4980 #define HSEM_C2ISR_ISF9_Pos      (9U)
4981 #define HSEM_C2ISR_ISF9_Msk      (0x1UL << HSEM_C2ISR_ISF9_Pos)                /*!< 0x00000200 */
4982 #define HSEM_C2ISR_ISF9          HSEM_C2ISR_ISF9_Msk                           /*!<semaphore 9 CPU2 interrupt status bit.  */
4983 #define HSEM_C2ISR_ISF10_Pos     (10U)
4984 #define HSEM_C2ISR_ISF10_Msk     (0x1UL << HSEM_C2ISR_ISF10_Pos)               /*!< 0x00000400 */
4985 #define HSEM_C2ISR_ISF10         HSEM_C2ISR_ISF10_Msk                          /*!<semaphore 10 CPU2 interrupt status bit. */
4986 #define HSEM_C2ISR_ISF11_Pos     (11U)
4987 #define HSEM_C2ISR_ISF11_Msk     (0x1UL << HSEM_C2ISR_ISF11_Pos)               /*!< 0x00000800 */
4988 #define HSEM_C2ISR_ISF11         HSEM_C2ISR_ISF11_Msk                          /*!<semaphore 11 CPU2 interrupt status bit. */
4989 #define HSEM_C2ISR_ISF12_Pos     (12U)
4990 #define HSEM_C2ISR_ISF12_Msk     (0x1UL << HSEM_C2ISR_ISF12_Pos)               /*!< 0x00001000 */
4991 #define HSEM_C2ISR_ISF12         HSEM_C2ISR_ISF12_Msk                          /*!<semaphore 12 CPU2 interrupt status bit. */
4992 #define HSEM_C2ISR_ISF13_Pos     (13U)
4993 #define HSEM_C2ISR_ISF13_Msk     (0x1UL << HSEM_C2ISR_ISF13_Pos)               /*!< 0x00002000 */
4994 #define HSEM_C2ISR_ISF13         HSEM_C2ISR_ISF13_Msk                          /*!<semaphore 13 CPU2 interrupt status bit. */
4995 #define HSEM_C2ISR_ISF14_Pos     (14U)
4996 #define HSEM_C2ISR_ISF14_Msk     (0x1UL << HSEM_C2ISR_ISF14_Pos)               /*!< 0x00004000 */
4997 #define HSEM_C2ISR_ISF14         HSEM_C2ISR_ISF14_Msk                          /*!<semaphore 14 CPU2 interrupt status bit. */
4998 #define HSEM_C2ISR_ISF15_Pos     (15U)
4999 #define HSEM_C2ISR_ISF15_Msk     (0x1UL << HSEM_C2ISR_ISF15_Pos)               /*!< 0x00008000 */
5000 #define HSEM_C2ISR_ISF15         HSEM_C2ISR_ISF15_Msk                          /*!<semaphore 15 CPU2 interrupt status bit. */
5001 #define HSEM_C2ISR_ISF16_Pos     (16U)
5002 #define HSEM_C2ISR_ISF16_Msk     (0x1UL << HSEM_C2ISR_ISF16_Pos)               /*!< 0x00010000 */
5003 #define HSEM_C2ISR_ISF16         HSEM_C2ISR_ISF16_Msk                          /*!<semaphore 16 CPU2 interrupt status bit. */
5004 #define HSEM_C2ISR_ISF17_Pos     (17U)
5005 #define HSEM_C2ISR_ISF17_Msk     (0x1UL << HSEM_C2ISR_ISF17_Pos)               /*!< 0x00020000 */
5006 #define HSEM_C2ISR_ISF17         HSEM_C2ISR_ISF17_Msk                          /*!<semaphore 17 CPU2 interrupt status bit. */
5007 #define HSEM_C2ISR_ISF18_Pos     (18U)
5008 #define HSEM_C2ISR_ISF18_Msk     (0x1UL << HSEM_C2ISR_ISF18_Pos)               /*!< 0x00040000 */
5009 #define HSEM_C2ISR_ISF18         HSEM_C2ISR_ISF18_Msk                          /*!<semaphore 18 CPU2 interrupt status bit. */
5010 #define HSEM_C2ISR_ISF19_Pos     (19U)
5011 #define HSEM_C2ISR_ISF19_Msk     (0x1UL << HSEM_C2ISR_ISF19_Pos)               /*!< 0x00080000 */
5012 #define HSEM_C2ISR_ISF19         HSEM_C2ISR_ISF19_Msk                          /*!<semaphore 19 CPU2 interrupt status bit. */
5013 #define HSEM_C2ISR_ISF20_Pos     (20U)
5014 #define HSEM_C2ISR_ISF20_Msk     (0x1UL << HSEM_C2ISR_ISF20_Pos)               /*!< 0x00100000 */
5015 #define HSEM_C2ISR_ISF20         HSEM_C2ISR_ISF20_Msk                          /*!<semaphore 20 CPU2 interrupt status bit. */
5016 #define HSEM_C2ISR_ISF21_Pos     (21U)
5017 #define HSEM_C2ISR_ISF21_Msk     (0x1UL << HSEM_C2ISR_ISF21_Pos)               /*!< 0x00200000 */
5018 #define HSEM_C2ISR_ISF21         HSEM_C2ISR_ISF21_Msk                          /*!<semaphore 21 CPU2 interrupt status bit. */
5019 #define HSEM_C2ISR_ISF22_Pos     (22U)
5020 #define HSEM_C2ISR_ISF22_Msk     (0x1UL << HSEM_C2ISR_ISF22_Pos)               /*!< 0x00400000 */
5021 #define HSEM_C2ISR_ISF22         HSEM_C2ISR_ISF22_Msk                          /*!<semaphore 22 CPU2 interrupt status bit. */
5022 #define HSEM_C2ISR_ISF23_Pos     (23U)
5023 #define HSEM_C2ISR_ISF23_Msk     (0x1UL << HSEM_C2ISR_ISF23_Pos)               /*!< 0x00800000 */
5024 #define HSEM_C2ISR_ISF23         HSEM_C2ISR_ISF23_Msk                          /*!<semaphore 23 CPU2 interrupt status bit. */
5025 #define HSEM_C2ISR_ISF24_Pos     (24U)
5026 #define HSEM_C2ISR_ISF24_Msk     (0x1UL << HSEM_C2ISR_ISF24_Pos)               /*!< 0x01000000 */
5027 #define HSEM_C2ISR_ISF24         HSEM_C2ISR_ISF24_Msk                          /*!<semaphore 24 CPU2 interrupt status bit. */
5028 #define HSEM_C2ISR_ISF25_Pos     (25U)
5029 #define HSEM_C2ISR_ISF25_Msk     (0x1UL << HSEM_C2ISR_ISF25_Pos)               /*!< 0x02000000 */
5030 #define HSEM_C2ISR_ISF25         HSEM_C2ISR_ISF25_Msk                          /*!<semaphore 25 CPU2 interrupt status bit. */
5031 #define HSEM_C2ISR_ISF26_Pos     (26U)
5032 #define HSEM_C2ISR_ISF26_Msk     (0x1UL << HSEM_C2ISR_ISF26_Pos)               /*!< 0x04000000 */
5033 #define HSEM_C2ISR_ISF26         HSEM_C2ISR_ISF26_Msk                          /*!<semaphore 26 CPU2 interrupt status bit. */
5034 #define HSEM_C2ISR_ISF27_Pos     (27U)
5035 #define HSEM_C2ISR_ISF27_Msk     (0x1UL << HSEM_C2ISR_ISF27_Pos)               /*!< 0x08000000 */
5036 #define HSEM_C2ISR_ISF27         HSEM_C2ISR_ISF27_Msk                          /*!<semaphore 27 CPU2 interrupt status bit. */
5037 #define HSEM_C2ISR_ISF28_Pos     (28U)
5038 #define HSEM_C2ISR_ISF28_Msk     (0x1UL << HSEM_C2ISR_ISF28_Pos)               /*!< 0x10000000 */
5039 #define HSEM_C2ISR_ISF28         HSEM_C2ISR_ISF28_Msk                          /*!<semaphore 28 CPU2 interrupt status bit. */
5040 #define HSEM_C2ISR_ISF29_Pos     (29U)
5041 #define HSEM_C2ISR_ISF29_Msk     (0x1UL << HSEM_C2ISR_ISF29_Pos)               /*!< 0x20000000 */
5042 #define HSEM_C2ISR_ISF29         HSEM_C2ISR_ISF29_Msk                          /*!<semaphore 29 CPU2 interrupt status bit. */
5043 #define HSEM_C2ISR_ISF30_Pos     (30U)
5044 #define HSEM_C2ISR_ISF30_Msk     (0x1UL << HSEM_C2ISR_ISF30_Pos)               /*!< 0x40000000 */
5045 #define HSEM_C2ISR_ISF30         HSEM_C2ISR_ISF30_Msk                          /*!<semaphore 30 CPU2 interrupt status bit. */
5046 #define HSEM_C2ISR_ISF31_Pos     (31U)
5047 #define HSEM_C2ISR_ISF31_Msk     (0x1UL << HSEM_C2ISR_ISF31_Pos)               /*!< 0x80000000 */
5048 #define HSEM_C2ISR_ISF31         HSEM_C2ISR_ISF31_Msk                          /*!<semaphore 31 CPU2 interrupt status bit. */
5049 
5050 /********************  Bit definition for HSEM_C2MISR register  *****************/
5051 #define HSEM_C2MISR_MISF0_Pos     (0U)
5052 #define HSEM_C2MISR_MISF0_Msk     (0x1UL << HSEM_C2MISR_MISF0_Pos)               /*!< 0x00000001 */
5053 #define HSEM_C2MISR_MISF0         HSEM_C2MISR_MISF0_Msk                          /*!<semaphore 0 CPU2 interrupt masked status bit.  */
5054 #define HSEM_C2MISR_MISF1_Pos     (1U)
5055 #define HSEM_C2MISR_MISF1_Msk     (0x1UL << HSEM_C2MISR_MISF1_Pos)               /*!< 0x00000002 */
5056 #define HSEM_C2MISR_MISF1         HSEM_C2MISR_MISF1_Msk                          /*!<semaphore 1 CPU2 interrupt masked status bit.  */
5057 #define HSEM_C2MISR_MISF2_Pos     (2U)
5058 #define HSEM_C2MISR_MISF2_Msk     (0x1UL << HSEM_C2MISR_MISF2_Pos)               /*!< 0x00000004 */
5059 #define HSEM_C2MISR_MISF2         HSEM_C2MISR_MISF2_Msk                          /*!<semaphore 2 CPU2 interrupt masked status bit.  */
5060 #define HSEM_C2MISR_MISF3_Pos     (3U)
5061 #define HSEM_C2MISR_MISF3_Msk     (0x1UL << HSEM_C2MISR_MISF3_Pos)               /*!< 0x00000008 */
5062 #define HSEM_C2MISR_MISF3         HSEM_C2MISR_MISF3_Msk                          /*!<semaphore 3 CPU2 interrupt masked status bit.  */
5063 #define HSEM_C2MISR_MISF4_Pos     (4U)
5064 #define HSEM_C2MISR_MISF4_Msk     (0x1UL << HSEM_C2MISR_MISF4_Pos)               /*!< 0x00000010 */
5065 #define HSEM_C2MISR_MISF4         HSEM_C2MISR_MISF4_Msk                          /*!<semaphore 4 CPU2 interrupt masked status bit.  */
5066 #define HSEM_C2MISR_MISF5_Pos     (5U)
5067 #define HSEM_C2MISR_MISF5_Msk     (0x1UL << HSEM_C2MISR_MISF5_Pos)               /*!< 0x00000020 */
5068 #define HSEM_C2MISR_MISF5         HSEM_C2MISR_MISF5_Msk                          /*!<semaphore 5 CPU2 interrupt masked status bit.  */
5069 #define HSEM_C2MISR_MISF6_Pos     (6U)
5070 #define HSEM_C2MISR_MISF6_Msk     (0x1UL << HSEM_C2MISR_MISF6_Pos)               /*!< 0x00000040 */
5071 #define HSEM_C2MISR_MISF6         HSEM_C2MISR_MISF6_Msk                          /*!<semaphore 6 CPU2 interrupt masked status bit.  */
5072 #define HSEM_C2MISR_MISF7_Pos     (7U)
5073 #define HSEM_C2MISR_MISF7_Msk     (0x1UL << HSEM_C2MISR_MISF7_Pos)               /*!< 0x00000080 */
5074 #define HSEM_C2MISR_MISF7         HSEM_C2MISR_MISF7_Msk                          /*!<semaphore 7 CPU2 interrupt masked status bit.  */
5075 #define HSEM_C2MISR_MISF8_Pos     (8U)
5076 #define HSEM_C2MISR_MISF8_Msk     (0x1UL << HSEM_C2MISR_MISF8_Pos)               /*!< 0x00000100 */
5077 #define HSEM_C2MISR_MISF8         HSEM_C2MISR_MISF8_Msk                          /*!<semaphore 8 CPU2 interrupt masked status bit.  */
5078 #define HSEM_C2MISR_MISF9_Pos     (9U)
5079 #define HSEM_C2MISR_MISF9_Msk     (0x1UL << HSEM_C2MISR_MISF9_Pos)               /*!< 0x00000200 */
5080 #define HSEM_C2MISR_MISF9         HSEM_C2MISR_MISF9_Msk                          /*!<semaphore 9 CPU2 interrupt masked status bit.  */
5081 #define HSEM_C2MISR_MISF10_Pos    (10U)
5082 #define HSEM_C2MISR_MISF10_Msk    (0x1UL << HSEM_C2MISR_MISF10_Pos)              /*!< 0x00000400 */
5083 #define HSEM_C2MISR_MISF10        HSEM_C2MISR_MISF10_Msk                         /*!<semaphore 10 CPU2 interrupt masked status bit. */
5084 #define HSEM_C2MISR_MISF11_Pos    (11U)
5085 #define HSEM_C2MISR_MISF11_Msk    (0x1UL << HSEM_C2MISR_MISF11_Pos)              /*!< 0x00000800 */
5086 #define HSEM_C2MISR_MISF11        HSEM_C2MISR_MISF11_Msk                         /*!<semaphore 11 CPU2 interrupt masked status bit. */
5087 #define HSEM_C2MISR_MISF12_Pos    (12U)
5088 #define HSEM_C2MISR_MISF12_Msk    (0x1UL << HSEM_C2MISR_MISF12_Pos)              /*!< 0x00001000 */
5089 #define HSEM_C2MISR_MISF12        HSEM_C2MISR_MISF12_Msk                         /*!<semaphore 12 CPU2 interrupt masked status bit. */
5090 #define HSEM_C2MISR_MISF13_Pos    (13U)
5091 #define HSEM_C2MISR_MISF13_Msk    (0x1UL << HSEM_C2MISR_MISF13_Pos)              /*!< 0x00002000 */
5092 #define HSEM_C2MISR_MISF13        HSEM_C2MISR_MISF13_Msk                         /*!<semaphore 13 CPU2 interrupt masked status bit. */
5093 #define HSEM_C2MISR_MISF14_Pos    (14U)
5094 #define HSEM_C2MISR_MISF14_Msk    (0x1UL << HSEM_C2MISR_MISF14_Pos)              /*!< 0x00004000 */
5095 #define HSEM_C2MISR_MISF14        HSEM_C2MISR_MISF14_Msk                         /*!<semaphore 14 CPU2 interrupt masked status bit. */
5096 #define HSEM_C2MISR_MISF15_Pos    (15U)
5097 #define HSEM_C2MISR_MISF15_Msk    (0x1UL << HSEM_C2MISR_MISF15_Pos)              /*!< 0x00008000 */
5098 #define HSEM_C2MISR_MISF15        HSEM_C2MISR_MISF15_Msk                         /*!<semaphore 15 CPU2 interrupt masked status bit. */
5099 #define HSEM_C2MISR_MISF16_Pos    (16U)
5100 #define HSEM_C2MISR_MISF16_Msk    (0x1UL << HSEM_C2MISR_MISF16_Pos)              /*!< 0x00010000 */
5101 #define HSEM_C2MISR_MISF16        HSEM_C2MISR_MISF16_Msk                         /*!<semaphore 16 CPU2 interrupt masked status bit. */
5102 #define HSEM_C2MISR_MISF17_Pos    (17U)
5103 #define HSEM_C2MISR_MISF17_Msk    (0x1UL << HSEM_C2MISR_MISF17_Pos)              /*!< 0x00020000 */
5104 #define HSEM_C2MISR_MISF17        HSEM_C2MISR_MISF17_Msk                         /*!<semaphore 17 CPU2 interrupt masked status bit. */
5105 #define HSEM_C2MISR_MISF18_Pos    (18U)
5106 #define HSEM_C2MISR_MISF18_Msk    (0x1UL << HSEM_C2MISR_MISF18_Pos)              /*!< 0x00040000 */
5107 #define HSEM_C2MISR_MISF18        HSEM_C2MISR_MISF18_Msk                         /*!<semaphore 18 CPU2 interrupt masked status bit. */
5108 #define HSEM_C2MISR_MISF19_Pos    (19U)
5109 #define HSEM_C2MISR_MISF19_Msk    (0x1UL << HSEM_C2MISR_MISF19_Pos)              /*!< 0x00080000 */
5110 #define HSEM_C2MISR_MISF19        HSEM_C2MISR_MISF19_Msk                         /*!<semaphore 19 CPU2 interrupt masked status bit. */
5111 #define HSEM_C2MISR_MISF20_Pos    (20U)
5112 #define HSEM_C2MISR_MISF20_Msk    (0x1UL << HSEM_C2MISR_MISF20_Pos)              /*!< 0x00100000 */
5113 #define HSEM_C2MISR_MISF20        HSEM_C2MISR_MISF20_Msk                         /*!<semaphore 20 CPU2 interrupt masked status bit. */
5114 #define HSEM_C2MISR_MISF21_Pos    (21U)
5115 #define HSEM_C2MISR_MISF21_Msk    (0x1UL << HSEM_C2MISR_MISF21_Pos)              /*!< 0x00200000 */
5116 #define HSEM_C2MISR_MISF21        HSEM_C2MISR_MISF21_Msk                         /*!<semaphore 21 CPU2 interrupt masked status bit. */
5117 #define HSEM_C2MISR_MISF22_Pos    (22U)
5118 #define HSEM_C2MISR_MISF22_Msk    (0x1UL << HSEM_C2MISR_MISF22_Pos)              /*!< 0x00400000 */
5119 #define HSEM_C2MISR_MISF22        HSEM_C2MISR_MISF22_Msk                         /*!<semaphore 22 CPU2 interrupt masked status bit. */
5120 #define HSEM_C2MISR_MISF23_Pos    (23U)
5121 #define HSEM_C2MISR_MISF23_Msk    (0x1UL << HSEM_C2MISR_MISF23_Pos)              /*!< 0x00800000 */
5122 #define HSEM_C2MISR_MISF23        HSEM_C2MISR_MISF23_Msk                         /*!<semaphore 23 CPU2 interrupt masked status bit. */
5123 #define HSEM_C2MISR_MISF24_Pos    (24U)
5124 #define HSEM_C2MISR_MISF24_Msk    (0x1UL << HSEM_C2MISR_MISF24_Pos)              /*!< 0x01000000 */
5125 #define HSEM_C2MISR_MISF24        HSEM_C2MISR_MISF24_Msk                         /*!<semaphore 24 CPU2 interrupt masked status bit. */
5126 #define HSEM_C2MISR_MISF25_Pos    (25U)
5127 #define HSEM_C2MISR_MISF25_Msk    (0x1UL << HSEM_C2MISR_MISF25_Pos)              /*!< 0x02000000 */
5128 #define HSEM_C2MISR_MISF25        HSEM_C2MISR_MISF25_Msk                         /*!<semaphore 25 CPU2 interrupt masked status bit. */
5129 #define HSEM_C2MISR_MISF26_Pos    (26U)
5130 #define HSEM_C2MISR_MISF26_Msk    (0x1UL << HSEM_C2MISR_MISF26_Pos)              /*!< 0x04000000 */
5131 #define HSEM_C2MISR_MISF26        HSEM_C2MISR_MISF26_Msk                         /*!<semaphore 26 CPU2 interrupt masked status bit. */
5132 #define HSEM_C2MISR_MISF27_Pos    (27U)
5133 #define HSEM_C2MISR_MISF27_Msk    (0x1UL << HSEM_C2MISR_MISF27_Pos)              /*!< 0x08000000 */
5134 #define HSEM_C2MISR_MISF27        HSEM_C2MISR_MISF27_Msk                         /*!<semaphore 27 CPU2 interrupt masked status bit. */
5135 #define HSEM_C2MISR_MISF28_Pos    (28U)
5136 #define HSEM_C2MISR_MISF28_Msk    (0x1UL << HSEM_C2MISR_MISF28_Pos)              /*!< 0x10000000 */
5137 #define HSEM_C2MISR_MISF28        HSEM_C2MISR_MISF28_Msk                         /*!<semaphore 28 CPU2 interrupt masked status bit. */
5138 #define HSEM_C2MISR_MISF29_Pos    (29U)
5139 #define HSEM_C2MISR_MISF29_Msk    (0x1UL << HSEM_C2MISR_MISF29_Pos)              /*!< 0x20000000 */
5140 #define HSEM_C2MISR_MISF29        HSEM_C2MISR_MISF29_Msk                         /*!<semaphore 29 CPU2 interrupt masked status bit. */
5141 #define HSEM_C2MISR_MISF30_Pos    (30U)
5142 #define HSEM_C2MISR_MISF30_Msk    (0x1UL << HSEM_C2MISR_MISF30_Pos)              /*!< 0x40000000 */
5143 #define HSEM_C2MISR_MISF30        HSEM_C2MISR_MISF30_Msk                         /*!<semaphore 30 CPU2 interrupt masked status bit. */
5144 #define HSEM_C2MISR_MISF31_Pos    (31U)
5145 #define HSEM_C2MISR_MISF31_Msk    (0x1UL << HSEM_C2MISR_MISF31_Pos)              /*!< 0x80000000 */
5146 #define HSEM_C2MISR_MISF31        HSEM_C2MISR_MISF31_Msk                         /*!<semaphore 31 CPU2 interrupt masked status bit. */
5147 
5148 /********************  Bit definition for HSEM_CR register  *****************/
5149 #define HSEM_CR_COREID_Pos       (8U)
5150 #define HSEM_CR_COREID_Msk       (0xFUL << HSEM_CR_COREID_Pos)                 /*!< 0x00000F00 */
5151 #define HSEM_CR_COREID           HSEM_CR_COREID_Msk                            /*!<CoreID of semaphores to be cleared. */
5152 #define HSEM_CR_COREID_CPU1      (0x4U << HSEM_CR_COREID_Pos)
5153 #define HSEM_CR_COREID_CPU2      (0x8U << HSEM_CR_COREID_Pos)
5154 #define HSEM_CR_COREID_CURRENT   HSEM_CR_COREID_CPU1
5155 #define HSEM_CR_KEY_Pos          (16U)
5156 #define HSEM_CR_KEY_Msk          (0xFFFFUL << HSEM_CR_KEY_Pos)                 /*!< 0xFFFF0000 */
5157 #define HSEM_CR_KEY              HSEM_CR_KEY_Msk                               /*!<semaphores clear key. */
5158 
5159 /********************  Bit definition for HSEM_KEYR register  *****************/
5160 #define HSEM_KEYR_KEY_Pos        (16U)
5161 #define HSEM_KEYR_KEY_Msk        (0xFFFFUL << HSEM_KEYR_KEY_Pos)               /*!< 0xFFFF0000 */
5162 #define HSEM_KEYR_KEY            HSEM_KEYR_KEY_Msk                             /*!<semaphores clear key. */
5163 
5164 /******************************************************************************/
5165 /*                                                                            */
5166 /*                      Inter-integrated Circuit Interface (I2C)              */
5167 /*                                                                            */
5168 /******************************************************************************/
5169 /*******************  Bit definition for I2C_CR1 register  *******************/
5170 #define I2C_CR1_PE_Pos               (0U)
5171 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
5172 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
5173 #define I2C_CR1_TXIE_Pos             (1U)
5174 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
5175 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
5176 #define I2C_CR1_RXIE_Pos             (2U)
5177 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
5178 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
5179 #define I2C_CR1_ADDRIE_Pos           (3U)
5180 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
5181 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
5182 #define I2C_CR1_NACKIE_Pos           (4U)
5183 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
5184 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
5185 #define I2C_CR1_STOPIE_Pos           (5U)
5186 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
5187 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
5188 #define I2C_CR1_TCIE_Pos             (6U)
5189 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
5190 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
5191 #define I2C_CR1_ERRIE_Pos            (7U)
5192 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
5193 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
5194 #define I2C_CR1_DNF_Pos              (8U)
5195 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
5196 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
5197 #define I2C_CR1_ANFOFF_Pos           (12U)
5198 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
5199 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
5200 #define I2C_CR1_SWRST_Pos            (13U)
5201 #define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */
5202 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset */
5203 #define I2C_CR1_TXDMAEN_Pos          (14U)
5204 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
5205 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
5206 #define I2C_CR1_RXDMAEN_Pos          (15U)
5207 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
5208 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
5209 #define I2C_CR1_SBC_Pos              (16U)
5210 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
5211 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
5212 #define I2C_CR1_NOSTRETCH_Pos        (17U)
5213 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
5214 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
5215 #define I2C_CR1_WUPEN_Pos            (18U)
5216 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
5217 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
5218 #define I2C_CR1_GCEN_Pos             (19U)
5219 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
5220 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
5221 #define I2C_CR1_SMBHEN_Pos           (20U)
5222 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
5223 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
5224 #define I2C_CR1_SMBDEN_Pos           (21U)
5225 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
5226 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
5227 #define I2C_CR1_ALERTEN_Pos          (22U)
5228 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
5229 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
5230 #define I2C_CR1_PECEN_Pos            (23U)
5231 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
5232 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
5233 
5234 /******************  Bit definition for I2C_CR2 register  ********************/
5235 #define I2C_CR2_SADD_Pos             (0U)
5236 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
5237 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
5238 #define I2C_CR2_RD_WRN_Pos           (10U)
5239 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
5240 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
5241 #define I2C_CR2_ADD10_Pos            (11U)
5242 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
5243 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
5244 #define I2C_CR2_HEAD10R_Pos          (12U)
5245 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
5246 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
5247 #define I2C_CR2_START_Pos            (13U)
5248 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
5249 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
5250 #define I2C_CR2_STOP_Pos             (14U)
5251 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
5252 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
5253 #define I2C_CR2_NACK_Pos             (15U)
5254 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
5255 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
5256 #define I2C_CR2_NBYTES_Pos           (16U)
5257 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
5258 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
5259 #define I2C_CR2_RELOAD_Pos           (24U)
5260 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
5261 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
5262 #define I2C_CR2_AUTOEND_Pos          (25U)
5263 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
5264 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
5265 #define I2C_CR2_PECBYTE_Pos          (26U)
5266 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
5267 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
5268 
5269 /*******************  Bit definition for I2C_OAR1 register  ******************/
5270 #define I2C_OAR1_OA1_Pos             (0U)
5271 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
5272 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
5273 #define I2C_OAR1_OA1MODE_Pos         (10U)
5274 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
5275 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
5276 #define I2C_OAR1_OA1EN_Pos           (15U)
5277 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
5278 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
5279 
5280 /*******************  Bit definition for I2C_OAR2 register  ******************/
5281 #define I2C_OAR2_OA2_Pos             (1U)
5282 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
5283 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
5284 #define I2C_OAR2_OA2MSK_Pos          (8U)
5285 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
5286 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
5287 #define I2C_OAR2_OA2NOMASK           (0x00000000UL)                            /*!< No mask                                        */
5288 #define I2C_OAR2_OA2MASK01_Pos       (8U)
5289 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
5290 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
5291 #define I2C_OAR2_OA2MASK02_Pos       (9U)
5292 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
5293 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
5294 #define I2C_OAR2_OA2MASK03_Pos       (8U)
5295 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
5296 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
5297 #define I2C_OAR2_OA2MASK04_Pos       (10U)
5298 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
5299 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
5300 #define I2C_OAR2_OA2MASK05_Pos       (8U)
5301 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
5302 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
5303 #define I2C_OAR2_OA2MASK06_Pos       (9U)
5304 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
5305 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
5306 #define I2C_OAR2_OA2MASK07_Pos       (8U)
5307 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
5308 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
5309 #define I2C_OAR2_OA2EN_Pos           (15U)
5310 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
5311 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
5312 
5313 /*******************  Bit definition for I2C_TIMINGR register *******************/
5314 #define I2C_TIMINGR_SCLL_Pos         (0U)
5315 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
5316 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
5317 #define I2C_TIMINGR_SCLH_Pos         (8U)
5318 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
5319 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
5320 #define I2C_TIMINGR_SDADEL_Pos       (16U)
5321 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
5322 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
5323 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
5324 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
5325 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
5326 #define I2C_TIMINGR_PRESC_Pos        (28U)
5327 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
5328 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
5329 
5330 /******************* Bit definition for I2C_TIMEOUTR register *******************/
5331 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
5332 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
5333 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
5334 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
5335 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
5336 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
5337 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
5338 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
5339 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
5340 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
5341 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
5342 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
5343 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
5344 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
5345 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
5346 
5347 /******************  Bit definition for I2C_ISR register  *********************/
5348 #define I2C_ISR_TXE_Pos              (0U)
5349 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
5350 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
5351 #define I2C_ISR_TXIS_Pos             (1U)
5352 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
5353 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
5354 #define I2C_ISR_RXNE_Pos             (2U)
5355 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
5356 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
5357 #define I2C_ISR_ADDR_Pos             (3U)
5358 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
5359 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
5360 #define I2C_ISR_NACKF_Pos            (4U)
5361 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
5362 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
5363 #define I2C_ISR_STOPF_Pos            (5U)
5364 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
5365 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
5366 #define I2C_ISR_TC_Pos               (6U)
5367 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
5368 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
5369 #define I2C_ISR_TCR_Pos              (7U)
5370 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
5371 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
5372 #define I2C_ISR_BERR_Pos             (8U)
5373 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
5374 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
5375 #define I2C_ISR_ARLO_Pos             (9U)
5376 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
5377 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
5378 #define I2C_ISR_OVR_Pos              (10U)
5379 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
5380 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
5381 #define I2C_ISR_PECERR_Pos           (11U)
5382 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
5383 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
5384 #define I2C_ISR_TIMEOUT_Pos          (12U)
5385 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
5386 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
5387 #define I2C_ISR_ALERT_Pos            (13U)
5388 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
5389 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
5390 #define I2C_ISR_BUSY_Pos             (15U)
5391 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
5392 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
5393 #define I2C_ISR_DIR_Pos              (16U)
5394 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
5395 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
5396 #define I2C_ISR_ADDCODE_Pos          (17U)
5397 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
5398 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
5399 
5400 /******************  Bit definition for I2C_ICR register  *********************/
5401 #define I2C_ICR_ADDRCF_Pos           (3U)
5402 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
5403 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
5404 #define I2C_ICR_NACKCF_Pos           (4U)
5405 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
5406 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
5407 #define I2C_ICR_STOPCF_Pos           (5U)
5408 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
5409 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
5410 #define I2C_ICR_BERRCF_Pos           (8U)
5411 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
5412 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
5413 #define I2C_ICR_ARLOCF_Pos           (9U)
5414 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
5415 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
5416 #define I2C_ICR_OVRCF_Pos            (10U)
5417 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
5418 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
5419 #define I2C_ICR_PECCF_Pos            (11U)
5420 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
5421 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
5422 #define I2C_ICR_TIMOUTCF_Pos         (12U)
5423 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
5424 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
5425 #define I2C_ICR_ALERTCF_Pos          (13U)
5426 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
5427 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
5428 
5429 /******************  Bit definition for I2C_PECR register  *********************/
5430 #define I2C_PECR_PEC_Pos             (0U)
5431 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
5432 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
5433 
5434 /******************  Bit definition for I2C_RXDR register  *********************/
5435 #define I2C_RXDR_RXDATA_Pos          (0U)
5436 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
5437 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
5438 
5439 /******************  Bit definition for I2C_TXDR register  *********************/
5440 #define I2C_TXDR_TXDATA_Pos          (0U)
5441 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
5442 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
5443 
5444 /******************************************************************************/
5445 /*                                                                            */
5446 /*                        Independent WATCHDOG (IWDG)                         */
5447 /*                                                                            */
5448 /******************************************************************************/
5449 /*******************  Bit definition for IWDG_KR register  ********************/
5450 #define IWDG_KR_KEY_Pos      (0U)
5451 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
5452 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
5453 
5454 /*******************  Bit definition for IWDG_PR register  ********************/
5455 #define IWDG_PR_PR_Pos       (0U)
5456 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
5457 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
5458 #define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
5459 #define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
5460 #define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
5461 
5462 /*******************  Bit definition for IWDG_RLR register  *******************/
5463 #define IWDG_RLR_RL_Pos      (0U)
5464 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
5465 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
5466 
5467 /*******************  Bit definition for IWDG_SR register  ********************/
5468 #define IWDG_SR_PVU_Pos      (0U)
5469 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
5470 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
5471 #define IWDG_SR_RVU_Pos      (1U)
5472 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
5473 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
5474 #define IWDG_SR_WVU_Pos      (2U)
5475 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
5476 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
5477 
5478 /*******************  Bit definition for IWDG_KR register  ********************/
5479 #define IWDG_WINR_WIN_Pos    (0U)
5480 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
5481 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
5482 
5483 /******************************************************************************/
5484 /*                                                                            */
5485 /*                               Power Control                                */
5486 /*                                                                            */
5487 /******************************************************************************/
5488 
5489 /********************  Bit definition for PWR_CR1 register  ********************/
5490 #define PWR_CR1_LPMS_Pos               (0U)
5491 #define PWR_CR1_LPMS_Msk               (0x7UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000007 */
5492 #define PWR_CR1_LPMS                   PWR_CR1_LPMS_Msk                        /*!< Low Power Mode Selection for CPU1 */
5493 #define PWR_CR1_LPMS_0                 (0x1U << PWR_CR1_LPMS_Pos)              /*!< 0x00000001 */
5494 #define PWR_CR1_LPMS_1                 (0x2U << PWR_CR1_LPMS_Pos)              /*!< 0x00000002 */
5495 #define PWR_CR1_LPMS_2                 (0x4U << PWR_CR1_LPMS_Pos)              /*!< 0x00000004 */
5496 
5497 #define PWR_CR1_FPDR_Pos               (4U)
5498 #define PWR_CR1_FPDR_Msk               (0x1UL << PWR_CR1_FPDR_Pos)             /*!< 0x00000010 */
5499 #define PWR_CR1_FPDR                   PWR_CR1_FPDR_Msk                        /*!< Flash power down mode during LPrun for CPU1 */
5500 
5501 #define PWR_CR1_FPDS_Pos               (5U)
5502 #define PWR_CR1_FPDS_Msk               (0x1UL << PWR_CR1_FPDS_Pos)             /*!< 0x00000020 */
5503 #define PWR_CR1_FPDS                   PWR_CR1_FPDS_Msk                        /*!< Flash power down mode during LPsleep for CPU1 */
5504 
5505 #define PWR_CR1_DBP_Pos                (8U)
5506 #define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */
5507 #define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Backup Domain write protection */
5508 
5509 #define PWR_CR1_LPR_Pos                (14U)
5510 #define PWR_CR1_LPR_Msk                (0x1UL << PWR_CR1_LPR_Pos)              /*!< 0x00004000 */
5511 #define PWR_CR1_LPR                    PWR_CR1_LPR_Msk                         /*!< Regulator Low-Power Run mode */
5512 
5513 /********************  Bit definition for PWR_CR2 register  ********************/
5514 #define PWR_CR2_PVDE_Pos               (0U)
5515 #define PWR_CR2_PVDE_Msk               (0x1UL << PWR_CR2_PVDE_Pos)             /*!< 0x00000001 */
5516 #define PWR_CR2_PVDE                   PWR_CR2_PVDE_Msk                        /*!< Power voltage detector enable */
5517 
5518 #define PWR_CR2_PLS_Pos                (1U)
5519 #define PWR_CR2_PLS_Msk                (0x7UL << PWR_CR2_PLS_Pos)              /*!< 0x0000000E */
5520 #define PWR_CR2_PLS                    PWR_CR2_PLS_Msk                         /*!< Power voltage detector level selection */
5521 #define PWR_CR2_PLS_0                  (0x1U << PWR_CR2_PLS_Pos)               /*!< 0x00000002 */
5522 #define PWR_CR2_PLS_1                  (0x2U << PWR_CR2_PLS_Pos)               /*!< 0x00000004 */
5523 #define PWR_CR2_PLS_2                  (0x4U << PWR_CR2_PLS_Pos)               /*!< 0x00000008 */
5524 
5525 #define PWR_CR2_PVME_Pos               (4U)
5526 #define PWR_CR2_PVME_Msk               (0x4UL << PWR_CR2_PVME_Pos)             /*!< 0x00000040 */
5527 #define PWR_CR2_PVME                   PWR_CR2_PVME_Msk                        /*!< Peripherical Voltage Monitor Enable for all power domains */
5528 #define PWR_CR2_PVME3_Pos              (6U)
5529 #define PWR_CR2_PVME3_Msk              (0x1UL << PWR_CR2_PVME3_Pos)            /*!< 0x00000040 */
5530 #define PWR_CR2_PVME3                  PWR_CR2_PVME3_Msk                       /*!< Peripherical Voltage Monitor Vdda Enable */
5531 
5532 /********************  Bit definition for PWR_CR3 register  ********************/
5533 #define PWR_CR3_EWUP_Pos               (0U)
5534 #define PWR_CR3_EWUP_Msk               (0x09UL << PWR_CR3_EWUP_Pos)            /*!< 0x00000009 */
5535 #define PWR_CR3_EWUP                   PWR_CR3_EWUP_Msk                        /*!< Enable all external Wake-Up lines  */
5536 #define PWR_CR3_EWUP1_Pos              (0U)
5537 #define PWR_CR3_EWUP1_Msk              (0x1UL << PWR_CR3_EWUP1_Pos)            /*!< 0x00000001 */
5538 #define PWR_CR3_EWUP1                  PWR_CR3_EWUP1_Msk                       /*!< Enable external WKUP Pin 1 [line 0] */
5539 #define PWR_CR3_EWUP4_Pos              (3U)
5540 #define PWR_CR3_EWUP4_Msk              (0x1UL << PWR_CR3_EWUP4_Pos)            /*!< 0x00000008 */
5541 #define PWR_CR3_EWUP4                  PWR_CR3_EWUP4_Msk                       /*!< Enable external WKUP Pin 4 [line 3] */
5542 
5543 #define PWR_CR3_EBORHSMPSFB_Pos        (8U)
5544 #define PWR_CR3_EBORHSMPSFB_Msk        (0x1UL << PWR_CR3_EBORHSMPSFB_Pos)      /*!< 0x00000100 */
5545 #define PWR_CR3_EBORHSMPSFB            PWR_CR3_EBORHSMPSFB_Msk                 /*!< BORH and SMPS Step Down converter forced in Bypass interrupts for CPU1 */
5546 
5547 #define PWR_CR3_RRS_Pos                (9U)
5548 #define PWR_CR3_RRS_Msk                (0x1UL << PWR_CR3_RRS_Pos)              /*!< 0x00000200 */
5549 #define PWR_CR3_RRS                    PWR_CR3_RRS_Msk                         /*!< SRAM2 retention in STANDBY mode */
5550 
5551 #define PWR_CR3_APC_Pos                (10U)
5552 #define PWR_CR3_APC_Msk                (0x1UL << PWR_CR3_APC_Pos)              /*!< 0x00000400 */
5553 #define PWR_CR3_APC                    PWR_CR3_APC_Msk                         /*!< Apply pull-up and pull-down configuration for CPU1 */
5554 
5555 #define PWR_CR3_ECRPE_Pos              (11U)
5556 #define PWR_CR3_ECRPE_Msk              (0x1UL << PWR_CR3_ECRPE_Pos)            /*!< 0x00000800 */
5557 #define PWR_CR3_ECRPE                  PWR_CR3_ECRPE_Msk                       /*!< Critical radio phase end of activity interrupt for CPU1 */
5558 #define PWR_CR3_EBLEA_Pos              (12U)
5559 #define PWR_CR3_EBLEA_Msk              (0x1UL << PWR_CR3_EBLEA_Pos)            /*!< 0x00010000 */
5560 #define PWR_CR3_EBLEA                  PWR_CR3_EBLEA_Msk                       /*!< BLE end of activity interrupt for CPU1 */
5561 #define PWR_CR3_EC2H_Pos               (14U)
5562 #define PWR_CR3_EC2H_Msk               (0x1UL << PWR_CR3_EC2H_Pos)             /*!< 0x00040000 */
5563 #define PWR_CR3_EC2H                    PWR_CR3_EC2H_Msk                       /*!< CPU2 Hold interrupt for CPU1 */
5564 
5565 #define PWR_CR3_EIWUL_Pos              (15U)
5566 #define PWR_CR3_EIWUL_Msk              (0x1UL << PWR_CR3_EIWUL_Pos)            /*!< 0x00080000 */
5567 #define PWR_CR3_EIWUL                  PWR_CR3_EIWUL_Msk                       /*!< Internal Wake-Up line interrupt for CPU1 */
5568 
5569 /********************  Bit definition for PWR_CR4 register  ********************/
5570 #define PWR_CR4_WP_Pos                 (0U)
5571 #define PWR_CR4_WP_Msk                 (0x09UL << PWR_CR4_WP_Pos)              /*!< 0x00000009 */
5572 #define PWR_CR4_WP                     PWR_CR4_WP_Msk                          /*!< Wake-Up polarity for all pins */
5573 #define PWR_CR4_WP1_Pos                (0U)
5574 #define PWR_CR4_WP1_Msk                (0x1UL << PWR_CR4_WP1_Pos)              /*!< 0x00000001 */
5575 #define PWR_CR4_WP1                    PWR_CR4_WP1_Msk                         /*!< Wake-Up Pin 1 [line 0] polarity */
5576 #define PWR_CR4_WP4_Pos                (3U)
5577 #define PWR_CR4_WP4_Msk                (0x1UL << PWR_CR4_WP4_Pos)              /*!< 0x00000008 */
5578 #define PWR_CR4_WP4                    PWR_CR4_WP4_Msk                         /*!< Wake-Up Pin 4 [line 3] polarity */
5579 
5580 #define PWR_CR4_VBE_Pos                (8U)
5581 #define PWR_CR4_VBE_Msk                (0x1UL << PWR_CR4_VBE_Pos)              /*!< 0x00000100 */
5582 #define PWR_CR4_VBE                    PWR_CR4_VBE_Msk                         /*!< VBAT battery charging enable  */
5583 #define PWR_CR4_VBRS_Pos               (9U)
5584 #define PWR_CR4_VBRS_Msk               (0x1UL << PWR_CR4_VBRS_Pos)             /*!< 0x00000200 */
5585 #define PWR_CR4_VBRS                   PWR_CR4_VBRS_Msk                        /*!< VBAT battery charging resistor selection */
5586 
5587 #define PWR_CR4_C2BOOT_Pos             (15U)
5588 #define PWR_CR4_C2BOOT_Msk             (0x1UL << PWR_CR4_C2BOOT_Pos)           /*!< 0x00008000 */
5589 #define PWR_CR4_C2BOOT                 PWR_CR4_C2BOOT_Msk                      /*!< Boot CPU2 after reset or wakeup from Stop or Standby modes */
5590 
5591 /********************  Bit definition for PWR_SR1 register  ********************/
5592 #define PWR_SR1_WUF_Pos                (0U)
5593 #define PWR_SR1_WUF_Msk                (0x09UL << PWR_SR1_WUF_Pos)             /*!< 0x00000009 */
5594 #define PWR_SR1_WUF                    PWR_SR1_WUF_Msk                         /*!< Wakeup Flags of all pins */
5595 #define PWR_SR1_WUF1_Pos               (0U)
5596 #define PWR_SR1_WUF1_Msk               (0x1UL << PWR_SR1_WUF1_Pos)             /*!< 0x00000001 */
5597 #define PWR_SR1_WUF1                   PWR_SR1_WUF1_Msk                        /*!< Wakeup Pin 1 [Flag 0] */
5598 #define PWR_SR1_WUF4_Pos               (3U)
5599 #define PWR_SR1_WUF4_Msk               (0x1UL << PWR_SR1_WUF4_Pos)             /*!< 0x00000008 */
5600 #define PWR_SR1_WUF4                   PWR_SR1_WUF4_Msk                        /*!< Wakeup Pin 4 [Flag 3] */
5601 
5602 #define PWR_SR1_SMPSFBF_Pos            (7U)
5603 #define PWR_SR1_SMPSFBF_Msk            (0x1UL << PWR_SR1_SMPSFBF_Pos)          /*!< 0x00000100 */
5604 #define PWR_SR1_SMPSFBF                PWR_SR1_SMPSFBF_Msk                     /*!< SMPS Step Down converter forced in bypass mode interrupt flag */
5605 
5606 #define PWR_SR1_BORHF_Pos              (8U)
5607 #define PWR_SR1_BORHF_Msk              (0x1UL << PWR_SR1_BORHF_Pos)            /*!< 0x00000100 */
5608 #define PWR_SR1_BORHF                  PWR_SR1_BORHF_Msk                       /*!< BORH interrupt flag */
5609 
5610 #define PWR_SR1_BLEWUF_Pos             (9U)
5611 #define PWR_SR1_BLEWUF_Msk             (0x1UL << PWR_SR1_BLEWUF_Pos)           /*!< 0x00000200 */
5612 #define PWR_SR1_BLEWUF                 PWR_SR1_BLEWUF_Msk                      /*!< BLE wakeup interrupt flag */
5613 
5614 #define PWR_SR1_CRPEF_Pos              (11U)
5615 #define PWR_SR1_CRPEF_Msk              (0x1UL << PWR_SR1_CRPEF_Pos)            /*!< 0x00000800 */
5616 #define PWR_SR1_CRPEF                  PWR_SR1_CRPEF_Msk                       /*!< Critical radio phase end of activity interrupt flag */
5617 #define PWR_SR1_BLEAF_Pos              (12U)
5618 #define PWR_SR1_BLEAF_Msk              (0x1UL << PWR_SR1_BLEAF_Pos)            /*!< 0x00001000 */
5619 #define PWR_SR1_BLEAF                  PWR_SR1_BLEAF_Msk                       /*!< BLE end of activity interrupt flag */
5620 
5621 #define PWR_SR1_C2HF_Pos               (14U)
5622 #define PWR_SR1_C2HF_Msk               (0x1UL << PWR_SR1_C2HF_Pos)             /*!< 0x00004000 */
5623 #define PWR_SR1_C2HF                   PWR_SR1_C2HF_Msk                        /*!< CPU2 Hold interrupt flag */
5624 
5625 #define PWR_SR1_WUFI_Pos               (15U)
5626 #define PWR_SR1_WUFI_Msk               (0x1UL << PWR_SR1_WUFI_Pos)             /*!< 0x00008000 */
5627 #define PWR_SR1_WUFI                   PWR_SR1_WUFI_Msk                        /*!< Internal wakeup interrupt flag */
5628 
5629 /********************  Bit definition for PWR_SR2 register  ********************/
5630 #define PWR_SR2_SMPSBF_Pos             (0U)
5631 #define PWR_SR2_SMPSBF_Msk             (0x1UL << PWR_SR2_SMPSBF_Pos)           /*!< 0x00000001 */
5632 #define PWR_SR2_SMPSBF                 PWR_SR2_SMPSBF_Msk                      /*!< SMPS step down converter in operating mode bypass flag */
5633 #define PWR_SR2_SMPSF_Pos              (1U)
5634 #define PWR_SR2_SMPSF_Msk              (0x1UL << PWR_SR2_SMPSF_Pos)            /*!< 0x00000002 */
5635 #define PWR_SR2_SMPSF                  PWR_SR2_SMPSF_Msk                       /*!< SMPS step down converter in operating mode step down flag */
5636 
5637 #define PWR_SR2_REGLPS_Pos             (8U)
5638 #define PWR_SR2_REGLPS_Msk             (0x1UL << PWR_SR2_REGLPS_Pos)           /*!< 0x00000100 */
5639 #define PWR_SR2_REGLPS                 PWR_SR2_REGLPS_Msk                      /*!< Low-power regulator started */
5640 #define PWR_SR2_REGLPF_Pos             (9U)
5641 #define PWR_SR2_REGLPF_Msk             (0x1UL << PWR_SR2_REGLPF_Pos)           /*!< 0x00000200 */
5642 #define PWR_SR2_REGLPF                 PWR_SR2_REGLPF_Msk                      /*!< Low-power regulator flag */
5643 
5644 #define PWR_SR2_PVDO_Pos               (11U)
5645 #define PWR_SR2_PVDO_Msk               (0x1UL << PWR_SR2_PVDO_Pos)             /*!< 0x00000800 */
5646 #define PWR_SR2_PVDO                   PWR_SR2_PVDO_Msk                        /*!< Power voltage detector output */
5647 
5648 #define PWR_SR2_PVMO3_Pos              (14U)
5649 #define PWR_SR2_PVMO3_Msk              (0x1UL << PWR_SR2_PVMO3_Pos)            /*!< 0x00004000 */
5650 #define PWR_SR2_PVMO3                  PWR_SR2_PVMO3_Msk                       /*!< Peripheral voltage monitor output 3: VDDA vs. 1.62V */
5651 
5652 /********************  Bit definition for PWR_SCR register  ********************/
5653 #define PWR_SCR_CWUF_Pos               (0U)
5654 #define PWR_SCR_CWUF_Msk               (0x09UL << PWR_SCR_CWUF_Pos)            /*!< 0x00000009 */
5655 #define PWR_SCR_CWUF                   PWR_SCR_CWUF_Msk                        /*!< Clear Wake-up Flags for all pins */
5656 #define PWR_SCR_CWUF1_Pos              (0U)
5657 #define PWR_SCR_CWUF1_Msk              (0x1UL << PWR_SCR_CWUF1_Pos)            /*!< 0x00000001 */
5658 #define PWR_SCR_CWUF1                  PWR_SCR_CWUF1_Msk                       /*!< Clear Wake-up Pin 1 [Flag 0] */
5659 #define PWR_SCR_CWUF4_Pos              (3U)
5660 #define PWR_SCR_CWUF4_Msk              (0x1UL << PWR_SCR_CWUF4_Pos)            /*!< 0x00000008 */
5661 #define PWR_SCR_CWUF4                  PWR_SCR_CWUF4_Msk                       /*!< Clear Wake-up Pin 4 [Flag 3] */
5662 
5663 #define PWR_SCR_CSMPSFBF_Pos           (7U)
5664 #define PWR_SCR_CSMPSFBF_Msk           (0x1UL << PWR_SCR_CSMPSFBF_Pos)         /*!< 0x00000080 */
5665 #define PWR_SCR_CSMPSFBF               PWR_SCR_CSMPSFBF_Msk                    /*!< Clear SMPS Step Down converter forced in bypass mode interrupt flag  */
5666 
5667 #define PWR_SCR_CBORHF_Pos             (8U)
5668 #define PWR_SCR_CBORHF_Msk             (0x1UL << PWR_SCR_CBORHF_Pos)           /*!< 0x00000100 */
5669 #define PWR_SCR_CBORHF                 PWR_SCR_CBORHF_Msk                      /*!< Clear BORH interrupt flag  */
5670 
5671 #define PWR_SCR_CBLEWUF_Pos            (9U)
5672 #define PWR_SCR_CBLEWUF_Msk            (0x1UL << PWR_SCR_CBLEWUF_Pos)          /*!< 0x00000200 */
5673 #define PWR_SCR_CBLEWUF                PWR_SCR_CBLEWUF_Msk                     /*!< Clear BLE wakeup interrupt flag */
5674 
5675 #define PWR_SCR_CCRPEF_Pos             (11U)
5676 #define PWR_SCR_CCRPEF_Msk             (0x1UL << PWR_SCR_CCRPEF_Pos)           /*!< 0x00000800 */
5677 #define PWR_SCR_CCRPEF                 PWR_SCR_CCRPEF_Msk                      /*!< Clear Critical radio phase end of activity interrupt flag */
5678 #define PWR_SCR_CBLEAF_Pos             (12U)
5679 #define PWR_SCR_CBLEAF_Msk             (0x1UL << PWR_SCR_CBLEAF_Pos)           /*!< 0x00001000 */
5680 #define PWR_SCR_CBLEAF                 PWR_SCR_CBLEAF_Msk                      /*!< Clear BLE end of activity interrupt flag */
5681 
5682 #define PWR_SCR_CC2HF_Pos              (14U)
5683 #define PWR_SCR_CC2HF_Msk              (0x1UL << PWR_SCR_CC2HF_Pos)            /*!< 0x00004000 */
5684 #define PWR_SCR_CC2HF                  PWR_SCR_CC2HF_Msk                       /*!< Clear CPU2 Hold interrupt flag */
5685 
5686 /********************  Bit definition for PWR_CR5 register  ********************/
5687 #define PWR_CR5_SMPSVOS_Pos            (0U)
5688 #define PWR_CR5_SMPSVOS_Msk            (0xFUL << PWR_CR5_SMPSVOS_Pos)          /*!< 0x0000000F */
5689 #define PWR_CR5_SMPSVOS                PWR_CR5_SMPSVOS_Msk                     /*!< SMPS step down converter voltage output scaling voltage level */
5690 #define PWR_CR5_SMPSVOS_0              (0x01U << PWR_CR5_SMPSVOS_Pos)          /*!< 0x00000001 */
5691 #define PWR_CR5_SMPSVOS_1              (0x02U << PWR_CR5_SMPSVOS_Pos)          /*!< 0x00000002 */
5692 #define PWR_CR5_SMPSVOS_2              (0x04U << PWR_CR5_SMPSVOS_Pos)          /*!< 0x00000004 */
5693 #define PWR_CR5_SMPSVOS_3              (0x08U << PWR_CR5_SMPSVOS_Pos)          /*!< 0x00000008 */
5694 
5695 #define PWR_CR5_SMPSSC_Pos             (4U)
5696 #define PWR_CR5_SMPSSC_Msk             (0x7UL << PWR_CR5_SMPSSC_Pos)           /*!< 0x00000070 */
5697 #define PWR_CR5_SMPSSC                 PWR_CR5_SMPSSC_Msk                      /*!< SMPS step down converter supply startup current selection */
5698 #define PWR_CR5_SMPSSC_0               (0x01U << PWR_CR5_SMPSSC_Pos)           /*!< 0x00000010 */
5699 #define PWR_CR5_SMPSSC_1               (0x02U << PWR_CR5_SMPSSC_Pos)           /*!< 0x00000020 */
5700 #define PWR_CR5_SMPSSC_2               (0x04U << PWR_CR5_SMPSSC_Pos)           /*!< 0x00000040 */
5701 
5702 #define PWR_CR5_BORHC_Pos              (8U)
5703 #define PWR_CR5_BORHC_Msk              (0x1UL << PWR_CR5_BORHC_Pos)            /*!< 0x00000100 */
5704 #define PWR_CR5_BORHC                  PWR_CR5_BORHC_Msk                       /*!< BORH configuration selection */
5705 
5706 #define PWR_CR5_SMPSEN_Pos             (15U)
5707 #define PWR_CR5_SMPSEN_Msk             (0x1UL << PWR_CR5_SMPSEN_Pos)           /*!< 0x00008000 */
5708 #define PWR_CR5_SMPSEN                 PWR_CR5_SMPSEN_Msk                      /*!< Enable SMPS Step Down converter SMPS mode enable */
5709 
5710 /********************  Bit definition for PWR_PUCRA register  *****************/
5711 #define PWR_PUCRA_PA0_Pos              (0U)
5712 #define PWR_PUCRA_PA0_Msk              (0x1UL << PWR_PUCRA_PA0_Pos)            /*!< 0x00000001 */
5713 #define PWR_PUCRA_PA0                  PWR_PUCRA_PA0_Msk                       /*!< Pin PA0 Pull-Up set */
5714 #define PWR_PUCRA_PA1_Pos              (1U)
5715 #define PWR_PUCRA_PA1_Msk              (0x1UL << PWR_PUCRA_PA1_Pos)            /*!< 0x00000002 */
5716 #define PWR_PUCRA_PA1                  PWR_PUCRA_PA1_Msk                       /*!< Pin PA1 Pull-Up set */
5717 #define PWR_PUCRA_PA2_Pos              (2U)
5718 #define PWR_PUCRA_PA2_Msk              (0x1UL << PWR_PUCRA_PA2_Pos)            /*!< 0x00000004 */
5719 #define PWR_PUCRA_PA2                  PWR_PUCRA_PA2_Msk                       /*!< Pin PA2 Pull-Up set */
5720 #define PWR_PUCRA_PA3_Pos              (3U)
5721 #define PWR_PUCRA_PA3_Msk              (0x1UL << PWR_PUCRA_PA3_Pos)            /*!< 0x00000008 */
5722 #define PWR_PUCRA_PA3                  PWR_PUCRA_PA3_Msk                       /*!< Pin PA3 Pull-Up set */
5723 #define PWR_PUCRA_PA4_Pos              (4U)
5724 #define PWR_PUCRA_PA4_Msk              (0x1UL << PWR_PUCRA_PA4_Pos)            /*!< 0x00000010 */
5725 #define PWR_PUCRA_PA4                  PWR_PUCRA_PA4_Msk                       /*!< Pin PA4 Pull-Up set */
5726 #define PWR_PUCRA_PA5_Pos              (5U)
5727 #define PWR_PUCRA_PA5_Msk              (0x1UL << PWR_PUCRA_PA5_Pos)            /*!< 0x00000020 */
5728 #define PWR_PUCRA_PA5                  PWR_PUCRA_PA5_Msk                       /*!< Pin PA5 Pull-Up set */
5729 #define PWR_PUCRA_PA6_Pos              (6U)
5730 #define PWR_PUCRA_PA6_Msk              (0x1UL << PWR_PUCRA_PA6_Pos)            /*!< 0x00000040 */
5731 #define PWR_PUCRA_PA6                  PWR_PUCRA_PA6_Msk                       /*!< Pin PA6 Pull-Up set */
5732 #define PWR_PUCRA_PA7_Pos              (7U)
5733 #define PWR_PUCRA_PA7_Msk              (0x1UL << PWR_PUCRA_PA7_Pos)            /*!< 0x00000080 */
5734 #define PWR_PUCRA_PA7                  PWR_PUCRA_PA7_Msk                       /*!< Pin PA7 Pull-Up set */
5735 #define PWR_PUCRA_PA8_Pos              (8U)
5736 #define PWR_PUCRA_PA8_Msk              (0x1UL << PWR_PUCRA_PA8_Pos)            /*!< 0x00000100 */
5737 #define PWR_PUCRA_PA8                  PWR_PUCRA_PA8_Msk                       /*!< Pin PA8 Pull-Up set */
5738 #define PWR_PUCRA_PA9_Pos              (9U)
5739 #define PWR_PUCRA_PA9_Msk              (0x1UL << PWR_PUCRA_PA9_Pos)            /*!< 0x00000200 */
5740 #define PWR_PUCRA_PA9                  PWR_PUCRA_PA9_Msk                       /*!< Pin PA9 Pull-Up set */
5741 #define PWR_PUCRA_PA10_Pos             (10U)
5742 #define PWR_PUCRA_PA10_Msk             (0x1UL << PWR_PUCRA_PA10_Pos)           /*!< 0x00000400 */
5743 #define PWR_PUCRA_PA10                 PWR_PUCRA_PA10_Msk                      /*!< Pin PA10 Pull-Up set */
5744 #define PWR_PUCRA_PA11_Pos             (11U)
5745 #define PWR_PUCRA_PA11_Msk             (0x1UL << PWR_PUCRA_PA11_Pos)           /*!< 0x00000800 */
5746 #define PWR_PUCRA_PA11                 PWR_PUCRA_PA11_Msk                      /*!< Pin PA11 Pull-Up set */
5747 #define PWR_PUCRA_PA12_Pos             (12U)
5748 #define PWR_PUCRA_PA12_Msk             (0x1UL << PWR_PUCRA_PA12_Pos)           /*!< 0x00001000 */
5749 #define PWR_PUCRA_PA12                 PWR_PUCRA_PA12_Msk                      /*!< Pin PA12 Pull-Up set */
5750 #define PWR_PUCRA_PA13_Pos             (13U)
5751 #define PWR_PUCRA_PA13_Msk             (0x1UL << PWR_PUCRA_PA13_Pos)           /*!< 0x00002000 */
5752 #define PWR_PUCRA_PA13                 PWR_PUCRA_PA13_Msk                      /*!< Pin PA13 Pull-Up set */
5753 #define PWR_PUCRA_PA15_Pos             (15U)
5754 #define PWR_PUCRA_PA15_Msk             (0x1UL << PWR_PUCRA_PA15_Pos)           /*!< 0x00008000 */
5755 #define PWR_PUCRA_PA15                 PWR_PUCRA_PA15_Msk                      /*!< Pin PA15 Pull-Up set */
5756 
5757 /********************  Bit definition for PWR_PDCRA register  *****************/
5758 #define PWR_PDCRA_PA0_Pos              (0U)
5759 #define PWR_PDCRA_PA0_Msk              (0x1UL << PWR_PDCRA_PA0_Pos)            /*!< 0x00000001 */
5760 #define PWR_PDCRA_PA0                  PWR_PDCRA_PA0_Msk                       /*!< Pin PA0 Pull-Down set */
5761 #define PWR_PDCRA_PA1_Pos              (1U)
5762 #define PWR_PDCRA_PA1_Msk              (0x1UL << PWR_PDCRA_PA1_Pos)            /*!< 0x00000002 */
5763 #define PWR_PDCRA_PA1                  PWR_PDCRA_PA1_Msk                       /*!< Pin PA1 Pull-Down set */
5764 #define PWR_PDCRA_PA2_Pos              (2U)
5765 #define PWR_PDCRA_PA2_Msk              (0x1UL << PWR_PDCRA_PA2_Pos)            /*!< 0x00000004 */
5766 #define PWR_PDCRA_PA2                  PWR_PDCRA_PA2_Msk                       /*!< Pin PA2 Pull-Down set */
5767 #define PWR_PDCRA_PA3_Pos              (3U)
5768 #define PWR_PDCRA_PA3_Msk              (0x1UL << PWR_PDCRA_PA3_Pos)            /*!< 0x00000008 */
5769 #define PWR_PDCRA_PA3                  PWR_PDCRA_PA3_Msk                       /*!< Pin PA3 Pull-Down set */
5770 #define PWR_PDCRA_PA4_Pos              (4U)
5771 #define PWR_PDCRA_PA4_Msk              (0x1UL << PWR_PDCRA_PA4_Pos)            /*!< 0x00000010 */
5772 #define PWR_PDCRA_PA4                  PWR_PDCRA_PA4_Msk                       /*!< Pin PA4 Pull-Down set */
5773 #define PWR_PDCRA_PA5_Pos              (5U)
5774 #define PWR_PDCRA_PA5_Msk              (0x1UL << PWR_PDCRA_PA5_Pos)            /*!< 0x00000020 */
5775 #define PWR_PDCRA_PA5                  PWR_PDCRA_PA5_Msk                       /*!< Pin PA5 Pull-Down set */
5776 #define PWR_PDCRA_PA6_Pos              (6U)
5777 #define PWR_PDCRA_PA6_Msk              (0x1UL << PWR_PDCRA_PA6_Pos)            /*!< 0x00000040 */
5778 #define PWR_PDCRA_PA6                  PWR_PDCRA_PA6_Msk                       /*!< Pin PA6 Pull-Down set */
5779 #define PWR_PDCRA_PA7_Pos              (7U)
5780 #define PWR_PDCRA_PA7_Msk              (0x1UL << PWR_PDCRA_PA7_Pos)            /*!< 0x00000080 */
5781 #define PWR_PDCRA_PA7                  PWR_PDCRA_PA7_Msk                       /*!< Pin PA7 Pull-Down set */
5782 #define PWR_PDCRA_PA8_Pos              (8U)
5783 #define PWR_PDCRA_PA8_Msk              (0x1UL << PWR_PDCRA_PA8_Pos)            /*!< 0x00000100 */
5784 #define PWR_PDCRA_PA8                  PWR_PDCRA_PA8_Msk                       /*!< Pin PA8 Pull-Down set */
5785 #define PWR_PDCRA_PA9_Pos              (9U)
5786 #define PWR_PDCRA_PA9_Msk              (0x1UL << PWR_PDCRA_PA9_Pos)            /*!< 0x00000200 */
5787 #define PWR_PDCRA_PA9                  PWR_PDCRA_PA9_Msk                       /*!< Pin PA9 Pull-Down set */
5788 #define PWR_PDCRA_PA10_Pos             (10U)
5789 #define PWR_PDCRA_PA10_Msk             (0x1UL << PWR_PDCRA_PA10_Pos)           /*!< 0x00000400 */
5790 #define PWR_PDCRA_PA10                 PWR_PDCRA_PA10_Msk                      /*!< Pin PA10 Pull-Down set */
5791 #define PWR_PDCRA_PA11_Pos             (11U)
5792 #define PWR_PDCRA_PA11_Msk             (0x1UL << PWR_PDCRA_PA11_Pos)           /*!< 0x00000800 */
5793 #define PWR_PDCRA_PA11                 PWR_PDCRA_PA11_Msk                      /*!< Pin PA11 Pull-Down set */
5794 #define PWR_PDCRA_PA12_Pos             (12U)
5795 #define PWR_PDCRA_PA12_Msk             (0x1UL << PWR_PDCRA_PA12_Pos)           /*!< 0x00001000 */
5796 #define PWR_PDCRA_PA12                 PWR_PDCRA_PA12_Msk                      /*!< Pin PA12 Pull-Down set */
5797 #define PWR_PDCRA_PA14_Pos             (14U)
5798 #define PWR_PDCRA_PA14_Msk             (0x1UL << PWR_PDCRA_PA14_Pos)           /*!< 0x00004000 */
5799 #define PWR_PDCRA_PA14                 PWR_PDCRA_PA14_Msk                      /*!< Pin PA14 Pull-Down set */
5800 
5801 /********************  Bit definition for PWR_PUCRB register  *****************/
5802 #define PWR_PUCRB_PB0_Pos              (0U)
5803 #define PWR_PUCRB_PB0_Msk              (0x1UL << PWR_PUCRB_PB0_Pos)            /*!< 0x00000001 */
5804 #define PWR_PUCRB_PB0                  PWR_PUCRB_PB0_Msk                       /*!< Pin PB0 Pull-Up set */
5805 #define PWR_PUCRB_PB1_Pos              (1U)
5806 #define PWR_PUCRB_PB1_Msk              (0x1UL << PWR_PUCRB_PB1_Pos)            /*!< 0x00000002 */
5807 #define PWR_PUCRB_PB1                  PWR_PUCRB_PB1_Msk                       /*!< Pin PB1 Pull-Up set */
5808 #define PWR_PUCRB_PB2_Pos              (2U)
5809 #define PWR_PUCRB_PB2_Msk              (0x1UL << PWR_PUCRB_PB2_Pos)            /*!< 0x00000004 */
5810 #define PWR_PUCRB_PB2                  PWR_PUCRB_PB2_Msk                       /*!< Pin PB2 Pull-Up set */
5811 #define PWR_PUCRB_PB3_Pos              (3U)
5812 #define PWR_PUCRB_PB3_Msk              (0x1UL << PWR_PUCRB_PB3_Pos)            /*!< 0x00000008 */
5813 #define PWR_PUCRB_PB3                  PWR_PUCRB_PB3_Msk                       /*!< Pin PB3 Pull-Up set */
5814 #define PWR_PUCRB_PB4_Pos              (4U)
5815 #define PWR_PUCRB_PB4_Msk              (0x1UL << PWR_PUCRB_PB4_Pos)            /*!< 0x00000010 */
5816 #define PWR_PUCRB_PB4                  PWR_PUCRB_PB4_Msk                       /*!< Pin PB4 Pull-Up set */
5817 #define PWR_PUCRB_PB5_Pos              (5U)
5818 #define PWR_PUCRB_PB5_Msk              (0x1UL << PWR_PUCRB_PB5_Pos)            /*!< 0x00000020 */
5819 #define PWR_PUCRB_PB5                  PWR_PUCRB_PB5_Msk                       /*!< Pin PB5 Pull-Up set */
5820 #define PWR_PUCRB_PB6_Pos              (6U)
5821 #define PWR_PUCRB_PB6_Msk              (0x1UL << PWR_PUCRB_PB6_Pos)            /*!< 0x00000040 */
5822 #define PWR_PUCRB_PB6                  PWR_PUCRB_PB6_Msk                       /*!< Pin PB6 Pull-Up set */
5823 #define PWR_PUCRB_PB7_Pos              (7U)
5824 #define PWR_PUCRB_PB7_Msk              (0x1UL << PWR_PUCRB_PB7_Pos)            /*!< 0x00000080 */
5825 #define PWR_PUCRB_PB7                  PWR_PUCRB_PB7_Msk                       /*!< Pin PB7 Pull-Up set */
5826 #define PWR_PUCRB_PB8_Pos              (8U)
5827 #define PWR_PUCRB_PB8_Msk              (0x1UL << PWR_PUCRB_PB8_Pos)            /*!< 0x00000100 */
5828 #define PWR_PUCRB_PB8                  PWR_PUCRB_PB8_Msk                       /*!< Pin PB8 Pull-Up set */
5829 #define PWR_PUCRB_PB9_Pos              (9U)
5830 #define PWR_PUCRB_PB9_Msk              (0x1UL << PWR_PUCRB_PB9_Pos)            /*!< 0x00000200 */
5831 #define PWR_PUCRB_PB9                  PWR_PUCRB_PB9_Msk                       /*!< Pin PB9 Pull-Up set */
5832 
5833 /********************  Bit definition for PWR_PDCRB register  *****************/
5834 #define PWR_PDCRB_PB0_Pos              (0U)
5835 #define PWR_PDCRB_PB0_Msk              (0x1UL << PWR_PDCRB_PB0_Pos)            /*!< 0x00000001 */
5836 #define PWR_PDCRB_PB0                  PWR_PDCRB_PB0_Msk                       /*!< Pin PB0 Pull-Down set */
5837 #define PWR_PDCRB_PB1_Pos              (1U)
5838 #define PWR_PDCRB_PB1_Msk              (0x1UL << PWR_PDCRB_PB1_Pos)            /*!< 0x00000002 */
5839 #define PWR_PDCRB_PB1                  PWR_PDCRB_PB1_Msk                       /*!< Pin PB1 Pull-Down set */
5840 #define PWR_PDCRB_PB2_Pos              (2U)
5841 #define PWR_PDCRB_PB2_Msk              (0x1UL << PWR_PDCRB_PB2_Pos)            /*!< 0x00000004 */
5842 #define PWR_PDCRB_PB2                  PWR_PDCRB_PB2_Msk                       /*!< Pin PB2 Pull-Down set */
5843 #define PWR_PDCRB_PB3_Pos              (3U)
5844 #define PWR_PDCRB_PB3_Msk              (0x1UL << PWR_PDCRB_PB3_Pos)            /*!< 0x00000008 */
5845 #define PWR_PDCRB_PB3                  PWR_PDCRB_PB3_Msk                       /*!< Pin PB3 Pull-Down set */
5846 #define PWR_PDCRB_PB5_Pos              (5U)
5847 #define PWR_PDCRB_PB5_Msk              (0x1UL << PWR_PDCRB_PB5_Pos)            /*!< 0x00000020 */
5848 #define PWR_PDCRB_PB5                  PWR_PDCRB_PB5_Msk                       /*!< Pin PB5 Pull-Down set */
5849 #define PWR_PDCRB_PB6_Pos              (6U)
5850 #define PWR_PDCRB_PB6_Msk              (0x1UL << PWR_PDCRB_PB6_Pos)            /*!< 0x00000040 */
5851 #define PWR_PDCRB_PB6                  PWR_PDCRB_PB6_Msk                       /*!< Pin PB6 Pull-Down set */
5852 #define PWR_PDCRB_PB7_Pos              (7U)
5853 #define PWR_PDCRB_PB7_Msk              (0x1UL << PWR_PDCRB_PB7_Pos)            /*!< 0x00000080 */
5854 #define PWR_PDCRB_PB7                  PWR_PDCRB_PB7_Msk                       /*!< Pin PB7 Pull-Down set */
5855 #define PWR_PDCRB_PB8_Pos              (8U)
5856 #define PWR_PDCRB_PB8_Msk              (0x1UL << PWR_PDCRB_PB8_Pos)            /*!< 0x00000100 */
5857 #define PWR_PDCRB_PB8                  PWR_PDCRB_PB8_Msk                       /*!< Pin PB8 Pull-Down set */
5858 #define PWR_PDCRB_PB9_Pos              (9U)
5859 #define PWR_PDCRB_PB9_Msk              (0x1UL << PWR_PDCRB_PB9_Pos)            /*!< 0x00000200 */
5860 #define PWR_PDCRB_PB9                  PWR_PDCRB_PB9_Msk                       /*!< Pin PB9 Pull-Down set */
5861 
5862 /********************  Bit definition for PWR_PUCRC register  *****************/
5863 #define PWR_PUCRC_PC14_Pos             (14U)
5864 #define PWR_PUCRC_PC14_Msk             (0x1UL << PWR_PUCRC_PC14_Pos)           /*!< 0x00004000 */
5865 #define PWR_PUCRC_PC14                 PWR_PUCRC_PC14_Msk                      /*!< Pin PC14 Pull-Up set */
5866 #define PWR_PUCRC_PC15_Pos             (15U)
5867 #define PWR_PUCRC_PC15_Msk             (0x1UL << PWR_PUCRC_PC15_Pos)           /*!< 0x00008000 */
5868 #define PWR_PUCRC_PC15                 PWR_PUCRC_PC15_Msk                      /*!< Pin PC15 Pull-Up set */
5869 
5870 /********************  Bit definition for PWR_PDCRC register  *****************/
5871 #define PWR_PDCRC_PC14_Pos             (14U)
5872 #define PWR_PDCRC_PC14_Msk             (0x1UL << PWR_PDCRC_PC14_Pos)           /*!< 0x00004000 */
5873 #define PWR_PDCRC_PC14                 PWR_PDCRC_PC14_Msk                      /*!< Pin PC14 Pull-Down set */
5874 #define PWR_PDCRC_PC15_Pos             (15U)
5875 #define PWR_PDCRC_PC15_Msk             (0x1UL << PWR_PDCRC_PC15_Pos)           /*!< 0x00008000 */
5876 #define PWR_PDCRC_PC15                 PWR_PDCRC_PC15_Msk                      /*!< Pin PC15 Pull-Down set */
5877 
5878 /********************  Bit definition for PWR_PUCRE register  *****************/
5879 #define PWR_PUCRE_PE4_Pos              (4U)
5880 #define PWR_PUCRE_PE4_Msk              (0x1UL << PWR_PUCRE_PE4_Pos)            /*!< 0x00000010 */
5881 #define PWR_PUCRE_PE4                  PWR_PUCRE_PE4_Msk                       /*!< Pin PE4 Pull-Up set */
5882 
5883 /********************  Bit definition for PWR_PDCRE register  *****************/
5884 #define PWR_PDCRE_PE4_Pos              (4U)
5885 #define PWR_PDCRE_PE4_Msk              (0x1UL << PWR_PDCRE_PE4_Pos)            /*!< 0x00000010 */
5886 #define PWR_PDCRE_PE4                  PWR_PDCRE_PE4_Msk                       /*!< Pin PE4 Pull-Down set */
5887 
5888 /********************  Bit definition for PWR_PUCRH register  *****************/
5889 #define PWR_PUCRH_PH3_Pos              (3U)
5890 #define PWR_PUCRH_PH3_Msk              (0x1UL << PWR_PUCRH_PH3_Pos)            /*!< 0x00000004 */
5891 #define PWR_PUCRH_PH3                  PWR_PUCRH_PH3_Msk                       /*!< Pin PH3 Pull-Up set */
5892 
5893 /********************  Bit definition for PWR_PDCRH register  *****************/
5894 #define PWR_PDCRH_PH3_Pos              (3U)
5895 #define PWR_PDCRH_PH3_Msk              (0x1UL << PWR_PDCRH_PH3_Pos)            /*!< 0x00000004 */
5896 #define PWR_PDCRH_PH3                  PWR_PDCRH_PH3_Msk                       /*!< Pin PH3 Pull-Down set */
5897 
5898 /********************  Bit definition for PWR_C2CR1 register  ********************/
5899 #define PWR_C2CR1_LPMS_Pos             (0U)
5900 #define PWR_C2CR1_LPMS_Msk             (0x7UL << PWR_C2CR1_LPMS_Pos)           /*!< 0x00000007 */
5901 #define PWR_C2CR1_LPMS                 PWR_C2CR1_LPMS_Msk                      /*!< Low Power Mode Selection for CPU2 */
5902 #define PWR_C2CR1_LPMS_0               (0x1U << PWR_C2CR1_LPMS_Pos)            /*!< 0x00000001 */
5903 #define PWR_C2CR1_LPMS_1               (0x2U << PWR_C2CR1_LPMS_Pos)            /*!< 0x00000002 */
5904 #define PWR_C2CR1_LPMS_2               (0x4U << PWR_C2CR1_LPMS_Pos)            /*!< 0x00000004 */
5905 
5906 #define PWR_C2CR1_FPDR_Pos             (4U)
5907 #define PWR_C2CR1_FPDR_Msk             (0x1UL << PWR_C2CR1_FPDR_Pos)           /*!< 0x00000010 */
5908 #define PWR_C2CR1_FPDR                 PWR_C2CR1_FPDR_Msk                      /*!< Flash power down mode during LPrun for CPU2 */
5909 
5910 #define PWR_C2CR1_FPDS_Pos             (5U)
5911 #define PWR_C2CR1_FPDS_Msk             (0x1UL << PWR_C2CR1_FPDS_Pos)           /*!< 0x00000020 */
5912 #define PWR_C2CR1_FPDS                 PWR_C2CR1_FPDS_Msk                      /*!< Flash power down mode during LPsleep for CPU2 */
5913 
5914 #define PWR_C2CR1_BLEEWKUP_Pos         (14U)
5915 #define PWR_C2CR1_BLEEWKUP_Msk         (0x1UL << PWR_C2CR1_BLEEWKUP_Pos)       /*!< 0x00008000 */
5916 #define PWR_C2CR1_BLEEWKUP             PWR_C2CR1_BLEEWKUP_Msk                  /*!< Radio BLE external wakeup signal */
5917 
5918 /********************  Bit definition for PWR_C2CR3 register  ********************/
5919 #define PWR_C2CR3_EWUP_Pos             (0U)
5920 #define PWR_C2CR3_EWUP_Msk             (0x09UL << PWR_C2CR3_EWUP_Pos)           /*!< 0x00000009 */
5921 #define PWR_C2CR3_EWUP                 PWR_C2CR3_EWUP_Msk                       /*!< Enable all external Wake-Up lines for CPU2 */
5922 #define PWR_C2CR3_EWUP1_Pos            (0U)
5923 #define PWR_C2CR3_EWUP1_Msk            (0x1UL << PWR_C2CR3_EWUP1_Pos)           /*!< 0x00000001 */
5924 #define PWR_C2CR3_EWUP1                PWR_C2CR3_EWUP1_Msk                      /*!< Enable external WKUP Pin 1 [line 0] for CPU2 */
5925 #define PWR_C2CR3_EWUP4_Pos            (3U)
5926 #define PWR_C2CR3_EWUP4_Msk            (0x1UL << PWR_C2CR3_EWUP4_Pos)           /*!< 0x00000008 */
5927 #define PWR_C2CR3_EWUP4                PWR_C2CR3_EWUP4_Msk                      /*!< Enable external WKUP Pin 4 [line 3] for CPU2 */
5928 
5929 #define PWR_C2CR3_EBLEWUP_Pos          (9U)
5930 #define PWR_C2CR3_EBLEWUP_Msk          (0x1UL << PWR_C2CR3_EBLEWUP_Pos)       /*!< 0x00000200 */
5931 #define PWR_C2CR3_EBLEWUP              PWR_C2CR3_EBLEWUP_Msk                 /*!< Enable BLE host wakeup interrupt for CPU2 */
5932 
5933 #define PWR_C2CR3_APC_Pos              (12U)
5934 #define PWR_C2CR3_APC_Msk              (0x1UL << PWR_C2CR3_APC_Pos)            /*!< 0x00001000 */
5935 #define PWR_C2CR3_APC                  PWR_C2CR3_APC_Msk                       /*!< Apply pull-up and pull-down configuration for CPU2 */
5936 
5937 #define PWR_C2CR3_EIWUL_Pos            (15U)
5938 #define PWR_C2CR3_EIWUL_Msk            (0x1UL << PWR_C2CR3_EIWUL_Pos)          /*!< 0x00008000 */
5939 #define PWR_C2CR3_EIWUL                PWR_C2CR3_EIWUL_Msk                     /*!< Internal Wake-Up line interrupt for CPU2 */
5940 
5941 /********************  Bit definition for PWR_EXTSCR register  ********************/
5942 #define PWR_EXTSCR_C1CSSF_Pos          (0U)
5943 #define PWR_EXTSCR_C1CSSF_Msk          (0x1UL << PWR_EXTSCR_C1CSSF_Pos)        /*!< 0x00000001 */
5944 #define PWR_EXTSCR_C1CSSF              PWR_EXTSCR_C1CSSF_Msk                   /*!< Clear standby and stop flags for CPU1 */
5945 #define PWR_EXTSCR_C2CSSF_Pos          (1U)
5946 #define PWR_EXTSCR_C2CSSF_Msk          (0x1UL << PWR_EXTSCR_C2CSSF_Pos)        /*!< 0x00000002 */
5947 #define PWR_EXTSCR_C2CSSF              PWR_EXTSCR_C2CSSF_Msk                   /*!< Clear standby and stop flags for CPU2 */
5948 #define PWR_EXTSCR_CCRPF_Pos           (2U)
5949 #define PWR_EXTSCR_CCRPF_Msk           (0x1UL << PWR_EXTSCR_CCRPF_Pos)         /*!< 0x00000004 */
5950 #define PWR_EXTSCR_CCRPF               PWR_EXTSCR_CCRPF_Msk                    /*!< Clear critical radio system phase flag */
5951 
5952 #define PWR_EXTSCR_C1SBF_Pos           (8U)
5953 #define PWR_EXTSCR_C1SBF_Msk           (0x1UL << PWR_EXTSCR_C1SBF_Pos)         /*!< 0x00000100 */
5954 #define PWR_EXTSCR_C1SBF               PWR_EXTSCR_C1SBF_Msk                    /*!< System standby flag for CPU1 */
5955 #define PWR_EXTSCR_C1STOPF_Pos         (9U)
5956 #define PWR_EXTSCR_C1STOPF_Msk         (0x1UL << PWR_EXTSCR_C1STOPF_Pos)       /*!< 0x00000200 */
5957 #define PWR_EXTSCR_C1STOPF             PWR_EXTSCR_C1STOPF_Msk                  /*!< System stop flag for CPU1 */
5958 #define PWR_EXTSCR_C2SBF_Pos           (10U)
5959 #define PWR_EXTSCR_C2SBF_Msk           (0x1UL << PWR_EXTSCR_C2SBF_Pos)         /*!< 0x00000400 */
5960 #define PWR_EXTSCR_C2SBF               PWR_EXTSCR_C2SBF_Msk                    /*!< System standby flag for CPU2 */
5961 #define PWR_EXTSCR_C2STOPF_Pos         (11U)
5962 #define PWR_EXTSCR_C2STOPF_Msk         (0x1UL << PWR_EXTSCR_C2STOPF_Pos)       /*!< 0x00000800 */
5963 #define PWR_EXTSCR_C2STOPF             PWR_EXTSCR_C2STOPF_Msk                  /*!< System stop flag for CPU2 */
5964 
5965 #define PWR_EXTSCR_CRPF_Pos            (13U)
5966 #define PWR_EXTSCR_CRPF_Msk            (0x1UL << PWR_EXTSCR_CRPF_Pos)          /*!< 0x00002000 */
5967 #define PWR_EXTSCR_CRPF                PWR_EXTSCR_CRPF_Msk                     /*!< Critical radio system phase flag */
5968 
5969 #define PWR_EXTSCR_C1DS_Pos            (14U)
5970 #define PWR_EXTSCR_C1DS_Msk            (0x1UL << PWR_EXTSCR_C1DS_Pos)          /*!< 0x00004000 */
5971 #define PWR_EXTSCR_C1DS                PWR_EXTSCR_C1DS_Msk                     /*!< CPU1 deepsleep mode flag */
5972 #define PWR_EXTSCR_C2DS_Pos            (15U)
5973 #define PWR_EXTSCR_C2DS_Msk            (0x1UL << PWR_EXTSCR_C2DS_Pos)          /*!< 0x00008000 */
5974 #define PWR_EXTSCR_C2DS                PWR_EXTSCR_C2DS_Msk                     /*!< CPU2 deepsleep mode flag */
5975 
5976 /******************************************************************************/
5977 /*                                                                            */
5978 /*                         Reset and Clock Control                            */
5979 /*                                                                            */
5980 /******************************************************************************/
5981 /*
5982   * @brief Specific device feature definitions
5983   */
5984 #define RCC_SMPS_SUPPORT
5985 
5986 /********************  Bit definition for RCC_CR register  *****************/
5987 #define RCC_CR_MSION_Pos                     (0U)
5988 #define RCC_CR_MSION_Msk                     (0x1UL << RCC_CR_MSION_Pos)       /*!< 0x00000001 */
5989 #define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
5990 #define RCC_CR_MSIRDY_Pos                    (1U)
5991 #define RCC_CR_MSIRDY_Msk                    (0x1UL << RCC_CR_MSIRDY_Pos)      /*!< 0x00000002 */
5992 #define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
5993 #define RCC_CR_MSIPLLEN_Pos                  (2U)
5994 #define RCC_CR_MSIPLLEN_Msk                  (0x1UL << RCC_CR_MSIPLLEN_Pos)    /*!< 0x00000004 */
5995 #define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
5996 
5997 /*!< MSIRANGE configuration : 12 frequency ranges available */
5998 #define RCC_CR_MSIRANGE_Pos                  (4U)
5999 #define RCC_CR_MSIRANGE_Msk                  (0xFUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000F0 */
6000 #define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
6001 #define RCC_CR_MSIRANGE_0                    (0x0U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000000 */
6002 #define RCC_CR_MSIRANGE_1                    (0x1U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000010 */
6003 #define RCC_CR_MSIRANGE_2                    (0x2U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000020 */
6004 #define RCC_CR_MSIRANGE_3                    (0x3U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000030 */
6005 #define RCC_CR_MSIRANGE_4                    (0x4U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000040 */
6006 #define RCC_CR_MSIRANGE_5                    (0x5U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000050 */
6007 #define RCC_CR_MSIRANGE_6                    (0x6U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000060 */
6008 #define RCC_CR_MSIRANGE_7                    (0x7U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000070 */
6009 #define RCC_CR_MSIRANGE_8                    (0x8U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000080 */
6010 #define RCC_CR_MSIRANGE_9                    (0x9U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000090 */
6011 #define RCC_CR_MSIRANGE_10                   (0xAU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000A0 */
6012 #define RCC_CR_MSIRANGE_11                   (0xBU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000B0 */
6013 
6014 #define RCC_CR_HSION_Pos                     (8U)
6015 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
6016 #define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
6017 #define RCC_CR_HSIKERON_Pos                  (9U)
6018 #define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
6019 #define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
6020 #define RCC_CR_HSIRDY_Pos                    (10U)
6021 #define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
6022 #define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
6023 #define RCC_CR_HSIASFS_Pos                   (11U)
6024 #define RCC_CR_HSIASFS_Msk                   (0x1UL << RCC_CR_HSIASFS_Pos)     /*!< 0x00000800 */
6025 #define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
6026 #define RCC_CR_HSIKERDY_Pos                  (12U)
6027 #define RCC_CR_HSIKERDY_Msk                  (0x1UL << RCC_CR_HSIKERDY_Pos)     /*!< 0x00001000 */
6028 #define RCC_CR_HSIKERDY                       RCC_CR_HSIKERDY_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel ready flag*/
6029 
6030 #define RCC_CR_HSEON_Pos                     (16U)
6031 #define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
6032 #define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
6033 #define RCC_CR_HSERDY_Pos                    (17U)
6034 #define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
6035 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
6036 #define RCC_CR_CSSON_Pos                     (19U)
6037 #define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
6038 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
6039 #define RCC_CR_HSEPRE_Pos                    (20U)
6040 #define RCC_CR_HSEPRE_Msk                    (0x1UL << RCC_CR_HSEPRE_Pos)       /*!< 0x00100000 */
6041 #define RCC_CR_HSEPRE                        RCC_CR_HSEPRE_Msk                  /*!< HSE sysclk prescaler */
6042 
6043 #define RCC_CR_PLLON_Pos                     (24U)
6044 #define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
6045 #define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
6046 #define RCC_CR_PLLRDY_Pos                    (25U)
6047 #define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
6048 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
6049 
6050 /********************  Bit definition for RCC_ICSCR register  ***************/
6051 /*!< MSICAL configuration */
6052 #define RCC_ICSCR_MSICAL_Pos                 (0U)
6053 #define RCC_ICSCR_MSICAL_Msk                 (0xFFUL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x000000FF */
6054 #define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
6055 #define RCC_ICSCR_MSICAL_0                   (0x01U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000001 */
6056 #define RCC_ICSCR_MSICAL_1                   (0x02U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000002 */
6057 #define RCC_ICSCR_MSICAL_2                   (0x04U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000004 */
6058 #define RCC_ICSCR_MSICAL_3                   (0x08U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000008 */
6059 #define RCC_ICSCR_MSICAL_4                   (0x10U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000010 */
6060 #define RCC_ICSCR_MSICAL_5                   (0x20U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000020 */
6061 #define RCC_ICSCR_MSICAL_6                   (0x40U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000040 */
6062 #define RCC_ICSCR_MSICAL_7                   (0x80U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000080 */
6063 
6064 /*!< MSITRIM configuration */
6065 #define RCC_ICSCR_MSITRIM_Pos                (8U)
6066 #define RCC_ICSCR_MSITRIM_Msk                (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
6067 #define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
6068 #define RCC_ICSCR_MSITRIM_0                  (0x01U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000100 */
6069 #define RCC_ICSCR_MSITRIM_1                  (0x02U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000200 */
6070 #define RCC_ICSCR_MSITRIM_2                  (0x04U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000400 */
6071 #define RCC_ICSCR_MSITRIM_3                  (0x08U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000800 */
6072 #define RCC_ICSCR_MSITRIM_4                  (0x10U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00001000 */
6073 #define RCC_ICSCR_MSITRIM_5                  (0x20U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00002000 */
6074 #define RCC_ICSCR_MSITRIM_6                  (0x40U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00004000 */
6075 #define RCC_ICSCR_MSITRIM_7                  (0x80U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00008000 */
6076 
6077 /*!< HSICAL configuration */
6078 #define RCC_ICSCR_HSICAL_Pos                 (16U)
6079 #define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
6080 #define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
6081 #define RCC_ICSCR_HSICAL_0                   (0x01U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00010000 */
6082 #define RCC_ICSCR_HSICAL_1                   (0x02U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00020000 */
6083 #define RCC_ICSCR_HSICAL_2                   (0x04U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00040000 */
6084 #define RCC_ICSCR_HSICAL_3                   (0x08U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00080000 */
6085 #define RCC_ICSCR_HSICAL_4                   (0x10U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00100000 */
6086 #define RCC_ICSCR_HSICAL_5                   (0x20U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00200000 */
6087 #define RCC_ICSCR_HSICAL_6                   (0x40U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00400000 */
6088 #define RCC_ICSCR_HSICAL_7                   (0x80U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00800000 */
6089 
6090 /*!< HSITRIM configuration */
6091 #define RCC_ICSCR_HSITRIM_Pos                (24U)
6092 #define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
6093 #define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
6094 #define RCC_ICSCR_HSITRIM_0                  (0x01U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x01000000 */
6095 #define RCC_ICSCR_HSITRIM_1                  (0x02U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x02000000 */
6096 #define RCC_ICSCR_HSITRIM_2                  (0x04U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x04000000 */
6097 #define RCC_ICSCR_HSITRIM_3                  (0x08U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x08000000 */
6098 #define RCC_ICSCR_HSITRIM_4                  (0x10U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x10000000 */
6099 #define RCC_ICSCR_HSITRIM_5                  (0x20U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x20000000 */
6100 #define RCC_ICSCR_HSITRIM_6                  (0x40U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x40000000 */
6101 
6102 /********************  Bit definition for RCC_CFGR register  ******************/
6103 /*!< SW configuration */
6104 #define RCC_CFGR_SW_Pos                      (0U)
6105 #define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */
6106 #define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
6107 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
6108 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
6109 
6110 /*!< SWS configuration */
6111 #define RCC_CFGR_SWS_Pos                     (2U)
6112 #define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
6113 #define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
6114 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
6115 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
6116 
6117 /*!< HPRE configuration */
6118 #define RCC_CFGR_HPRE_Pos                    (4U)
6119 #define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
6120 #define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
6121 #define RCC_CFGR_HPRE_0                      (0x1U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
6122 #define RCC_CFGR_HPRE_1                      (0x2U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
6123 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
6124 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
6125 
6126 /*!< PPRE1 configuration */
6127 #define RCC_CFGR_PPRE1_Pos                   (8U)
6128 #define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
6129 #define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
6130 #define RCC_CFGR_PPRE1_0                     (0x1U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
6131 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
6132 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
6133 
6134 /*!< PPRE2 configuration */
6135 #define RCC_CFGR_PPRE2_Pos                   (11U)
6136 #define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
6137 #define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
6138 #define RCC_CFGR_PPRE2_0                     (0x1U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
6139 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
6140 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
6141 
6142 /*!< STOPWUCK configuration */
6143 #define RCC_CFGR_STOPWUCK_Pos                (15U)
6144 #define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)  /*!< 0x00008000 */
6145 #define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
6146 
6147 /*!< HPREF configuration */
6148 #define RCC_CFGR_HPREF_Pos                   (16U)
6149 #define RCC_CFGR_HPREF_Msk                   (0x1UL << RCC_CFGR_HPREF_Pos)     /*!< 0x00010000 */
6150 #define RCC_CFGR_HPREF                       RCC_CFGR_HPREF_Msk                /*!< AHB prescaler flag */
6151 
6152 /*!< PPRE1F configuration */
6153 #define RCC_CFGR_PPRE1F_Pos                  (17U)
6154 #define RCC_CFGR_PPRE1F_Msk                  (0x1UL << RCC_CFGR_PPRE1F_Pos)    /*!< 0x00020000 */
6155 #define RCC_CFGR_PPRE1F                      RCC_CFGR_PPRE1F_Msk               /*!< CPU1 APB1 prescaler flag */
6156 
6157 /*!< PPRE2F configuration */
6158 #define RCC_CFGR_PPRE2F_Pos                  (18U)
6159 #define RCC_CFGR_PPRE2F_Msk                  (0x1UL << RCC_CFGR_PPRE2F_Pos)    /*!< 0x00040000 */
6160 #define RCC_CFGR_PPRE2F                      RCC_CFGR_PPRE2F_Msk               /*!< APB2 prescaler flag */
6161 
6162 /*!< MCOSEL configuration */
6163 #define RCC_CFGR_MCOSEL_Pos                  (24U)
6164 #define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x0F000000 */
6165 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
6166 #define RCC_CFGR_MCOSEL_0                    (0x1U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
6167 #define RCC_CFGR_MCOSEL_1                    (0x2U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
6168 #define RCC_CFGR_MCOSEL_2                    (0x4U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
6169 #define RCC_CFGR_MCOSEL_3                    (0x8U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
6170 
6171 /*!< MCOPRE configuration */
6172 #define RCC_CFGR_MCOPRE_Pos                  (28U)
6173 #define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */
6174 #define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
6175 #define RCC_CFGR_MCOPRE_0                    (0x1U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
6176 #define RCC_CFGR_MCOPRE_1                    (0x2U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
6177 #define RCC_CFGR_MCOPRE_2                    (0x4U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
6178 
6179 /********************  Bit definition for RCC_PLLCFGR register  ***************/
6180 #define RCC_PLLCFGR_PLLSRC_Pos               (0U)
6181 #define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
6182 #define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk
6183 #define RCC_PLLCFGR_PLLSRC_0                 (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
6184 #define RCC_PLLCFGR_PLLSRC_1                 (0x2U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
6185 
6186 #define RCC_PLLCFGR_PLLM_Pos                 (4U)
6187 #define RCC_PLLCFGR_PLLM_Msk                 (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
6188 #define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
6189 #define RCC_PLLCFGR_PLLM_0                   (0x1U << RCC_PLLCFGR_PLLM_Pos)  /*!< 0x00000010 */
6190 #define RCC_PLLCFGR_PLLM_1                   (0x2U << RCC_PLLCFGR_PLLM_Pos)  /*!< 0x00000020 */
6191 #define RCC_PLLCFGR_PLLM_2                   (0x4U << RCC_PLLCFGR_PLLM_Pos)  /*!< 0x00000040 */
6192 
6193 #define RCC_PLLCFGR_PLLN_Pos                 (8U)
6194 #define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
6195 #define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk
6196 #define RCC_PLLCFGR_PLLN_0                   (0x01U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
6197 #define RCC_PLLCFGR_PLLN_1                   (0x02U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
6198 #define RCC_PLLCFGR_PLLN_2                   (0x04U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
6199 #define RCC_PLLCFGR_PLLN_3                   (0x08U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
6200 #define RCC_PLLCFGR_PLLN_4                   (0x10U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
6201 #define RCC_PLLCFGR_PLLN_5                   (0x20U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
6202 #define RCC_PLLCFGR_PLLN_6                   (0x40U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
6203 
6204 #define RCC_PLLCFGR_PLLPEN_Pos               (16U)
6205 #define RCC_PLLCFGR_PLLPEN_Msk               (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
6206 #define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk
6207 #define RCC_PLLCFGR_PLLP_Pos                 (17U)
6208 #define RCC_PLLCFGR_PLLP_Msk                 (0x1FUL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x003E0000 */
6209 #define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk
6210 #define RCC_PLLCFGR_PLLP_0                   (0x01U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
6211 #define RCC_PLLCFGR_PLLP_1                   (0x02U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00040000 */
6212 #define RCC_PLLCFGR_PLLP_2                   (0x04U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00080000 */
6213 #define RCC_PLLCFGR_PLLP_3                   (0x08U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00100000 */
6214 #define RCC_PLLCFGR_PLLP_4                   (0x10U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00200000 */
6215 
6216 #define RCC_PLLCFGR_PLLQEN_Pos               (24U)
6217 #define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x01000000 */
6218 #define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk
6219 #define RCC_PLLCFGR_PLLQ_Pos                 (25U)
6220 #define RCC_PLLCFGR_PLLQ_Msk                 (0x7UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0E000000 */
6221 #define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk
6222 #define RCC_PLLCFGR_PLLQ_0                   (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
6223 #define RCC_PLLCFGR_PLLQ_1                   (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
6224 #define RCC_PLLCFGR_PLLQ_2                   (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
6225 
6226 #define RCC_PLLCFGR_PLLREN_Pos               (28U)
6227 #define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x10000000 */
6228 #define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk
6229 #define RCC_PLLCFGR_PLLR_Pos                 (29U)
6230 #define RCC_PLLCFGR_PLLR_Msk                 (0x7UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0xE0000000 */
6231 #define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk
6232 #define RCC_PLLCFGR_PLLR_0                   (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
6233 #define RCC_PLLCFGR_PLLR_1                   (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
6234 #define RCC_PLLCFGR_PLLR_2                   (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x80000000 */
6235 
6236 /********************  Bit definition for RCC_CIER register  ******************/
6237 #define RCC_CIER_LSI1RDYIE_Pos               (0U)
6238 #define RCC_CIER_LSI1RDYIE_Msk               (0x1UL << RCC_CIER_LSI1RDYIE_Pos)  /*!< 0x00000001 */
6239 #define RCC_CIER_LSI1RDYIE                   RCC_CIER_LSI1RDYIE_Msk
6240 #define RCC_CIER_LSERDYIE_Pos                (1U)
6241 #define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)   /*!< 0x00000002 */
6242 #define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk
6243 #define RCC_CIER_MSIRDYIE_Pos                (2U)
6244 #define RCC_CIER_MSIRDYIE_Msk                (0x1UL << RCC_CIER_MSIRDYIE_Pos)   /*!< 0x00000004 */
6245 #define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk
6246 #define RCC_CIER_HSIRDYIE_Pos                (3U)
6247 #define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)   /*!< 0x00000008 */
6248 #define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk
6249 #define RCC_CIER_HSERDYIE_Pos                (4U)
6250 #define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)   /*!< 0x00000010 */
6251 #define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk
6252 #define RCC_CIER_PLLRDYIE_Pos                (5U)
6253 #define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
6254 #define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk
6255 #define RCC_CIER_LSECSSIE_Pos                (9U)
6256 #define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)   /*!< 0x00000200 */
6257 #define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk
6258 #define RCC_CIER_LSI2RDYIE_Pos               (11U)
6259 #define RCC_CIER_LSI2RDYIE_Msk               (0x1UL << RCC_CIER_LSI2RDYIE_Pos)  /*!< 0x00000800 */
6260 #define RCC_CIER_LSI2RDYIE                   RCC_CIER_LSI2RDYIE_Msk
6261 
6262 
6263 /********************  Bit definition for RCC_CIFR register  ******************/
6264 #define RCC_CIFR_LSI1RDYF_Pos                (0U)
6265 #define RCC_CIFR_LSI1RDYF_Msk                (0x1UL << RCC_CIFR_LSI1RDYF_Pos)  /*!< 0x00000001 */
6266 #define RCC_CIFR_LSI1RDYF                    RCC_CIFR_LSI1RDYF_Msk
6267 #define RCC_CIFR_LSERDYF_Pos                 (1U)
6268 #define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */
6269 #define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk
6270 #define RCC_CIFR_MSIRDYF_Pos                 (2U)
6271 #define RCC_CIFR_MSIRDYF_Msk                 (0x1UL << RCC_CIFR_MSIRDYF_Pos)   /*!< 0x00000004 */
6272 #define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk
6273 #define RCC_CIFR_HSIRDYF_Pos                 (3U)
6274 #define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */
6275 #define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk
6276 #define RCC_CIFR_HSERDYF_Pos                 (4U)
6277 #define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */
6278 #define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk
6279 #define RCC_CIFR_PLLRDYF_Pos                 (5U)
6280 #define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
6281 #define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk
6282 #define RCC_CIFR_CSSF_Pos                    (8U)
6283 #define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)   /*!< 0x00000100 */
6284 #define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk
6285 #define RCC_CIFR_LSECSSF_Pos                 (9U)
6286 #define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */
6287 #define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk
6288 #define RCC_CIFR_LSI2RDYF_Pos                (11U)
6289 #define RCC_CIFR_LSI2RDYF_Msk                (0x1UL << RCC_CIFR_LSI2RDYF_Pos)  /*!< 0x00000800 */
6290 #define RCC_CIFR_LSI2RDYF                    RCC_CIFR_LSI2RDYF_Msk
6291 
6292 /********************  Bit definition for RCC_CICR register  ******************/
6293 #define RCC_CICR_LSI1RDYC_Pos               (0U)
6294 #define RCC_CICR_LSI1RDYC_Msk               (0x1UL << RCC_CICR_LSI1RDYC_Pos)  /*!< 0x00000001 */
6295 #define RCC_CICR_LSI1RDYC                   RCC_CICR_LSI1RDYC_Msk
6296 #define RCC_CICR_LSERDYC_Pos                (1U)
6297 #define RCC_CICR_LSERDYC_Msk                (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */
6298 #define RCC_CICR_LSERDYC                    RCC_CICR_LSERDYC_Msk
6299 #define RCC_CICR_MSIRDYC_Pos                (2U)
6300 #define RCC_CICR_MSIRDYC_Msk                (0x1UL << RCC_CICR_MSIRDYC_Pos)   /*!< 0x00000004 */
6301 #define RCC_CICR_MSIRDYC                    RCC_CICR_MSIRDYC_Msk
6302 #define RCC_CICR_HSIRDYC_Pos                (3U)
6303 #define RCC_CICR_HSIRDYC_Msk                (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */
6304 #define RCC_CICR_HSIRDYC                    RCC_CICR_HSIRDYC_Msk
6305 #define RCC_CICR_HSERDYC_Pos                (4U)
6306 #define RCC_CICR_HSERDYC_Msk                (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */
6307 #define RCC_CICR_HSERDYC                    RCC_CICR_HSERDYC_Msk
6308 #define RCC_CICR_PLLRDYC_Pos                (5U)
6309 #define RCC_CICR_PLLRDYC_Msk                (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
6310 #define RCC_CICR_PLLRDYC                    RCC_CICR_PLLRDYC_Msk
6311 #define RCC_CICR_CSSC_Pos                   (8U)
6312 #define RCC_CICR_CSSC_Msk                   (0x1UL << RCC_CICR_CSSC_Pos)   /*!< 0x00000100 */
6313 #define RCC_CICR_CSSC                       RCC_CICR_CSSC_Msk
6314 #define RCC_CICR_LSECSSC_Pos                (9U)
6315 #define RCC_CICR_LSECSSC_Msk                (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */
6316 #define RCC_CICR_LSECSSC                    RCC_CICR_LSECSSC_Msk
6317 #define RCC_CICR_LSI2RDYC_Pos               (11U)
6318 #define RCC_CICR_LSI2RDYC_Msk               (0x1UL << RCC_CICR_LSI2RDYC_Pos)  /*!< 0x00000800 */
6319 #define RCC_CICR_LSI2RDYC                   RCC_CICR_LSI2RDYC_Msk
6320 
6321 /********************  Bit definition for RCC_SMPSCR register  ******************/
6322 #define RCC_SMPSCR_SMPSSEL_Pos               (0U)
6323 #define RCC_SMPSCR_SMPSSEL_Msk               (0x3UL << RCC_SMPSCR_SMPSSEL_Pos)  /*!< 0x00000003 */
6324 #define RCC_SMPSCR_SMPSSEL                   RCC_SMPSCR_SMPSSEL_Msk
6325 #define RCC_SMPSCR_SMPSSEL_0                 (0x1U << RCC_SMPSCR_SMPSSEL_Pos)   /*!< 0x00000001 */
6326 #define RCC_SMPSCR_SMPSSEL_1                 (0x2U << RCC_SMPSCR_SMPSSEL_Pos)   /*!< 0x00000002 */
6327 
6328 #define RCC_SMPSCR_SMPSDIV_Pos               (4U)
6329 #define RCC_SMPSCR_SMPSDIV_Msk               (0x3UL << RCC_SMPSCR_SMPSDIV_Pos)  /*!< 0x00000030 */
6330 #define RCC_SMPSCR_SMPSDIV                   RCC_SMPSCR_SMPSDIV_Msk
6331 #define RCC_SMPSCR_SMPSDIV_0                 (0x1U << RCC_SMPSCR_SMPSDIV_Pos)   /*!< 0x00000010 */
6332 #define RCC_SMPSCR_SMPSDIV_1                 (0x2U << RCC_SMPSCR_SMPSDIV_Pos)   /*!< 0x00000020 */
6333 
6334 #define RCC_SMPSCR_SMPSSWS_Pos               (8U)
6335 #define RCC_SMPSCR_SMPSSWS_Msk               (0x3UL << RCC_SMPSCR_SMPSSWS_Pos)  /*!< 0x00000300 */
6336 #define RCC_SMPSCR_SMPSSWS                   RCC_SMPSCR_SMPSSWS_Msk
6337 #define RCC_SMPSCR_SMPSSWS_0                 (0x1U << RCC_SMPSCR_SMPSSWS_Pos)   /*!< 0x00000100 */
6338 #define RCC_SMPSCR_SMPSSWS_1                 (0x2U << RCC_SMPSCR_SMPSSWS_Pos)   /*!< 0x00000200 */
6339 
6340 /********************  Bit definition for RCC_AHB1RSTR register  **************/
6341 #define RCC_AHB1RSTR_DMA1RST_Pos             (0U)
6342 #define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
6343 #define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk
6344 #define RCC_AHB1RSTR_DMAMUX1RST_Pos          (2U)
6345 #define RCC_AHB1RSTR_DMAMUX1RST_Msk          (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos) /*!< 0x00000004 */
6346 #define RCC_AHB1RSTR_DMAMUX1RST              RCC_AHB1RSTR_DMAMUX1RST_Msk
6347 #define RCC_AHB1RSTR_CRCRST_Pos              (12U)
6348 #define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
6349 #define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk
6350 #define RCC_AHB1RSTR_TSCRST_Pos              (16U)
6351 #define RCC_AHB1RSTR_TSCRST_Msk              (0x1UL << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
6352 #define RCC_AHB1RSTR_TSCRST                  RCC_AHB1RSTR_TSCRST_Msk
6353 
6354 /********************  Bit definition for RCC_AHB2RSTR register  ***************/
6355 #define RCC_AHB2RSTR_GPIOARST_Pos           (0U)
6356 #define RCC_AHB2RSTR_GPIOARST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
6357 #define RCC_AHB2RSTR_GPIOARST               RCC_AHB2RSTR_GPIOARST_Msk
6358 #define RCC_AHB2RSTR_GPIOBRST_Pos           (1U)
6359 #define RCC_AHB2RSTR_GPIOBRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
6360 #define RCC_AHB2RSTR_GPIOBRST               RCC_AHB2RSTR_GPIOBRST_Msk
6361 #define RCC_AHB2RSTR_GPIOCRST_Pos           (2U)
6362 #define RCC_AHB2RSTR_GPIOCRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
6363 #define RCC_AHB2RSTR_GPIOCRST               RCC_AHB2RSTR_GPIOCRST_Msk
6364 #define RCC_AHB2RSTR_GPIOERST_Pos           (4U)
6365 #define RCC_AHB2RSTR_GPIOERST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
6366 #define RCC_AHB2RSTR_GPIOERST               RCC_AHB2RSTR_GPIOERST_Msk
6367 #define RCC_AHB2RSTR_GPIOHRST_Pos           (7U)
6368 #define RCC_AHB2RSTR_GPIOHRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
6369 #define RCC_AHB2RSTR_GPIOHRST               RCC_AHB2RSTR_GPIOHRST_Msk
6370 
6371 /********************  Bit definition for RCC_AHB3RSTR register  ***************/
6372 #define RCC_AHB3RSTR_PKARST_Pos             (16U)
6373 #define RCC_AHB3RSTR_PKARST_Msk             (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00010000 */
6374 #define RCC_AHB3RSTR_PKARST                 RCC_AHB3RSTR_PKARST_Msk
6375 #define RCC_AHB3RSTR_AES2RST_Pos            (17U)
6376 #define RCC_AHB3RSTR_AES2RST_Msk            (0x1UL << RCC_AHB3RSTR_AES2RST_Pos) /*!< 0x00020000 */
6377 #define RCC_AHB3RSTR_AES2RST                RCC_AHB3RSTR_AES2RST_Msk
6378 #define RCC_AHB3RSTR_RNGRST_Pos             (18U)
6379 #define RCC_AHB3RSTR_RNGRST_Msk             (0x1UL << RCC_AHB3RSTR_RNGRST_Pos) /*!< 0x00040000 */
6380 #define RCC_AHB3RSTR_RNGRST                 RCC_AHB3RSTR_RNGRST_Msk
6381 #define RCC_AHB3RSTR_HSEMRST_Pos            (19U)
6382 #define RCC_AHB3RSTR_HSEMRST_Msk            (0x1UL << RCC_AHB3RSTR_HSEMRST_Pos) /*!< 0x00080000 */
6383 #define RCC_AHB3RSTR_HSEMRST                RCC_AHB3RSTR_HSEMRST_Msk
6384 #define RCC_AHB3RSTR_IPCCRST_Pos            (20U)
6385 #define RCC_AHB3RSTR_IPCCRST_Msk            (0x1UL << RCC_AHB3RSTR_IPCCRST_Pos) /*!< 0x00100000 */
6386 #define RCC_AHB3RSTR_IPCCRST                RCC_AHB3RSTR_IPCCRST_Msk
6387 #define RCC_AHB3RSTR_FLASHRST_Pos           (25U)
6388 #define RCC_AHB3RSTR_FLASHRST_Msk           (0x1UL << RCC_AHB3RSTR_FLASHRST_Pos) /*!< 0x02000000 */
6389 #define RCC_AHB3RSTR_FLASHRST               RCC_AHB3RSTR_FLASHRST_Msk
6390 
6391 /********************  Bit definition for RCC_APB1RSTR1 register  **************/
6392 #define RCC_APB1RSTR1_TIM2RST_Pos           (0U)
6393 #define RCC_APB1RSTR1_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
6394 #define RCC_APB1RSTR1_TIM2RST               RCC_APB1RSTR1_TIM2RST_Msk
6395 #define RCC_APB1RSTR1_I2C1RST_Pos           (21U)
6396 #define RCC_APB1RSTR1_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
6397 #define RCC_APB1RSTR1_I2C1RST               RCC_APB1RSTR1_I2C1RST_Msk
6398 #define RCC_APB1RSTR1_LPTIM1RST_Pos         (31U)
6399 #define RCC_APB1RSTR1_LPTIM1RST_Msk         (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
6400 #define RCC_APB1RSTR1_LPTIM1RST             RCC_APB1RSTR1_LPTIM1RST_Msk
6401 
6402 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
6403 #define RCC_APB1RSTR2_LPUART1RST_Pos        (0U)
6404 #define RCC_APB1RSTR2_LPUART1RST_Msk        (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
6405 #define RCC_APB1RSTR2_LPUART1RST            RCC_APB1RSTR2_LPUART1RST_Msk
6406 #define RCC_APB1RSTR2_LPTIM2RST_Pos         (5U)
6407 #define RCC_APB1RSTR2_LPTIM2RST_Msk         (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
6408 #define RCC_APB1RSTR2_LPTIM2RST             RCC_APB1RSTR2_LPTIM2RST_Msk
6409 
6410 /********************  Bit definition for RCC_APB2RSTR register  **************/
6411 #define RCC_APB2RSTR_ADCRST_Pos             (9U)
6412 #define RCC_APB2RSTR_ADCRST_Msk             (0x1UL << RCC_APB2RSTR_ADCRST_Pos)    /*!< 0x00000200 */
6413 #define RCC_APB2RSTR_ADCRST                 RCC_APB2RSTR_ADCRST_Msk
6414 #define RCC_APB2RSTR_TIM1RST_Pos            (11U)
6415 #define RCC_APB2RSTR_TIM1RST_Msk            (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)   /*!< 0x00000800 */
6416 #define RCC_APB2RSTR_TIM1RST                RCC_APB2RSTR_TIM1RST_Msk
6417 #define RCC_APB2RSTR_SPI1RST_Pos            (12U)
6418 #define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)   /*!< 0x00001000 */
6419 #define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk
6420 #define RCC_APB2RSTR_USART1RST_Pos          (14U)
6421 #define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
6422 #define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk
6423 
6424 /********************  Bit definition for RCC_APB3RSTR register  **************/
6425 #define RCC_APB3RSTR_RFRST_Pos             (0U)
6426 #define RCC_APB3RSTR_RFRST_Msk             (0x1UL << RCC_APB3RSTR_RFRST_Pos) /*!< 0x00000001 */
6427 #define RCC_APB3RSTR_RFRST                 RCC_APB3RSTR_RFRST_Msk
6428 
6429 /********************  Bit definition for RCC_AHB1ENR register  ****************/
6430 #define RCC_AHB1ENR_DMA1EN_Pos              (0U)
6431 #define RCC_AHB1ENR_DMA1EN_Msk              (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)  /*!< 0x00000001 */
6432 #define RCC_AHB1ENR_DMA1EN                  RCC_AHB1ENR_DMA1EN_Msk
6433 #define RCC_AHB1ENR_DMAMUX1EN_Pos           (2U)
6434 #define RCC_AHB1ENR_DMAMUX1EN_Msk           (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos) /*!< 0x00000004 */
6435 #define RCC_AHB1ENR_DMAMUX1EN               RCC_AHB1ENR_DMAMUX1EN_Msk
6436 #define RCC_AHB1ENR_CRCEN_Pos               (12U)
6437 #define RCC_AHB1ENR_CRCEN_Msk               (0x1UL << RCC_AHB1ENR_CRCEN_Pos)   /*!< 0x00001000 */
6438 #define RCC_AHB1ENR_CRCEN                   RCC_AHB1ENR_CRCEN_Msk
6439 #define RCC_AHB1ENR_TSCEN_Pos               (16U)
6440 #define RCC_AHB1ENR_TSCEN_Msk               (0x1UL << RCC_AHB1ENR_TSCEN_Pos)   /*!< 0x00010000 */
6441 #define RCC_AHB1ENR_TSCEN                   RCC_AHB1ENR_TSCEN_Msk
6442 
6443 /********************  Bit definition for RCC_AHB2ENR register  ***************/
6444 #define RCC_AHB2ENR_GPIOAEN_Pos             (0U)
6445 #define RCC_AHB2ENR_GPIOAEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
6446 #define RCC_AHB2ENR_GPIOAEN                 RCC_AHB2ENR_GPIOAEN_Msk
6447 #define RCC_AHB2ENR_GPIOBEN_Pos             (1U)
6448 #define RCC_AHB2ENR_GPIOBEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
6449 #define RCC_AHB2ENR_GPIOBEN                 RCC_AHB2ENR_GPIOBEN_Msk
6450 #define RCC_AHB2ENR_GPIOCEN_Pos             (2U)
6451 #define RCC_AHB2ENR_GPIOCEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
6452 #define RCC_AHB2ENR_GPIOCEN                 RCC_AHB2ENR_GPIOCEN_Msk
6453 #define RCC_AHB2ENR_GPIOEEN_Pos             (4U)
6454 #define RCC_AHB2ENR_GPIOEEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
6455 #define RCC_AHB2ENR_GPIOEEN                 RCC_AHB2ENR_GPIOEEN_Msk
6456 #define RCC_AHB2ENR_GPIOHEN_Pos             (7U)
6457 #define RCC_AHB2ENR_GPIOHEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
6458 #define RCC_AHB2ENR_GPIOHEN                 RCC_AHB2ENR_GPIOHEN_Msk
6459 
6460 /********************  Bit definition for RCC_AHB3ENR register  ***************/
6461 #define RCC_AHB3ENR_PKAEN_Pos               (16U)
6462 #define RCC_AHB3ENR_PKAEN_Msk               (0x1UL << RCC_AHB3ENR_PKAEN_Pos)   /*!< 0x00010000 */
6463 #define RCC_AHB3ENR_PKAEN                   RCC_AHB3ENR_PKAEN_Msk
6464 #define RCC_AHB3ENR_AES2EN_Pos              (17U)
6465 #define RCC_AHB3ENR_AES2EN_Msk              (0x1UL << RCC_AHB3ENR_AES2EN_Pos) /*!< 0x00020000 */
6466 #define RCC_AHB3ENR_AES2EN                  RCC_AHB3ENR_AES2EN_Msk
6467 #define RCC_AHB3ENR_RNGEN_Pos               (18U)
6468 #define RCC_AHB3ENR_RNGEN_Msk               (0x1UL << RCC_AHB3ENR_RNGEN_Pos)  /*!< 0x00040000 */
6469 #define RCC_AHB3ENR_RNGEN                   RCC_AHB3ENR_RNGEN_Msk
6470 #define RCC_AHB3ENR_HSEMEN_Pos              (19U)
6471 #define RCC_AHB3ENR_HSEMEN_Msk              (0x1UL << RCC_AHB3ENR_HSEMEN_Pos)  /*!< 0x00080000 */
6472 #define RCC_AHB3ENR_HSEMEN                  RCC_AHB3ENR_HSEMEN_Msk
6473 #define RCC_AHB3ENR_IPCCEN_Pos              (20U)
6474 #define RCC_AHB3ENR_IPCCEN_Msk              (0x1UL << RCC_AHB3ENR_IPCCEN_Pos)  /*!< 0x00100000 */
6475 #define RCC_AHB3ENR_IPCCEN                  RCC_AHB3ENR_IPCCEN_Msk
6476 #define RCC_AHB3ENR_FLASHEN_Pos             (25U)
6477 #define RCC_AHB3ENR_FLASHEN_Msk             (0x1UL << RCC_AHB3ENR_FLASHEN_Pos)   /*!< 0x02000000 */
6478 #define RCC_AHB3ENR_FLASHEN                 RCC_AHB3ENR_FLASHEN_Msk
6479 
6480 /********************  Bit definition for RCC_APB1ENR1 register  **************/
6481 #define RCC_APB1ENR1_TIM2EN_Pos             (0U)
6482 #define RCC_APB1ENR1_TIM2EN_Msk             (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
6483 #define RCC_APB1ENR1_TIM2EN                 RCC_APB1ENR1_TIM2EN_Msk
6484 #define RCC_APB1ENR1_RTCAPBEN_Pos           (10U)
6485 #define RCC_APB1ENR1_RTCAPBEN_Msk           (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
6486 #define RCC_APB1ENR1_RTCAPBEN               RCC_APB1ENR1_RTCAPBEN_Msk
6487 #define RCC_APB1ENR1_WWDGEN_Pos             (11U)
6488 #define RCC_APB1ENR1_WWDGEN_Msk             (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
6489 #define RCC_APB1ENR1_WWDGEN                 RCC_APB1ENR1_WWDGEN_Msk
6490 #define RCC_APB1ENR1_I2C1EN_Pos             (21U)
6491 #define RCC_APB1ENR1_I2C1EN_Msk             (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
6492 #define RCC_APB1ENR1_I2C1EN                 RCC_APB1ENR1_I2C1EN_Msk
6493 #define RCC_APB1ENR1_LPTIM1EN_Pos           (31U)
6494 #define RCC_APB1ENR1_LPTIM1EN_Msk           (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
6495 #define RCC_APB1ENR1_LPTIM1EN               RCC_APB1ENR1_LPTIM1EN_Msk
6496 
6497 /********************  Bit definition for RCC_APB1ENR2 register  **************/
6498 #define RCC_APB1ENR2_LPUART1EN_Pos          (0U)
6499 #define RCC_APB1ENR2_LPUART1EN_Msk         (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
6500 #define RCC_APB1ENR2_LPUART1EN              RCC_APB1ENR2_LPUART1EN_Msk
6501 #define RCC_APB1ENR2_LPTIM2EN_Pos           (5U)
6502 #define RCC_APB1ENR2_LPTIM2EN_Msk           (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
6503 #define RCC_APB1ENR2_LPTIM2EN               RCC_APB1ENR2_LPTIM2EN_Msk
6504 
6505 /********************  Bit definition for RCC_APB2ENR register  **************/
6506 #define RCC_APB2ENR_ADCEN_Pos               (9U)
6507 #define RCC_APB2ENR_ADCEN_Msk               (0x1UL << RCC_APB2ENR_ADCEN_Pos)    /*!< 0x00000200 */
6508 #define RCC_APB2ENR_ADCEN                   RCC_APB2ENR_ADCEN_Msk
6509 #define RCC_APB2ENR_TIM1EN_Pos              (11U)
6510 #define RCC_APB2ENR_TIM1EN_Msk              (0x1UL << RCC_APB2ENR_TIM1EN_Pos)   /*!< 0x00000800 */
6511 #define RCC_APB2ENR_TIM1EN                  RCC_APB2ENR_TIM1EN_Msk
6512 #define RCC_APB2ENR_SPI1EN_Pos              (12U)
6513 #define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
6514 #define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk
6515 #define RCC_APB2ENR_USART1EN_Pos            (14U)
6516 #define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
6517 #define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk
6518 
6519 /********************  Bit definition for RCC_AHB1SMENR register  ****************/
6520 #define RCC_AHB1SMENR_DMA1SMEN_Pos          (0U)
6521 #define RCC_AHB1SMENR_DMA1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
6522 #define RCC_AHB1SMENR_DMA1SMEN              RCC_AHB1SMENR_DMA1SMEN_Msk
6523 #define RCC_AHB1SMENR_DMAMUX1SMEN_Pos       (2U)
6524 #define RCC_AHB1SMENR_DMAMUX1SMEN_Msk       (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos) /*!< 0x00000004 */
6525 #define RCC_AHB1SMENR_DMAMUX1SMEN           RCC_AHB1SMENR_DMAMUX1SMEN_Msk
6526 #define RCC_AHB1SMENR_SRAM1SMEN_Pos         (9U)
6527 #define RCC_AHB1SMENR_SRAM1SMEN_Msk         (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
6528 #define RCC_AHB1SMENR_SRAM1SMEN             RCC_AHB1SMENR_SRAM1SMEN_Msk
6529 #define RCC_AHB1SMENR_CRCSMEN_Pos           (12U)
6530 #define RCC_AHB1SMENR_CRCSMEN_Msk           (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
6531 #define RCC_AHB1SMENR_CRCSMEN               RCC_AHB1SMENR_CRCSMEN_Msk
6532 #define RCC_AHB1SMENR_TSCSMEN_Pos           (16U)
6533 #define RCC_AHB1SMENR_TSCSMEN_Msk           (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
6534 #define RCC_AHB1SMENR_TSCSMEN               RCC_AHB1SMENR_TSCSMEN_Msk
6535 
6536 /********************  Bit definition for RCC_AHB2SMENR register  ***************/
6537 #define RCC_AHB2SMENR_GPIOASMEN_Pos         (0U)
6538 #define RCC_AHB2SMENR_GPIOASMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
6539 #define RCC_AHB2SMENR_GPIOASMEN             RCC_AHB2SMENR_GPIOASMEN_Msk
6540 #define RCC_AHB2SMENR_GPIOBSMEN_Pos         (1U)
6541 #define RCC_AHB2SMENR_GPIOBSMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
6542 #define RCC_AHB2SMENR_GPIOBSMEN             RCC_AHB2SMENR_GPIOBSMEN_Msk
6543 #define RCC_AHB2SMENR_GPIOCSMEN_Pos         (2U)
6544 #define RCC_AHB2SMENR_GPIOCSMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
6545 #define RCC_AHB2SMENR_GPIOCSMEN             RCC_AHB2SMENR_GPIOCSMEN_Msk
6546 #define RCC_AHB2SMENR_GPIOESMEN_Pos         (4U)
6547 #define RCC_AHB2SMENR_GPIOESMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
6548 #define RCC_AHB2SMENR_GPIOESMEN             RCC_AHB2SMENR_GPIOESMEN_Msk
6549 #define RCC_AHB2SMENR_GPIOHSMEN_Pos         (7U)
6550 #define RCC_AHB2SMENR_GPIOHSMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
6551 #define RCC_AHB2SMENR_GPIOHSMEN             RCC_AHB2SMENR_GPIOHSMEN_Msk
6552 
6553 /********************  Bit definition for RCC_AHB3SMENR register  ***************/
6554 #define RCC_AHB3SMENR_PKASMEN_Pos           (16U)
6555 #define RCC_AHB3SMENR_PKASMEN_Msk           (0x1UL << RCC_AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */
6556 #define RCC_AHB3SMENR_PKASMEN               RCC_AHB3SMENR_PKASMEN_Msk
6557 #define RCC_AHB3SMENR_AES2SMEN_Pos          (17U)
6558 #define RCC_AHB3SMENR_AES2SMEN_Msk          (0x1UL << RCC_AHB3SMENR_AES2SMEN_Pos) /*!< 0x00020000 */
6559 #define RCC_AHB3SMENR_AES2SMEN              RCC_AHB3SMENR_AES2SMEN_Msk
6560 #define RCC_AHB3SMENR_RNGSMEN_Pos           (18U)
6561 #define RCC_AHB3SMENR_RNGSMEN_Msk           (0x1UL << RCC_AHB3SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
6562 #define RCC_AHB3SMENR_RNGSMEN                RCC_AHB3SMENR_RNGSMEN_Msk
6563 #define RCC_AHB3SMENR_SRAM2SMEN_Pos         (24U)
6564 #define RCC_AHB3SMENR_SRAM2SMEN_Msk         (0x1UL << RCC_AHB3SMENR_SRAM2SMEN_Pos) /*!< 0x01000000 */
6565 #define RCC_AHB3SMENR_SRAM2SMEN             RCC_AHB3SMENR_SRAM2SMEN_Msk
6566 #define RCC_AHB3SMENR_FLASHSMEN_Pos         (25U)
6567 #define RCC_AHB3SMENR_FLASHSMEN_Msk         (0x1UL << RCC_AHB3SMENR_FLASHSMEN_Pos) /*!< 0x02000000 */
6568 #define RCC_AHB3SMENR_FLASHSMEN             RCC_AHB3SMENR_FLASHSMEN_Msk
6569 
6570 /********************  Bit definition for RCC_APB1SMENR1 register  **************/
6571 #define RCC_APB1SMENR1_TIM2SMEN_Pos         (0U)
6572 #define RCC_APB1SMENR1_TIM2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
6573 #define RCC_APB1SMENR1_TIM2SMEN             RCC_APB1SMENR1_TIM2SMEN_Msk
6574 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos       (10U)
6575 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk       (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
6576 #define RCC_APB1SMENR1_RTCAPBSMEN           RCC_APB1SMENR1_RTCAPBSMEN_Msk
6577 #define RCC_APB1SMENR1_WWDGSMEN_Pos         (11U)
6578 #define RCC_APB1SMENR1_WWDGSMEN_Msk         (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
6579 #define RCC_APB1SMENR1_WWDGSMEN             RCC_APB1SMENR1_WWDGSMEN_Msk
6580 #define RCC_APB1SMENR1_I2C1SMEN_Pos         (21U)
6581 #define RCC_APB1SMENR1_I2C1SMEN_Msk         (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
6582 #define RCC_APB1SMENR1_I2C1SMEN             RCC_APB1SMENR1_I2C1SMEN_Msk
6583 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos       (31U)
6584 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk       (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
6585 #define RCC_APB1SMENR1_LPTIM1SMEN           RCC_APB1SMENR1_LPTIM1SMEN_Msk
6586 
6587 /********************  Bit definition for RCC_APB1SMENR2 register  **************/
6588 #define RCC_APB1SMENR2_LPUART1SMEN_Pos      (0U)
6589 #define RCC_APB1SMENR2_LPUART1SMEN_Msk      (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
6590 #define RCC_APB1SMENR2_LPUART1SMEN          RCC_APB1SMENR2_LPUART1SMEN_Msk
6591 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos       (5U)
6592 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
6593 #define RCC_APB1SMENR2_LPTIM2SMEN           RCC_APB1SMENR2_LPTIM2SMEN_Msk
6594 
6595 /********************  Bit definition for RCC_APB2SMENR register  **************/
6596 #define RCC_APB2SMENR_ADCSMEN_Pos           (9U)
6597 #define RCC_APB2SMENR_ADCSMEN_Msk           (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)    /*!< 0x00000200 */
6598 #define RCC_APB2SMENR_ADCSMEN               RCC_APB2SMENR_ADCSMEN_Msk
6599 #define RCC_APB2SMENR_TIM1SMEN_Pos          (11U)
6600 #define RCC_APB2SMENR_TIM1SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)   /*!< 0x00000800 */
6601 #define RCC_APB2SMENR_TIM1SMEN              RCC_APB2SMENR_TIM1SMEN_Msk
6602 #define RCC_APB2SMENR_SPI1SMEN_Pos          (12U)
6603 #define RCC_APB2SMENR_SPI1SMEN_Msk          (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)   /*!< 0x00001000 */
6604 #define RCC_APB2SMENR_SPI1SMEN              RCC_APB2SMENR_SPI1SMEN_Msk
6605 #define RCC_APB2SMENR_USART1SMEN_Pos        (14U)
6606 #define RCC_APB2SMENR_USART1SMEN_Msk        (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
6607 #define RCC_APB2SMENR_USART1SMEN            RCC_APB2SMENR_USART1SMEN_Msk
6608 
6609 /********************  Bit definition for RCC_CCIPR register  ******************/
6610 #define RCC_CCIPR_USART1SEL_Pos             (0U)
6611 #define RCC_CCIPR_USART1SEL_Msk             (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
6612 #define RCC_CCIPR_USART1SEL                 RCC_CCIPR_USART1SEL_Msk
6613 #define RCC_CCIPR_USART1SEL_0               (0x1U << RCC_CCIPR_USART1SEL_Pos)  /*!< 0x00000001 */
6614 #define RCC_CCIPR_USART1SEL_1               (0x2U << RCC_CCIPR_USART1SEL_Pos)  /*!< 0x00000002 */
6615 
6616 #define RCC_CCIPR_LPUART1SEL_Pos            (10U)
6617 #define RCC_CCIPR_LPUART1SEL_Msk            (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
6618 #define RCC_CCIPR_LPUART1SEL                RCC_CCIPR_LPUART1SEL_Msk
6619 #define RCC_CCIPR_LPUART1SEL_0              (0x1U << RCC_CCIPR_LPUART1SEL_Pos)  /*!< 0x00000400 */
6620 #define RCC_CCIPR_LPUART1SEL_1              (0x2U << RCC_CCIPR_LPUART1SEL_Pos)  /*!< 0x00000800 */
6621 
6622 #define RCC_CCIPR_I2C1SEL_Pos               (12U)
6623 #define RCC_CCIPR_I2C1SEL_Msk               (0x3UL << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00003000 */
6624 #define RCC_CCIPR_I2C1SEL                   RCC_CCIPR_I2C1SEL_Msk
6625 #define RCC_CCIPR_I2C1SEL_0                 (0x1U << RCC_CCIPR_I2C1SEL_Pos)    /*!< 0x00001000 */
6626 #define RCC_CCIPR_I2C1SEL_1                 (0x2U << RCC_CCIPR_I2C1SEL_Pos)    /*!< 0x00002000 */
6627 
6628 #define RCC_CCIPR_LPTIM1SEL_Pos             (18U)
6629 #define RCC_CCIPR_LPTIM1SEL_Msk             (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
6630 #define RCC_CCIPR_LPTIM1SEL                 RCC_CCIPR_LPTIM1SEL_Msk
6631 #define RCC_CCIPR_LPTIM1SEL_0               (0x1U << RCC_CCIPR_LPTIM1SEL_Pos)  /*!< 0x00040000 */
6632 #define RCC_CCIPR_LPTIM1SEL_1               (0x2U << RCC_CCIPR_LPTIM1SEL_Pos)  /*!< 0x00080000 */
6633 
6634 #define RCC_CCIPR_LPTIM2SEL_Pos             (20U)
6635 #define RCC_CCIPR_LPTIM2SEL_Msk             (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
6636 #define RCC_CCIPR_LPTIM2SEL                 RCC_CCIPR_LPTIM2SEL_Msk
6637 #define RCC_CCIPR_LPTIM2SEL_0               (0x1U << RCC_CCIPR_LPTIM2SEL_Pos)  /*!< 0x00100000 */
6638 #define RCC_CCIPR_LPTIM2SEL_1               (0x2U << RCC_CCIPR_LPTIM2SEL_Pos)  /*!< 0x00200000 */
6639 
6640 #define RCC_CCIPR_CLK48SEL_Pos              (26U)
6641 #define RCC_CCIPR_CLK48SEL_Msk              (0x3UL << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x0C000000 */
6642 #define RCC_CCIPR_CLK48SEL                  RCC_CCIPR_CLK48SEL_Msk
6643 #define RCC_CCIPR_CLK48SEL_0                (0x1U << RCC_CCIPR_CLK48SEL_Pos)   /*!< 0x04000000 */
6644 #define RCC_CCIPR_CLK48SEL_1                (0x2U << RCC_CCIPR_CLK48SEL_Pos)   /*!< 0x08000000 */
6645 
6646 #define RCC_CCIPR_ADCSEL_Pos                (28U)
6647 #define RCC_CCIPR_ADCSEL_Msk                (0x3UL << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x30000000 */
6648 #define RCC_CCIPR_ADCSEL                    RCC_CCIPR_ADCSEL_Msk
6649 #define RCC_CCIPR_ADCSEL_0                  (0x1U << RCC_CCIPR_ADCSEL_Pos)     /*!< 0x10000000 */
6650 #define RCC_CCIPR_ADCSEL_1                  (0x2U << RCC_CCIPR_ADCSEL_Pos)     /*!< 0x20000000 */
6651 
6652 #define RCC_CCIPR_RNGSEL_Pos                (30U)
6653 #define RCC_CCIPR_RNGSEL_Msk                (0x3UL << RCC_CCIPR_RNGSEL_Pos)    /*!< 0xC0000000 */
6654 #define RCC_CCIPR_RNGSEL                    RCC_CCIPR_RNGSEL_Msk
6655 #define RCC_CCIPR_RNGSEL_0                  (0x1U << RCC_CCIPR_RNGSEL_Pos)     /*!< 0x40000000 */
6656 #define RCC_CCIPR_RNGSEL_1                  (0x2U << RCC_CCIPR_RNGSEL_Pos)     /*!< 0x80000000 */
6657 
6658 /********************  Bit definition for RCC_BDCR register  ******************/
6659 #define RCC_BDCR_LSEON_Pos                  (0U)
6660 #define RCC_BDCR_LSEON_Msk                  (0x1UL << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
6661 #define RCC_BDCR_LSEON                      RCC_BDCR_LSEON_Msk
6662 #define RCC_BDCR_LSERDY_Pos                 (1U)
6663 #define RCC_BDCR_LSERDY_Msk                 (0x1UL << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
6664 #define RCC_BDCR_LSERDY                     RCC_BDCR_LSERDY_Msk
6665 #define RCC_BDCR_LSEBYP_Pos                 (2U)
6666 #define RCC_BDCR_LSEBYP_Msk                 (0x1UL << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
6667 #define RCC_BDCR_LSEBYP                     RCC_BDCR_LSEBYP_Msk
6668 
6669 #define RCC_BDCR_LSEDRV_Pos                 (3U)
6670 #define RCC_BDCR_LSEDRV_Msk                 (0x3UL << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000018 */
6671 #define RCC_BDCR_LSEDRV                     RCC_BDCR_LSEDRV_Msk
6672 #define RCC_BDCR_LSEDRV_0                   (0x1U << RCC_BDCR_LSEDRV_Pos)      /*!< 0x00000008 */
6673 #define RCC_BDCR_LSEDRV_1                   (0x2U << RCC_BDCR_LSEDRV_Pos)      /*!< 0x00000010 */
6674 
6675 #define RCC_BDCR_LSECSSON_Pos               (5U)
6676 #define RCC_BDCR_LSECSSON_Msk               (0x1UL << RCC_BDCR_LSECSSON_Pos)   /*!< 0x00000020 */
6677 #define RCC_BDCR_LSECSSON                   RCC_BDCR_LSECSSON_Msk
6678 #define RCC_BDCR_LSECSSD_Pos                (6U)
6679 #define RCC_BDCR_LSECSSD_Msk                (0x1UL << RCC_BDCR_LSECSSD_Pos)    /*!< 0x00000040 */
6680 #define RCC_BDCR_LSECSSD                    RCC_BDCR_LSECSSD_Msk
6681 
6682 #define RCC_BDCR_RTCSEL_Pos                 (8U)
6683 #define RCC_BDCR_RTCSEL_Msk                 (0x3UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
6684 #define RCC_BDCR_RTCSEL                     RCC_BDCR_RTCSEL_Msk
6685 #define RCC_BDCR_RTCSEL_0                   (0x1U << RCC_BDCR_RTCSEL_Pos)      /*!< 0x00000100 */
6686 #define RCC_BDCR_RTCSEL_1                   (0x2U << RCC_BDCR_RTCSEL_Pos)      /*!< 0x00000200 */
6687 
6688 #define RCC_BDCR_RTCEN_Pos                  (15U)
6689 #define RCC_BDCR_RTCEN_Msk                  (0x1UL << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
6690 #define RCC_BDCR_RTCEN                      RCC_BDCR_RTCEN_Msk
6691 
6692 #define RCC_BDCR_BDRST_Pos                  (16U)
6693 #define RCC_BDCR_BDRST_Msk                  (0x1UL << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
6694 #define RCC_BDCR_BDRST                      RCC_BDCR_BDRST_Msk
6695 
6696 #define RCC_BDCR_LSCOEN_Pos                 (24U)
6697 #define RCC_BDCR_LSCOEN_Msk                 (0x1UL << RCC_BDCR_LSCOEN_Pos)     /*!< 0x01000000 */
6698 #define RCC_BDCR_LSCOEN                     RCC_BDCR_LSCOEN_Msk
6699 #define RCC_BDCR_LSCOSEL_Pos                (25U)
6700 #define RCC_BDCR_LSCOSEL_Msk                (0x1UL << RCC_BDCR_LSCOSEL_Pos)    /*!< 0x02000000 */
6701 #define RCC_BDCR_LSCOSEL                    RCC_BDCR_LSCOSEL_Msk
6702 
6703 /********************  Bit definition for RCC_CSR register  *******************/
6704 #define RCC_CSR_LSI1ON_Pos                  (0U)
6705 #define RCC_CSR_LSI1ON_Msk                  (0x1UL << RCC_CSR_LSI1ON_Pos)      /*!< 0x00000001 */
6706 #define RCC_CSR_LSI1ON                      RCC_CSR_LSI1ON_Msk
6707 #define RCC_CSR_LSI1RDY_Pos                 (1U)
6708 #define RCC_CSR_LSI1RDY_Msk                 (0x1UL << RCC_CSR_LSI1RDY_Pos)     /*!< 0x00000002 */
6709 #define RCC_CSR_LSI1RDY                     RCC_CSR_LSI1RDY_Msk
6710 #define RCC_CSR_LSI2ON_Pos                  (2U)
6711 #define RCC_CSR_LSI2ON_Msk                  (0x1UL << RCC_CSR_LSI2ON_Pos)      /*!< 0x00000004 */
6712 #define RCC_CSR_LSI2ON                      RCC_CSR_LSI2ON_Msk
6713 #define RCC_CSR_LSI2RDY_Pos                 (3U)
6714 #define RCC_CSR_LSI2RDY_Msk                 (0x1UL << RCC_CSR_LSI2RDY_Pos)     /*!< 0x00000008 */
6715 #define RCC_CSR_LSI2RDY                     RCC_CSR_LSI2RDY_Msk
6716 #define RCC_CSR_LSI2TRIM_Pos                (8U)
6717 #define RCC_CSR_LSI2TRIM_Msk                (0xFUL << RCC_CSR_LSI2TRIM_Pos)      /*!< 0x00000F00 */
6718 #define RCC_CSR_LSI2TRIM                    RCC_CSR_LSI2TRIM_Msk
6719 #define RCC_CSR_LSI2TRIM_0                  (0x1U << RCC_CSR_LSI2TRIM_Pos)       /*!< 0x00000100 */
6720 #define RCC_CSR_LSI2TRIM_1                  (0x2U << RCC_CSR_LSI2TRIM_Pos)       /*!< 0x00000200 */
6721 #define RCC_CSR_LSI2TRIM_2                  (0x4U << RCC_CSR_LSI2TRIM_Pos)       /*!< 0x00000400 */
6722 #define RCC_CSR_LSI2TRIM_3                  (0x8U << RCC_CSR_LSI2TRIM_Pos)       /*!< 0x00000800 */
6723 #define RCC_CSR_RFWKPSEL_Pos                (14U)
6724 #define RCC_CSR_RFWKPSEL_Msk                (0x3UL << RCC_CSR_RFWKPSEL_Pos)    /*!< 0x0000C000 */
6725 #define RCC_CSR_RFWKPSEL                    RCC_CSR_RFWKPSEL_Msk
6726 #define RCC_CSR_RFWKPSEL_0                  (0x1U << RCC_CSR_RFWKPSEL_Pos)     /*!< 0x00004000 */
6727 #define RCC_CSR_RFWKPSEL_1                  (0x2U << RCC_CSR_RFWKPSEL_Pos)     /*!< 0x00008000 */
6728 #define RCC_CSR_RFRSTS_Pos                  (16U)
6729 #define RCC_CSR_RFRSTS_Msk                  (0x1UL << RCC_CSR_RFRSTS_Pos)      /*!< 0x00010000 */
6730 #define RCC_CSR_RFRSTS                      RCC_CSR_RFRSTS_Msk
6731 #define RCC_CSR_RMVF_Pos                    (23U)
6732 #define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)        /*!< 0x00800000 */
6733 #define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk
6734 #define RCC_CSR_OBLRSTF_Pos                 (25U)
6735 #define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)     /*!< 0x02000000 */
6736 #define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk
6737 #define RCC_CSR_PINRSTF_Pos                 (26U)
6738 #define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
6739 #define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk
6740 #define RCC_CSR_BORRSTF_Pos                 (27U)
6741 #define RCC_CSR_BORRSTF_Msk                 (0x1UL << RCC_CSR_BORRSTF_Pos)     /*!< 0x08000000 */
6742 #define RCC_CSR_BORRSTF                     RCC_CSR_BORRSTF_Msk
6743 #define RCC_CSR_SFTRSTF_Pos                 (28U)
6744 #define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
6745 #define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk
6746 #define RCC_CSR_IWDGRSTF_Pos                (29U)
6747 #define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
6748 #define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk
6749 #define RCC_CSR_WWDGRSTF_Pos                (30U)
6750 #define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
6751 #define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk
6752 #define RCC_CSR_LPWRRSTF_Pos                (31U)
6753 #define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
6754 #define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk
6755 
6756 /********************  Bit definition for RCC_HSECR register  *******************/
6757 #define RCC_HSECR_UNLOCKED_Pos              (0U)
6758 #define RCC_HSECR_UNLOCKED_Msk              (0x1UL << RCC_HSECR_UNLOCKED_Pos)  /*!< 0x00000001 */
6759 #define RCC_HSECR_UNLOCKED                  RCC_HSECR_UNLOCKED_Msk
6760 
6761 #define RCC_HSECR_HSES_Pos                  (3U)
6762 #define RCC_HSECR_HSES_Msk                  (0x1UL << RCC_HSECR_HSES_Pos)      /*!< 0x00000008 */
6763 #define RCC_HSECR_HSES                      RCC_HSECR_HSES_Msk
6764 
6765 #define RCC_HSECR_HSEGMC_Pos                (4U)
6766 #define RCC_HSECR_HSEGMC_Msk                (0x7UL << RCC_HSECR_HSEGMC_Pos)       /*!< 0x00000070 */
6767 #define RCC_HSECR_HSEGMC                    RCC_HSECR_HSEGMC_Msk
6768 #define RCC_HSECR_HSEGMC0_Pos               (4U)
6769 #define RCC_HSECR_HSEGMC0_Msk               (0x1UL << RCC_HSECR_HSEGMC0_Pos)      /*!< 0x00000010 */
6770 #define RCC_HSECR_HSEGMC0                   RCC_HSECR_HSEGMC0_Msk
6771 #define RCC_HSECR_HSEGMC1_Pos               (5U)
6772 #define RCC_HSECR_HSEGMC1_Msk               (0x1UL << RCC_HSECR_HSEGMC1_Pos)      /*!< 0x00000020 */
6773 #define RCC_HSECR_HSEGMC1                   RCC_HSECR_HSEGMC1_Msk
6774 #define RCC_HSECR_HSEGMC2_Pos               (6U)
6775 #define RCC_HSECR_HSEGMC2_Msk               (0x1UL << RCC_HSECR_HSEGMC2_Pos)      /*!< 0x00000040 */
6776 #define RCC_HSECR_HSEGMC2                   RCC_HSECR_HSEGMC2_Msk
6777 
6778 #define RCC_HSECR_HSETUNE_Pos              (8U)
6779 #define RCC_HSECR_HSETUNE_Msk              (0x3FUL << RCC_HSECR_HSETUNE_Pos)   /*!< 0x00003F00 */
6780 #define RCC_HSECR_HSETUNE                  RCC_HSECR_HSETUNE_Msk
6781 #define RCC_HSECR_HSETUNE0_Pos             (8U)
6782 #define RCC_HSECR_HSETUNE0_Msk             (0x1UL << RCC_HSECR_HSETUNE0_Pos)   /*!< 0x00000100 */
6783 #define RCC_HSECR_HSETUNE0                 RCC_HSECR_HSETUNE0_Msk
6784 #define RCC_HSECR_HSETUNE1_Pos             (9U)
6785 #define RCC_HSECR_HSETUNE1_Msk             (0x1UL << RCC_HSECR_HSETUNE1_Pos)   /*!< 0x00000200 */
6786 #define RCC_HSECR_HSETUNE1                 RCC_HSECR_HSETUNE1_Msk
6787 #define RCC_HSECR_HSETUNE2_Pos             (10U)
6788 #define RCC_HSECR_HSETUNE2_Msk             (0x1UL << RCC_HSECR_HSETUNE2_Pos)   /*!< 0x00000400 */
6789 #define RCC_HSECR_HSETUNE2                 RCC_HSECR_HSETUNE2_Msk
6790 #define RCC_HSECR_HSETUNE3_Pos             (11U)
6791 #define RCC_HSECR_HSETUNE3_Msk             (0x1UL << RCC_HSECR_HSETUNE3_Pos)   /*!< 0x00000800 */
6792 #define RCC_HSECR_HSETUNE3                 RCC_HSECR_HSETUNE3_Msk
6793 #define RCC_HSECR_HSETUNE4_Pos             (12U)
6794 #define RCC_HSECR_HSETUNE4_Msk             (0x1UL << RCC_HSECR_HSETUNE4_Pos)   /*!< 0x00001000 */
6795 #define RCC_HSECR_HSETUNE4                 RCC_HSECR_HSETUNE4_Msk
6796 #define RCC_HSECR_HSETUNE5_Pos             (13U)
6797 #define RCC_HSECR_HSETUNE5_Msk             (0x1UL << RCC_HSECR_HSETUNE5_Pos)   /*!< 0x00002000 */
6798 #define RCC_HSECR_HSETUNE5                 RCC_HSECR_HSETUNE5_Msk
6799 
6800 /********************  Bit definition for RCC_EXTCFGR register  *******************/
6801 #define RCC_EXTCFGR_SHDHPRE_Pos             (0U)
6802 #define RCC_EXTCFGR_SHDHPRE_Msk             (0xFUL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x0000000F */
6803 #define RCC_EXTCFGR_SHDHPRE                 RCC_EXTCFGR_SHDHPRE_Msk
6804 #define RCC_EXTCFGR_SHDHPRE_0               (0x1U << RCC_EXTCFGR_SHDHPRE_Pos)  /*!< 0x00000001 */
6805 #define RCC_EXTCFGR_SHDHPRE_1               (0x2U << RCC_EXTCFGR_SHDHPRE_Pos)  /*!< 0x00000002 */
6806 #define RCC_EXTCFGR_SHDHPRE_2               (0x4U << RCC_EXTCFGR_SHDHPRE_Pos)  /*!< 0x00000004 */
6807 #define RCC_EXTCFGR_SHDHPRE_3               (0x8U << RCC_EXTCFGR_SHDHPRE_Pos)  /*!< 0x00000008 */
6808 
6809 #define RCC_EXTCFGR_C2HPRE_Pos              (4U)
6810 #define RCC_EXTCFGR_C2HPRE_Msk              (0xFUL << RCC_EXTCFGR_C2HPRE_Pos) /*!< 0x000000F0 */
6811 #define RCC_EXTCFGR_C2HPRE                  RCC_EXTCFGR_C2HPRE_Msk
6812 #define RCC_EXTCFGR_C2HPRE_0                (0x1U << RCC_EXTCFGR_C2HPRE_Pos) /*!< 0x00000010 */
6813 #define RCC_EXTCFGR_C2HPRE_1                (0x2U << RCC_EXTCFGR_C2HPRE_Pos) /*!< 0x00000020 */
6814 #define RCC_EXTCFGR_C2HPRE_2                (0x4U << RCC_EXTCFGR_C2HPRE_Pos) /*!< 0x00000040 */
6815 #define RCC_EXTCFGR_C2HPRE_3                (0x8U << RCC_EXTCFGR_C2HPRE_Pos) /*!< 0x00000080 */
6816 
6817 #define RCC_EXTCFGR_SHDHPREF_Pos            (16U)
6818 #define RCC_EXTCFGR_SHDHPREF_Msk            (0x1UL << RCC_EXTCFGR_SHDHPREF_Pos) /*!< 0x00010000 */
6819 #define RCC_EXTCFGR_SHDHPREF                RCC_EXTCFGR_SHDHPREF_Msk
6820 #define RCC_EXTCFGR_C2HPREF_Pos             (17U)
6821 #define RCC_EXTCFGR_C2HPREF_Msk             (0x1UL << RCC_EXTCFGR_C2HPREF_Pos) /*!< 0x00020000 */
6822 #define RCC_EXTCFGR_C2HPREF                 RCC_EXTCFGR_C2HPREF_Msk
6823 #define RCC_EXTCFGR_RFCSS_Pos               (20U)
6824 #define RCC_EXTCFGR_RFCSS_Msk               (0x1UL << RCC_EXTCFGR_RFCSS_Pos)   /*!< 0x00100000 */
6825 #define RCC_EXTCFGR_RFCSS                   RCC_EXTCFGR_RFCSS_Msk
6826 
6827 /********************  Bit definition for RCC_C2AHB1ENR register  ****************/
6828 #define RCC_C2AHB1ENR_DMA1EN_Pos            (0U)
6829 #define RCC_C2AHB1ENR_DMA1EN_Msk            (0x1UL << RCC_C2AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
6830 #define RCC_C2AHB1ENR_DMA1EN                RCC_C2AHB1ENR_DMA1EN_Msk
6831 #define RCC_C2AHB1ENR_DMAMUX1EN_Pos         (2U)
6832 #define RCC_C2AHB1ENR_DMAMUX1EN_Msk         (0x1UL << RCC_C2AHB1ENR_DMAMUX1EN_Pos) /*!< 0x00000004 */
6833 #define RCC_C2AHB1ENR_DMAMUX1EN             RCC_C2AHB1ENR_DMAMUX1EN_Msk
6834 #define RCC_C2AHB1ENR_SRAM1EN_Pos           (9U)
6835 #define RCC_C2AHB1ENR_SRAM1EN_Msk           (0x1UL << RCC_C2AHB1ENR_SRAM1EN_Pos) /*!< 0x00000200 */
6836 #define RCC_C2AHB1ENR_SRAM1EN                RCC_C2AHB1ENR_SRAM1EN_Msk
6837 #define RCC_C2AHB1ENR_CRCEN_Pos             (12U)
6838 #define RCC_C2AHB1ENR_CRCEN_Msk             (0x1UL << RCC_C2AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
6839 #define RCC_C2AHB1ENR_CRCEN                  RCC_C2AHB1ENR_CRCEN_Msk
6840 #define RCC_C2AHB1ENR_TSCEN_Pos             (16U)
6841 #define RCC_C2AHB1ENR_TSCEN_Msk             (0x1UL << RCC_C2AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */
6842 #define RCC_C2AHB1ENR_TSCEN                 RCC_C2AHB1ENR_TSCEN_Msk
6843 
6844 /********************  Bit definition for RCC_C2AHB2ENR register  ***************/
6845 #define RCC_C2AHB2ENR_GPIOAEN_Pos          (0U)
6846 #define RCC_C2AHB2ENR_GPIOAEN_Msk          (0x1UL << RCC_C2AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
6847 #define RCC_C2AHB2ENR_GPIOAEN              RCC_C2AHB2ENR_GPIOAEN_Msk
6848 #define RCC_C2AHB2ENR_GPIOBEN_Pos          (1U)
6849 #define RCC_C2AHB2ENR_GPIOBEN_Msk          (0x1UL << RCC_C2AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
6850 #define RCC_C2AHB2ENR_GPIOBEN              RCC_C2AHB2ENR_GPIOBEN_Msk
6851 #define RCC_C2AHB2ENR_GPIOCEN_Pos          (2U)
6852 #define RCC_C2AHB2ENR_GPIOCEN_Msk          (0x1UL << RCC_C2AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
6853 #define RCC_C2AHB2ENR_GPIOCEN              RCC_C2AHB2ENR_GPIOCEN_Msk
6854 #define RCC_C2AHB2ENR_GPIOEEN_Pos          (4U)
6855 #define RCC_C2AHB2ENR_GPIOEEN_Msk          (0x1UL << RCC_C2AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
6856 #define RCC_C2AHB2ENR_GPIOEEN              RCC_C2AHB2ENR_GPIOEEN_Msk
6857 #define RCC_C2AHB2ENR_GPIOHEN_Pos          (7U)
6858 #define RCC_C2AHB2ENR_GPIOHEN_Msk          (0x1UL << RCC_C2AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
6859 #define RCC_C2AHB2ENR_GPIOHEN              RCC_C2AHB2ENR_GPIOHEN_Msk
6860 
6861 /********************  Bit definition for RCC_C2AHB3ENR register  ***************/
6862 #define RCC_C2AHB3ENR_PKAEN_Pos            (16U)
6863 #define RCC_C2AHB3ENR_PKAEN_Msk            (0x1UL << RCC_C2AHB3ENR_PKAEN_Pos) /*!< 0x00010000 */
6864 #define RCC_C2AHB3ENR_PKAEN                RCC_C2AHB3ENR_PKAEN_Msk
6865 #define RCC_C2AHB3ENR_AES2EN_Pos           (17U)
6866 #define RCC_C2AHB3ENR_AES2EN_Msk           (0x1UL << RCC_C2AHB3ENR_AES2EN_Pos) /*!< 0x00020000 */
6867 #define RCC_C2AHB3ENR_AES2EN               RCC_C2AHB3ENR_AES2EN_Msk
6868 #define RCC_C2AHB3ENR_RNGEN_Pos            (18U)
6869 #define RCC_C2AHB3ENR_RNGEN_Msk            (0x1UL << RCC_C2AHB3ENR_RNGEN_Pos) /*!< 0x00040000 */
6870 #define RCC_C2AHB3ENR_RNGEN                RCC_C2AHB3ENR_RNGEN_Msk
6871 #define RCC_C2AHB3ENR_HSEMEN_Pos           (19U)
6872 #define RCC_C2AHB3ENR_HSEMEN_Msk           (0x1UL << RCC_C2AHB3ENR_HSEMEN_Pos) /*!< 0x00080000 */
6873 #define RCC_C2AHB3ENR_HSEMEN               RCC_C2AHB3ENR_HSEMEN_Msk
6874 #define RCC_C2AHB3ENR_IPCCEN_Pos           (20U)
6875 #define RCC_C2AHB3ENR_IPCCEN_Msk           (0x1UL << RCC_C2AHB3ENR_IPCCEN_Pos) /*!< 0x00100000 */
6876 #define RCC_C2AHB3ENR_IPCCEN               RCC_C2AHB3ENR_IPCCEN_Msk
6877 #define RCC_C2AHB3ENR_FLASHEN_Pos          (25U)
6878 #define RCC_C2AHB3ENR_FLASHEN_Msk          (0x1UL << RCC_C2AHB3ENR_FLASHEN_Pos) /*!< 0x02000000 */
6879 #define RCC_C2AHB3ENR_FLASHEN              RCC_C2AHB3ENR_FLASHEN_Msk
6880 
6881 /********************  Bit definition for RCC_C2APB1ENR1 register  **************/
6882 #define RCC_C2APB1ENR1_TIM2EN_Pos          (0U)
6883 #define RCC_C2APB1ENR1_TIM2EN_Msk          (0x1UL << RCC_C2APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
6884 #define RCC_C2APB1ENR1_TIM2EN              RCC_C2APB1ENR1_TIM2EN_Msk
6885 #define RCC_C2APB1ENR1_RTCAPBEN_Pos        (10U)
6886 #define RCC_C2APB1ENR1_RTCAPBEN_Msk        (0x1UL << RCC_C2APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
6887 #define RCC_C2APB1ENR1_RTCAPBEN            RCC_C2APB1ENR1_RTCAPBEN_Msk
6888 #define RCC_C2APB1ENR1_I2C1EN_Pos          (21U)
6889 #define RCC_C2APB1ENR1_I2C1EN_Msk          (0x1UL << RCC_C2APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
6890 #define RCC_C2APB1ENR1_I2C1EN              RCC_C2APB1ENR1_I2C1EN_Msk
6891 #define RCC_C2APB1ENR1_LPTIM1EN_Pos        (31U)
6892 #define RCC_C2APB1ENR1_LPTIM1EN_Msk        (0x1UL << RCC_C2APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
6893 #define RCC_C2APB1ENR1_LPTIM1EN            RCC_C2APB1ENR1_LPTIM1EN_Msk
6894 
6895 /********************  Bit definition for RCC_C2APB1ENR2 register  **************/
6896 #define RCC_C2APB1ENR2_LPUART1EN_Pos       (0U)
6897 #define RCC_C2APB1ENR2_LPUART1EN_Msk       (0x1UL << RCC_C2APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
6898 #define RCC_C2APB1ENR2_LPUART1EN           RCC_C2APB1ENR2_LPUART1EN_Msk
6899 #define RCC_C2APB1ENR2_LPTIM2EN_Pos        (5U)
6900 #define RCC_C2APB1ENR2_LPTIM2EN_Msk        (0x1UL << RCC_C2APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
6901 #define RCC_C2APB1ENR2_LPTIM2EN            RCC_C2APB1ENR2_LPTIM2EN_Msk
6902 
6903 /********************  Bit definition for RCC_C2APB2ENR register  **************/
6904 #define RCC_C2APB2ENR_ADCEN_Pos            (9U)
6905 #define RCC_C2APB2ENR_ADCEN_Msk            (0x1UL << RCC_C2APB2ENR_ADCEN_Pos)    /*!< 0x00000200 */
6906 #define RCC_C2APB2ENR_ADCEN                RCC_C2APB2ENR_ADCEN_Msk
6907 #define RCC_C2APB2ENR_TIM1EN_Pos           (11U)
6908 #define RCC_C2APB2ENR_TIM1EN_Msk           (0x1UL << RCC_C2APB2ENR_TIM1EN_Pos)   /*!< 0x00000800 */
6909 #define RCC_C2APB2ENR_TIM1EN               RCC_C2APB2ENR_TIM1EN_Msk
6910 #define RCC_C2APB2ENR_SPI1EN_Pos           (12U)
6911 #define RCC_C2APB2ENR_SPI1EN_Msk           (0x1UL << RCC_C2APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
6912 #define RCC_C2APB2ENR_SPI1EN               RCC_C2APB2ENR_SPI1EN_Msk
6913 #define RCC_C2APB2ENR_USART1EN_Pos         (14U)
6914 #define RCC_C2APB2ENR_USART1EN_Msk         (0x1UL << RCC_C2APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
6915 #define RCC_C2APB2ENR_USART1EN             RCC_C2APB2ENR_USART1EN_Msk
6916 
6917 /********************  Bit definition for RCC_C2APB3ENR register  **************/
6918 #define RCC_C2APB3ENR_BLEEN_Pos            (0U)
6919 #define RCC_C2APB3ENR_BLEEN_Msk            (0x1UL << RCC_C2APB3ENR_BLEEN_Pos) /*!< 0x00000001 */
6920 #define RCC_C2APB3ENR_BLEEN                RCC_C2APB3ENR_BLEEN_Msk
6921 
6922 /********************  Bit definition for RCC_C2AHB1SMENR register  ****************/
6923 #define RCC_C2AHB1SMENR_DMA1SMEN_Pos       (0U)
6924 #define RCC_C2AHB1SMENR_DMA1SMEN_Msk       (0x1UL << RCC_C2AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
6925 #define RCC_C2AHB1SMENR_DMA1SMEN           RCC_C2AHB1SMENR_DMA1SMEN_Msk
6926 #define RCC_C2AHB1SMENR_DMAMUX1SMEN_Pos    (2U)
6927 #define RCC_C2AHB1SMENR_DMAMUX1SMEN_Msk    (0x1UL << RCC_C2AHB1SMENR_DMAMUX1SMEN_Pos) /*!< 0x00000004 */
6928 #define RCC_C2AHB1SMENR_DMAMUX1SMEN        RCC_C2AHB1SMENR_DMAMUX1SMEN_Msk
6929 #define RCC_C2AHB1SMENR_SRAM1SMEN_Pos      (9U)
6930 #define RCC_C2AHB1SMENR_SRAM1SMEN_Msk      (0x1UL << RCC_C2AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
6931 #define RCC_C2AHB1SMENR_SRAM1SMEN          RCC_C2AHB1SMENR_SRAM1SMEN_Msk
6932 #define RCC_C2AHB1SMENR_CRCSMEN_Pos        (12U)
6933 #define RCC_C2AHB1SMENR_CRCSMEN_Msk        (0x1UL << RCC_C2AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
6934 #define RCC_C2AHB1SMENR_CRCSMEN            RCC_C2AHB1SMENR_CRCSMEN_Msk
6935 #define RCC_C2AHB1SMENR_TSCSMEN_Pos        (16U)
6936 #define RCC_C2AHB1SMENR_TSCSMEN_Msk        (0x1UL << RCC_C2AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
6937 #define RCC_C2AHB1SMENR_TSCSMEN            RCC_C2AHB1SMENR_TSCSMEN_Msk
6938 
6939 /********************  Bit definition for RCC_C2AHB2SMENR register  ***************/
6940 #define RCC_C2AHB2SMENR_GPIOASMEN_Pos      (0U)
6941 #define RCC_C2AHB2SMENR_GPIOASMEN_Msk      (0x1UL << RCC_C2AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
6942 #define RCC_C2AHB2SMENR_GPIOASMEN          RCC_C2AHB2SMENR_GPIOASMEN_Msk
6943 #define RCC_C2AHB2SMENR_GPIOBSMEN_Pos      (1U)
6944 #define RCC_C2AHB2SMENR_GPIOBSMEN_Msk      (0x1UL << RCC_C2AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
6945 #define RCC_C2AHB2SMENR_GPIOBSMEN          RCC_C2AHB2SMENR_GPIOBSMEN_Msk
6946 #define RCC_C2AHB2SMENR_GPIOCSMEN_Pos      (2U)
6947 #define RCC_C2AHB2SMENR_GPIOCSMEN_Msk      (0x1UL << RCC_C2AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
6948 #define RCC_C2AHB2SMENR_GPIOCSMEN          RCC_C2AHB2SMENR_GPIOCSMEN_Msk
6949 #define RCC_C2AHB2SMENR_GPIOESMEN_Pos      (4U)
6950 #define RCC_C2AHB2SMENR_GPIOESMEN_Msk      (0x1UL << RCC_C2AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
6951 #define RCC_C2AHB2SMENR_GPIOESMEN          RCC_C2AHB2SMENR_GPIOESMEN_Msk
6952 #define RCC_C2AHB2SMENR_GPIOHSMEN_Pos      (7U)
6953 #define RCC_C2AHB2SMENR_GPIOHSMEN_Msk      (0x1UL << RCC_C2AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
6954 #define RCC_C2AHB2SMENR_GPIOHSMEN          RCC_C2AHB2SMENR_GPIOHSMEN_Msk
6955 
6956 /********************  Bit definition for RCC_C2AHB3SMENR register  ***************/
6957 #define RCC_C2AHB3SMENR_PKASMEN_Pos        (16U)
6958 #define RCC_C2AHB3SMENR_PKASMEN_Msk        (0x1UL << RCC_C2AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */
6959 #define RCC_C2AHB3SMENR_PKASMEN            RCC_C2AHB3SMENR_PKASMEN_Msk
6960 #define RCC_C2AHB3SMENR_AES2SMEN_Pos       (17U)
6961 #define RCC_C2AHB3SMENR_AES2SMEN_Msk       (0x1UL << RCC_C2AHB3SMENR_AES2SMEN_Pos) /*!< 0x00020000 */
6962 #define RCC_C2AHB3SMENR_AES2SMEN           RCC_C2AHB3SMENR_AES2SMEN_Msk
6963 #define RCC_C2AHB3SMENR_RNGSMEN_Pos        (18U)
6964 #define RCC_C2AHB3SMENR_RNGSMEN_Msk        (0x1UL << RCC_C2AHB3SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
6965 #define RCC_C2AHB3SMENR_RNGSMEN            RCC_C2AHB3SMENR_RNGSMEN_Msk
6966 #define RCC_C2AHB3SMENR_SRAM2SMEN_Pos      (24U)
6967 #define RCC_C2AHB3SMENR_SRAM2SMEN_Msk      (0x1UL << RCC_C2AHB3SMENR_SRAM2SMEN_Pos) /*!< 0x01000000 */
6968 #define RCC_C2AHB3SMENR_SRAM2SMEN           RCC_C2AHB3SMENR_SRAM2SMEN_Msk
6969 #define RCC_C2AHB3SMENR_FLASHSMEN_Pos      (25U)
6970 #define RCC_C2AHB3SMENR_FLASHSMEN_Msk      (0x1UL << RCC_C2AHB3SMENR_FLASHSMEN_Pos) /*!< 0x02000000 */
6971 #define RCC_C2AHB3SMENR_FLASHSMEN          RCC_C2AHB3SMENR_FLASHSMEN_Msk
6972 
6973 /********************  Bit definition for RCC_C2APB1SMENR1 register  **************/
6974 #define RCC_C2APB1SMENR1_TIM2SMEN_Pos      (0U)
6975 #define RCC_C2APB1SMENR1_TIM2SMEN_Msk      (0x1UL << RCC_C2APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
6976 #define RCC_C2APB1SMENR1_TIM2SMEN          RCC_C2APB1SMENR1_TIM2SMEN_Msk
6977 #define RCC_C2APB1SMENR1_RTCAPBSMEN_Pos    (10U)
6978 #define RCC_C2APB1SMENR1_RTCAPBSMEN_Msk    (0x1UL << RCC_C2APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
6979 #define RCC_C2APB1SMENR1_RTCAPBSMEN        RCC_C2APB1SMENR1_RTCAPBSMEN_Msk
6980 #define RCC_C2APB1SMENR1_I2C1SMEN_Pos      (21U)
6981 #define RCC_C2APB1SMENR1_I2C1SMEN_Msk      (0x1UL << RCC_C2APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
6982 #define RCC_C2APB1SMENR1_I2C1SMEN          RCC_C2APB1SMENR1_I2C1SMEN_Msk
6983 #define RCC_C2APB1SMENR1_LPTIM1SMEN_Pos    (31U)
6984 #define RCC_C2APB1SMENR1_LPTIM1SMEN_Msk    (0x1UL << RCC_C2APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
6985 #define RCC_C2APB1SMENR1_LPTIM1SMEN        RCC_C2APB1SMENR1_LPTIM1SMEN_Msk
6986 
6987 /********************  Bit definition for RCC_C2APB1SMENR2 register  **************/
6988 #define RCC_C2APB1SMENR2_LPUART1SMEN_Pos    (0U)
6989 #define RCC_C2APB1SMENR2_LPUART1SMEN_Msk    (0x1UL << RCC_C2APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
6990 #define RCC_C2APB1SMENR2_LPUART1SMEN        RCC_C2APB1SMENR2_LPUART1SMEN_Msk
6991 #define RCC_C2APB1SMENR2_LPTIM2SMEN_Pos     (5U)
6992 #define RCC_C2APB1SMENR2_LPTIM2SMEN_Msk     (0x1UL << RCC_C2APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
6993 #define RCC_C2APB1SMENR2_LPTIM2SMEN         RCC_C2APB1SMENR2_LPTIM2SMEN_Msk
6994 
6995 /********************  Bit definition for RCC_C2APB2SMENR register  **************/
6996 #define RCC_C2APB2SMENR_ADCSMEN_Pos        (9U)
6997 #define RCC_C2APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_C2APB2SMENR_ADCSMEN_Pos)    /*!< 0x00000200 */
6998 #define RCC_C2APB2SMENR_ADCSMEN            RCC_C2APB2SMENR_ADCSMEN_Msk
6999 #define RCC_C2APB2SMENR_TIM1SMEN_Pos       (11U)
7000 #define RCC_C2APB2SMENR_TIM1SMEN_Msk       (0x1UL << RCC_C2APB2SMENR_TIM1SMEN_Pos)   /*!< 0x00000800 */
7001 #define RCC_C2APB2SMENR_TIM1SMEN           RCC_C2APB2SMENR_TIM1SMEN_Msk
7002 #define RCC_C2APB2SMENR_SPI1SMEN_Pos       (12U)
7003 #define RCC_C2APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_C2APB2SMENR_SPI1SMEN_Pos)   /*!< 0x00001000 */
7004 #define RCC_C2APB2SMENR_SPI1SMEN           RCC_C2APB2SMENR_SPI1SMEN_Msk
7005 #define RCC_C2APB2SMENR_USART1SMEN_Pos     (14U)
7006 #define RCC_C2APB2SMENR_USART1SMEN_Msk     (0x1UL << RCC_C2APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
7007 #define RCC_C2APB2SMENR_USART1SMEN         RCC_C2APB2SMENR_USART1SMEN_Msk
7008 
7009 /********************  Bit definition for RCC_C2APB3SMENR register  **************/
7010 #define RCC_C2APB3SMENR_BLESMEN_Pos        (0U)
7011 #define RCC_C2APB3SMENR_BLESMEN_Msk        (0x1UL << RCC_C2APB3SMENR_BLESMEN_Pos) /*!< 0x00000001 */
7012 #define RCC_C2APB3SMENR_BLESMEN            RCC_C2APB3SMENR_BLESMEN_Msk
7013 
7014 /******************************************************************************/
7015 /*                                                                            */
7016 /*                                    RNG                                     */
7017 /*                                                                            */
7018 /******************************************************************************/
7019 /********************  Bits definition for  register  *******************/
7020 #define RNG_CR_RNGEN_Pos    (2U)
7021 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
7022 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
7023 #define RNG_CR_IE_Pos       (3U)
7024 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
7025 #define RNG_CR_IE           RNG_CR_IE_Msk
7026 #define RNG_CR_CED_Pos      (5U)
7027 #define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */
7028 #define RNG_CR_CED          RNG_CR_CED_Msk
7029 
7030 /********************  Bits definition for RNG_SR register  *******************/
7031 #define RNG_SR_DRDY_Pos     (0U)
7032 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
7033 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
7034 #define RNG_SR_CECS_Pos     (1U)
7035 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
7036 #define RNG_SR_CECS         RNG_SR_CECS_Msk
7037 #define RNG_SR_SECS_Pos     (2U)
7038 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
7039 #define RNG_SR_SECS         RNG_SR_SECS_Msk
7040 #define RNG_SR_CEIS_Pos     (5U)
7041 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
7042 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
7043 #define RNG_SR_SEIS_Pos     (6U)
7044 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
7045 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
7046 
7047 /******************************************************************************/
7048 /*                                                                            */
7049 /*                           Real-Time Clock (RTC)                            */
7050 /*                                                                            */
7051 /******************************************************************************/
7052 /*
7053   * @brief Specific device feature definitions
7054   */
7055 #define RTC_TAMPER2_SUPPORT
7056 #define RTC_WAKEUP_SUPPORT
7057 #define RTC_BACKUP_SUPPORT
7058 #define RTC_CPU2_SUPPORT_D
7059 #define RTC_INTERNALTS_SUPPORT
7060 
7061 /********************  Bits definition for RTC_TR register  *******************/
7062 #define RTC_TR_PM_Pos                  (22U)
7063 #define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
7064 #define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!< AM/PM notation */
7065 #define RTC_TR_HT_Pos                  (20U)
7066 #define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
7067 #define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!< Hour tens in BCD format */
7068 #define RTC_TR_HT_0                    (0x1U << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
7069 #define RTC_TR_HT_1                    (0x2U << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
7070 #define RTC_TR_HU_Pos                  (16U)
7071 #define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
7072 #define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!< Hour units in BCD format */
7073 #define RTC_TR_HU_0                    (0x1U << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
7074 #define RTC_TR_HU_1                    (0x2U << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
7075 #define RTC_TR_HU_2                    (0x4U << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
7076 #define RTC_TR_HU_3                    (0x8U << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
7077 #define RTC_TR_MNT_Pos                 (12U)
7078 #define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
7079 #define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!< Minute tens in BCD format */
7080 #define RTC_TR_MNT_0                   (0x1U << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
7081 #define RTC_TR_MNT_1                   (0x2U << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
7082 #define RTC_TR_MNT_2                   (0x4U << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
7083 #define RTC_TR_MNU_Pos                 (8U)
7084 #define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
7085 #define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!< Minute unit in BCD format */
7086 #define RTC_TR_MNU_0                   (0x1U << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
7087 #define RTC_TR_MNU_1                   (0x2U << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
7088 #define RTC_TR_MNU_2                   (0x4U << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
7089 #define RTC_TR_MNU_3                   (0x8U << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
7090 #define RTC_TR_ST_Pos                  (4U)
7091 #define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
7092 #define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!< Second tens in BCD format */
7093 #define RTC_TR_ST_0                    (0x1U << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
7094 #define RTC_TR_ST_1                    (0x2U << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
7095 #define RTC_TR_ST_2                    (0x4U << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
7096 #define RTC_TR_SU_Pos                  (0U)
7097 #define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
7098 #define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!< Second units in BCD format */
7099 #define RTC_TR_SU_0                    (0x1U << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
7100 #define RTC_TR_SU_1                    (0x2U << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
7101 #define RTC_TR_SU_2                    (0x4U << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
7102 #define RTC_TR_SU_3                    (0x8U << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
7103 
7104 /********************  Bits definition for RTC_DR register  *******************/
7105 #define RTC_DR_YT_Pos                  (20U)
7106 #define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
7107 #define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!< Year tens in BCD format */
7108 #define RTC_DR_YT_0                    (0x1U << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
7109 #define RTC_DR_YT_1                    (0x2U << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
7110 #define RTC_DR_YT_2                    (0x4U << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
7111 #define RTC_DR_YT_3                    (0x8U << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
7112 #define RTC_DR_YU_Pos                  (16U)
7113 #define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
7114 #define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!< Years units in BCD format */
7115 #define RTC_DR_YU_0                    (0x1U << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
7116 #define RTC_DR_YU_1                    (0x2U << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
7117 #define RTC_DR_YU_2                    (0x4U << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
7118 #define RTC_DR_YU_3                    (0x8U << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
7119 #define RTC_DR_WDU_Pos                 (13U)
7120 #define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
7121 #define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!< Week day units */
7122 #define RTC_DR_WDU_0                   (0x1U << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
7123 #define RTC_DR_WDU_1                   (0x2U << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
7124 #define RTC_DR_WDU_2                   (0x4U << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
7125 #define RTC_DR_MT_Pos                  (12U)
7126 #define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
7127 #define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!< Month tens in BCD format */
7128 #define RTC_DR_MU_Pos                  (8U)
7129 #define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
7130 #define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!< Month units in BCD format */
7131 #define RTC_DR_MU_0                    (0x1U << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
7132 #define RTC_DR_MU_1                    (0x2U << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
7133 #define RTC_DR_MU_2                    (0x4U << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
7134 #define RTC_DR_MU_3                    (0x8U << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
7135 #define RTC_DR_DT_Pos                  (4U)
7136 #define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
7137 #define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!< Date tens in BCD format */
7138 #define RTC_DR_DT_0                    (0x1U << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
7139 #define RTC_DR_DT_1                    (0x2U << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
7140 #define RTC_DR_DU_Pos                  (0U)
7141 #define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
7142 #define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!< Date units in BCD format */
7143 #define RTC_DR_DU_0                    (0x1U << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
7144 #define RTC_DR_DU_1                    (0x2U << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
7145 #define RTC_DR_DU_2                    (0x4U << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
7146 #define RTC_DR_DU_3                    (0x8U << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
7147 
7148 /********************  Bits definition for RTC_CR register  *******************/
7149 #define RTC_CR_ITSE_Pos                (24U)
7150 #define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
7151 #define RTC_CR_ITSE                    RTC_CR_ITSE_Msk                         /*!< Timestamp on internal event enable */
7152 #define RTC_CR_COE_Pos                 (23U)
7153 #define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
7154 #define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!< Calibration output enable */
7155 #define RTC_CR_OSEL_Pos                (21U)
7156 #define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
7157 #define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!< Output selection */
7158 #define RTC_CR_OSEL_0                  (0x1U << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
7159 #define RTC_CR_OSEL_1                  (0x2U << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
7160 #define RTC_CR_POL_Pos                 (20U)
7161 #define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
7162 #define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!< Output polarity */
7163 #define RTC_CR_COSEL_Pos               (19U)
7164 #define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
7165 #define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!< Calibration output selection */
7166 #define RTC_CR_BKP_Pos                 (18U)
7167 #define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
7168 #define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!< Backup */
7169 #define RTC_CR_SUB1H_Pos               (17U)
7170 #define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
7171 #define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!< Subtract 1 hour (winter time change) */
7172 #define RTC_CR_ADD1H_Pos               (16U)
7173 #define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
7174 #define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!< Add 1 hour (summer time change) */
7175 #define RTC_CR_TSIE_Pos                (15U)
7176 #define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
7177 #define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!< Time-stamp interrupt enable */
7178 #define RTC_CR_WUTIE_Pos               (14U)
7179 #define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
7180 #define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!< Wakeup timer interrupt enable */
7181 #define RTC_CR_ALRBIE_Pos              (13U)
7182 #define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
7183 #define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!< Alarm B interrupt enable */
7184 #define RTC_CR_ALRAIE_Pos              (12U)
7185 #define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
7186 #define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!< Alarm A interrupt enable */
7187 #define RTC_CR_TSE_Pos                 (11U)
7188 #define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
7189 #define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!< Timestamp on RTC TS input edge enable */
7190 #define RTC_CR_WUTE_Pos                (10U)
7191 #define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
7192 #define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!< Wakeup timer enable */
7193 #define RTC_CR_ALRBE_Pos               (9U)
7194 #define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
7195 #define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!< Alarm B enable */
7196 #define RTC_CR_ALRAE_Pos               (8U)
7197 #define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
7198 #define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!< Alarm A enable */
7199 #define RTC_CR_FMT_Pos                 (6U)
7200 #define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
7201 #define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!< Hour AM/PM or 24H format */
7202 #define RTC_CR_BYPSHAD_Pos             (5U)
7203 #define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
7204 #define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!< Bypass the shadow registers */
7205 #define RTC_CR_REFCKON_Pos             (4U)
7206 #define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
7207 #define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!< RTC_REFIN reference clock detection enable (50 or 60 Hz) */
7208 #define RTC_CR_TSEDGE_Pos              (3U)
7209 #define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
7210 #define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!< Timestamp event active edge */
7211 #define RTC_CR_WUCKSEL_Pos             (0U)
7212 #define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
7213 #define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!< Wakekup clock selection */
7214 #define RTC_CR_WUCKSEL_0               (0x1U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
7215 #define RTC_CR_WUCKSEL_1               (0x2U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
7216 #define RTC_CR_WUCKSEL_2               (0x4U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
7217 
7218 /********************  Bits definition for RTC_ISR register  ******************/
7219 #define RTC_ISR_ITSF_Pos               (17U)
7220 #define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */
7221 #define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk                        /*!< Internal timestamp flag */
7222 #define RTC_ISR_RECALPF_Pos            (16U)
7223 #define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */
7224 #define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!< Recalibration pending flag */
7225 #define RTC_ISR_TAMP2F_Pos             (14U)
7226 #define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */
7227 #define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!< RTC_TAMP2 detection flag */
7228 #define RTC_ISR_TSOVF_Pos              (12U)
7229 #define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */
7230 #define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!< Timestamp overflow flag */
7231 #define RTC_ISR_TSF_Pos                (11U)
7232 #define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */
7233 #define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!< Timestamp flag */
7234 #define RTC_ISR_WUTF_Pos               (10U)
7235 #define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */
7236 #define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!< Wakeup timer flag */
7237 #define RTC_ISR_ALRBF_Pos              (9U)
7238 #define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */
7239 #define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!< Alarm B flag */
7240 #define RTC_ISR_ALRAF_Pos              (8U)
7241 #define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */
7242 #define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!< Alarm A flag */
7243 #define RTC_ISR_INIT_Pos               (7U)
7244 #define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */
7245 #define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!< Initialization mode */
7246 #define RTC_ISR_INITF_Pos              (6U)
7247 #define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */
7248 #define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!< Initialization flag */
7249 #define RTC_ISR_RSF_Pos                (5U)
7250 #define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */
7251 #define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!< Registers synchronization flag */
7252 #define RTC_ISR_INITS_Pos              (4U)
7253 #define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */
7254 #define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!< Initialization status flag */
7255 #define RTC_ISR_SHPF_Pos               (3U)
7256 #define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */
7257 #define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!< Shift operation pending */
7258 #define RTC_ISR_WUTWF_Pos              (2U)
7259 #define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */
7260 #define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!< Wakeup timer write flag */
7261 #define RTC_ISR_ALRBWF_Pos             (1U)
7262 #define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */
7263 #define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!< Alarm B write flag */
7264 #define RTC_ISR_ALRAWF_Pos             (0U)
7265 #define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */
7266 #define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!< Alarm A write flag */
7267 
7268 /********************  Bits definition for RTC_PRER register  *****************/
7269 #define RTC_PRER_PREDIV_A_Pos          (16U)
7270 #define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
7271 #define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!< Asynchronous prescaler factor */
7272 #define RTC_PRER_PREDIV_S_Pos          (0U)
7273 #define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
7274 #define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!< Synchronous prescaler factor */
7275 
7276 /********************  Bits definition for RTC_WUTR register  *****************/
7277 #define RTC_WUTR_WUT_Pos               (0U)
7278 #define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
7279 #define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        /*!< Wakeup auto-reload value bits */
7280 
7281 /********************  Bits definition for RTC_ALRMAR register  ***************/
7282 #define RTC_ALRMAR_MSK4_Pos            (31U)
7283 #define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
7284 #define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!< Alarm A date mask */
7285 #define RTC_ALRMAR_WDSEL_Pos           (30U)
7286 #define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
7287 #define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!< Alarm A week day selection */
7288 #define RTC_ALRMAR_DT_Pos              (28U)
7289 #define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
7290 #define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!< Alarm A date tens in BCD format */
7291 #define RTC_ALRMAR_DT_0                (0x1U << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
7292 #define RTC_ALRMAR_DT_1                (0x2U << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
7293 #define RTC_ALRMAR_DU_Pos              (24U)
7294 #define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
7295 #define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!< Alarm A date units in BCD format */
7296 #define RTC_ALRMAR_DU_0                (0x1U << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
7297 #define RTC_ALRMAR_DU_1                (0x2U << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
7298 #define RTC_ALRMAR_DU_2                (0x4U << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
7299 #define RTC_ALRMAR_DU_3                (0x8U << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
7300 #define RTC_ALRMAR_MSK3_Pos            (23U)
7301 #define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
7302 #define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!< Alarm A hours mask */
7303 #define RTC_ALRMAR_PM_Pos              (22U)
7304 #define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
7305 #define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!< Alarm A AM/PM or 24H format */
7306 #define RTC_ALRMAR_HT_Pos              (20U)
7307 #define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
7308 #define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!< Alarm A hour tens in BCD format */
7309 #define RTC_ALRMAR_HT_0                (0x1U << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
7310 #define RTC_ALRMAR_HT_1                (0x2U << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
7311 #define RTC_ALRMAR_HU_Pos              (16U)
7312 #define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
7313 #define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!< Alarm A hour units in BCD format */
7314 #define RTC_ALRMAR_HU_0                (0x1U << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
7315 #define RTC_ALRMAR_HU_1                (0x2U << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
7316 #define RTC_ALRMAR_HU_2                (0x4U << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
7317 #define RTC_ALRMAR_HU_3                (0x8U << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
7318 #define RTC_ALRMAR_MSK2_Pos            (15U)
7319 #define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
7320 #define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!< Alarm A minutes mask */
7321 #define RTC_ALRMAR_MNT_Pos             (12U)
7322 #define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
7323 #define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!< Alarm A minute tens in BCD format */
7324 #define RTC_ALRMAR_MNT_0               (0x1U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
7325 #define RTC_ALRMAR_MNT_1               (0x2U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
7326 #define RTC_ALRMAR_MNT_2               (0x4U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
7327 #define RTC_ALRMAR_MNU_Pos             (8U)
7328 #define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
7329 #define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!< Alarm A minute units in BCD format */
7330 #define RTC_ALRMAR_MNU_0               (0x1U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
7331 #define RTC_ALRMAR_MNU_1               (0x2U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
7332 #define RTC_ALRMAR_MNU_2               (0x4U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
7333 #define RTC_ALRMAR_MNU_3               (0x8U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
7334 #define RTC_ALRMAR_MSK1_Pos            (7U)
7335 #define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
7336 #define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!< Alarm A seconds mask */
7337 #define RTC_ALRMAR_ST_Pos              (4U)
7338 #define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
7339 #define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!< Alarm A second tens in BCD format */
7340 #define RTC_ALRMAR_ST_0                (0x1U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
7341 #define RTC_ALRMAR_ST_1                (0x2U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
7342 #define RTC_ALRMAR_ST_2                (0x4U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
7343 #define RTC_ALRMAR_SU_Pos              (0U)
7344 #define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
7345 #define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!< Alarm A second units in BCD format */
7346 #define RTC_ALRMAR_SU_0                (0x1U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
7347 #define RTC_ALRMAR_SU_1                (0x2U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
7348 #define RTC_ALRMAR_SU_2                (0x4U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
7349 #define RTC_ALRMAR_SU_3                (0x8U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
7350 
7351 /********************  Bits definition for RTC_ALRMBR register  ***************/
7352 #define RTC_ALRMBR_MSK4_Pos            (31U)
7353 #define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
7354 #define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!< Alarm B date mask */
7355 #define RTC_ALRMBR_WDSEL_Pos           (30U)
7356 #define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
7357 #define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!< Alarm B week day selection */
7358 #define RTC_ALRMBR_DT_Pos              (28U)
7359 #define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
7360 #define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!< Alarm B data tens in BCD format */
7361 #define RTC_ALRMBR_DT_0                (0x1U << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
7362 #define RTC_ALRMBR_DT_1                (0x2U << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
7363 #define RTC_ALRMBR_DU_Pos              (24U)
7364 #define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
7365 #define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!< Alarm B data units or day in BCD format */
7366 #define RTC_ALRMBR_DU_0                (0x1U << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
7367 #define RTC_ALRMBR_DU_1                (0x2U << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
7368 #define RTC_ALRMBR_DU_2                (0x4U << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
7369 #define RTC_ALRMBR_DU_3                (0x8U << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
7370 #define RTC_ALRMBR_MSK3_Pos            (23U)
7371 #define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
7372 #define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!< Alarm B hour mask */
7373 #define RTC_ALRMBR_PM_Pos              (22U)
7374 #define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
7375 #define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!< Alarm B AM/PM or 24H format */
7376 #define RTC_ALRMBR_HT_Pos              (20U)
7377 #define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
7378 #define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!< Alarm B hour tens in BCD format */
7379 #define RTC_ALRMBR_HT_0                (0x1U << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
7380 #define RTC_ALRMBR_HT_1                (0x2U << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
7381 #define RTC_ALRMBR_HU_Pos              (16U)
7382 #define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
7383 #define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!< Alarm B hour units in BCD format */
7384 #define RTC_ALRMBR_HU_0                (0x1U << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
7385 #define RTC_ALRMBR_HU_1                (0x2U << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
7386 #define RTC_ALRMBR_HU_2                (0x4U << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
7387 #define RTC_ALRMBR_HU_3                (0x8U << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
7388 #define RTC_ALRMBR_MSK2_Pos            (15U)
7389 #define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
7390 #define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!< Alarm B minutes mask */
7391 #define RTC_ALRMBR_MNT_Pos             (12U)
7392 #define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
7393 #define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!< Alarm B minute tens in BCD format */
7394 #define RTC_ALRMBR_MNT_0               (0x1U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
7395 #define RTC_ALRMBR_MNT_1               (0x2U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
7396 #define RTC_ALRMBR_MNT_2               (0x4U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
7397 #define RTC_ALRMBR_MNU_Pos             (8U)
7398 #define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
7399 #define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!< Alarm B minute units in BCD format */
7400 #define RTC_ALRMBR_MNU_0               (0x1U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
7401 #define RTC_ALRMBR_MNU_1               (0x2U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
7402 #define RTC_ALRMBR_MNU_2               (0x4U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
7403 #define RTC_ALRMBR_MNU_3               (0x8U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
7404 #define RTC_ALRMBR_MSK1_Pos            (7U)
7405 #define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
7406 #define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!< Alarm B seconds mask */
7407 #define RTC_ALRMBR_ST_Pos              (4U)
7408 #define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
7409 #define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!< Alarm B second tens in BCD format */
7410 #define RTC_ALRMBR_ST_0                (0x1U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
7411 #define RTC_ALRMBR_ST_1                (0x2U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
7412 #define RTC_ALRMBR_ST_2                (0x4U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
7413 #define RTC_ALRMBR_SU_Pos              (0U)
7414 #define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
7415 #define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!< Alarm B second units in BCD format */
7416 #define RTC_ALRMBR_SU_0                (0x1U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
7417 #define RTC_ALRMBR_SU_1                (0x2U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
7418 #define RTC_ALRMBR_SU_2                (0x4U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
7419 #define RTC_ALRMBR_SU_3                (0x8U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
7420 
7421 /********************  Bits definition for RTC_WPR register  ******************/
7422 #define RTC_WPR_KEY_Pos                (0U)
7423 #define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
7424 #define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!< Write protection key */
7425 
7426 /********************  Bits definition for RTC_SSR register  ******************/
7427 #define RTC_SSR_SS_Pos                 (0U)
7428 #define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */
7429 #define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!< Sub second value */
7430 
7431 /********************  Bits definition for RTC_SHIFTR register  ***************/
7432 #define RTC_SHIFTR_SUBFS_Pos           (0U)
7433 #define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
7434 #define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!< Subtract a fraction of a second */
7435 #define RTC_SHIFTR_ADD1S_Pos           (31U)
7436 #define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
7437 #define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!< Add on second */
7438 
7439 /********************  Bits definition for RTC_TSTR register  *****************/
7440 #define RTC_TSTR_PM_Pos                (22U)
7441 #define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
7442 #define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!< Timestamp AM/PM or 24H format */
7443 #define RTC_TSTR_HT_Pos                (20U)
7444 #define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
7445 #define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!< Timestamp hour tens in BCD format */
7446 #define RTC_TSTR_HT_0                  (0x1U << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
7447 #define RTC_TSTR_HT_1                  (0x2U << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
7448 #define RTC_TSTR_HU_Pos                (16U)
7449 #define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
7450 #define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!< Timestamp hour units in BCD format */
7451 #define RTC_TSTR_HU_0                  (0x1U << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
7452 #define RTC_TSTR_HU_1                  (0x2U << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
7453 #define RTC_TSTR_HU_2                  (0x4U << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
7454 #define RTC_TSTR_HU_3                  (0x8U << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
7455 #define RTC_TSTR_MNT_Pos               (12U)
7456 #define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
7457 #define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!< Timestamp minute tens in BCD format */
7458 #define RTC_TSTR_MNT_0                 (0x1U << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
7459 #define RTC_TSTR_MNT_1                 (0x2U << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
7460 #define RTC_TSTR_MNT_2                 (0x4U << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
7461 #define RTC_TSTR_MNU_Pos               (8U)
7462 #define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
7463 #define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!< Timestamp minute units in BCD format */
7464 #define RTC_TSTR_MNU_0                 (0x1U << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
7465 #define RTC_TSTR_MNU_1                 (0x2U << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
7466 #define RTC_TSTR_MNU_2                 (0x4U << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
7467 #define RTC_TSTR_MNU_3                 (0x8U << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
7468 #define RTC_TSTR_ST_Pos                (4U)
7469 #define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
7470 #define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!< Timestamp second tens in BCD format */
7471 #define RTC_TSTR_ST_0                  (0x1U << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
7472 #define RTC_TSTR_ST_1                  (0x2U << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
7473 #define RTC_TSTR_ST_2                  (0x4U << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
7474 #define RTC_TSTR_SU_Pos                (0U)
7475 #define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
7476 #define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!< Timestamp second units in BCD format */
7477 #define RTC_TSTR_SU_0                  (0x1U << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
7478 #define RTC_TSTR_SU_1                  (0x2U << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
7479 #define RTC_TSTR_SU_2                  (0x4U << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
7480 #define RTC_TSTR_SU_3                  (0x8U << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
7481 
7482 /********************  Bits definition for RTC_TSDR register  *****************/
7483 #define RTC_TSDR_WDU_Pos               (13U)
7484 #define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
7485 #define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!< Timestamp week day units */
7486 #define RTC_TSDR_WDU_0                 (0x1U << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
7487 #define RTC_TSDR_WDU_1                 (0x2U << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
7488 #define RTC_TSDR_WDU_2                 (0x4U << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
7489 #define RTC_TSDR_MT_Pos                (12U)
7490 #define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
7491 #define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!< Timestamp month tens in BCD format */
7492 #define RTC_TSDR_MU_Pos                (8U)
7493 #define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
7494 #define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!< Timestamp month units in BCD format */
7495 #define RTC_TSDR_MU_0                  (0x1U << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
7496 #define RTC_TSDR_MU_1                  (0x2U << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
7497 #define RTC_TSDR_MU_2                  (0x4U << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
7498 #define RTC_TSDR_MU_3                  (0x8U << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
7499 #define RTC_TSDR_DT_Pos                (4U)
7500 #define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
7501 #define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!< Timestamp date tens in BCD format */
7502 #define RTC_TSDR_DT_0                  (0x1U << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
7503 #define RTC_TSDR_DT_1                  (0x2U << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
7504 #define RTC_TSDR_DU_Pos                (0U)
7505 #define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
7506 #define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!< Timestamp date units in BCD format */
7507 #define RTC_TSDR_DU_0                  (0x1U << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
7508 #define RTC_TSDR_DU_1                  (0x2U << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
7509 #define RTC_TSDR_DU_2                  (0x4U << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
7510 #define RTC_TSDR_DU_3                  (0x8U << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
7511 
7512 /********************  Bits definition for RTC_TSSSR register  ****************/
7513 #define RTC_TSSSR_SS_Pos               (0U)
7514 #define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */
7515 #define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        /*!< Timestamp sub second value */
7516 
7517 /********************  Bits definition for RTC_CALR register  *****************/
7518 #define RTC_CALR_CALP_Pos              (15U)
7519 #define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
7520 #define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!< Increase frequency of RTC 488.5 ppm */
7521 #define RTC_CALR_CALW8_Pos             (14U)
7522 #define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
7523 #define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!< Use a 8-second calibration cycle period */
7524 #define RTC_CALR_CALW16_Pos            (13U)
7525 #define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
7526 #define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!< Use a 16-second calibration cycle period */
7527 #define RTC_CALR_CALM_Pos              (0U)
7528 #define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
7529 #define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!< Calibration minus */
7530 #define RTC_CALR_CALM_0                (0x001U << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
7531 #define RTC_CALR_CALM_1                (0x002U << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
7532 #define RTC_CALR_CALM_2                (0x004U << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
7533 #define RTC_CALR_CALM_3                (0x008U << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
7534 #define RTC_CALR_CALM_4                (0x010U << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
7535 #define RTC_CALR_CALM_5                (0x020U << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
7536 #define RTC_CALR_CALM_6                (0x040U << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
7537 #define RTC_CALR_CALM_7                (0x080U << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
7538 #define RTC_CALR_CALM_8                (0x100U << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
7539 
7540 /********************  Bits definition for RTC_TAMPCR register  ****************/
7541 #define RTC_TAMPCR_TAMP2MF_Pos         (21U)
7542 #define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */
7543 #define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!< Tamper 2 generates a trigger event */
7544 #define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)
7545 #define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */
7546 #define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!< Tamper 2 no erase backup registers */
7547 #define RTC_TAMPCR_TAMP2IE_Pos         (19U)
7548 #define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */
7549 #define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!< Tamper 2 interrupt enable */
7550 #define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)
7551 #define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */
7552 #define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!< RTC_TAMPx pull-up disable */
7553 #define RTC_TAMPCR_TAMPPRCH_Pos        (13U)
7554 #define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */
7555 #define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!< RTC_TAMPx precharge duration */
7556 #define RTC_TAMPCR_TAMPPRCH_0          (0x1U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
7557 #define RTC_TAMPCR_TAMPPRCH_1          (0x2U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
7558 #define RTC_TAMPCR_TAMPFLT_Pos         (11U)
7559 #define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */
7560 #define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!< RTC_TAMPx filter count */
7561 #define RTC_TAMPCR_TAMPFLT_0           (0x1U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
7562 #define RTC_TAMPCR_TAMPFLT_1           (0x2U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
7563 #define RTC_TAMPCR_TAMPFREQ_Pos        (8U)
7564 #define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */
7565 #define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!< Tamper sampling frequency */
7566 #define RTC_TAMPCR_TAMPFREQ_0          (0x1U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
7567 #define RTC_TAMPCR_TAMPFREQ_1          (0x2U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
7568 #define RTC_TAMPCR_TAMPFREQ_2          (0x4U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
7569 #define RTC_TAMPCR_TAMPTS_Pos          (7U)
7570 #define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */
7571 #define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!< Activate timestamp on tamper detection event */
7572 #define RTC_TAMPCR_TAMP2TRG_Pos        (4U)
7573 #define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */
7574 #define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!< Active level for RTC_TAMP2 input */
7575 #define RTC_TAMPCR_TAMP2E_Pos          (3U)
7576 #define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */
7577 #define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!< RTC_TAMP2 detection enable */
7578 #define RTC_TAMPCR_TAMPIE_Pos          (2U)
7579 #define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */
7580 #define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!< Tampers interrupt enable */
7581 
7582 /********************  Bits definition for RTC_ALRMASSR register  *************/
7583 #define RTC_ALRMASSR_MASKSS_Pos        (24U)
7584 #define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */
7585 #define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 /*!< Alarm A mask the most-significant bits starting at this bit */
7586 #define RTC_ALRMASSR_MASKSS_0          (0x1U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
7587 #define RTC_ALRMASSR_MASKSS_1          (0x2U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
7588 #define RTC_ALRMASSR_MASKSS_2          (0x4U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
7589 #define RTC_ALRMASSR_MASKSS_3          (0x8U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
7590 #define RTC_ALRMASSR_SS_Pos            (0U)                                    /*!< Alarm A sub seconds value*/
7591 #define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
7592 #define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk
7593 
7594 /********************  Bits definition for RTC_ALRMBSSR register  *************/
7595 #define RTC_ALRMBSSR_MASKSS_Pos        (24U)
7596 #define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */
7597 #define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 /*!< Alarm B mask the most-significant bits starting at this bit */
7598 #define RTC_ALRMBSSR_MASKSS_0          (0x1U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
7599 #define RTC_ALRMBSSR_MASKSS_1          (0x2U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
7600 #define RTC_ALRMBSSR_MASKSS_2          (0x4U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
7601 #define RTC_ALRMBSSR_MASKSS_3          (0x8U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
7602 #define RTC_ALRMBSSR_SS_Pos            (0U)                                    /*!< Alarm B sub seconds value*/
7603 #define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
7604 #define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk
7605 
7606 /********************  Bits definition for RTC_OR register  ****************/
7607 #define RTC_OR_OUT_RMP_Pos             (1U)
7608 #define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)       /*!< 0x00000002 */
7609 #define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                  /*!< RTC_OUT remap */
7610 
7611 /********************  Bits definition for RTC_BKP0R register  ****************/
7612 #define RTC_BKP0R_Pos                  (0U)
7613 #define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */
7614 #define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!< RTC backup register 0 */
7615 
7616 /********************  Bits definition for RTC_BKP1R register  ****************/
7617 #define RTC_BKP1R_Pos                  (0U)
7618 #define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */
7619 #define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!< RTC backup register 1 */
7620 
7621 /********************  Bits definition for RTC_BKP2R register  ****************/
7622 #define RTC_BKP2R_Pos                  (0U)
7623 #define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */
7624 #define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!< RTC backup register 2 */
7625 
7626 /********************  Bits definition for RTC_BKP3R register  ****************/
7627 #define RTC_BKP3R_Pos                  (0U)
7628 #define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */
7629 #define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!< RTC backup register 3 */
7630 
7631 /********************  Bits definition for RTC_BKP4R register  ****************/
7632 #define RTC_BKP4R_Pos                  (0U)
7633 #define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */
7634 #define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!< RTC backup register 4 */
7635 
7636 /********************  Bits definition for RTC_BKP5R register  ****************/
7637 #define RTC_BKP5R_Pos                  (0U)
7638 #define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */
7639 #define RTC_BKP5R                      RTC_BKP5R_Msk                           /*!< RTC backup register 5 */
7640 
7641 /********************  Bits definition for RTC_BKP6R register  ****************/
7642 #define RTC_BKP6R_Pos                  (0U)
7643 #define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */
7644 #define RTC_BKP6R                      RTC_BKP6R_Msk                           /*!< RTC backup register 6 */
7645 
7646 /********************  Bits definition for RTC_BKP7R register  ****************/
7647 #define RTC_BKP7R_Pos                  (0U)
7648 #define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */
7649 #define RTC_BKP7R                      RTC_BKP7R_Msk                           /*!< RTC backup register 7 */
7650 
7651 /********************  Bits definition for RTC_BKP8R register  ****************/
7652 #define RTC_BKP8R_Pos                  (0U)
7653 #define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */
7654 #define RTC_BKP8R                      RTC_BKP8R_Msk                           /*!< RTC backup register 8 */
7655 
7656 /********************  Bits definition for RTC_BKP9R register  ****************/
7657 #define RTC_BKP9R_Pos                  (0U)
7658 #define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */
7659 #define RTC_BKP9R                      RTC_BKP9R_Msk                           /*!< RTC backup register 9 */
7660 
7661 /********************  Bits definition for RTC_BKP10R register  ***************/
7662 #define RTC_BKP10R_Pos                 (0U)
7663 #define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */
7664 #define RTC_BKP10R                     RTC_BKP10R_Msk                          /*!< RTC backup register 10 */
7665 
7666 /********************  Bits definition for RTC_BKP11R register  ***************/
7667 #define RTC_BKP11R_Pos                 (0U)
7668 #define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */
7669 #define RTC_BKP11R                     RTC_BKP11R_Msk                          /*!< RTC backup register 11 */
7670 
7671 /********************  Bits definition for RTC_BKP12R register  ***************/
7672 #define RTC_BKP12R_Pos                 (0U)
7673 #define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */
7674 #define RTC_BKP12R                     RTC_BKP12R_Msk                          /*!< RTC backup register 12 */
7675 
7676 /********************  Bits definition for RTC_BKP13R register  ***************/
7677 #define RTC_BKP13R_Pos                 (0U)
7678 #define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */
7679 #define RTC_BKP13R                     RTC_BKP13R_Msk                          /*!< RTC backup register 13 */
7680 
7681 /********************  Bits definition for RTC_BKP14R register  ***************/
7682 #define RTC_BKP14R_Pos                 (0U)
7683 #define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */
7684 #define RTC_BKP14R                     RTC_BKP14R_Msk                          /*!< RTC backup register 14 */
7685 
7686 /********************  Bits definition for RTC_BKP15R register  ***************/
7687 #define RTC_BKP15R_Pos                 (0U)
7688 #define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */
7689 #define RTC_BKP15R                     RTC_BKP15R_Msk                          /*!< RTC backup register 15 */
7690 
7691 /********************  Bits definition for RTC_BKP16R register  ***************/
7692 #define RTC_BKP16R_Pos                 (0U)
7693 #define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */
7694 #define RTC_BKP16R                     RTC_BKP16R_Msk                          /*!< RTC backup register 16 */
7695 
7696 /********************  Bits definition for RTC_BKP17R register  ***************/
7697 #define RTC_BKP17R_Pos                 (0U)
7698 #define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */
7699 #define RTC_BKP17R                     RTC_BKP17R_Msk                          /*!< RTC backup register 17 */
7700 
7701 /********************  Bits definition for RTC_BKP18R register  ***************/
7702 #define RTC_BKP18R_Pos                 (0U)
7703 #define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */
7704 #define RTC_BKP18R                     RTC_BKP18R_Msk                          /*!< RTC backup register 18 */
7705 
7706 /********************  Bits definition for RTC_BKP19R register  ***************/
7707 #define RTC_BKP19R_Pos                 (0U)
7708 #define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */
7709 #define RTC_BKP19R                     RTC_BKP19R_Msk                          /*!< RTC backup register 19 */
7710 
7711 /******************** Number of backup registers ******************************/
7712 #define RTC_BKP_NUMBER                 (20U)
7713 
7714 /******************************************************************************/
7715 /*                                                                            */
7716 /*                        Serial Peripheral Interface (SPI)                   */
7717 /*                                                                            */
7718 /******************************************************************************/
7719 /*******************  Bit definition for SPI_CR1 register  ********************/
7720 #define SPI_CR1_CPHA_Pos            (0U)
7721 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */
7722 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
7723 #define SPI_CR1_CPOL_Pos            (1U)
7724 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */
7725 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
7726 #define SPI_CR1_MSTR_Pos            (2U)
7727 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */
7728 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
7729 
7730 #define SPI_CR1_BR_Pos              (3U)
7731 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */
7732 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
7733 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */
7734 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */
7735 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */
7736 
7737 #define SPI_CR1_SPE_Pos             (6U)
7738 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */
7739 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
7740 #define SPI_CR1_LSBFIRST_Pos        (7U)
7741 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */
7742 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
7743 #define SPI_CR1_SSI_Pos             (8U)
7744 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */
7745 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
7746 #define SPI_CR1_SSM_Pos             (9U)
7747 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */
7748 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
7749 #define SPI_CR1_RXONLY_Pos          (10U)
7750 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */
7751 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
7752 #define SPI_CR1_CRCL_Pos            (11U)
7753 #define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */
7754 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
7755 #define SPI_CR1_CRCNEXT_Pos         (12U)
7756 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */
7757 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
7758 #define SPI_CR1_CRCEN_Pos           (13U)
7759 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */
7760 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
7761 #define SPI_CR1_BIDIOE_Pos          (14U)
7762 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */
7763 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
7764 #define SPI_CR1_BIDIMODE_Pos        (15U)
7765 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */
7766 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
7767 
7768 /*******************  Bit definition for SPI_CR2 register  ********************/
7769 #define SPI_CR2_RXDMAEN_Pos         (0U)
7770 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */
7771 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
7772 #define SPI_CR2_TXDMAEN_Pos         (1U)
7773 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */
7774 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
7775 #define SPI_CR2_SSOE_Pos            (2U)
7776 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */
7777 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
7778 #define SPI_CR2_NSSP_Pos            (3U)
7779 #define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */
7780 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
7781 #define SPI_CR2_FRF_Pos             (4U)
7782 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */
7783 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
7784 #define SPI_CR2_ERRIE_Pos           (5U)
7785 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */
7786 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
7787 #define SPI_CR2_RXNEIE_Pos          (6U)
7788 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */
7789 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
7790 #define SPI_CR2_TXEIE_Pos           (7U)
7791 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */
7792 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
7793 #define SPI_CR2_DS_Pos              (8U)
7794 #define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */
7795 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
7796 #define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */
7797 #define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */
7798 #define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */
7799 #define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */
7800 #define SPI_CR2_FRXTH_Pos           (12U)
7801 #define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */
7802 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
7803 #define SPI_CR2_LDMARX_Pos          (13U)
7804 #define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */
7805 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
7806 #define SPI_CR2_LDMATX_Pos          (14U)
7807 #define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */
7808 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
7809 
7810 /********************  Bit definition for SPI_SR register  ********************/
7811 #define SPI_SR_RXNE_Pos             (0U)
7812 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */
7813 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
7814 #define SPI_SR_TXE_Pos              (1U)
7815 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */
7816 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
7817 #define SPI_SR_CRCERR_Pos           (4U)
7818 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */
7819 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
7820 #define SPI_SR_MODF_Pos             (5U)
7821 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */
7822 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
7823 #define SPI_SR_OVR_Pos              (6U)
7824 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
7825 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
7826 #define SPI_SR_BSY_Pos              (7U)
7827 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */
7828 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
7829 #define SPI_SR_FRE_Pos              (8U)
7830 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */
7831 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
7832 #define SPI_SR_FRLVL_Pos            (9U)
7833 #define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */
7834 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
7835 #define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */
7836 #define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */
7837 #define SPI_SR_FTLVL_Pos            (11U)
7838 #define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */
7839 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
7840 #define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */
7841 #define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */
7842 
7843 /********************  Bit definition for SPI_DR register  ********************/
7844 #define SPI_DR_DR_Pos               (0U)
7845 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */
7846 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
7847 
7848 /*******************  Bit definition for SPI_CRCPR register  ******************/
7849 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
7850 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */
7851 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
7852 
7853 /******************  Bit definition for SPI_RXCRCR register  ******************/
7854 #define SPI_RXCRCR_RXCRC_Pos        (0U)
7855 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */
7856 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
7857 
7858 /******************  Bit definition for SPI_TXCRCR register  ******************/
7859 #define SPI_TXCRCR_TXCRC_Pos        (0U)
7860 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */
7861 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
7862 
7863 /******************************************************************************/
7864 /*                                                                            */
7865 /*                          Touch Sensing Controller (TSC)                    */
7866 /*                                                                            */
7867 /******************************************************************************/
7868 /*******************  Bit definition for TSC_CR register  *********************/
7869 #define TSC_CR_TSCE_Pos          (0U)
7870 #define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                    /*!< 0x00000001 */
7871 #define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!< Touch sensing controller enable */
7872 #define TSC_CR_START_Pos         (1U)
7873 #define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                   /*!< 0x00000002 */
7874 #define TSC_CR_START             TSC_CR_START_Msk                              /*!< Start a new acquisition */
7875 #define TSC_CR_AM_Pos            (2U)
7876 #define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                      /*!< 0x00000004 */
7877 #define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!< Acquisition mode */
7878 #define TSC_CR_SYNCPOL_Pos       (3U)
7879 #define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                 /*!< 0x00000008 */
7880 #define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!< Synchronization pin polarity */
7881 #define TSC_CR_IODEF_Pos         (4U)
7882 #define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                   /*!< 0x00000010 */
7883 #define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!< IO default mode */
7884 
7885 #define TSC_CR_MCV_Pos           (5U)
7886 #define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                     /*!< 0x000000E0 */
7887 #define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!< MCV[2:0] bits (Max Count Value) */
7888 #define TSC_CR_MCV_0             (0x1U << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
7889 #define TSC_CR_MCV_1             (0x2U << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
7890 #define TSC_CR_MCV_2             (0x4U << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
7891 
7892 #define TSC_CR_PGPSC_Pos         (12U)
7893 #define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00007000 */
7894 #define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!< PGPSC[2:0] bits (Pulse Generator Prescaler) */
7895 #define TSC_CR_PGPSC_0           (0x1U << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
7896 #define TSC_CR_PGPSC_1           (0x2U << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
7897 #define TSC_CR_PGPSC_2           (0x4U << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
7898 
7899 #define TSC_CR_SSPSC_Pos         (15U)
7900 #define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                   /*!< 0x00008000 */
7901 #define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!< Spread Spectrum Prescaler */
7902 #define TSC_CR_SSE_Pos           (16U)
7903 #define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                     /*!< 0x00010000 */
7904 #define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!< Spread Spectrum Enable */
7905 
7906 #define TSC_CR_SSD_Pos           (17U)
7907 #define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                    /*!< 0x00FE0000 */
7908 #define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!< SSD[6:0] bits (Spread Spectrum Deviation) */
7909 #define TSC_CR_SSD_0             (0x01U << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
7910 #define TSC_CR_SSD_1             (0x02U << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
7911 #define TSC_CR_SSD_2             (0x04U << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
7912 #define TSC_CR_SSD_3             (0x08U << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
7913 #define TSC_CR_SSD_4             (0x10U << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
7914 #define TSC_CR_SSD_5             (0x20U << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
7915 #define TSC_CR_SSD_6             (0x40U << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
7916 
7917 #define TSC_CR_CTPL_Pos          (24U)
7918 #define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                    /*!< 0x0F000000 */
7919 #define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!< CTPL[3:0] bits (Charge Transfer pulse low) */
7920 #define TSC_CR_CTPL_0            (0x1U << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
7921 #define TSC_CR_CTPL_1            (0x2U << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
7922 #define TSC_CR_CTPL_2            (0x4U << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
7923 #define TSC_CR_CTPL_3            (0x8U << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
7924 
7925 #define TSC_CR_CTPH_Pos          (28U)
7926 #define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                    /*!< 0xF0000000 */
7927 #define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!< CTPH[3:0] bits (Charge Transfer pulse high) */
7928 #define TSC_CR_CTPH_0            (0x1U << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
7929 #define TSC_CR_CTPH_1            (0x2U << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
7930 #define TSC_CR_CTPH_2            (0x4U << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
7931 #define TSC_CR_CTPH_3            (0x8U << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
7932 
7933 /*******************  Bit definition for TSC_IER register  ********************/
7934 #define TSC_IER_EOAIE_Pos        (0U)
7935 #define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                  /*!< 0x00000001 */
7936 #define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!< End of acquisition interrupt enable */
7937 #define TSC_IER_MCEIE_Pos        (1U)
7938 #define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                  /*!< 0x00000002 */
7939 #define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!< Max count error interrupt enable */
7940 
7941 /*******************  Bit definition for TSC_ICR register  ********************/
7942 #define TSC_ICR_EOAIC_Pos        (0U)
7943 #define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                  /*!< 0x00000001 */
7944 #define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!< End of acquisition interrupt clear */
7945 #define TSC_ICR_MCEIC_Pos        (1U)
7946 #define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                  /*!< 0x00000002 */
7947 #define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!< Max count error interrupt clear */
7948 
7949 /*******************  Bit definition for TSC_ISR register  ********************/
7950 #define TSC_ISR_EOAF_Pos         (0U)
7951 #define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                   /*!< 0x00000001 */
7952 #define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!< End of acquisition flag */
7953 #define TSC_ISR_MCEF_Pos         (1U)
7954 #define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                   /*!< 0x00000002 */
7955 #define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!< Max count error flag */
7956 
7957 /*******************  Bit definition for TSC_IOHCR register  ******************/
7958 #define TSC_IOHCR_G1_IO1_Pos     (0U)
7959 #define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)               /*!< 0x00000001 */
7960 #define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!< GROUP1_IO1 schmitt trigger hysteresis mode */
7961 #define TSC_IOHCR_G1_IO2_Pos     (1U)
7962 #define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)               /*!< 0x00000002 */
7963 #define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!< GROUP1_IO2 schmitt trigger hysteresis mode */
7964 #define TSC_IOHCR_G1_IO3_Pos     (2U)
7965 #define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)               /*!< 0x00000004 */
7966 #define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!< GROUP1_IO3 schmitt trigger hysteresis mode */
7967 #define TSC_IOHCR_G1_IO4_Pos     (3U)
7968 #define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)               /*!< 0x00000008 */
7969 #define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!< GROUP1_IO4 schmitt trigger hysteresis mode */
7970 #define TSC_IOHCR_G2_IO1_Pos     (4U)
7971 #define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)               /*!< 0x00000010 */
7972 #define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!< GROUP2_IO1 schmitt trigger hysteresis mode */
7973 #define TSC_IOHCR_G2_IO2_Pos     (5U)
7974 #define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)               /*!< 0x00000020 */
7975 #define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!< GROUP2_IO2 schmitt trigger hysteresis mode */
7976 #define TSC_IOHCR_G2_IO3_Pos     (6U)
7977 #define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)               /*!< 0x00000040 */
7978 #define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!< GROUP2_IO3 schmitt trigger hysteresis mode */
7979 #define TSC_IOHCR_G2_IO4_Pos     (7U)
7980 #define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)               /*!< 0x00000080 */
7981 #define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!< GROUP2_IO4 schmitt trigger hysteresis mode */
7982 #define TSC_IOHCR_G3_IO1_Pos     (8U)
7983 #define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)               /*!< 0x00000100 */
7984 #define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!< GROUP3_IO1 schmitt trigger hysteresis mode */
7985 #define TSC_IOHCR_G3_IO2_Pos     (9U)
7986 #define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)               /*!< 0x00000200 */
7987 #define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!< GROUP3_IO2 schmitt trigger hysteresis mode */
7988 #define TSC_IOHCR_G3_IO3_Pos     (10U)
7989 #define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)               /*!< 0x00000400 */
7990 #define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!< GROUP3_IO3 schmitt trigger hysteresis mode */
7991 #define TSC_IOHCR_G3_IO4_Pos     (11U)
7992 #define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)               /*!< 0x00000800 */
7993 #define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!< GROUP3_IO4 schmitt trigger hysteresis mode */
7994 #define TSC_IOHCR_G4_IO1_Pos     (12U)
7995 #define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)               /*!< 0x00001000 */
7996 #define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!< GROUP4_IO1 schmitt trigger hysteresis mode */
7997 #define TSC_IOHCR_G4_IO2_Pos     (13U)
7998 #define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)               /*!< 0x00002000 */
7999 #define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!< GROUP4_IO2 schmitt trigger hysteresis mode */
8000 #define TSC_IOHCR_G4_IO3_Pos     (14U)
8001 #define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)               /*!< 0x00004000 */
8002 #define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!< GROUP4_IO3 schmitt trigger hysteresis mode */
8003 #define TSC_IOHCR_G4_IO4_Pos     (15U)
8004 #define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)               /*!< 0x00008000 */
8005 #define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!< GROUP4_IO4 schmitt trigger hysteresis mode */
8006 #define TSC_IOHCR_G5_IO1_Pos     (16U)
8007 #define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)               /*!< 0x00010000 */
8008 #define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!< GROUP5_IO1 schmitt trigger hysteresis mode */
8009 #define TSC_IOHCR_G5_IO2_Pos     (17U)
8010 #define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)               /*!< 0x00020000 */
8011 #define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!< GROUP5_IO2 schmitt trigger hysteresis mode */
8012 #define TSC_IOHCR_G5_IO3_Pos     (18U)
8013 #define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)               /*!< 0x00040000 */
8014 #define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!< GROUP5_IO3 schmitt trigger hysteresis mode */
8015 #define TSC_IOHCR_G5_IO4_Pos     (19U)
8016 #define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)               /*!< 0x00080000 */
8017 #define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!< GROUP5_IO4 schmitt trigger hysteresis mode */
8018 #define TSC_IOHCR_G6_IO1_Pos     (20U)
8019 #define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)               /*!< 0x00100000 */
8020 #define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!< GROUP6_IO1 schmitt trigger hysteresis mode */
8021 #define TSC_IOHCR_G6_IO2_Pos     (21U)
8022 #define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)               /*!< 0x00200000 */
8023 #define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!< GROUP6_IO2 schmitt trigger hysteresis mode */
8024 #define TSC_IOHCR_G6_IO3_Pos     (22U)
8025 #define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)               /*!< 0x00400000 */
8026 #define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!< GROUP6_IO3 schmitt trigger hysteresis mode */
8027 #define TSC_IOHCR_G6_IO4_Pos     (23U)
8028 #define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)               /*!< 0x00800000 */
8029 #define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!< GROUP6_IO4 schmitt trigger hysteresis mode */
8030 #define TSC_IOHCR_G7_IO1_Pos     (24U)
8031 #define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)               /*!< 0x01000000 */
8032 #define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!< GROUP7_IO1 schmitt trigger hysteresis mode */
8033 #define TSC_IOHCR_G7_IO2_Pos     (25U)
8034 #define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)               /*!< 0x02000000 */
8035 #define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!< GROUP7_IO2 schmitt trigger hysteresis mode */
8036 #define TSC_IOHCR_G7_IO3_Pos     (26U)
8037 #define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)               /*!< 0x04000000 */
8038 #define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!< GROUP7_IO3 schmitt trigger hysteresis mode */
8039 #define TSC_IOHCR_G7_IO4_Pos     (27U)
8040 #define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)               /*!< 0x08000000 */
8041 #define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!< GROUP7_IO4 schmitt trigger hysteresis mode */
8042 
8043 /*******************  Bit definition for TSC_IOASCR register  *****************/
8044 #define TSC_IOASCR_G1_IO1_Pos    (0U)
8045 #define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)              /*!< 0x00000001 */
8046 #define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!< GROUP1_IO1 analog switch enable */
8047 #define TSC_IOASCR_G1_IO2_Pos    (1U)
8048 #define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)              /*!< 0x00000002 */
8049 #define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!< GROUP1_IO2 analog switch enable */
8050 #define TSC_IOASCR_G1_IO3_Pos    (2U)
8051 #define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)              /*!< 0x00000004 */
8052 #define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!< GROUP1_IO3 analog switch enable */
8053 #define TSC_IOASCR_G1_IO4_Pos    (3U)
8054 #define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)              /*!< 0x00000008 */
8055 #define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!< GROUP1_IO4 analog switch enable */
8056 #define TSC_IOASCR_G2_IO1_Pos    (4U)
8057 #define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)              /*!< 0x00000010 */
8058 #define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!< GROUP2_IO1 analog switch enable */
8059 #define TSC_IOASCR_G2_IO2_Pos    (5U)
8060 #define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)              /*!< 0x00000020 */
8061 #define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!< GROUP2_IO2 analog switch enable */
8062 #define TSC_IOASCR_G2_IO3_Pos    (6U)
8063 #define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)              /*!< 0x00000040 */
8064 #define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!< GROUP2_IO3 analog switch enable */
8065 #define TSC_IOASCR_G2_IO4_Pos    (7U)
8066 #define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)              /*!< 0x00000080 */
8067 #define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!< GROUP2_IO4 analog switch enable */
8068 #define TSC_IOASCR_G3_IO1_Pos    (8U)
8069 #define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)              /*!< 0x00000100 */
8070 #define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!< GROUP3_IO1 analog switch enable */
8071 #define TSC_IOASCR_G3_IO2_Pos    (9U)
8072 #define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)              /*!< 0x00000200 */
8073 #define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!< GROUP3_IO2 analog switch enable */
8074 #define TSC_IOASCR_G3_IO3_Pos    (10U)
8075 #define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)              /*!< 0x00000400 */
8076 #define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!< GROUP3_IO3 analog switch enable */
8077 #define TSC_IOASCR_G3_IO4_Pos    (11U)
8078 #define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)              /*!< 0x00000800 */
8079 #define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!< GROUP3_IO4 analog switch enable */
8080 #define TSC_IOASCR_G4_IO1_Pos    (12U)
8081 #define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)              /*!< 0x00001000 */
8082 #define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!< GROUP4_IO1 analog switch enable */
8083 #define TSC_IOASCR_G4_IO2_Pos    (13U)
8084 #define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)              /*!< 0x00002000 */
8085 #define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!< GROUP4_IO2 analog switch enable */
8086 #define TSC_IOASCR_G4_IO3_Pos    (14U)
8087 #define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)              /*!< 0x00004000 */
8088 #define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!< GROUP4_IO3 analog switch enable */
8089 #define TSC_IOASCR_G4_IO4_Pos    (15U)
8090 #define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)              /*!< 0x00008000 */
8091 #define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!< GROUP4_IO4 analog switch enable */
8092 #define TSC_IOASCR_G5_IO1_Pos    (16U)
8093 #define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)              /*!< 0x00010000 */
8094 #define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!< GROUP5_IO1 analog switch enable */
8095 #define TSC_IOASCR_G5_IO2_Pos    (17U)
8096 #define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)              /*!< 0x00020000 */
8097 #define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!< GROUP5_IO2 analog switch enable */
8098 #define TSC_IOASCR_G5_IO3_Pos    (18U)
8099 #define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)              /*!< 0x00040000 */
8100 #define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!< GROUP5_IO3 analog switch enable */
8101 #define TSC_IOASCR_G5_IO4_Pos    (19U)
8102 #define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)              /*!< 0x00080000 */
8103 #define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!< GROUP5_IO4 analog switch enable */
8104 #define TSC_IOASCR_G6_IO1_Pos    (20U)
8105 #define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)              /*!< 0x00100000 */
8106 #define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!< GROUP6_IO1 analog switch enable */
8107 #define TSC_IOASCR_G6_IO2_Pos    (21U)
8108 #define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)              /*!< 0x00200000 */
8109 #define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!< GROUP6_IO2 analog switch enable */
8110 #define TSC_IOASCR_G6_IO3_Pos    (22U)
8111 #define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)              /*!< 0x00400000 */
8112 #define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!< GROUP6_IO3 analog switch enable */
8113 #define TSC_IOASCR_G6_IO4_Pos    (23U)
8114 #define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)              /*!< 0x00800000 */
8115 #define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!< GROUP6_IO4 analog switch enable */
8116 #define TSC_IOASCR_G7_IO1_Pos    (24U)
8117 #define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)              /*!< 0x01000000 */
8118 #define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!< GROUP7_IO1 analog switch enable */
8119 #define TSC_IOASCR_G7_IO2_Pos    (25U)
8120 #define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)              /*!< 0x02000000 */
8121 #define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!< GROUP7_IO2 analog switch enable */
8122 #define TSC_IOASCR_G7_IO3_Pos    (26U)
8123 #define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)              /*!< 0x04000000 */
8124 #define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!< GROUP7_IO3 analog switch enable */
8125 #define TSC_IOASCR_G7_IO4_Pos    (27U)
8126 #define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)              /*!< 0x08000000 */
8127 #define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!< GROUP7_IO4 analog switch enable */
8128 
8129 /*******************  Bit definition for TSC_IOSCR register  ******************/
8130 #define TSC_IOSCR_G1_IO1_Pos     (0U)
8131 #define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)               /*!< 0x00000001 */
8132 #define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!< GROUP1_IO1 sampling mode */
8133 #define TSC_IOSCR_G1_IO2_Pos     (1U)
8134 #define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)               /*!< 0x00000002 */
8135 #define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!< GROUP1_IO2 sampling mode */
8136 #define TSC_IOSCR_G1_IO3_Pos     (2U)
8137 #define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)               /*!< 0x00000004 */
8138 #define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!< GROUP1_IO3 sampling mode */
8139 #define TSC_IOSCR_G1_IO4_Pos     (3U)
8140 #define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)               /*!< 0x00000008 */
8141 #define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!< GROUP1_IO4 sampling mode */
8142 #define TSC_IOSCR_G2_IO1_Pos     (4U)
8143 #define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)               /*!< 0x00000010 */
8144 #define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!< GROUP2_IO1 sampling mode */
8145 #define TSC_IOSCR_G2_IO2_Pos     (5U)
8146 #define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)               /*!< 0x00000020 */
8147 #define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!< GROUP2_IO2 sampling mode */
8148 #define TSC_IOSCR_G2_IO3_Pos     (6U)
8149 #define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)               /*!< 0x00000040 */
8150 #define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!< GROUP2_IO3 sampling mode */
8151 #define TSC_IOSCR_G2_IO4_Pos     (7U)
8152 #define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)               /*!< 0x00000080 */
8153 #define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!< GROUP2_IO4 sampling mode */
8154 #define TSC_IOSCR_G3_IO1_Pos     (8U)
8155 #define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)               /*!< 0x00000100 */
8156 #define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!< GROUP3_IO1 sampling mode */
8157 #define TSC_IOSCR_G3_IO2_Pos     (9U)
8158 #define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)               /*!< 0x00000200 */
8159 #define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!< GROUP3_IO2 sampling mode */
8160 #define TSC_IOSCR_G3_IO3_Pos     (10U)
8161 #define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)               /*!< 0x00000400 */
8162 #define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!< GROUP3_IO3 sampling mode */
8163 #define TSC_IOSCR_G3_IO4_Pos     (11U)
8164 #define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)               /*!< 0x00000800 */
8165 #define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!< GROUP3_IO4 sampling mode */
8166 #define TSC_IOSCR_G4_IO1_Pos     (12U)
8167 #define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)               /*!< 0x00001000 */
8168 #define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!< GROUP4_IO1 sampling mode */
8169 #define TSC_IOSCR_G4_IO2_Pos     (13U)
8170 #define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)               /*!< 0x00002000 */
8171 #define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!< GROUP4_IO2 sampling mode */
8172 #define TSC_IOSCR_G4_IO3_Pos     (14U)
8173 #define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)               /*!< 0x00004000 */
8174 #define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!< GROUP4_IO3 sampling mode */
8175 #define TSC_IOSCR_G4_IO4_Pos     (15U)
8176 #define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)               /*!< 0x00008000 */
8177 #define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!< GROUP4_IO4 sampling mode */
8178 #define TSC_IOSCR_G5_IO1_Pos     (16U)
8179 #define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)               /*!< 0x00010000 */
8180 #define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!< GROUP5_IO1 sampling mode */
8181 #define TSC_IOSCR_G5_IO2_Pos     (17U)
8182 #define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)               /*!< 0x00020000 */
8183 #define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!< GROUP5_IO2 sampling mode */
8184 #define TSC_IOSCR_G5_IO3_Pos     (18U)
8185 #define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)               /*!< 0x00040000 */
8186 #define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!< GROUP5_IO3 sampling mode */
8187 #define TSC_IOSCR_G5_IO4_Pos     (19U)
8188 #define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)               /*!< 0x00080000 */
8189 #define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!< GROUP5_IO4 sampling mode */
8190 #define TSC_IOSCR_G6_IO1_Pos     (20U)
8191 #define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)               /*!< 0x00100000 */
8192 #define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!< GROUP6_IO1 sampling mode */
8193 #define TSC_IOSCR_G6_IO2_Pos     (21U)
8194 #define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)               /*!< 0x00200000 */
8195 #define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!< GROUP6_IO2 sampling mode */
8196 #define TSC_IOSCR_G6_IO3_Pos     (22U)
8197 #define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)               /*!< 0x00400000 */
8198 #define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!< GROUP6_IO3 sampling mode */
8199 #define TSC_IOSCR_G6_IO4_Pos     (23U)
8200 #define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)               /*!< 0x00800000 */
8201 #define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!< GROUP6_IO4 sampling mode */
8202 #define TSC_IOSCR_G7_IO1_Pos     (24U)
8203 #define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)               /*!< 0x01000000 */
8204 #define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!< GROUP7_IO1 sampling mode */
8205 #define TSC_IOSCR_G7_IO2_Pos     (25U)
8206 #define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)               /*!< 0x02000000 */
8207 #define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!< GROUP7_IO2 sampling mode */
8208 #define TSC_IOSCR_G7_IO3_Pos     (26U)
8209 #define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)               /*!< 0x04000000 */
8210 #define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!< GROUP7_IO3 sampling mode */
8211 #define TSC_IOSCR_G7_IO4_Pos     (27U)
8212 #define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)               /*!< 0x08000000 */
8213 #define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!< GROUP7_IO4 sampling mode */
8214 
8215 /*******************  Bit definition for TSC_IOCCR register  ******************/
8216 #define TSC_IOCCR_G1_IO1_Pos     (0U)
8217 #define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)               /*!< 0x00000001 */
8218 #define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!< GROUP1_IO1 channel mode */
8219 #define TSC_IOCCR_G1_IO2_Pos     (1U)
8220 #define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)               /*!< 0x00000002 */
8221 #define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!< GROUP1_IO2 channel mode */
8222 #define TSC_IOCCR_G1_IO3_Pos     (2U)
8223 #define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)               /*!< 0x00000004 */
8224 #define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!< GROUP1_IO3 channel mode */
8225 #define TSC_IOCCR_G1_IO4_Pos     (3U)
8226 #define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)               /*!< 0x00000008 */
8227 #define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!< GROUP1_IO4 channel mode */
8228 #define TSC_IOCCR_G2_IO1_Pos     (4U)
8229 #define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)               /*!< 0x00000010 */
8230 #define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!< GROUP2_IO1 channel mode */
8231 #define TSC_IOCCR_G2_IO2_Pos     (5U)
8232 #define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)               /*!< 0x00000020 */
8233 #define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!< GROUP2_IO2 channel mode */
8234 #define TSC_IOCCR_G2_IO3_Pos     (6U)
8235 #define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)               /*!< 0x00000040 */
8236 #define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!< GROUP2_IO3 channel mode */
8237 #define TSC_IOCCR_G2_IO4_Pos     (7U)
8238 #define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)               /*!< 0x00000080 */
8239 #define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!< GROUP2_IO4 channel mode */
8240 #define TSC_IOCCR_G3_IO1_Pos     (8U)
8241 #define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)               /*!< 0x00000100 */
8242 #define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!< GROUP3_IO1 channel mode */
8243 #define TSC_IOCCR_G3_IO2_Pos     (9U)
8244 #define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)               /*!< 0x00000200 */
8245 #define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!< GROUP3_IO2 channel mode */
8246 #define TSC_IOCCR_G3_IO3_Pos     (10U)
8247 #define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)               /*!< 0x00000400 */
8248 #define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!< GROUP3_IO3 channel mode */
8249 #define TSC_IOCCR_G3_IO4_Pos     (11U)
8250 #define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)               /*!< 0x00000800 */
8251 #define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!< GROUP3_IO4 channel mode */
8252 #define TSC_IOCCR_G4_IO1_Pos     (12U)
8253 #define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)               /*!< 0x00001000 */
8254 #define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!< GROUP4_IO1 channel mode */
8255 #define TSC_IOCCR_G4_IO2_Pos     (13U)
8256 #define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)               /*!< 0x00002000 */
8257 #define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!< GROUP4_IO2 channel mode */
8258 #define TSC_IOCCR_G4_IO3_Pos     (14U)
8259 #define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)               /*!< 0x00004000 */
8260 #define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!< GROUP4_IO3 channel mode */
8261 #define TSC_IOCCR_G4_IO4_Pos     (15U)
8262 #define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)               /*!< 0x00008000 */
8263 #define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!< GROUP4_IO4 channel mode */
8264 #define TSC_IOCCR_G5_IO1_Pos     (16U)
8265 #define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)               /*!< 0x00010000 */
8266 #define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!< GROUP5_IO1 channel mode */
8267 #define TSC_IOCCR_G5_IO2_Pos     (17U)
8268 #define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)               /*!< 0x00020000 */
8269 #define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!< GROUP5_IO2 channel mode */
8270 #define TSC_IOCCR_G5_IO3_Pos     (18U)
8271 #define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)               /*!< 0x00040000 */
8272 #define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!< GROUP5_IO3 channel mode */
8273 #define TSC_IOCCR_G5_IO4_Pos     (19U)
8274 #define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)               /*!< 0x00080000 */
8275 #define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!< GROUP5_IO4 channel mode */
8276 #define TSC_IOCCR_G6_IO1_Pos     (20U)
8277 #define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)               /*!< 0x00100000 */
8278 #define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!< GROUP6_IO1 channel mode */
8279 #define TSC_IOCCR_G6_IO2_Pos     (21U)
8280 #define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)               /*!< 0x00200000 */
8281 #define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!< GROUP6_IO2 channel mode */
8282 #define TSC_IOCCR_G6_IO3_Pos     (22U)
8283 #define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)               /*!< 0x00400000 */
8284 #define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!< GROUP6_IO3 channel mode */
8285 #define TSC_IOCCR_G6_IO4_Pos     (23U)
8286 #define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)               /*!< 0x00800000 */
8287 #define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!< GROUP6_IO4 channel mode */
8288 #define TSC_IOCCR_G7_IO1_Pos     (24U)
8289 #define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)               /*!< 0x01000000 */
8290 #define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!< GROUP7_IO1 channel mode */
8291 #define TSC_IOCCR_G7_IO2_Pos     (25U)
8292 #define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)               /*!< 0x02000000 */
8293 #define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!< GROUP7_IO2 channel mode */
8294 #define TSC_IOCCR_G7_IO3_Pos     (26U)
8295 #define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)               /*!< 0x04000000 */
8296 #define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!< GROUP7_IO3 channel mode */
8297 #define TSC_IOCCR_G7_IO4_Pos     (27U)
8298 #define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)               /*!< 0x08000000 */
8299 #define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!< GROUP7_IO4 channel mode */
8300 
8301 /*******************  Bit definition for TSC_IOGCSR register  *****************/
8302 #define TSC_IOGCSR_G1E_Pos       (0U)
8303 #define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                 /*!< 0x00000001 */
8304 #define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!< Analog IO GROUP1 enable */
8305 #define TSC_IOGCSR_G2E_Pos       (1U)
8306 #define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                 /*!< 0x00000002 */
8307 #define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!< Analog IO GROUP2 enable */
8308 #define TSC_IOGCSR_G3E_Pos       (2U)
8309 #define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                 /*!< 0x00000004 */
8310 #define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!< Analog IO GROUP3 enable */
8311 #define TSC_IOGCSR_G4E_Pos       (3U)
8312 #define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                 /*!< 0x00000008 */
8313 #define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!< Analog IO GROUP4 enable */
8314 #define TSC_IOGCSR_G5E_Pos       (4U)
8315 #define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                 /*!< 0x00000010 */
8316 #define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!< Analog IO GROUP5 enable */
8317 #define TSC_IOGCSR_G6E_Pos       (5U)
8318 #define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                 /*!< 0x00000020 */
8319 #define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!< Analog IO GROUP6 enable */
8320 #define TSC_IOGCSR_G7E_Pos       (6U)
8321 #define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                 /*!< 0x00000040 */
8322 #define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!< Analog IO GROUP7 enable */
8323 #define TSC_IOGCSR_G1S_Pos       (16U)
8324 #define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                 /*!< 0x00010000 */
8325 #define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!< Analog IO GROUP1 status */
8326 #define TSC_IOGCSR_G2S_Pos       (17U)
8327 #define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                 /*!< 0x00020000 */
8328 #define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!< Analog IO GROUP2 status */
8329 #define TSC_IOGCSR_G3S_Pos       (18U)
8330 #define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                 /*!< 0x00040000 */
8331 #define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!< Analog IO GROUP3 status */
8332 #define TSC_IOGCSR_G4S_Pos       (19U)
8333 #define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                 /*!< 0x00080000 */
8334 #define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!< Analog IO GROUP4 status */
8335 #define TSC_IOGCSR_G5S_Pos       (20U)
8336 #define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                 /*!< 0x00100000 */
8337 #define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!< Analog IO GROUP5 status */
8338 #define TSC_IOGCSR_G6S_Pos       (21U)
8339 #define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                 /*!< 0x00200000 */
8340 #define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!< Analog IO GROUP6 status */
8341 #define TSC_IOGCSR_G7S_Pos       (22U)
8342 #define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                 /*!< 0x00400000 */
8343 #define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!< Analog IO GROUP7 status */
8344 
8345 /*******************  Bit definition for TSC_IOGXCR register  *****************/
8346 #define TSC_IOGXCR_CNT_Pos       (0U)
8347 #define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)              /*!< 0x00003FFF */
8348 #define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!< CNT[13:0] bits (Counter value) */
8349 
8350 /******************************************************************************/
8351 /*                                                                            */
8352 /*                                 SYSCFG                                     */
8353 /*                                                                            */
8354 /******************************************************************************/
8355 /*****************  Bit definition for SYSCFG_MEMRMP register  (SYSCFG memory remap register) ***********************************/
8356 #define SYSCFG_MEMRMP_MEM_MODE_Pos              (0U)
8357 #define SYSCFG_MEMRMP_MEM_MODE_Msk              (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000007 */
8358 #define SYSCFG_MEMRMP_MEM_MODE                  SYSCFG_MEMRMP_MEM_MODE_Msk                      /*!< SYSCFG_Memory Remap Config */
8359 #define SYSCFG_MEMRMP_MEM_MODE_0                (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos)            /*!< 0x00000001 */
8360 #define SYSCFG_MEMRMP_MEM_MODE_1                (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos)            /*!< 0x00000002 */
8361 #define SYSCFG_MEMRMP_MEM_MODE_2                (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos)            /*!< 0x00000004 */
8362 
8363 /*****************  Bit definition for SYSCFG_CFGR1 register  (SYSCFG configuration register 1) ****************************************************************/
8364 #define SYSCFG_CFGR1_BOOSTEN_Pos                (8U)
8365 #define SYSCFG_CFGR1_BOOSTEN_Msk                (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)             /*!< 0x00000100 */
8366 #define SYSCFG_CFGR1_BOOSTEN                    SYSCFG_CFGR1_BOOSTEN_Msk                        /*!< I/O analog switch voltage booster enable                  */
8367 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos            (16U)
8368 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)         /*!< 0x00010000 */
8369 #define SYSCFG_CFGR1_I2C_PB6_FMP                SYSCFG_CFGR1_I2C_PB6_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB6 */
8370 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos            (17U)
8371 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)         /*!< 0x00020000 */
8372 #define SYSCFG_CFGR1_I2C_PB7_FMP                SYSCFG_CFGR1_I2C_PB7_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB7 */
8373 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos            (18U)
8374 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)         /*!< 0x00040000 */
8375 #define SYSCFG_CFGR1_I2C_PB8_FMP                SYSCFG_CFGR1_I2C_PB8_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB8 */
8376 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos            (19U)
8377 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)         /*!< 0x00080000 */
8378 #define SYSCFG_CFGR1_I2C_PB9_FMP                SYSCFG_CFGR1_I2C_PB9_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB9 */
8379 #define SYSCFG_CFGR1_I2C1_FMP_Pos               (20U)
8380 #define SYSCFG_CFGR1_I2C1_FMP_Msk               (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)            /*!< 0x00100000 */
8381 #define SYSCFG_CFGR1_I2C1_FMP                   SYSCFG_CFGR1_I2C1_FMP_Msk                       /*!< I2C1 Fast-mode Plus (Fm+) driving capability activation   */
8382 #define SYSCFG_CFGR1_FPU_IE_Pos                 (26U)
8383 #define SYSCFG_CFGR1_FPU_IE_Msk                 (0x3FUL << SYSCFG_CFGR1_FPU_IE_Pos)             /*!< 0xFC000000 */
8384 #define SYSCFG_CFGR1_FPU_IE                     SYSCFG_CFGR1_FPU_IE_Msk                         /*!< Cortex M4 Floating Point Unit interrupts enable bits      */
8385 #define SYSCFG_CFGR1_FPU_IE_0                   (0x01U << SYSCFG_CFGR1_FPU_IE_Pos)              /*!< 0x04000000 */
8386 #define SYSCFG_CFGR1_FPU_IE_1                   (0x02U << SYSCFG_CFGR1_FPU_IE_Pos)              /*!< 0x08000000 */
8387 #define SYSCFG_CFGR1_FPU_IE_2                   (0x04U << SYSCFG_CFGR1_FPU_IE_Pos)              /*!< 0x10000000 */
8388 #define SYSCFG_CFGR1_FPU_IE_3                   (0x08U << SYSCFG_CFGR1_FPU_IE_Pos)              /*!< 0x20000000 */
8389 #define SYSCFG_CFGR1_FPU_IE_4                   (0x10U << SYSCFG_CFGR1_FPU_IE_Pos)              /*!< 0x40000000 */
8390 #define SYSCFG_CFGR1_FPU_IE_5                   (0x20U << SYSCFG_CFGR1_FPU_IE_Pos)              /*!< 0x80000000 */
8391 
8392 /*****************  Bit definition for SYSCFG_EXTICR1 register  (External interrupt configuration register 1) ********************************/
8393 #define SYSCFG_EXTICR1_EXTI0_Pos                (0U)
8394 #define SYSCFG_EXTICR1_EXTI0_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)             /*!< 0x00000007 */
8395 #define SYSCFG_EXTICR1_EXTI0                    SYSCFG_EXTICR1_EXTI0_Msk                        /*!< External Interrupt Line 0 configuration */
8396 #define SYSCFG_EXTICR1_EXTI1_Pos                (4U)
8397 #define SYSCFG_EXTICR1_EXTI1_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)             /*!< 0x00000070 */
8398 #define SYSCFG_EXTICR1_EXTI1                    SYSCFG_EXTICR1_EXTI1_Msk                        /*!< External Interrupt Line 1 configuration */
8399 #define SYSCFG_EXTICR1_EXTI2_Pos                (8U)
8400 #define SYSCFG_EXTICR1_EXTI2_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)             /*!< 0x00000700 */
8401 #define SYSCFG_EXTICR1_EXTI2                    SYSCFG_EXTICR1_EXTI2_Msk                        /*!< External Interrupt Line 2 configuration */
8402 #define SYSCFG_EXTICR1_EXTI3_Pos                (12U)
8403 #define SYSCFG_EXTICR1_EXTI3_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)             /*!< 0x00007000 */
8404 #define SYSCFG_EXTICR1_EXTI3                    SYSCFG_EXTICR1_EXTI3_Msk                        /*!< External Interrupt Line 3 configuration */
8405 
8406 /**
8407   * @brief  External Interrupt Line 0 Source Input configuration
8408   */
8409 #define SYSCFG_EXTICR1_EXTI0_PA                 (0x00000000UL)  /*!< PA[0] pin */
8410 #define SYSCFG_EXTICR1_EXTI0_PB                 (0x00000001UL)  /*!< PB[0] pin */
8411 
8412 /**
8413   * @brief  External Interrupt Line 1 Source Input configuration
8414   */
8415 #define SYSCFG_EXTICR1_EXTI1_PA                 (0x00000000UL)  /*!< PA[1] pin */
8416 #define SYSCFG_EXTICR1_EXTI1_PB                 (0x00000010UL)  /*!< PB[1] pin */
8417 #define SYSCFG_EXTICR1_EXTI1_PC                 (0x00000020UL)  /*!< PC[1] pin */
8418 
8419 /**
8420   * @brief  External Interrupt Line 2 Source Input configuration
8421   */
8422 #define SYSCFG_EXTICR1_EXTI2_PA                 (0x00000000UL)  /*!< PA[2] pin */
8423 #define SYSCFG_EXTICR1_EXTI2_PB                 (0x00000100UL)  /*!< PB[2] pin */
8424 
8425 /**
8426   * @brief  External Interrupt Line 3 Source Input configuration
8427   */
8428 #define SYSCFG_EXTICR1_EXTI3_PA                 (0x00000000UL)  /*!< PA[3] pin */
8429 #define SYSCFG_EXTICR1_EXTI3_PB                 (0x00001000UL)  /*!< PB[3] pin */
8430 #define SYSCFG_EXTICR1_EXTI3_PH                 (0x00007000UL)  /*!< PH[3] pin */
8431 
8432 /*****************  Bit definition for SYSCFG_EXTICR2 register  (External interrupt configuration register 2) ********************************/
8433 #define SYSCFG_EXTICR2_EXTI4_Pos                (0U)
8434 #define SYSCFG_EXTICR2_EXTI4_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)             /*!< 0x00000007 */
8435 #define SYSCFG_EXTICR2_EXTI4                    SYSCFG_EXTICR2_EXTI4_Msk                        /*!< External Interrupt Line 4 configuration */
8436 #define SYSCFG_EXTICR2_EXTI5_Pos                (4U)
8437 #define SYSCFG_EXTICR2_EXTI5_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)             /*!< 0x00000070 */
8438 #define SYSCFG_EXTICR2_EXTI5                    SYSCFG_EXTICR2_EXTI5_Msk                        /*!< External Interrupt Line 5 configuration */
8439 #define SYSCFG_EXTICR2_EXTI6_Pos                (8U)
8440 #define SYSCFG_EXTICR2_EXTI6_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)             /*!< 0x00000700 */
8441 #define SYSCFG_EXTICR2_EXTI6                    SYSCFG_EXTICR2_EXTI6_Msk                        /*!< External Interrupt Line 6 configuration */
8442 #define SYSCFG_EXTICR2_EXTI7_Pos                (12U)
8443 #define SYSCFG_EXTICR2_EXTI7_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)             /*!< 0x00007000 */
8444 #define SYSCFG_EXTICR2_EXTI7                    SYSCFG_EXTICR2_EXTI7_Msk                        /*!< External Interrupt Line 7 configuration */
8445 
8446 /**
8447   * @brief  External Interrupt Line 4 Source Input configuration
8448   */
8449 #define SYSCFG_EXTICR2_EXTI4_PA                 (0x00000000UL)  /*!< PA[4] pin  */
8450 #define SYSCFG_EXTICR2_EXTI4_PB                 (0x00000001UL)  /*!< PB[4] pin  */
8451 #define SYSCFG_EXTICR2_EXTI4_PE                 (0x00000004UL)  /*!< PE[4] pin  */
8452 
8453 /**
8454   * @brief  External Interrupt Line 5 Source Input configuration
8455   */
8456 #define SYSCFG_EXTICR2_EXTI5_PA                 (0x00000000UL)  /*!< PA[5] pin  */
8457 #define SYSCFG_EXTICR2_EXTI5_PB                 (0x00000010UL)  /*!< PB[5] pin  */
8458 
8459 /**
8460   * @brief  External Interrupt Line 6 Source Input configuration
8461   */
8462 #define SYSCFG_EXTICR2_EXTI6_PA                 (0x00000000UL)  /*!< PA[6] pin  */
8463 #define SYSCFG_EXTICR2_EXTI6_PB                 (0x00000100UL)  /*!< PB[6] pin  */
8464 
8465 /**
8466   * @brief  External Interrupt Line 7 Source Input configuration
8467   */
8468 #define SYSCFG_EXTICR2_EXTI7_PA                 (0x00000000UL)  /*!< PA[7] pin  */
8469 #define SYSCFG_EXTICR2_EXTI7_PB                 (0x00001000UL)  /*!< PB[7] pin  */
8470 
8471 /*****************  Bit definition for SYSCFG_EXTICR3 register  (External interrupt configuration register 3) ********************************/
8472 #define SYSCFG_EXTICR3_EXTI8_Pos                (0U)
8473 #define SYSCFG_EXTICR3_EXTI8_Msk                (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)             /*!< 0x00000007 */
8474 #define SYSCFG_EXTICR3_EXTI8                    SYSCFG_EXTICR3_EXTI8_Msk                        /*!< External Interrupt Line 8 configuration */
8475 #define SYSCFG_EXTICR3_EXTI9_Pos                (4U)
8476 #define SYSCFG_EXTICR3_EXTI9_Msk                (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)             /*!< 0x00000070 */
8477 #define SYSCFG_EXTICR3_EXTI9                    SYSCFG_EXTICR3_EXTI9_Msk                        /*!< External Interrupt Line 9 configuration */
8478 #define SYSCFG_EXTICR3_EXTI10_Pos               (8U)
8479 #define SYSCFG_EXTICR3_EXTI10_Msk               (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)            /*!< 0x00000700 */
8480 #define SYSCFG_EXTICR3_EXTI10                   SYSCFG_EXTICR3_EXTI10_Msk                       /*!< External Interrupt Line 10 configuration */
8481 #define SYSCFG_EXTICR3_EXTI11_Pos               (12U)
8482 #define SYSCFG_EXTICR3_EXTI11_Msk               (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)            /*!< 0x0000F000 */
8483 #define SYSCFG_EXTICR3_EXTI11                   SYSCFG_EXTICR3_EXTI11_Msk                       /*!< External Interrupt Line 11 configuration */
8484 
8485 /**
8486   * @brief  External Interrupt Line 8 Source Input configuration
8487   */
8488 #define SYSCFG_EXTICR3_EXTI8_PA                 (0x00000000UL)  /*!< PA[8] pin  */
8489 #define SYSCFG_EXTICR3_EXTI8_PB                 (0x00000001UL)  /*!< PB[8] pin  */
8490 
8491 /**
8492   * @brief  External Interrupt Line 9 Source Input configuration
8493   */
8494 #define SYSCFG_EXTICR3_EXTI9_PA                 (0x00000000UL)  /*!< PA[9] pin  */
8495 #define SYSCFG_EXTICR3_EXTI9_PB                 (0x00000010UL)  /*!< PB[9] pin  */
8496 
8497 /**
8498   * @brief  External Interrupt Line 10 Source Input configuration
8499   */
8500 #define SYSCFG_EXTICR3_EXTI10_PA                (0x00000000UL)  /*!< PA[10] pin */
8501 #define SYSCFG_EXTICR3_EXTI10_PB                (0x00000100UL)  /*!< PB[10] pin */
8502 
8503 /**
8504   * @brief  External Interrupt Line 11 Source Input configuration
8505   */
8506 #define SYSCFG_EXTICR3_EXTI11_PA                (0x00000000UL)  /*!< PA[11] pin */
8507 #define SYSCFG_EXTICR3_EXTI11_PB                (0x00001000UL)  /*!< PB[11] pin */
8508 
8509 /*****************  Bit definition for SYSCFG_EXTICR4 register  (External interrupt configuration register 4) *********************************/
8510 #define SYSCFG_EXTICR4_EXTI12_Pos               (0U)
8511 #define SYSCFG_EXTICR4_EXTI12_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)            /*!< 0x00000007 */
8512 #define SYSCFG_EXTICR4_EXTI12                   SYSCFG_EXTICR4_EXTI12_Msk                       /*!< External Interrupt Line 12 configuration */
8513 #define SYSCFG_EXTICR4_EXTI13_Pos               (4U)
8514 #define SYSCFG_EXTICR4_EXTI13_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)            /*!< 0x00000070 */
8515 #define SYSCFG_EXTICR4_EXTI13                   SYSCFG_EXTICR4_EXTI13_Msk                       /*!< External Interrupt Line 13 configuration */
8516 #define SYSCFG_EXTICR4_EXTI14_Pos               (8U)
8517 #define SYSCFG_EXTICR4_EXTI14_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)            /*!< 0x00000700 */
8518 #define SYSCFG_EXTICR4_EXTI14                   SYSCFG_EXTICR4_EXTI14_Msk                       /*!< External Interrupt Line 14 configuration */
8519 #define SYSCFG_EXTICR4_EXTI15_Pos               (12U)
8520 #define SYSCFG_EXTICR4_EXTI15_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)            /*!< 0x00007000 */
8521 #define SYSCFG_EXTICR4_EXTI15                   SYSCFG_EXTICR4_EXTI15_Msk                       /*!< External Interrupt Line 15 configuration */
8522 
8523 /**
8524   * @brief  External Interrupt Line 12 Source Input configuration
8525   */
8526 #define SYSCFG_EXTICR4_EXTI12_PA                (0x00000000UL)  /*!< PA[12] pin */
8527 #define SYSCFG_EXTICR4_EXTI12_PB                (0x00000001UL)  /*!< PB[12] pin */
8528 
8529 /**
8530   * @brief  External Interrupt Line 13 Source Input configuration
8531   */
8532 #define SYSCFG_EXTICR4_EXTI13_PA                (0x00000000UL)  /*!< PA[13] pin */
8533 #define SYSCFG_EXTICR4_EXTI13_PB                (0x00000010UL)  /*!< PB[13] pin */
8534 
8535 /**
8536   * @brief  External Interrupt Line 14 Source Input configuration
8537   */
8538 #define SYSCFG_EXTICR4_EXTI14_PA                (0x00000000UL)  /*!< PA[14] pin */
8539 #define SYSCFG_EXTICR4_EXTI14_PB                (0x00000100UL)  /*!< PB[14] pin */
8540 #define SYSCFG_EXTICR4_EXTI14_PC                (0x00000200UL)  /*!< PC[14] pin */
8541 
8542 /**
8543   * @brief  External Interrupt Line 15 Source Input configuration
8544   */
8545 #define SYSCFG_EXTICR4_EXTI15_PA                (0x00000000UL)  /*!< PA[15] pin */
8546 #define SYSCFG_EXTICR4_EXTI15_PB                (0x00001000UL)  /*!< PB[15] pin */
8547 #define SYSCFG_EXTICR4_EXTI15_PC                (0x00002000UL)  /*!< PC[15] pin */
8548 
8549 /*****************  Bit definition for SYSCFG_SCSR register  (SYSCFG SRAM2 control and status register) *********************************************************/
8550 #define SYSCFG_SCSR_SRAM2ER_Pos                 (0U)
8551 #define SYSCFG_SCSR_SRAM2ER_Msk                 (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)              /*!< 0x00000001 */
8552 #define SYSCFG_SCSR_SRAM2ER                     SYSCFG_SCSR_SRAM2ER_Msk                         /*!< SRAM2 and PKA RAM Erase                                    */
8553 #define SYSCFG_SCSR_SRAM2BSY_Pos                (1U)
8554 #define SYSCFG_SCSR_SRAM2BSY_Msk                (0x1UL << SYSCFG_SCSR_SRAM2BSY_Pos)             /*!< 0x00000002 */
8555 #define SYSCFG_SCSR_SRAM2BSY                    SYSCFG_SCSR_SRAM2BSY_Msk                        /*!< SRAM2 and PKA RAM busy by erase operation                  */
8556 #define SYSCFG_SCSR_C2RFD_Pos                   (31U)
8557 #define SYSCFG_SCSR_C2RFD_Msk                   (0x1UL << SYSCFG_SCSR_C2RFD_Pos)                /*!< 0x80000000 */
8558 #define SYSCFG_SCSR_C2RFD                       SYSCFG_SCSR_C2RFD_Msk                           /*!< CPU2 SRAM fetch (execution) disable                        */
8559 
8560 /*****************  Bit definition for SYSCFG_CFGR2 register  (SYSCFG configuration register 2) *****************************************************************/
8561 #define SYSCFG_CFGR2_CLL_Pos                    (0U)
8562 #define SYSCFG_CFGR2_CLL_Msk                    (0x1UL << SYSCFG_CFGR2_CLL_Pos)                 /*!< 0x00000001 */
8563 #define SYSCFG_CFGR2_CLL                        SYSCFG_CFGR2_CLL_Msk                            /*!< Cortex M4 LOCKUP (hardfault) output enable                 */
8564 #define SYSCFG_CFGR2_SPL_Pos                    (1U)
8565 #define SYSCFG_CFGR2_SPL_Msk                    (0x1UL << SYSCFG_CFGR2_SPL_Pos)                 /*!< 0x00000002 */
8566 #define SYSCFG_CFGR2_SPL                        SYSCFG_CFGR2_SPL_Msk                            /*!< SRAM2 Parity Lock                                          */
8567 #define SYSCFG_CFGR2_PVDL_Pos                   (2U)
8568 #define SYSCFG_CFGR2_PVDL_Msk                   (0x1UL << SYSCFG_CFGR2_PVDL_Pos)                /*!< 0x00000004 */
8569 #define SYSCFG_CFGR2_PVDL                       SYSCFG_CFGR2_PVDL_Msk                           /*!< PVD Lock                                                   */
8570 #define SYSCFG_CFGR2_ECCL_Pos                   (3U)
8571 #define SYSCFG_CFGR2_ECCL_Msk                   (0x1UL << SYSCFG_CFGR2_ECCL_Pos)                /*!< 0x00000008 */
8572 #define SYSCFG_CFGR2_ECCL                       SYSCFG_CFGR2_ECCL_Msk                           /*!< ECC Lock                                                   */
8573 #define SYSCFG_CFGR2_SPF_Pos                    (8U)
8574 #define SYSCFG_CFGR2_SPF_Msk                    (0x1UL << SYSCFG_CFGR2_SPF_Pos)                 /*!< 0x00000100 */
8575 #define SYSCFG_CFGR2_SPF                        SYSCFG_CFGR2_SPF_Msk                            /*!< SRAM2 Parity Lock                                          */
8576 
8577 /*****************  Bit definition for SYSCFG_SWPR1 register  (SYSCFG SRAM2A write protection register) *********************************************************/
8578 #define SYSCFG_SWPR1_PAGE0_Pos                  (0U)
8579 #define SYSCFG_SWPR1_PAGE0_Msk                  (0x1UL << SYSCFG_SWPR1_PAGE0_Pos)               /*!< 0x00000001 */
8580 #define SYSCFG_SWPR1_PAGE0                      SYSCFG_SWPR1_PAGE0_Msk                          /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF)   */
8581 #define SYSCFG_SWPR1_PAGE1_Pos                  (1U)
8582 #define SYSCFG_SWPR1_PAGE1_Msk                  (0x1UL << SYSCFG_SWPR1_PAGE1_Pos)               /*!< 0x00000002 */
8583 #define SYSCFG_SWPR1_PAGE1                      SYSCFG_SWPR1_PAGE1_Msk                          /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF)   */
8584 #define SYSCFG_SWPR1_PAGE2_Pos                  (2U)
8585 #define SYSCFG_SWPR1_PAGE2_Msk                  (0x1UL << SYSCFG_SWPR1_PAGE2_Pos)               /*!< 0x00000004 */
8586 #define SYSCFG_SWPR1_PAGE2                      SYSCFG_SWPR1_PAGE2_Msk                          /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF)   */
8587 #define SYSCFG_SWPR1_PAGE3_Pos                  (3U)
8588 #define SYSCFG_SWPR1_PAGE3_Msk                  (0x1UL << SYSCFG_SWPR1_PAGE3_Pos)               /*!< 0x00000008 */
8589 #define SYSCFG_SWPR1_PAGE3                      SYSCFG_SWPR1_PAGE3_Msk                          /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF)   */
8590 #define SYSCFG_SWPR1_PAGE4_Pos                  (4U)
8591 #define SYSCFG_SWPR1_PAGE4_Msk                  (0x1UL << SYSCFG_SWPR1_PAGE4_Pos)               /*!< 0x00000010 */
8592 #define SYSCFG_SWPR1_PAGE4                      SYSCFG_SWPR1_PAGE4_Msk                          /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF)   */
8593 #define SYSCFG_SWPR1_PAGE5_Pos                  (5U)
8594 #define SYSCFG_SWPR1_PAGE5_Msk                  (0x1UL << SYSCFG_SWPR1_PAGE5_Pos)               /*!< 0x00000020 */
8595 #define SYSCFG_SWPR1_PAGE5                      SYSCFG_SWPR1_PAGE5_Msk                          /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF)   */
8596 #define SYSCFG_SWPR1_PAGE6_Pos                  (6U)
8597 #define SYSCFG_SWPR1_PAGE6_Msk                  (0x1UL << SYSCFG_SWPR1_PAGE6_Pos)               /*!< 0x00000040 */
8598 #define SYSCFG_SWPR1_PAGE6                      SYSCFG_SWPR1_PAGE6_Msk                          /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF)   */
8599 #define SYSCFG_SWPR1_PAGE7_Pos                  (7U)
8600 #define SYSCFG_SWPR1_PAGE7_Msk                  (0x1UL << SYSCFG_SWPR1_PAGE7_Pos)               /*!< 0x00000080 */
8601 #define SYSCFG_SWPR1_PAGE7                      SYSCFG_SWPR1_PAGE7_Msk                          /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF)   */
8602 #define SYSCFG_SWPR1_PAGE8_Pos                  (8U)
8603 #define SYSCFG_SWPR1_PAGE8_Msk                  (0x1UL << SYSCFG_SWPR1_PAGE8_Pos)               /*!< 0x00000100 */
8604 #define SYSCFG_SWPR1_PAGE8                      SYSCFG_SWPR1_PAGE8_Msk                          /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF)   */
8605 #define SYSCFG_SWPR1_PAGE9_Pos                  (9U)
8606 #define SYSCFG_SWPR1_PAGE9_Msk                  (0x1UL << SYSCFG_SWPR1_PAGE9_Pos)               /*!< 0x00000200 */
8607 #define SYSCFG_SWPR1_PAGE9                      SYSCFG_SWPR1_PAGE9_Msk                          /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF)   */
8608 #define SYSCFG_SWPR1_PAGE10_Pos                 (10U)
8609 #define SYSCFG_SWPR1_PAGE10_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE10_Pos)              /*!< 0x00000400 */
8610 #define SYSCFG_SWPR1_PAGE10                     SYSCFG_SWPR1_PAGE10_Msk                         /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF)  */
8611 #define SYSCFG_SWPR1_PAGE11_Pos                 (11U)
8612 #define SYSCFG_SWPR1_PAGE11_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE11_Pos)              /*!< 0x00000800 */
8613 #define SYSCFG_SWPR1_PAGE11                     SYSCFG_SWPR1_PAGE11_Msk                         /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF)  */
8614 #define SYSCFG_SWPR1_PAGE12_Pos                 (12U)
8615 #define SYSCFG_SWPR1_PAGE12_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE12_Pos)              /*!< 0x00001000 */
8616 #define SYSCFG_SWPR1_PAGE12                     SYSCFG_SWPR1_PAGE12_Msk                         /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF)  */
8617 #define SYSCFG_SWPR1_PAGE13_Pos                 (13U)
8618 #define SYSCFG_SWPR1_PAGE13_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE13_Pos)              /*!< 0x00002000 */
8619 #define SYSCFG_SWPR1_PAGE13                     SYSCFG_SWPR1_PAGE13_Msk                         /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF)  */
8620 #define SYSCFG_SWPR1_PAGE14_Pos                 (14U)
8621 #define SYSCFG_SWPR1_PAGE14_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE14_Pos)              /*!< 0x00004000 */
8622 #define SYSCFG_SWPR1_PAGE14                     SYSCFG_SWPR1_PAGE14_Msk                         /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF)  */
8623 #define SYSCFG_SWPR1_PAGE15_Pos                 (15U)
8624 #define SYSCFG_SWPR1_PAGE15_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE15_Pos)              /*!< 0x00008000 */
8625 #define SYSCFG_SWPR1_PAGE15                     SYSCFG_SWPR1_PAGE15_Msk                         /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF)  */
8626 #define SYSCFG_SWPR1_PAGE16_Pos                 (16U)
8627 #define SYSCFG_SWPR1_PAGE16_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE16_Pos)              /*!< 0x00010000 */
8628 #define SYSCFG_SWPR1_PAGE16                     SYSCFG_SWPR1_PAGE16_Msk                         /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF)  */
8629 #define SYSCFG_SWPR1_PAGE17_Pos                 (17U)
8630 #define SYSCFG_SWPR1_PAGE17_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE17_Pos)              /*!< 0x00020000 */
8631 #define SYSCFG_SWPR1_PAGE17                     SYSCFG_SWPR1_PAGE17_Msk                         /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF)  */
8632 #define SYSCFG_SWPR1_PAGE18_Pos                 (18U)
8633 #define SYSCFG_SWPR1_PAGE18_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE18_Pos)              /*!< 0x00040000 */
8634 #define SYSCFG_SWPR1_PAGE18                     SYSCFG_SWPR1_PAGE18_Msk                         /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF)  */
8635 #define SYSCFG_SWPR1_PAGE19_Pos                 (19U)
8636 #define SYSCFG_SWPR1_PAGE19_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE19_Pos)              /*!< 0x00080000 */
8637 #define SYSCFG_SWPR1_PAGE19                     SYSCFG_SWPR1_PAGE19_Msk                         /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF)  */
8638 #define SYSCFG_SWPR1_PAGE20_Pos                 (20U)
8639 #define SYSCFG_SWPR1_PAGE20_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE20_Pos)              /*!< 0x00100000 */
8640 #define SYSCFG_SWPR1_PAGE20                     SYSCFG_SWPR1_PAGE20_Msk                         /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF)  */
8641 #define SYSCFG_SWPR1_PAGE21_Pos                 (21U)
8642 #define SYSCFG_SWPR1_PAGE21_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE21_Pos)              /*!< 0x00200000 */
8643 #define SYSCFG_SWPR1_PAGE21                     SYSCFG_SWPR1_PAGE21_Msk                         /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF)  */
8644 #define SYSCFG_SWPR1_PAGE22_Pos                 (22U)
8645 #define SYSCFG_SWPR1_PAGE22_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE22_Pos)              /*!< 0x00400000 */
8646 #define SYSCFG_SWPR1_PAGE22                     SYSCFG_SWPR1_PAGE22_Msk                         /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF)  */
8647 #define SYSCFG_SWPR1_PAGE23_Pos                 (23U)
8648 #define SYSCFG_SWPR1_PAGE23_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE23_Pos)              /*!< 0x00800000 */
8649 #define SYSCFG_SWPR1_PAGE23                     SYSCFG_SWPR1_PAGE23_Msk                         /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF)  */
8650 #define SYSCFG_SWPR1_PAGE24_Pos                 (24U)
8651 #define SYSCFG_SWPR1_PAGE24_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE24_Pos)              /*!< 0x01000000 */
8652 #define SYSCFG_SWPR1_PAGE24                     SYSCFG_SWPR1_PAGE24_Msk                         /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF)  */
8653 #define SYSCFG_SWPR1_PAGE25_Pos                 (25U)
8654 #define SYSCFG_SWPR1_PAGE25_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE25_Pos)              /*!< 0x02000000 */
8655 #define SYSCFG_SWPR1_PAGE25                     SYSCFG_SWPR1_PAGE25_Msk                         /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF)  */
8656 #define SYSCFG_SWPR1_PAGE26_Pos                 (26U)
8657 #define SYSCFG_SWPR1_PAGE26_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE26_Pos)              /*!< 0x04000000 */
8658 #define SYSCFG_SWPR1_PAGE26                     SYSCFG_SWPR1_PAGE26_Msk                         /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF)  */
8659 #define SYSCFG_SWPR1_PAGE27_Pos                 (27U)
8660 #define SYSCFG_SWPR1_PAGE27_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE27_Pos)              /*!< 0x08000000 */
8661 #define SYSCFG_SWPR1_PAGE27                     SYSCFG_SWPR1_PAGE27_Msk                         /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF)  */
8662 #define SYSCFG_SWPR1_PAGE28_Pos                 (28U)
8663 #define SYSCFG_SWPR1_PAGE28_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE28_Pos)              /*!< 0x10000000 */
8664 #define SYSCFG_SWPR1_PAGE28                     SYSCFG_SWPR1_PAGE28_Msk                         /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF)  */
8665 #define SYSCFG_SWPR1_PAGE29_Pos                 (29U)
8666 #define SYSCFG_SWPR1_PAGE29_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE29_Pos)              /*!< 0x20000000 */
8667 #define SYSCFG_SWPR1_PAGE29                     SYSCFG_SWPR1_PAGE29_Msk                         /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF)  */
8668 #define SYSCFG_SWPR1_PAGE30_Pos                 (30U)
8669 #define SYSCFG_SWPR1_PAGE30_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE30_Pos)              /*!< 0x40000000 */
8670 #define SYSCFG_SWPR1_PAGE30                     SYSCFG_SWPR1_PAGE30_Msk                         /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF)  */
8671 #define SYSCFG_SWPR1_PAGE31_Pos                 (31U)
8672 #define SYSCFG_SWPR1_PAGE31_Msk                 (0x1UL << SYSCFG_SWPR1_PAGE31_Pos)              /*!< 0x80000000 */
8673 #define SYSCFG_SWPR1_PAGE31                     SYSCFG_SWPR1_PAGE31_Msk                         /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF)  */
8674 
8675 /*****************  Bit definition for SYSCFG_SKR register  (SYSCFG SRAM2 key register) *************************************************************************/
8676 #define SYSCFG_SKR_KEY_Pos                      (0U)
8677 #define SYSCFG_SKR_KEY_Msk                      (0xFFUL << SYSCFG_SKR_KEY_Pos)                  /*!< 0x000000FF */
8678 #define SYSCFG_SKR_KEY                          SYSCFG_SKR_KEY_Msk                              /*!< SRAM2 write protection key for software erase              */
8679 
8680 /*****************  Bit definition for SYSCFG_SWPR2 register  (SYSCFG SRAM2 write protection register) **********************************************************/
8681 #define SYSCFG_SWPR2_PAGE32_Pos                 (0U)
8682 #define SYSCFG_SWPR2_PAGE32_Msk                 (0x1UL << SYSCFG_SWPR2_PAGE32_Pos)              /*!< 0x00000001 */
8683 #define SYSCFG_SWPR2_PAGE32                     SYSCFG_SWPR2_PAGE32_Msk                         /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF)   */
8684 #define SYSCFG_SWPR2_PAGE33_Pos                 (1U)
8685 #define SYSCFG_SWPR2_PAGE33_Msk                 (0x1UL << SYSCFG_SWPR2_PAGE33_Pos)              /*!< 0x00000002 */
8686 #define SYSCFG_SWPR2_PAGE33                     SYSCFG_SWPR2_PAGE33_Msk                         /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF)   */
8687 #define SYSCFG_SWPR2_PAGE34_Pos                 (2U)
8688 #define SYSCFG_SWPR2_PAGE34_Msk                 (0x1UL << SYSCFG_SWPR2_PAGE34_Pos)              /*!< 0x00000004 */
8689 #define SYSCFG_SWPR2_PAGE34                     SYSCFG_SWPR2_PAGE34_Msk                         /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF)   */
8690 #define SYSCFG_SWPR2_PAGE35_Pos                 (3U)
8691 #define SYSCFG_SWPR2_PAGE35_Msk                 (0x1UL << SYSCFG_SWPR2_PAGE35_Pos)              /*!< 0x00000008 */
8692 #define SYSCFG_SWPR2_PAGE35                     SYSCFG_SWPR2_PAGE35_Msk                         /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF)   */
8693 
8694 /*****************  Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/
8695 #define SYSCFG_IMR1_TIM1IM_Pos                  (13U)
8696 #define SYSCFG_IMR1_TIM1IM_Msk                  (0x1UL << SYSCFG_IMR1_TIM1IM_Pos)             /*!< 0x00002000 */
8697 #define SYSCFG_IMR1_TIM1IM                      SYSCFG_IMR1_TIM1IM_Msk                        /*!< Enabling of interrupt from Timer 1 to CPU1                        */
8698 #define SYSCFG_IMR1_EXTI5IM_Pos                 (21U)
8699 #define SYSCFG_IMR1_EXTI5IM_Msk                 (0x1UL << SYSCFG_IMR1_EXTI5IM_Pos)            /*!< 0x00200000 */
8700 #define SYSCFG_IMR1_EXTI5IM                     SYSCFG_IMR1_EXTI5IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 5 to CPU1      */
8701 #define SYSCFG_IMR1_EXTI6IM_Pos                 (22U)
8702 #define SYSCFG_IMR1_EXTI6IM_Msk                 (0x1UL << SYSCFG_IMR1_EXTI6IM_Pos)            /*!< 0x00400000 */
8703 #define SYSCFG_IMR1_EXTI6IM                     SYSCFG_IMR1_EXTI6IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 6 to CPU1      */
8704 #define SYSCFG_IMR1_EXTI7IM_Pos                 (23U)
8705 #define SYSCFG_IMR1_EXTI7IM_Msk                 (0x1UL << SYSCFG_IMR1_EXTI7IM_Pos)            /*!< 0x00800000 */
8706 #define SYSCFG_IMR1_EXTI7IM                     SYSCFG_IMR1_EXTI7IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 7 to CPU1      */
8707 #define SYSCFG_IMR1_EXTI8IM_Pos                 (24U)
8708 #define SYSCFG_IMR1_EXTI8IM_Msk                 (0x1UL << SYSCFG_IMR1_EXTI8IM_Pos)            /*!< 0x01000000 */
8709 #define SYSCFG_IMR1_EXTI8IM                     SYSCFG_IMR1_EXTI8IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 8 to CPU1      */
8710 #define SYSCFG_IMR1_EXTI9IM_Pos                 (25U)
8711 #define SYSCFG_IMR1_EXTI9IM_Msk                 (0x1UL << SYSCFG_IMR1_EXTI9IM_Pos)            /*!< 0x02000000 */
8712 #define SYSCFG_IMR1_EXTI9IM                     SYSCFG_IMR1_EXTI9IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 9 to CPU1      */
8713 #define SYSCFG_IMR1_EXTI10IM_Pos                (26U)
8714 #define SYSCFG_IMR1_EXTI10IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI10IM_Pos)           /*!< 0x04000000 */
8715 #define SYSCFG_IMR1_EXTI10IM                    SYSCFG_IMR1_EXTI10IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 10 to CPU1     */
8716 #define SYSCFG_IMR1_EXTI11IM_Pos                (27U)
8717 #define SYSCFG_IMR1_EXTI11IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI11IM_Pos)           /*!< 0x08000000 */
8718 #define SYSCFG_IMR1_EXTI11IM                    SYSCFG_IMR1_EXTI11IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 11 to CPU1     */
8719 #define SYSCFG_IMR1_EXTI12IM_Pos                (28U)
8720 #define SYSCFG_IMR1_EXTI12IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI12IM_Pos)           /*!< 0x10000000 */
8721 #define SYSCFG_IMR1_EXTI12IM                    SYSCFG_IMR1_EXTI12IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 12 to CPU1     */
8722 #define SYSCFG_IMR1_EXTI13IM_Pos                (29U)
8723 #define SYSCFG_IMR1_EXTI13IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI13IM_Pos)           /*!< 0x20000000 */
8724 #define SYSCFG_IMR1_EXTI13IM                    SYSCFG_IMR1_EXTI13IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 13 to CPU1     */
8725 #define SYSCFG_IMR1_EXTI14IM_Pos                (30U)
8726 #define SYSCFG_IMR1_EXTI14IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI14IM_Pos)           /*!< 0x40000000 */
8727 #define SYSCFG_IMR1_EXTI14IM                    SYSCFG_IMR1_EXTI14IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 14 to CPU1     */
8728 #define SYSCFG_IMR1_EXTI15IM_Pos                (31U)
8729 #define SYSCFG_IMR1_EXTI15IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI15IM_Pos)           /*!< 0x80000000 */
8730 #define SYSCFG_IMR1_EXTI15IM                    SYSCFG_IMR1_EXTI15IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 15 to CPU1     */
8731 
8732 /*****************  Bit definition for SYSCFG_IMR2 register (Interrupt masks control and status register on CPU1 - part 2) *******************************************/
8733 #define SYSCFG_IMR2_PVM3IM_Pos                  (18U)
8734 #define SYSCFG_IMR2_PVM3IM_Msk                  (0x1UL << SYSCFG_IMR2_PVM3IM_Pos)             /*!< 0x00040000 */
8735 #define SYSCFG_IMR2_PVM3IM                      SYSCFG_IMR2_PVM3IM_Msk                        /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU1     */
8736 #define SYSCFG_IMR2_PVDIM_Pos                   (20U)
8737 #define SYSCFG_IMR2_PVDIM_Msk                   (0x1UL << SYSCFG_IMR2_PVDIM_Pos)              /*!< 0x00100000 */
8738 #define SYSCFG_IMR2_PVDIM                       SYSCFG_IMR2_PVDIM_Msk                         /*!< Enabling of interrupt from Power Voltage Detector to CPU1         */
8739 
8740 /*****************  Bit definition for SYSCFG_C2IMR1 register (Interrupt masks control and status register on CPU2 - part 1) *******************************************/
8741 #define SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Pos    (0U)
8742 #define SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Msk    (0x1UL << SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Pos) /*!< 0x00000001 */
8743 #define SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM        SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Msk            /* !< Enabling of interrupt from RTC TimeStamp, RTC Tampers
8744                                                                                                       and LSE Clock Security System to CPU2                            */
8745 #define SYSCFG_C2IMR1_RTCWKUPIM_Pos             (3U)
8746 #define SYSCFG_C2IMR1_RTCWKUPIM_Msk             (0x1UL << SYSCFG_C2IMR1_RTCWKUPIM_Pos)          /*!< 0x00000008 */
8747 #define SYSCFG_C2IMR1_RTCWKUPIM                 SYSCFG_C2IMR1_RTCWKUPIM_Msk                     /*!< Enabling of interrupt from RTC Wakeup to CPU2                     */
8748 #define SYSCFG_C2IMR1_RTCALARMIM_Pos            (4U)
8749 #define SYSCFG_C2IMR1_RTCALARMIM_Msk            (0x1UL << SYSCFG_C2IMR1_RTCALARMIM_Pos)         /*!< 0x00000010 */
8750 #define SYSCFG_C2IMR1_RTCALARMIM                SYSCFG_C2IMR1_RTCALARMIM_Msk                    /*!< Enabling of interrupt from RTC Alarms to CPU2                     */
8751 #define SYSCFG_C2IMR1_RCCIM_Pos                 (5U)
8752 #define SYSCFG_C2IMR1_RCCIM_Msk                 (0x1UL << SYSCFG_C2IMR1_RCCIM_Pos)              /*!< 0x00000020 */
8753 #define SYSCFG_C2IMR1_RCCIM                     SYSCFG_C2IMR1_RCCIM_Msk                         /*!< Enabling of interrupt from RCC to CPU2                            */
8754 #define SYSCFG_C2IMR1_FLASHIM_Pos               (6U)
8755 #define SYSCFG_C2IMR1_FLASHIM_Msk               (0x1UL << SYSCFG_C2IMR1_FLASHIM_Pos)            /*!< 0x00000040 */
8756 #define SYSCFG_C2IMR1_FLASHIM                   SYSCFG_C2IMR1_FLASHIM_Msk                       /*!< Enabling of interrupt from FLASH to CPU2                          */
8757 #define SYSCFG_C2IMR1_PKAIM_Pos                 (8U)
8758 #define SYSCFG_C2IMR1_PKAIM_Msk                 (0x1UL << SYSCFG_C2IMR1_PKAIM_Pos)              /*!< 0x00000100 */
8759 #define SYSCFG_C2IMR1_PKAIM                     SYSCFG_C2IMR1_PKAIM_Msk                         /*!< Enabling of interrupt from Public Key Accelerator to CPU2         */
8760 #define SYSCFG_C2IMR1_RNGIM_Pos                 (9U)
8761 #define SYSCFG_C2IMR1_RNGIM_Msk                 (0x1UL << SYSCFG_C2IMR1_RNGIM_Pos)              /*!< 0x00000200 */
8762 #define SYSCFG_C2IMR1_RNGIM                     SYSCFG_C2IMR1_RNGIM_Msk                         /*!< Enabling of interrupt from Random Number Generator to CPU2        */
8763 #define SYSCFG_C2IMR1_COMPIM_Pos                (11U)
8764 #define SYSCFG_C2IMR1_COMPIM_Msk                (0x1UL << SYSCFG_C2IMR1_COMPIM_Pos)             /*!< 0x00000800 */
8765 #define SYSCFG_C2IMR1_COMPIM                    SYSCFG_C2IMR1_COMPIM_Msk                        /*!< Enabling of interrupt from Comparator to CPU2                     */
8766 #define SYSCFG_C2IMR1_ADCIM_Pos                 (12U)
8767 #define SYSCFG_C2IMR1_ADCIM_Msk                 (0x1UL << SYSCFG_C2IMR1_ADCIM_Pos)              /*!< 0x00001000 */
8768 #define SYSCFG_C2IMR1_ADCIM                     SYSCFG_C2IMR1_ADCIM_Msk                         /*!< Enabling of interrupt from Analog Digital Converter to CPU2       */
8769 #define SYSCFG_C2IMR1_EXTI0IM_Pos               (16U)
8770 #define SYSCFG_C2IMR1_EXTI0IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI0IM_Pos)            /*!< 0x00010000 */
8771 #define SYSCFG_C2IMR1_EXTI0IM                   SYSCFG_C2IMR1_EXTI0IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 0 to CPU2      */
8772 #define SYSCFG_C2IMR1_EXTI1IM_Pos               (17U)
8773 #define SYSCFG_C2IMR1_EXTI1IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI1IM_Pos)            /*!< 0x00020000 */
8774 #define SYSCFG_C2IMR1_EXTI1IM                   SYSCFG_C2IMR1_EXTI1IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 1 to CPU2      */
8775 #define SYSCFG_C2IMR1_EXTI2IM_Pos               (18U)
8776 #define SYSCFG_C2IMR1_EXTI2IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI2IM_Pos)            /*!< 0x00040000 */
8777 #define SYSCFG_C2IMR1_EXTI2IM                   SYSCFG_C2IMR1_EXTI2IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 2 to CPU2      */
8778 #define SYSCFG_C2IMR1_EXTI3IM_Pos               (19U)
8779 #define SYSCFG_C2IMR1_EXTI3IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI3IM_Pos)            /*!< 0x00080000 */
8780 #define SYSCFG_C2IMR1_EXTI3IM                   SYSCFG_C2IMR1_EXTI3IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 3 to CPU2      */
8781 #define SYSCFG_C2IMR1_EXTI4IM_Pos               (20U)
8782 #define SYSCFG_C2IMR1_EXTI4IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI4IM_Pos)            /*!< 0x00100000 */
8783 #define SYSCFG_C2IMR1_EXTI4IM                   SYSCFG_C2IMR1_EXTI4IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 4 to CPU2      */
8784 #define SYSCFG_C2IMR1_EXTI5IM_Pos               (21U)
8785 #define SYSCFG_C2IMR1_EXTI5IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI5IM_Pos)            /*!< 0x00200000 */
8786 #define SYSCFG_C2IMR1_EXTI5IM                   SYSCFG_C2IMR1_EXTI5IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 5 to CPU2      */
8787 #define SYSCFG_C2IMR1_EXTI6IM_Pos               (22U)
8788 #define SYSCFG_C2IMR1_EXTI6IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI6IM_Pos)            /*!< 0x00400000 */
8789 #define SYSCFG_C2IMR1_EXTI6IM                   SYSCFG_C2IMR1_EXTI6IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 6 to CPU2      */
8790 #define SYSCFG_C2IMR1_EXTI7IM_Pos               (23U)
8791 #define SYSCFG_C2IMR1_EXTI7IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI7IM_Pos)            /*!< 0x00800000 */
8792 #define SYSCFG_C2IMR1_EXTI7IM                   SYSCFG_C2IMR1_EXTI7IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 7 to CPU2      */
8793 #define SYSCFG_C2IMR1_EXTI8IM_Pos               (24U)
8794 #define SYSCFG_C2IMR1_EXTI8IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI8IM_Pos)            /*!< 0x01000000 */
8795 #define SYSCFG_C2IMR1_EXTI8IM                   SYSCFG_C2IMR1_EXTI8IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 8 to CPU2      */
8796 #define SYSCFG_C2IMR1_EXTI9IM_Pos               (25U)
8797 #define SYSCFG_C2IMR1_EXTI9IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI9IM_Pos)            /*!< 0x02000000 */
8798 #define SYSCFG_C2IMR1_EXTI9IM                   SYSCFG_C2IMR1_EXTI9IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 9 to CPU2      */
8799 #define SYSCFG_C2IMR1_EXTI10IM_Pos              (26U)
8800 #define SYSCFG_C2IMR1_EXTI10IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI10IM_Pos)           /*!< 0x04000000 */
8801 #define SYSCFG_C2IMR1_EXTI10IM                  SYSCFG_C2IMR1_EXTI10IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 10 to CPU2     */
8802 #define SYSCFG_C2IMR1_EXTI11IM_Pos              (27U)
8803 #define SYSCFG_C2IMR1_EXTI11IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI11IM_Pos)           /*!< 0x08000000 */
8804 #define SYSCFG_C2IMR1_EXTI11IM                  SYSCFG_C2IMR1_EXTI11IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 11 to CPU2     */
8805 #define SYSCFG_C2IMR1_EXTI12IM_Pos              (28U)
8806 #define SYSCFG_C2IMR1_EXTI12IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI12IM_Pos)           /*!< 0x10000000 */
8807 #define SYSCFG_C2IMR1_EXTI12IM                  SYSCFG_C2IMR1_EXTI12IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 12 to CPU2     */
8808 #define SYSCFG_C2IMR1_EXTI13IM_Pos              (29U)
8809 #define SYSCFG_C2IMR1_EXTI13IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI13IM_Pos)           /*!< 0x20000000 */
8810 #define SYSCFG_C2IMR1_EXTI13IM                  SYSCFG_C2IMR1_EXTI13IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 13 to CPU2     */
8811 #define SYSCFG_C2IMR1_EXTI14IM_Pos              (30U)
8812 #define SYSCFG_C2IMR1_EXTI14IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI14IM_Pos)           /*!< 0x40000000 */
8813 #define SYSCFG_C2IMR1_EXTI14IM                  SYSCFG_C2IMR1_EXTI14IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 14 to CPU2     */
8814 #define SYSCFG_C2IMR1_EXTI15IM_Pos              (31U)
8815 #define SYSCFG_C2IMR1_EXTI15IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI15IM_Pos)           /*!< 0x80000000 */
8816 #define SYSCFG_C2IMR1_EXTI15IM                  SYSCFG_C2IMR1_EXTI15IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 15 to CPU2     */
8817 
8818 /*****************  Bit definition for SYSCFG_C2IMR2 register (Interrupt masks control and status register on CPU2 - part 2) *******************************************/
8819 #define SYSCFG_C2IMR2_DMA1CH1IM_Pos             (0U)
8820 #define SYSCFG_C2IMR2_DMA1CH1IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH1IM_Pos)          /*!< 0x00000001 */
8821 #define SYSCFG_C2IMR2_DMA1CH1IM                 SYSCFG_C2IMR2_DMA1CH1IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 1 to CPU2                 */
8822 #define SYSCFG_C2IMR2_DMA1CH2IM_Pos             (1U)
8823 #define SYSCFG_C2IMR2_DMA1CH2IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH2IM_Pos)          /*!< 0x00000002 */
8824 #define SYSCFG_C2IMR2_DMA1CH2IM                 SYSCFG_C2IMR2_DMA1CH2IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 2 to CPU2                 */
8825 #define SYSCFG_C2IMR2_DMA1CH3IM_Pos             (2U)
8826 #define SYSCFG_C2IMR2_DMA1CH3IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH3IM_Pos)          /*!< 0x00000004 */
8827 #define SYSCFG_C2IMR2_DMA1CH3IM                 SYSCFG_C2IMR2_DMA1CH3IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 3 to CPU2                 */
8828 #define SYSCFG_C2IMR2_DMA1CH4IM_Pos             (3U)
8829 #define SYSCFG_C2IMR2_DMA1CH4IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH4IM_Pos)          /*!< 0x00000008 */
8830 #define SYSCFG_C2IMR2_DMA1CH4IM                 SYSCFG_C2IMR2_DMA1CH4IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 4 to CPU2                 */
8831 #define SYSCFG_C2IMR2_DMA1CH5IM_Pos             (4U)
8832 #define SYSCFG_C2IMR2_DMA1CH5IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH5IM_Pos)          /*!< 0x00000010 */
8833 #define SYSCFG_C2IMR2_DMA1CH5IM                 SYSCFG_C2IMR2_DMA1CH5IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 5 to CPU2                 */
8834 #define SYSCFG_C2IMR2_DMA1CH6IM_Pos             (5U)
8835 #define SYSCFG_C2IMR2_DMA1CH6IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH6IM_Pos)          /*!< 0x00000020 */
8836 #define SYSCFG_C2IMR2_DMA1CH6IM                 SYSCFG_C2IMR2_DMA1CH6IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 6 to CPU2                 */
8837 #define SYSCFG_C2IMR2_DMA1CH7IM_Pos             (6U)
8838 #define SYSCFG_C2IMR2_DMA1CH7IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH7IM_Pos)          /*!< 0x00000040 */
8839 #define SYSCFG_C2IMR2_DMA1CH7IM                 SYSCFG_C2IMR2_DMA1CH7IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 7 to CPU2                 */
8840 #define SYSCFG_C2IMR2_DMAMUX1IM_Pos             (15U)
8841 #define SYSCFG_C2IMR2_DMAMUX1IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMAMUX1IM_Pos)          /*!< 0x00008000 */
8842 #define SYSCFG_C2IMR2_DMAMUX1IM                 SYSCFG_C2IMR2_DMAMUX1IM_Msk                     /*!< Enabling of interrupt from DMAMUX1 to CPU2                        */
8843 #define SYSCFG_C2IMR2_PVM3IM_Pos                (18U)
8844 #define SYSCFG_C2IMR2_PVM3IM_Msk                (0x1UL << SYSCFG_C2IMR2_PVM3IM_Pos)             /*!< 0x00040000 */
8845 #define SYSCFG_C2IMR2_PVM3IM                    SYSCFG_C2IMR2_PVM3IM_Msk                        /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU2     */
8846 #define SYSCFG_C2IMR2_PVDIM_Pos                 (20U)
8847 #define SYSCFG_C2IMR2_PVDIM_Msk                 (0x1UL << SYSCFG_C2IMR2_PVDIM_Pos)              /*!< 0x00100000 */
8848 #define SYSCFG_C2IMR2_PVDIM                     SYSCFG_C2IMR2_PVDIM_Msk                         /*!< Enabling of interrupt from Power Voltage Detector to CPU2         */
8849 #define SYSCFG_C2IMR2_TSCIM_Pos                 (21U)
8850 #define SYSCFG_C2IMR2_TSCIM_Msk                 (0x1UL << SYSCFG_C2IMR2_TSCIM_Pos)              /*!< 0x00200000 */
8851 #define SYSCFG_C2IMR2_TSCIM                     SYSCFG_C2IMR2_TSCIM_Msk                         /*!< Enabling of interrupt from Touch Sensing Controller to CPU2       */
8852 
8853 /*****************  Bit definition for SYSCFG_SIPCR register (SYSCFG secure IP control register) *****************************************************************************/
8854 #define SYSCFG_SIPCR_SAES2_Pos                  (1U)
8855 #define SYSCFG_SIPCR_SAES2_Msk                  (0x1UL << SYSCFG_SIPCR_SAES2_Pos)               /*!< 0x00000002 */
8856 #define SYSCFG_SIPCR_SAES2                      SYSCFG_SIPCR_SAES2_Msk                          /*!< Enabling the security access of Advanced Encryption Standard 2          */
8857 #define SYSCFG_SIPCR_SPKA_Pos                   (2U)
8858 #define SYSCFG_SIPCR_SPKA_Msk                   (0x1UL << SYSCFG_SIPCR_SPKA_Pos)                /*!< 0x00000004 */
8859 #define SYSCFG_SIPCR_SPKA                       SYSCFG_SIPCR_SPKA_Msk                           /*!< Enabling the security access of Public Key Accelerator                  */
8860 #define SYSCFG_SIPCR_SRNG_Pos                   (3U)
8861 #define SYSCFG_SIPCR_SRNG_Msk                   (0x1UL << SYSCFG_SIPCR_SRNG_Pos)                /*!< 0x00000008 */
8862 #define SYSCFG_SIPCR_SRNG                       SYSCFG_SIPCR_SRNG_Msk                           /*!< Enabling the security access of Random Number Generator                 */
8863 
8864 /******************************************************************************/
8865 /*                                                                            */
8866 /*                                    TIM                                     */
8867 /*                                                                            */
8868 /******************************************************************************/
8869 /*******************  Bit definition for TIM_CR1 register  ********************/
8870 #define TIM_CR1_CEN_Pos           (0U)
8871 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
8872 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
8873 #define TIM_CR1_UDIS_Pos          (1U)
8874 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
8875 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
8876 #define TIM_CR1_URS_Pos           (2U)
8877 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
8878 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
8879 #define TIM_CR1_OPM_Pos           (3U)
8880 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
8881 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
8882 #define TIM_CR1_DIR_Pos           (4U)
8883 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
8884 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
8885 
8886 #define TIM_CR1_CMS_Pos           (5U)
8887 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
8888 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
8889 #define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
8890 #define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
8891 
8892 #define TIM_CR1_ARPE_Pos          (7U)
8893 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
8894 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
8895 
8896 #define TIM_CR1_CKD_Pos           (8U)
8897 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
8898 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
8899 #define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
8900 #define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
8901 
8902 #define TIM_CR1_UIFREMAP_Pos      (11U)
8903 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
8904 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
8905 
8906 /*******************  Bit definition for TIM_CR2 register  ********************/
8907 #define TIM_CR2_CCPC_Pos          (0U)
8908 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
8909 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
8910 #define TIM_CR2_CCUS_Pos          (2U)
8911 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
8912 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
8913 #define TIM_CR2_CCDS_Pos          (3U)
8914 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
8915 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
8916 
8917 #define TIM_CR2_MMS_Pos           (4U)
8918 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
8919 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
8920 #define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
8921 #define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
8922 #define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
8923 
8924 #define TIM_CR2_TI1S_Pos          (7U)
8925 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
8926 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
8927 #define TIM_CR2_OIS1_Pos          (8U)
8928 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
8929 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
8930 #define TIM_CR2_OIS1N_Pos         (9U)
8931 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
8932 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
8933 #define TIM_CR2_OIS2_Pos          (10U)
8934 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
8935 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
8936 #define TIM_CR2_OIS2N_Pos         (11U)
8937 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
8938 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
8939 #define TIM_CR2_OIS3_Pos          (12U)
8940 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
8941 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
8942 #define TIM_CR2_OIS3N_Pos         (13U)
8943 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
8944 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
8945 #define TIM_CR2_OIS4_Pos          (14U)
8946 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
8947 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
8948 #define TIM_CR2_OIS5_Pos          (16U)
8949 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
8950 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
8951 #define TIM_CR2_OIS6_Pos          (18U)
8952 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
8953 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
8954 
8955 #define TIM_CR2_MMS2_Pos          (20U)
8956 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
8957 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
8958 #define TIM_CR2_MMS2_0            (0x1U << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
8959 #define TIM_CR2_MMS2_1            (0x2U << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
8960 #define TIM_CR2_MMS2_2            (0x4U << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
8961 #define TIM_CR2_MMS2_3            (0x8U << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
8962 
8963 /*******************  Bit definition for TIM_SMCR register  *******************/
8964 #define TIM_SMCR_SMS_Pos          (0U)
8965 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
8966 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
8967 #define TIM_SMCR_SMS_0            (0x00001U << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
8968 #define TIM_SMCR_SMS_1            (0x00002U << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
8969 #define TIM_SMCR_SMS_2            (0x00004U << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
8970 #define TIM_SMCR_SMS_3            (0x10000U << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
8971 
8972 #define TIM_SMCR_OCCS_Pos         (3U)
8973 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
8974 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
8975 
8976 #define TIM_SMCR_TS_Pos           (4U)
8977 #define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
8978 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
8979 #define TIM_SMCR_TS_0             (0x00001U << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */
8980 #define TIM_SMCR_TS_1             (0x00002U << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */
8981 #define TIM_SMCR_TS_2             (0x00004U << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */
8982 #define TIM_SMCR_TS_3             (0x10000U << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */
8983 #define TIM_SMCR_TS_4             (0x20000U << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */
8984 
8985 #define TIM_SMCR_MSM_Pos          (7U)
8986 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
8987 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
8988 
8989 #define TIM_SMCR_ETF_Pos          (8U)
8990 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
8991 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
8992 #define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
8993 #define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
8994 #define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
8995 #define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
8996 
8997 #define TIM_SMCR_ETPS_Pos         (12U)
8998 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
8999 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
9000 #define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
9001 #define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
9002 
9003 #define TIM_SMCR_ECE_Pos          (14U)
9004 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
9005 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
9006 #define TIM_SMCR_ETP_Pos          (15U)
9007 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
9008 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
9009 
9010 /*******************  Bit definition for TIM_DIER register  *******************/
9011 #define TIM_DIER_UIE_Pos          (0U)
9012 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
9013 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
9014 #define TIM_DIER_CC1IE_Pos        (1U)
9015 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
9016 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
9017 #define TIM_DIER_CC2IE_Pos        (2U)
9018 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
9019 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
9020 #define TIM_DIER_CC3IE_Pos        (3U)
9021 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
9022 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
9023 #define TIM_DIER_CC4IE_Pos        (4U)
9024 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
9025 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
9026 #define TIM_DIER_COMIE_Pos        (5U)
9027 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
9028 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
9029 #define TIM_DIER_TIE_Pos          (6U)
9030 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
9031 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
9032 #define TIM_DIER_BIE_Pos          (7U)
9033 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
9034 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
9035 #define TIM_DIER_UDE_Pos          (8U)
9036 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
9037 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
9038 #define TIM_DIER_CC1DE_Pos        (9U)
9039 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
9040 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
9041 #define TIM_DIER_CC2DE_Pos        (10U)
9042 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
9043 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
9044 #define TIM_DIER_CC3DE_Pos        (11U)
9045 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
9046 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
9047 #define TIM_DIER_CC4DE_Pos        (12U)
9048 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
9049 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
9050 #define TIM_DIER_COMDE_Pos        (13U)
9051 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
9052 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
9053 #define TIM_DIER_TDE_Pos          (14U)
9054 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
9055 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
9056 
9057 /********************  Bit definition for TIM_SR register  ********************/
9058 #define TIM_SR_UIF_Pos            (0U)
9059 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
9060 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
9061 #define TIM_SR_CC1IF_Pos          (1U)
9062 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
9063 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
9064 #define TIM_SR_CC2IF_Pos          (2U)
9065 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
9066 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
9067 #define TIM_SR_CC3IF_Pos          (3U)
9068 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
9069 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
9070 #define TIM_SR_CC4IF_Pos          (4U)
9071 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
9072 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
9073 #define TIM_SR_COMIF_Pos          (5U)
9074 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
9075 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
9076 #define TIM_SR_TIF_Pos            (6U)
9077 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
9078 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
9079 #define TIM_SR_BIF_Pos            (7U)
9080 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
9081 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
9082 #define TIM_SR_B2IF_Pos           (8U)
9083 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
9084 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
9085 #define TIM_SR_CC1OF_Pos          (9U)
9086 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
9087 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
9088 #define TIM_SR_CC2OF_Pos          (10U)
9089 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
9090 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
9091 #define TIM_SR_CC3OF_Pos          (11U)
9092 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
9093 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
9094 #define TIM_SR_CC4OF_Pos          (12U)
9095 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
9096 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
9097 #define TIM_SR_SBIF_Pos           (13U)
9098 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
9099 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
9100 #define TIM_SR_CC5IF_Pos          (16U)
9101 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
9102 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
9103 #define TIM_SR_CC6IF_Pos          (17U)
9104 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
9105 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
9106 
9107 
9108 /*******************  Bit definition for TIM_EGR register  ********************/
9109 #define TIM_EGR_UG_Pos            (0U)
9110 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
9111 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
9112 #define TIM_EGR_CC1G_Pos          (1U)
9113 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
9114 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
9115 #define TIM_EGR_CC2G_Pos          (2U)
9116 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
9117 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
9118 #define TIM_EGR_CC3G_Pos          (3U)
9119 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
9120 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
9121 #define TIM_EGR_CC4G_Pos          (4U)
9122 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
9123 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
9124 #define TIM_EGR_COMG_Pos          (5U)
9125 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
9126 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
9127 #define TIM_EGR_TG_Pos            (6U)
9128 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
9129 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
9130 #define TIM_EGR_BG_Pos            (7U)
9131 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
9132 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
9133 #define TIM_EGR_B2G_Pos           (8U)
9134 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
9135 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
9136 
9137 
9138 /******************  Bit definition for TIM_CCMR1 register  *******************/
9139 #define TIM_CCMR1_CC1S_Pos        (0U)
9140 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
9141 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
9142 #define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
9143 #define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
9144 
9145 #define TIM_CCMR1_OC1FE_Pos       (2U)
9146 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
9147 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
9148 #define TIM_CCMR1_OC1PE_Pos       (3U)
9149 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
9150 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
9151 
9152 #define TIM_CCMR1_OC1M_Pos        (4U)
9153 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
9154 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
9155 #define TIM_CCMR1_OC1M_0          (0x0001U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
9156 #define TIM_CCMR1_OC1M_1          (0x0002U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
9157 #define TIM_CCMR1_OC1M_2          (0x0004U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
9158 #define TIM_CCMR1_OC1M_3          (0x1000U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
9159 
9160 #define TIM_CCMR1_OC1CE_Pos       (7U)
9161 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
9162 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
9163 
9164 #define TIM_CCMR1_CC2S_Pos        (8U)
9165 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
9166 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
9167 #define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
9168 #define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
9169 
9170 #define TIM_CCMR1_OC2FE_Pos       (10U)
9171 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
9172 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
9173 #define TIM_CCMR1_OC2PE_Pos       (11U)
9174 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
9175 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
9176 
9177 #define TIM_CCMR1_OC2M_Pos        (12U)
9178 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
9179 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
9180 #define TIM_CCMR1_OC2M_0          (0x0001U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
9181 #define TIM_CCMR1_OC2M_1          (0x0002U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
9182 #define TIM_CCMR1_OC2M_2          (0x0004U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
9183 #define TIM_CCMR1_OC2M_3          (0x1000U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
9184 
9185 #define TIM_CCMR1_OC2CE_Pos       (15U)
9186 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
9187 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
9188 
9189 /*----------------------------------------------------------------------------*/
9190 #define TIM_CCMR1_IC1PSC_Pos      (2U)
9191 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
9192 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
9193 #define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
9194 #define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
9195 
9196 #define TIM_CCMR1_IC1F_Pos        (4U)
9197 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
9198 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
9199 #define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
9200 #define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
9201 #define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
9202 #define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
9203 
9204 #define TIM_CCMR1_IC2PSC_Pos      (10U)
9205 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
9206 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
9207 #define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
9208 #define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
9209 
9210 #define TIM_CCMR1_IC2F_Pos        (12U)
9211 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
9212 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
9213 #define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
9214 #define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
9215 #define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
9216 #define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
9217 
9218 /******************  Bit definition for TIM_CCMR2 register  *******************/
9219 #define TIM_CCMR2_CC3S_Pos        (0U)
9220 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
9221 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
9222 #define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
9223 #define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
9224 
9225 #define TIM_CCMR2_OC3FE_Pos       (2U)
9226 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
9227 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
9228 #define TIM_CCMR2_OC3PE_Pos       (3U)
9229 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
9230 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
9231 
9232 #define TIM_CCMR2_OC3M_Pos        (4U)
9233 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
9234 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
9235 #define TIM_CCMR2_OC3M_0          (0x0001U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000010 */
9236 #define TIM_CCMR2_OC3M_1          (0x0002U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000020 */
9237 #define TIM_CCMR2_OC3M_2          (0x0004U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000040 */
9238 #define TIM_CCMR2_OC3M_3          (0x1000U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
9239 
9240 #define TIM_CCMR2_OC3CE_Pos       (7U)
9241 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
9242 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
9243 
9244 #define TIM_CCMR2_CC4S_Pos        (8U)
9245 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
9246 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
9247 #define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
9248 #define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
9249 
9250 #define TIM_CCMR2_OC4FE_Pos       (10U)
9251 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
9252 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
9253 #define TIM_CCMR2_OC4PE_Pos       (11U)
9254 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
9255 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
9256 
9257 #define TIM_CCMR2_OC4M_Pos        (12U)
9258 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
9259 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
9260 #define TIM_CCMR2_OC4M_0          (0x0001U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00001000 */
9261 #define TIM_CCMR2_OC4M_1          (0x0002U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00002000 */
9262 #define TIM_CCMR2_OC4M_2          (0x0004U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00004000 */
9263 #define TIM_CCMR2_OC4M_3          (0x1000U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
9264 
9265 #define TIM_CCMR2_OC4CE_Pos       (15U)
9266 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
9267 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
9268 
9269 /*----------------------------------------------------------------------------*/
9270 #define TIM_CCMR2_IC3PSC_Pos      (2U)
9271 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
9272 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
9273 #define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
9274 #define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
9275 
9276 #define TIM_CCMR2_IC3F_Pos        (4U)
9277 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
9278 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
9279 #define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
9280 #define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
9281 #define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
9282 #define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
9283 
9284 #define TIM_CCMR2_IC4PSC_Pos      (10U)
9285 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
9286 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
9287 #define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
9288 #define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
9289 
9290 #define TIM_CCMR2_IC4F_Pos        (12U)
9291 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
9292 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
9293 #define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
9294 #define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
9295 #define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
9296 #define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
9297 
9298 /******************  Bit definition for TIM_CCMR3 register  *******************/
9299 #define TIM_CCMR3_OC5FE_Pos       (2U)
9300 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
9301 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
9302 #define TIM_CCMR3_OC5PE_Pos       (3U)
9303 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
9304 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
9305 
9306 #define TIM_CCMR3_OC5M_Pos        (4U)
9307 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
9308 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
9309 #define TIM_CCMR3_OC5M_0          (0x0001U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */
9310 #define TIM_CCMR3_OC5M_1          (0x0002U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */
9311 #define TIM_CCMR3_OC5M_2          (0x0004U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */
9312 #define TIM_CCMR3_OC5M_3          (0x1000U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
9313 
9314 #define TIM_CCMR3_OC5CE_Pos       (7U)
9315 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
9316 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
9317 
9318 #define TIM_CCMR3_OC6FE_Pos       (10U)
9319 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
9320 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
9321 #define TIM_CCMR3_OC6PE_Pos       (11U)
9322 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
9323 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
9324 
9325 #define TIM_CCMR3_OC6M_Pos        (12U)
9326 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
9327 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
9328 #define TIM_CCMR3_OC6M_0          (0x0001U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */
9329 #define TIM_CCMR3_OC6M_1          (0x0002U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */
9330 #define TIM_CCMR3_OC6M_2          (0x0004U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */
9331 #define TIM_CCMR3_OC6M_3          (0x1000U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
9332 
9333 #define TIM_CCMR3_OC6CE_Pos       (15U)
9334 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
9335 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
9336 
9337 /*******************  Bit definition for TIM_CCER register  *******************/
9338 #define TIM_CCER_CC1E_Pos         (0U)
9339 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
9340 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
9341 #define TIM_CCER_CC1P_Pos         (1U)
9342 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
9343 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
9344 #define TIM_CCER_CC1NE_Pos        (2U)
9345 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
9346 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
9347 #define TIM_CCER_CC1NP_Pos        (3U)
9348 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
9349 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
9350 #define TIM_CCER_CC2E_Pos         (4U)
9351 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
9352 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
9353 #define TIM_CCER_CC2P_Pos         (5U)
9354 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
9355 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
9356 #define TIM_CCER_CC2NE_Pos        (6U)
9357 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
9358 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
9359 #define TIM_CCER_CC2NP_Pos        (7U)
9360 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
9361 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
9362 #define TIM_CCER_CC3E_Pos         (8U)
9363 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
9364 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
9365 #define TIM_CCER_CC3P_Pos         (9U)
9366 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
9367 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
9368 #define TIM_CCER_CC3NE_Pos        (10U)
9369 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
9370 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
9371 #define TIM_CCER_CC3NP_Pos        (11U)
9372 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
9373 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
9374 #define TIM_CCER_CC4E_Pos         (12U)
9375 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
9376 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
9377 #define TIM_CCER_CC4P_Pos         (13U)
9378 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
9379 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
9380 #define TIM_CCER_CC4NP_Pos        (15U)
9381 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
9382 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
9383 #define TIM_CCER_CC5E_Pos         (16U)
9384 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
9385 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
9386 #define TIM_CCER_CC5P_Pos         (17U)
9387 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
9388 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
9389 #define TIM_CCER_CC6E_Pos         (20U)
9390 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
9391 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
9392 #define TIM_CCER_CC6P_Pos         (21U)
9393 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
9394 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
9395 
9396 /*******************  Bit definition for TIM_CNT register  ********************/
9397 #define TIM_CNT_CNT_Pos           (0U)
9398 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
9399 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
9400 #define TIM_CNT_UIFCPY_Pos        (31U)
9401 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
9402 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
9403 
9404 /*******************  Bit definition for TIM_PSC register  ********************/
9405 #define TIM_PSC_PSC_Pos           (0U)
9406 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
9407 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
9408 
9409 /*******************  Bit definition for TIM_ARR register  ********************/
9410 #define TIM_ARR_ARR_Pos           (0U)
9411 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
9412 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
9413 
9414 /*******************  Bit definition for TIM_RCR register  ********************/
9415 #define TIM_RCR_REP_Pos           (0U)
9416 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
9417 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
9418 
9419 /*******************  Bit definition for TIM_CCR1 register  *******************/
9420 #define TIM_CCR1_CCR1_Pos         (0U)
9421 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
9422 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
9423 
9424 /*******************  Bit definition for TIM_CCR2 register  *******************/
9425 #define TIM_CCR2_CCR2_Pos         (0U)
9426 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
9427 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
9428 
9429 /*******************  Bit definition for TIM_CCR3 register  *******************/
9430 #define TIM_CCR3_CCR3_Pos         (0U)
9431 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
9432 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
9433 
9434 /*******************  Bit definition for TIM_CCR4 register  *******************/
9435 #define TIM_CCR4_CCR4_Pos         (0U)
9436 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
9437 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
9438 
9439 /*******************  Bit definition for TIM_CCR5 register  *******************/
9440 #define TIM_CCR5_CCR5_Pos         (0U)
9441 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
9442 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
9443 #define TIM_CCR5_GC5C1_Pos        (29U)
9444 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
9445 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
9446 #define TIM_CCR5_GC5C2_Pos        (30U)
9447 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
9448 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
9449 #define TIM_CCR5_GC5C3_Pos        (31U)
9450 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
9451 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
9452 
9453 /*******************  Bit definition for TIM_CCR6 register  *******************/
9454 #define TIM_CCR6_CCR6_Pos         (0U)
9455 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
9456 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
9457 
9458 /*******************  Bit definition for TIM_BDTR register  *******************/
9459 #define TIM_BDTR_DTG_Pos          (0U)
9460 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
9461 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
9462 #define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
9463 #define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
9464 #define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
9465 #define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
9466 #define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
9467 #define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
9468 #define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
9469 #define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
9470 
9471 #define TIM_BDTR_LOCK_Pos         (8U)
9472 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
9473 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
9474 #define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
9475 #define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
9476 
9477 #define TIM_BDTR_OSSI_Pos         (10U)
9478 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
9479 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
9480 #define TIM_BDTR_OSSR_Pos         (11U)
9481 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
9482 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
9483 #define TIM_BDTR_BKE_Pos          (12U)
9484 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
9485 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
9486 #define TIM_BDTR_BKP_Pos          (13U)
9487 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
9488 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
9489 #define TIM_BDTR_AOE_Pos          (14U)
9490 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
9491 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
9492 #define TIM_BDTR_MOE_Pos          (15U)
9493 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
9494 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
9495 
9496 #define TIM_BDTR_BKF_Pos          (16U)
9497 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
9498 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
9499 #define TIM_BDTR_BK2F_Pos         (20U)
9500 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
9501 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
9502 
9503 #define TIM_BDTR_BK2E_Pos         (24U)
9504 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
9505 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
9506 #define TIM_BDTR_BK2P_Pos         (25U)
9507 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
9508 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
9509 
9510 #define TIM_BDTR_BKDSRM_Pos       (26U)
9511 #define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
9512 #define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
9513 #define TIM_BDTR_BK2DSRM_Pos      (27U)
9514 #define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
9515 #define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
9516 
9517 #define TIM_BDTR_BKBID_Pos        (28U)
9518 #define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
9519 #define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
9520 #define TIM_BDTR_BK2BID_Pos       (29U)
9521 #define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
9522 #define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
9523 
9524 /*******************  Bit definition for TIM_DCR register  ********************/
9525 #define TIM_DCR_DBA_Pos           (0U)
9526 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
9527 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
9528 #define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
9529 #define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
9530 #define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
9531 #define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
9532 #define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
9533 
9534 #define TIM_DCR_DBL_Pos           (8U)
9535 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
9536 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
9537 #define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
9538 #define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
9539 #define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
9540 #define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
9541 #define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
9542 
9543 /*******************  Bit definition for TIM_DMAR register  *******************/
9544 #define TIM_DMAR_DMAB_Pos         (0U)
9545 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
9546 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
9547 
9548 /*******************  Bit definition for TIM1_OR register  *******************/
9549 #define TIM1_OR_ETR_ADC1_RMP_Pos      (0U)
9550 #define TIM1_OR_ETR_ADC1_RMP_Msk      (0x3UL << TIM1_OR_ETR_ADC1_RMP_Pos)    /*!< 0x00000003 */
9551 #define TIM1_OR_ETR_ADC1_RMP          TIM1_OR_ETR_ADC1_RMP_Msk               /*!< TIM1_ETR_ADC1 remapping capability*/
9552 #define TIM1_OR_ETR_ADC1_RMP_0        (0x1U << TIM1_OR_ETR_ADC1_RMP_Pos)     /*!< 0x00000001 */
9553 #define TIM1_OR_ETR_ADC1_RMP_1        (0x2U << TIM1_OR_ETR_ADC1_RMP_Pos)     /*!< 0x00000002 */
9554 #define TIM1_OR_TI1_RMP_Pos            (4U)
9555 #define TIM1_OR_TI1_RMP_Msk            (0x1UL << TIM1_OR_TI1_RMP_Pos)          /*!< 0x00000010 */
9556 #define TIM1_OR_TI1_RMP                TIM1_OR_TI1_RMP_Msk                     /*!< Input Capture 1 remap*/
9557 
9558 /*******************  Bit definition for TIM2_OR register  *******************/
9559 #define TIM2_OR_TI4_RMP_Pos      (2U)
9560 #define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)              /*!< 0x0000000C */
9561 #define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                         /*!< TI4 Input capture 4 remap*/
9562 #define TIM2_OR_TI4_RMP_0        (0x1U << TIM2_OR_TI4_RMP_Pos)               /*!< 0x00000004 */
9563 #define TIM2_OR_ETR_RMP_Pos      (1U)
9564 #define TIM2_OR_ETR_RMP_Msk      (0x1UL << TIM2_OR_ETR_RMP_Pos)              /*!< 0x00000002 */
9565 #define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                         /*!< External trigger remap*/
9566 
9567 /*******************  Bit definition for TIM1_AF1 register  *******************/
9568 #define TIM1_AF1_BKINE_Pos             (0U)
9569 #define TIM1_AF1_BKINE_Msk             (0x1UL << TIM1_AF1_BKINE_Pos)           /*!< 0x00000001 */
9570 #define TIM1_AF1_BKINE                 TIM1_AF1_BKINE_Msk                      /*!<BRK BKIN input enable */
9571 #define TIM1_AF1_BKCMP1E_Pos           (1U)
9572 #define TIM1_AF1_BKCMP1E_Msk           (0x1UL << TIM1_AF1_BKCMP1E_Pos)         /*!< 0x00000002 */
9573 #define TIM1_AF1_BKCMP1E               TIM1_AF1_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
9574 #define TIM1_AF1_BKINP_Pos             (9U)
9575 #define TIM1_AF1_BKINP_Msk             (0x1UL << TIM1_AF1_BKINP_Pos)           /*!< 0x00000200 */
9576 #define TIM1_AF1_BKINP                 TIM1_AF1_BKINP_Msk                      /*!<BRK BKIN input polarity */
9577 #define TIM1_AF1_BKCMP1P_Pos           (10U)
9578 #define TIM1_AF1_BKCMP1P_Msk           (0x1UL << TIM1_AF1_BKCMP1P_Pos)         /*!< 0x00000400 */
9579 #define TIM1_AF1_BKCMP1P               TIM1_AF1_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
9580 #define TIM1_AF1_ETRSEL_Pos            (14U)
9581 #define TIM1_AF1_ETRSEL_Msk            (0x7UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x0001C000 */
9582 #define TIM1_AF1_ETRSEL                TIM1_AF1_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
9583 #define TIM1_AF1_ETRSEL_0              (0x1U << TIM1_AF1_ETRSEL_Pos)           /*!< 0x00004000 */
9584 #define TIM1_AF1_ETRSEL_1              (0x2U << TIM1_AF1_ETRSEL_Pos)           /*!< 0x00008000 */
9585 #define TIM1_AF1_ETRSEL_2              (0x4U << TIM1_AF1_ETRSEL_Pos)           /*!< 0x00010000 */
9586 
9587 /*******************  Bit definition for TIM2_AF1 register  *******************/
9588 #define TIM2_AF1_ETRSEL_Pos       (14U)
9589 #define TIM2_AF1_ETRSEL_Msk       (0x7UL << TIM2_AF1_ETRSEL_Pos)               /*!< 0x0001C000 */
9590 #define TIM2_AF1_ETRSEL           (0x00001C000)                                /*!< External trigger source selection */
9591 #define TIM2_AF1_ETRSEL_0         (0x000004000)                                /*!< Bit_0 */
9592 #define TIM2_AF1_ETRSEL_1         (0x000008000)                                /*!< Bit_1 */
9593 #define TIM2_AF1_ETRSEL_2         (0x000010000)                                /*!< Bit_2 */
9594 
9595 /*******************  Bit definition for TIM17_AF1 register  *******************/
9596 #define TIM17_AF1_BKINE_Pos             (0U)
9597 #define TIM17_AF1_BKINE_Msk             (0x1UL << TIM17_AF1_BKINE_Pos)           /*!< 0x00000001 */
9598 #define TIM17_AF1_BKINE                 TIM17_AF1_BKINE_Msk                      /*!<BRK BKIN input enable */
9599 #define TIM17_AF1_BKINP_Pos            (9U)
9600 #define TIM17_AF1_BKINP_Msk            (0x1UL << TIM17_AF1_BKINP_Pos)          /*!< 0x00000200 */
9601 #define TIM17_AF1_BKINP                TIM17_AF1_BKINP_Msk                     /*!<BRK BKIN2 input polarity */
9602 
9603 /*******************  Bit definition for TIM1_AF2 register  *******************/
9604 #define TIM1_AF2_BK2INE_Pos            (0U)
9605 #define TIM1_AF2_BK2INE_Msk            (0x1UL << TIM1_AF2_BK2INE_Pos)          /*!< 0x00000001 */
9606 #define TIM1_AF2_BK2INE                TIM1_AF2_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
9607 #define TIM1_AF2_BK2CMP1E_Pos          (1U)
9608 #define TIM1_AF2_BK2CMP1E_Msk          (0x1UL << TIM1_AF2_BK2CMP1E_Pos)        /*!< 0x00000002 */
9609 #define TIM1_AF2_BK2CMP1E              TIM1_AF2_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
9610 #define TIM1_AF2_BK2INP_Pos            (9U)
9611 #define TIM1_AF2_BK2INP_Msk            (0x1UL << TIM1_AF2_BK2INP_Pos)          /*!< 0x00000200 */
9612 #define TIM1_AF2_BK2INP                TIM1_AF2_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
9613 #define TIM1_AF2_BK2CMP1P_Pos          (10U)
9614 #define TIM1_AF2_BK2CMP1P_Msk          (0x1UL << TIM1_AF2_BK2CMP1P_Pos)        /*!< 0x00000400 */
9615 #define TIM1_AF2_BK2CMP1P              TIM1_AF2_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
9616 
9617 /******************************************************************************/
9618 /*                                                                            */
9619 /*                         Low Power Timer (LPTIM)                            */
9620 /*                                                                            */
9621 /******************************************************************************/
9622 
9623 /******************  Bit definition for LPTIM_ISR register  *******************/
9624 #define LPTIM_ISR_CMPM_Pos          (0U)
9625 #define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
9626 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
9627 #define LPTIM_ISR_ARRM_Pos          (1U)
9628 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
9629 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
9630 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
9631 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
9632 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
9633 #define LPTIM_ISR_CMPOK_Pos         (3U)
9634 #define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
9635 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
9636 #define LPTIM_ISR_ARROK_Pos         (4U)
9637 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
9638 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
9639 #define LPTIM_ISR_UP_Pos            (5U)
9640 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
9641 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
9642 #define LPTIM_ISR_DOWN_Pos          (6U)
9643 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
9644 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
9645 
9646 /******************  Bit definition for LPTIM_ICR register  *******************/
9647 #define LPTIM_ICR_CMPMCF_Pos        (0U)
9648 #define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
9649 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
9650 #define LPTIM_ICR_ARRMCF_Pos        (1U)
9651 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
9652 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
9653 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
9654 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
9655 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
9656 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
9657 #define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
9658 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
9659 #define LPTIM_ICR_ARROKCF_Pos       (4U)
9660 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
9661 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
9662 #define LPTIM_ICR_UPCF_Pos          (5U)
9663 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
9664 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
9665 #define LPTIM_ICR_DOWNCF_Pos        (6U)
9666 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
9667 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
9668 
9669 /******************  Bit definition for LPTIM_IER register ********************/
9670 #define LPTIM_IER_CMPMIE_Pos        (0U)
9671 #define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
9672 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
9673 #define LPTIM_IER_ARRMIE_Pos        (1U)
9674 #define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
9675 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
9676 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
9677 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
9678 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
9679 #define LPTIM_IER_CMPOKIE_Pos       (3U)
9680 #define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
9681 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
9682 #define LPTIM_IER_ARROKIE_Pos       (4U)
9683 #define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
9684 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
9685 #define LPTIM_IER_UPIE_Pos          (5U)
9686 #define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
9687 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
9688 #define LPTIM_IER_DOWNIE_Pos        (6U)
9689 #define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
9690 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
9691 
9692 /******************  Bit definition for LPTIM_CFGR register *******************/
9693 #define LPTIM_CFGR_CKSEL_Pos        (0U)
9694 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
9695 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
9696 
9697 #define LPTIM_CFGR_CKPOL_Pos        (1U)
9698 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
9699 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
9700 #define LPTIM_CFGR_CKPOL_0          (0x1U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
9701 #define LPTIM_CFGR_CKPOL_1          (0x2U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
9702 
9703 #define LPTIM_CFGR_CKFLT_Pos        (3U)
9704 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
9705 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
9706 #define LPTIM_CFGR_CKFLT_0          (0x1U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
9707 #define LPTIM_CFGR_CKFLT_1          (0x2U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
9708 
9709 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
9710 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
9711 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
9712 #define LPTIM_CFGR_TRGFLT_0         (0x1U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
9713 #define LPTIM_CFGR_TRGFLT_1         (0x2U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
9714 
9715 #define LPTIM_CFGR_PRESC_Pos        (9U)
9716 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
9717 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
9718 #define LPTIM_CFGR_PRESC_0          (0x1U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
9719 #define LPTIM_CFGR_PRESC_1          (0x2U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
9720 #define LPTIM_CFGR_PRESC_2          (0x4U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
9721 
9722 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
9723 #define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
9724 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
9725 #define LPTIM_CFGR_TRIGSEL_0        (0x1U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
9726 #define LPTIM_CFGR_TRIGSEL_1        (0x2U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
9727 #define LPTIM_CFGR_TRIGSEL_2        (0x4U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
9728 
9729 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
9730 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
9731 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
9732 #define LPTIM_CFGR_TRIGEN_0         (0x1U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
9733 #define LPTIM_CFGR_TRIGEN_1         (0x2U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
9734 
9735 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
9736 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
9737 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timeout enable */
9738 #define LPTIM_CFGR_WAVE_Pos         (20U)
9739 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
9740 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
9741 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
9742 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
9743 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
9744 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
9745 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
9746 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
9747 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
9748 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
9749 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
9750 #define LPTIM_CFGR_ENC_Pos          (24U)
9751 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
9752 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
9753 
9754 /******************  Bit definition for LPTIM_CR register  ********************/
9755 #define LPTIM_CR_ENABLE_Pos         (0U)
9756 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
9757 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
9758 #define LPTIM_CR_SNGSTRT_Pos        (1U)
9759 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
9760 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
9761 #define LPTIM_CR_CNTSTRT_Pos        (2U)
9762 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
9763 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
9764 #define LPTIM_CR_COUNTRST_Pos       (3U)
9765 #define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
9766 #define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
9767 #define LPTIM_CR_RSTARE_Pos         (4U)
9768 #define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
9769 #define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
9770 
9771 /******************  Bit definition for LPTIM_CMP register  *******************/
9772 #define LPTIM_CMP_CMP_Pos           (0U)
9773 #define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
9774 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
9775 
9776 /******************  Bit definition for LPTIM_ARR register  *******************/
9777 #define LPTIM_ARR_ARR_Pos           (0U)
9778 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
9779 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
9780 
9781 /******************  Bit definition for LPTIM_CNT register  *******************/
9782 #define LPTIM_CNT_CNT_Pos           (0U)
9783 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
9784 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
9785 
9786 /******************  Bit definition for LPTIM_OR register  *******************/
9787 #define LPTIM_OR_OR_Pos             (0U)
9788 #define LPTIM_OR_OR_Msk             (0x1UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000001 */
9789 #define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */
9790 #define LPTIM_OR_OR_0               (0x1U << LPTIM_OR_OR_Pos)                  /*!< 0x00000001 */
9791 
9792 /******************************************************************************/
9793 /*                                                                            */
9794 /*         Inter-Processor Communication Controller (IPCC)                    */
9795 /*                                                                            */
9796 /******************************************************************************/
9797 
9798 /**********************  Bit definition for IPCC_C1CR register  ***************/
9799 #define IPCC_C1CR_RXOIE_Pos      (0U)
9800 #define IPCC_C1CR_RXOIE_Msk      (0x1UL << IPCC_C1CR_RXOIE_Pos)                /*!< 0x00000001 */
9801 #define IPCC_C1CR_RXOIE          IPCC_C1CR_RXOIE_Msk                           /*!< Processor M4 Receive channel occupied interrupt enable */
9802 #define IPCC_C1CR_TXFIE_Pos      (16U)
9803 #define IPCC_C1CR_TXFIE_Msk      (0x1UL << IPCC_C1CR_TXFIE_Pos)                /*!< 0x00010000 */
9804 #define IPCC_C1CR_TXFIE          IPCC_C1CR_TXFIE_Msk                           /*!< Processor M4 Transmit channel free interrupt enable */
9805 
9806 /**********************  Bit definition for IPCC_C1MR register  **************/
9807 #define IPCC_C1MR_CH1OM_Pos      (0U)
9808 #define IPCC_C1MR_CH1OM_Msk      (0x1UL << IPCC_C1MR_CH1OM_Pos)                /*!< 0x00000001 */
9809 #define IPCC_C1MR_CH1OM          IPCC_C1MR_CH1OM_Msk                           /*!< M4 Channel1 occupied interrupt mask */
9810 #define IPCC_C1MR_CH2OM_Pos      (1U)
9811 #define IPCC_C1MR_CH2OM_Msk      (0x1UL << IPCC_C1MR_CH2OM_Pos)                /*!< 0x00000002 */
9812 #define IPCC_C1MR_CH2OM          IPCC_C1MR_CH2OM_Msk                           /*!< M4 Channel2 occupied interrupt mask */
9813 #define IPCC_C1MR_CH3OM_Pos      (2U)
9814 #define IPCC_C1MR_CH3OM_Msk      (0x1UL << IPCC_C1MR_CH3OM_Pos)                /*!< 0x00000004 */
9815 #define IPCC_C1MR_CH3OM          IPCC_C1MR_CH3OM_Msk                           /*!< M4 Channel3 occupied interrupt mask */
9816 #define IPCC_C1MR_CH4OM_Pos      (3U)
9817 #define IPCC_C1MR_CH4OM_Msk      (0x1UL << IPCC_C1MR_CH4OM_Pos)                /*!< 0x00000008 */
9818 #define IPCC_C1MR_CH4OM          IPCC_C1MR_CH4OM_Msk                           /*!< M4 Channel4 occupied interrupt mask */
9819 #define IPCC_C1MR_CH5OM_Pos      (4U)
9820 #define IPCC_C1MR_CH5OM_Msk      (0x1UL << IPCC_C1MR_CH5OM_Pos)                /*!< 0x00000010 */
9821 #define IPCC_C1MR_CH5OM          IPCC_C1MR_CH5OM_Msk                           /*!< M4 Channel5 occupied interrupt mask */
9822 #define IPCC_C1MR_CH6OM_Pos      (5U)
9823 #define IPCC_C1MR_CH6OM_Msk      (0x1UL << IPCC_C1MR_CH6OM_Pos)                /*!< 0x00000020 */
9824 #define IPCC_C1MR_CH6OM          IPCC_C1MR_CH6OM_Msk                           /*!< M4 Channel6 occupied interrupt mask */
9825 
9826 #define IPCC_C1MR_CH1FM_Pos      (16U)
9827 #define IPCC_C1MR_CH1FM_Msk      (0x1UL << IPCC_C1MR_CH1FM_Pos)                /*!< 0x00010000 */
9828 #define IPCC_C1MR_CH1FM          IPCC_C1MR_CH1FM_Msk                           /*!< M4 Transmit Channel1 free interrupt mask */
9829 #define IPCC_C1MR_CH2FM_Pos      (17U)
9830 #define IPCC_C1MR_CH2FM_Msk      (0x1UL << IPCC_C1MR_CH2FM_Pos)                /*!< 0x00020000 */
9831 #define IPCC_C1MR_CH2FM          IPCC_C1MR_CH2FM_Msk                           /*!< M4 Transmit Channel2 free interrupt mask */
9832 #define IPCC_C1MR_CH3FM_Pos      (18U)
9833 #define IPCC_C1MR_CH3FM_Msk      (0x1UL << IPCC_C1MR_CH3FM_Pos)                /*!< 0x00040000 */
9834 #define IPCC_C1MR_CH3FM          IPCC_C1MR_CH3FM_Msk                           /*!< M4 Transmit Channel3 free interrupt mask */
9835 #define IPCC_C1MR_CH4FM_Pos      (19U)
9836 #define IPCC_C1MR_CH4FM_Msk      (0x1UL << IPCC_C1MR_CH4FM_Pos)                /*!< 0x00080000 */
9837 #define IPCC_C1MR_CH4FM          IPCC_C1MR_CH4FM_Msk                           /*!< M4 Transmit Channel4 free interrupt mask */
9838 #define IPCC_C1MR_CH5FM_Pos      (20U)
9839 #define IPCC_C1MR_CH5FM_Msk      (0x1UL << IPCC_C1MR_CH5FM_Pos)                /*!< 0x00100000 */
9840 #define IPCC_C1MR_CH5FM          IPCC_C1MR_CH5FM_Msk                           /*!< M4 Transmit Channel5 free interrupt mask */
9841 #define IPCC_C1MR_CH6FM_Pos      (21U)
9842 #define IPCC_C1MR_CH6FM_Msk      (0x1UL << IPCC_C1MR_CH6FM_Pos)                /*!< 0x00200000 */
9843 #define IPCC_C1MR_CH6FM          IPCC_C1MR_CH6FM_Msk                           /*!< M4 Transmit Channel6 free interrupt mask */
9844 
9845 /**********************  Bit definition for IPCC_C1SCR register  ***************/
9846 #define IPCC_C1SCR_CH1C_Pos      (0U)
9847 #define IPCC_C1SCR_CH1C_Msk      (0x1UL << IPCC_C1SCR_CH1C_Pos)                /*!< 0x00000001 */
9848 #define IPCC_C1SCR_CH1C          IPCC_C1SCR_CH1C_Msk                           /*!< M4 receive Channel1 status clear */
9849 #define IPCC_C1SCR_CH2C_Pos      (1U)
9850 #define IPCC_C1SCR_CH2C_Msk      (0x1UL << IPCC_C1SCR_CH2C_Pos)                /*!< 0x00000002 */
9851 #define IPCC_C1SCR_CH2C          IPCC_C1SCR_CH2C_Msk                           /*!< M4 receive Channel2 status clear */
9852 #define IPCC_C1SCR_CH3C_Pos      (2U)
9853 #define IPCC_C1SCR_CH3C_Msk      (0x1UL << IPCC_C1SCR_CH3C_Pos)                /*!< 0x00000004 */
9854 #define IPCC_C1SCR_CH3C          IPCC_C1SCR_CH3C_Msk                           /*!< M4 receive Channel3 status clear */
9855 #define IPCC_C1SCR_CH4C_Pos      (3U)
9856 #define IPCC_C1SCR_CH4C_Msk      (0x1UL << IPCC_C1SCR_CH4C_Pos)                /*!< 0x00000008 */
9857 #define IPCC_C1SCR_CH4C          IPCC_C1SCR_CH4C_Msk                           /*!< M4 receive Channel4 status clear */
9858 #define IPCC_C1SCR_CH5C_Pos      (4U)
9859 #define IPCC_C1SCR_CH5C_Msk      (0x1UL << IPCC_C1SCR_CH5C_Pos)                /*!< 0x00000010 */
9860 #define IPCC_C1SCR_CH5C          IPCC_C1SCR_CH5C_Msk                           /*!< M4 receive Channel5 status clear */
9861 #define IPCC_C1SCR_CH6C_Pos      (5U)
9862 #define IPCC_C1SCR_CH6C_Msk      (0x1UL << IPCC_C1SCR_CH6C_Pos)                /*!< 0x00000020 */
9863 #define IPCC_C1SCR_CH6C          IPCC_C1SCR_CH6C_Msk                           /*!< M4 receive Channel6 status clear */
9864 
9865 #define IPCC_C1SCR_CH1S_Pos      (16U)
9866 #define IPCC_C1SCR_CH1S_Msk      (0x1UL << IPCC_C1SCR_CH1S_Pos)                /*!< 0x00010000 */
9867 #define IPCC_C1SCR_CH1S          IPCC_C1SCR_CH1S_Msk                           /*!< M4 transmit Channel1 status set */
9868 #define IPCC_C1SCR_CH2S_Pos      (17U)
9869 #define IPCC_C1SCR_CH2S_Msk      (0x1UL << IPCC_C1SCR_CH2S_Pos)                /*!< 0x00020000 */
9870 #define IPCC_C1SCR_CH2S          IPCC_C1SCR_CH2S_Msk                           /*!< M4 transmit Channel2 status set  */
9871 #define IPCC_C1SCR_CH3S_Pos      (18U)
9872 #define IPCC_C1SCR_CH3S_Msk      (0x1UL << IPCC_C1SCR_CH3S_Pos)                /*!< 0x00040000 */
9873 #define IPCC_C1SCR_CH3S          IPCC_C1SCR_CH3S_Msk                           /*!< M4 transmit Channel3 status set  */
9874 #define IPCC_C1SCR_CH4S_Pos      (19U)
9875 #define IPCC_C1SCR_CH4S_Msk      (0x1UL << IPCC_C1SCR_CH4S_Pos)                /*!< 0x00080000 */
9876 #define IPCC_C1SCR_CH4S          IPCC_C1SCR_CH4S_Msk                           /*!< M4 transmit Channel4 status set  */
9877 #define IPCC_C1SCR_CH5S_Pos      (20U)
9878 #define IPCC_C1SCR_CH5S_Msk      (0x1UL << IPCC_C1SCR_CH5S_Pos)                /*!< 0x00100000 */
9879 #define IPCC_C1SCR_CH5S          IPCC_C1SCR_CH5S_Msk                           /*!< M4 transmit Channel5 status set  */
9880 #define IPCC_C1SCR_CH6S_Pos      (21U)
9881 #define IPCC_C1SCR_CH6S_Msk      (0x1UL << IPCC_C1SCR_CH6S_Pos)                /*!< 0x00200000 */
9882 #define IPCC_C1SCR_CH6S          IPCC_C1SCR_CH6S_Msk                           /*!< M4 transmit Channel6 status set  */
9883 
9884 /**********************  Bit definition for IPCC_C1TOC2SR register  ***************/
9885 #define IPCC_C1TOC2SR_CH1F_Pos    (0U)
9886 #define IPCC_C1TOC2SR_CH1F_Msk    (0x1UL << IPCC_C1TOC2SR_CH1F_Pos)            /*!< 0x00000001 */
9887 #define IPCC_C1TOC2SR_CH1F        IPCC_C1TOC2SR_CH1F_Msk                       /*!< M4 transmit to M4 receive Channel1 status flag before masking */
9888 #define IPCC_C1TOC2SR_CH2F_Pos    (1U)
9889 #define IPCC_C1TOC2SR_CH2F_Msk    (0x1UL << IPCC_C1TOC2SR_CH2F_Pos)            /*!< 0x00000002 */
9890 #define IPCC_C1TOC2SR_CH2F        IPCC_C1TOC2SR_CH2F_Msk                       /*!< M4 transmit to M4 receive Channel2 status flag before masking */
9891 #define IPCC_C1TOC2SR_CH3F_Pos    (2U)
9892 #define IPCC_C1TOC2SR_CH3F_Msk    (0x1UL << IPCC_C1TOC2SR_CH3F_Pos)            /*!< 0x00000004 */
9893 #define IPCC_C1TOC2SR_CH3F        IPCC_C1TOC2SR_CH3F_Msk                       /*!< M4 transmit to M4 receive Channel3 status flag before masking */
9894 #define IPCC_C1TOC2SR_CH4F_Pos    (3U)
9895 #define IPCC_C1TOC2SR_CH4F_Msk    (0x1UL << IPCC_C1TOC2SR_CH4F_Pos)            /*!< 0x00000008 */
9896 #define IPCC_C1TOC2SR_CH4F        IPCC_C1TOC2SR_CH4F_Msk                       /*!< M4 transmit to M4 receive Channel4 status flag before masking */
9897 #define IPCC_C1TOC2SR_CH5F_Pos    (4U)
9898 #define IPCC_C1TOC2SR_CH5F_Msk    (0x1UL << IPCC_C1TOC2SR_CH5F_Pos)            /*!< 0x00000010 */
9899 #define IPCC_C1TOC2SR_CH5F        IPCC_C1TOC2SR_CH5F_Msk                       /*!< M4 transmit to M4 receive Channel5 status flag before masking */
9900 #define IPCC_C1TOC2SR_CH6F_Pos    (5U)
9901 #define IPCC_C1TOC2SR_CH6F_Msk    (0x1UL << IPCC_C1TOC2SR_CH6F_Pos)            /*!< 0x00000020 */
9902 #define IPCC_C1TOC2SR_CH6F        IPCC_C1TOC2SR_CH6F_Msk                       /*!< M4 transmit to M4 receive Channel6 status flag before masking */
9903 
9904 /**********************  Bit definition for IPCC_C2CR register  ***************/
9905 #define IPCC_C2CR_RXOIE_Pos      (0U)
9906 #define IPCC_C2CR_RXOIE_Msk      (0x1UL << IPCC_C2CR_RXOIE_Pos)                /*!< 0x00000001 */
9907 #define IPCC_C2CR_RXOIE          IPCC_C2CR_RXOIE_Msk                           /*!< Processor M0+ Receive channel occupied interrupt enable */
9908 #define IPCC_C2CR_TXFIE_Pos      (16U)
9909 #define IPCC_C2CR_TXFIE_Msk      (0x1UL << IPCC_C2CR_TXFIE_Pos)                /*!< 0x00010000 */
9910 #define IPCC_C2CR_TXFIE          IPCC_C2CR_TXFIE_Msk                           /*!< Processor M0+ Transmit channel free interrupt enable */
9911 
9912 /**********************  Bit definition for IPCC_C2MR register  ***************/
9913 #define IPCC_C2MR_CH1OM_Pos      (0U)
9914 #define IPCC_C2MR_CH1OM_Msk      (0x1UL << IPCC_C2MR_CH1OM_Pos)                /*!< 0x00000001 */
9915 #define IPCC_C2MR_CH1OM          IPCC_C2MR_CH1OM_Msk                           /*!< M0+ Channel1 occupied interrupt mask */
9916 #define IPCC_C2MR_CH2OM_Pos      (1U)
9917 #define IPCC_C2MR_CH2OM_Msk      (0x1UL << IPCC_C2MR_CH2OM_Pos)                /*!< 0x00000002 */
9918 #define IPCC_C2MR_CH2OM          IPCC_C2MR_CH2OM_Msk                           /*!< M0+ Channel2 occupied interrupt mask */
9919 #define IPCC_C2MR_CH3OM_Pos      (2U)
9920 #define IPCC_C2MR_CH3OM_Msk      (0x1UL << IPCC_C2MR_CH3OM_Pos)                /*!< 0x00000004 */
9921 #define IPCC_C2MR_CH3OM          IPCC_C2MR_CH3OM_Msk                           /*!< M0+ Channel3 occupied interrupt mask */
9922 #define IPCC_C2MR_CH4OM_Pos      (3U)
9923 #define IPCC_C2MR_CH4OM_Msk      (0x1UL << IPCC_C2MR_CH4OM_Pos)                /*!< 0x00000008 */
9924 #define IPCC_C2MR_CH4OM          IPCC_C2MR_CH4OM_Msk                           /*!< M0+ Channel4 occupied interrupt mask */
9925 #define IPCC_C2MR_CH5OM_Pos      (4U)
9926 #define IPCC_C2MR_CH5OM_Msk      (0x1UL << IPCC_C2MR_CH5OM_Pos)                /*!< 0x00000010 */
9927 #define IPCC_C2MR_CH5OM          IPCC_C2MR_CH5OM_Msk                           /*!< M0+ Channel5 occupied interrupt mask */
9928 #define IPCC_C2MR_CH6OM_Pos      (5U)
9929 #define IPCC_C2MR_CH6OM_Msk      (0x1UL << IPCC_C2MR_CH6OM_Pos)                /*!< 0x00000020 */
9930 #define IPCC_C2MR_CH6OM          IPCC_C2MR_CH6OM_Msk                           /*!< M0+ Channel6 occupied interrupt mask */
9931 
9932 #define IPCC_C2MR_CH1FM_Pos      (16U)
9933 #define IPCC_C2MR_CH1FM_Msk      (0x1UL << IPCC_C2MR_CH1FM_Pos)                /*!< 0x00010000 */
9934 #define IPCC_C2MR_CH1FM          IPCC_C2MR_CH1FM_Msk                           /*!< M0+ Transmit Channel1 free interrupt mask */
9935 #define IPCC_C2MR_CH2FM_Pos      (17U)
9936 #define IPCC_C2MR_CH2FM_Msk      (0x1UL << IPCC_C2MR_CH2FM_Pos)                /*!< 0x00020000 */
9937 #define IPCC_C2MR_CH2FM          IPCC_C2MR_CH2FM_Msk                           /*!< M0+ Transmit Channel2 free interrupt mask */
9938 #define IPCC_C2MR_CH3FM_Pos      (18U)
9939 #define IPCC_C2MR_CH3FM_Msk      (0x1UL << IPCC_C2MR_CH3FM_Pos)                /*!< 0x00040000 */
9940 #define IPCC_C2MR_CH3FM          IPCC_C2MR_CH3FM_Msk                           /*!< M0+ Transmit Channel3 free interrupt mask */
9941 #define IPCC_C2MR_CH4FM_Pos      (19U)
9942 #define IPCC_C2MR_CH4FM_Msk      (0x1UL << IPCC_C2MR_CH4FM_Pos)                /*!< 0x00080000 */
9943 #define IPCC_C2MR_CH4FM          IPCC_C2MR_CH4FM_Msk                           /*!< M0+ Transmit Channel4 free interrupt mask */
9944 #define IPCC_C2MR_CH5FM_Pos      (20U)
9945 #define IPCC_C2MR_CH5FM_Msk      (0x1UL << IPCC_C2MR_CH5FM_Pos)                /*!< 0x00100000 */
9946 #define IPCC_C2MR_CH5FM          IPCC_C2MR_CH5FM_Msk                           /*!< M0+ Transmit Channel5 free interrupt mask */
9947 #define IPCC_C2MR_CH6FM_Pos      (21U)
9948 #define IPCC_C2MR_CH6FM_Msk      (0x1UL << IPCC_C2MR_CH6FM_Pos)                /*!< 0x00200000 */
9949 #define IPCC_C2MR_CH6FM          IPCC_C2MR_CH6FM_Msk                           /*!< M0+ Transmit Channel6 free interrupt mask */
9950 
9951 /**********************  Bit definition for IPCC_C2SCR register  ***************/
9952 #define IPCC_C2SCR_CH1C_Pos      (0U)
9953 #define IPCC_C2SCR_CH1C_Msk      (0x1UL << IPCC_C2SCR_CH1C_Pos)                /*!< 0x00000001 */
9954 #define IPCC_C2SCR_CH1C          IPCC_C2SCR_CH1C_Msk                           /*!< M0+ receive Channel1 status clear */
9955 #define IPCC_C2SCR_CH2C_Pos      (1U)
9956 #define IPCC_C2SCR_CH2C_Msk      (0x1UL << IPCC_C2SCR_CH2C_Pos)                /*!< 0x00000002 */
9957 #define IPCC_C2SCR_CH2C          IPCC_C2SCR_CH2C_Msk                           /*!< M0+ receive Channel2 status clear */
9958 #define IPCC_C2SCR_CH3C_Pos      (2U)
9959 #define IPCC_C2SCR_CH3C_Msk      (0x1UL << IPCC_C2SCR_CH3C_Pos)                /*!< 0x00000004 */
9960 #define IPCC_C2SCR_CH3C          IPCC_C2SCR_CH3C_Msk                           /*!< M0+ receive Channel3 status clear */
9961 #define IPCC_C2SCR_CH4C_Pos      (3U)
9962 #define IPCC_C2SCR_CH4C_Msk      (0x1UL << IPCC_C2SCR_CH4C_Pos)                /*!< 0x00000008 */
9963 #define IPCC_C2SCR_CH4C          IPCC_C2SCR_CH4C_Msk                           /*!< M0+ receive Channel4 status clear */
9964 #define IPCC_C2SCR_CH5C_Pos      (4U)
9965 #define IPCC_C2SCR_CH5C_Msk      (0x1UL << IPCC_C2SCR_CH5C_Pos)                /*!< 0x00000010 */
9966 #define IPCC_C2SCR_CH5C          IPCC_C2SCR_CH5C_Msk                           /*!< M0+ receive Channel5 status clear */
9967 #define IPCC_C2SCR_CH6C_Pos      (5U)
9968 #define IPCC_C2SCR_CH6C_Msk      (0x1UL << IPCC_C2SCR_CH6C_Pos)                /*!< 0x00000020 */
9969 #define IPCC_C2SCR_CH6C          IPCC_C2SCR_CH6C_Msk                           /*!< M0+ receive Channel6 status clear */
9970 
9971 #define IPCC_C2SCR_CH1S_Pos      (16U)
9972 #define IPCC_C2SCR_CH1S_Msk      (0x1UL << IPCC_C2SCR_CH1S_Pos)                /*!< 0x00010000 */
9973 #define IPCC_C2SCR_CH1S          IPCC_C2SCR_CH1S_Msk                           /*!< M0+ transmit Channel1 status set  */
9974 #define IPCC_C2SCR_CH2S_Pos      (17U)
9975 #define IPCC_C2SCR_CH2S_Msk      (0x1UL << IPCC_C2SCR_CH2S_Pos)                /*!< 0x00020000 */
9976 #define IPCC_C2SCR_CH2S          IPCC_C2SCR_CH2S_Msk                           /*!< M0+ transmit Channel2 status set  */
9977 #define IPCC_C2SCR_CH3S_Pos      (18U)
9978 #define IPCC_C2SCR_CH3S_Msk      (0x1UL << IPCC_C2SCR_CH3S_Pos)                /*!< 0x00040000 */
9979 #define IPCC_C2SCR_CH3S          IPCC_C2SCR_CH3S_Msk                           /*!< M0+ transmit Channel3 status set  */
9980 #define IPCC_C2SCR_CH4S_Pos      (19U)
9981 #define IPCC_C2SCR_CH4S_Msk      (0x1UL << IPCC_C2SCR_CH4S_Pos)                /*!< 0x00080000 */
9982 #define IPCC_C2SCR_CH4S          IPCC_C2SCR_CH4S_Msk                           /*!< M0+ transmit Channel4 status set  */
9983 #define IPCC_C2SCR_CH5S_Pos      (20U)
9984 #define IPCC_C2SCR_CH5S_Msk      (0x1UL << IPCC_C2SCR_CH5S_Pos)                /*!< 0x00100000 */
9985 #define IPCC_C2SCR_CH5S          IPCC_C2SCR_CH5S_Msk                           /*!< M0+ transmit Channel5 status set  */
9986 #define IPCC_C2SCR_CH6S_Pos      (21U)
9987 #define IPCC_C2SCR_CH6S_Msk      (0x1UL << IPCC_C2SCR_CH6S_Pos)                /*!< 0x00200000 */
9988 #define IPCC_C2SCR_CH6S          IPCC_C2SCR_CH6S_Msk                           /*!< M0+ transmit Channel6 status set  */
9989 
9990 /**********************  Bit definition for IPCC_C2TOC1SR register  ***************/
9991 #define IPCC_C2TOC1SR_CH1F_Pos    (0U)
9992 #define IPCC_C2TOC1SR_CH1F_Msk    (0x1UL << IPCC_C2TOC1SR_CH1F_Pos)            /*!< 0x00000001 */
9993 #define IPCC_C2TOC1SR_CH1F        IPCC_C2TOC1SR_CH1F_Msk                       /*!< M0+ transmit to M0 receive Channel1 status flag before masking */
9994 #define IPCC_C2TOC1SR_CH2F_Pos    (1U)
9995 #define IPCC_C2TOC1SR_CH2F_Msk    (0x1UL << IPCC_C2TOC1SR_CH2F_Pos)            /*!< 0x00000002 */
9996 #define IPCC_C2TOC1SR_CH2F        IPCC_C2TOC1SR_CH2F_Msk                       /*!< M0+ transmit to M0 receive Channel2 status flag before masking */
9997 #define IPCC_C2TOC1SR_CH3F_Pos    (2U)
9998 #define IPCC_C2TOC1SR_CH3F_Msk    (0x1UL << IPCC_C2TOC1SR_CH3F_Pos)            /*!< 0x00000004 */
9999 #define IPCC_C2TOC1SR_CH3F        IPCC_C2TOC1SR_CH3F_Msk                       /*!< M0+ transmit to M0 receive Channel3 status flag before masking */
10000 #define IPCC_C2TOC1SR_CH4F_Pos    (3U)
10001 #define IPCC_C2TOC1SR_CH4F_Msk    (0x1UL << IPCC_C2TOC1SR_CH4F_Pos)            /*!< 0x00000008 */
10002 #define IPCC_C2TOC1SR_CH4F        IPCC_C2TOC1SR_CH4F_Msk                       /*!< M0+ transmit to M0 receive Channel4 status flag before masking */
10003 #define IPCC_C2TOC1SR_CH5F_Pos    (4U)
10004 #define IPCC_C2TOC1SR_CH5F_Msk    (0x1UL << IPCC_C2TOC1SR_CH5F_Pos)            /*!< 0x00000010 */
10005 #define IPCC_C2TOC1SR_CH5F        IPCC_C2TOC1SR_CH5F_Msk                       /*!< M0+ transmit to M0 receive Channel5 status flag before masking */
10006 #define IPCC_C2TOC1SR_CH6F_Pos    (5U)
10007 #define IPCC_C2TOC1SR_CH6F_Msk    (0x1UL << IPCC_C2TOC1SR_CH6F_Pos)            /*!< 0x00000020 */
10008 #define IPCC_C2TOC1SR_CH6F        IPCC_C2TOC1SR_CH6F_Msk                       /*!< M0+ transmit to M0 receive Channel6 status flag before masking */
10009 
10010 /**********************  Bit definition for IPCC_C1CR register  ***************/
10011 #define IPCC_CR_RXOIE_Pos         IPCC_C1CR_RXOIE_Pos
10012 #define IPCC_CR_RXOIE_Msk         IPCC_C1CR_RXOIE_Msk
10013 #define IPCC_CR_RXOIE             IPCC_C1CR_RXOIE
10014 #define IPCC_CR_TXFIE_Pos         IPCC_C1CR_TXFIE_Pos
10015 #define IPCC_CR_TXFIE_Msk         IPCC_C1CR_TXFIE_Msk
10016 #define IPCC_CR_TXFIE             IPCC_C1CR_TXFIE
10017 
10018 /**********************  Bit definition for IPCC_C1MR register  **************/
10019 #define IPCC_MR_CH1OM_Pos         IPCC_C1MR_CH1OM_Pos
10020 #define IPCC_MR_CH1OM_Msk         IPCC_C1MR_CH1OM_Msk
10021 #define IPCC_MR_CH1OM             IPCC_C1MR_CH1OM
10022 #define IPCC_MR_CH2OM_Pos         IPCC_C1MR_CH2OM_Pos
10023 #define IPCC_MR_CH2OM_Msk         IPCC_C1MR_CH2OM_Msk
10024 #define IPCC_MR_CH2OM             IPCC_C1MR_CH2OM
10025 #define IPCC_MR_CH3OM_Pos         IPCC_C1MR_CH3OM_Pos
10026 #define IPCC_MR_CH3OM_Msk         IPCC_C1MR_CH3OM_Msk
10027 #define IPCC_MR_CH3OM             IPCC_C1MR_CH3OM
10028 #define IPCC_MR_CH4OM_Pos         IPCC_C1MR_CH4OM_Pos
10029 #define IPCC_MR_CH4OM_Msk         IPCC_C1MR_CH4OM_Msk
10030 #define IPCC_MR_CH4OM             IPCC_C1MR_CH4OM
10031 #define IPCC_MR_CH5OM_Pos         IPCC_C1MR_CH5OM_Pos
10032 #define IPCC_MR_CH5OM_Msk         IPCC_C1MR_CH5OM_Msk
10033 #define IPCC_MR_CH5OM             IPCC_C1MR_CH5OM
10034 #define IPCC_MR_CH6OM_Pos         IPCC_C1MR_CH6OM_Pos
10035 #define IPCC_MR_CH6OM_Msk         IPCC_C1MR_CH6OM_Msk
10036 #define IPCC_MR_CH6OM             IPCC_C1MR_CH6OM
10037 
10038 #define IPCC_MR_CH1FM_Pos         IPCC_C1MR_CH1FM_Pos
10039 #define IPCC_MR_CH1FM_Msk         IPCC_C1MR_CH1FM_Msk
10040 #define IPCC_MR_CH1FM             IPCC_C1MR_CH1FM
10041 #define IPCC_MR_CH2FM_Pos         IPCC_C1MR_CH2FM_Pos
10042 #define IPCC_MR_CH2FM_Msk         IPCC_C1MR_CH2FM_Msk
10043 #define IPCC_MR_CH2FM             IPCC_C1MR_CH2FM
10044 #define IPCC_MR_CH3FM_Pos         IPCC_C1MR_CH3FM_Pos
10045 #define IPCC_MR_CH3FM_Msk         IPCC_C1MR_CH3FM_Msk
10046 #define IPCC_MR_CH3FM             IPCC_C1MR_CH3FM
10047 #define IPCC_MR_CH4FM_Pos         IPCC_C1MR_CH4FM_Pos
10048 #define IPCC_MR_CH4FM_Msk         IPCC_C1MR_CH4FM_Msk
10049 #define IPCC_MR_CH4FM             IPCC_C1MR_CH4FM
10050 #define IPCC_MR_CH5FM_Pos         IPCC_C1MR_CH5FM_Pos
10051 #define IPCC_MR_CH5FM_Msk         IPCC_C1MR_CH5FM_Msk
10052 #define IPCC_MR_CH5FM             IPCC_C1MR_CH5FM
10053 #define IPCC_MR_CH6FM_Pos         IPCC_C1MR_CH6FM_Pos
10054 #define IPCC_MR_CH6FM_Msk         IPCC_C1MR_CH6FM_Msk
10055 #define IPCC_MR_CH6FM             IPCC_C1MR_CH6FM
10056 
10057 /**********************  Bit definition for IPCC_C1SCR register  ***************/
10058 #define IPCC_SCR_CH1C_Pos         IPCC_C1SCR_CH1C_Pos
10059 #define IPCC_SCR_CH1C_Msk         IPCC_C1SCR_CH1C_Msk
10060 #define IPCC_SCR_CH1C             IPCC_C1SCR_CH1C
10061 #define IPCC_SCR_CH2C_Pos         IPCC_C1SCR_CH2C_Pos
10062 #define IPCC_SCR_CH2C_Msk         IPCC_C1SCR_CH2C_Msk
10063 #define IPCC_SCR_CH2C             IPCC_C1SCR_CH2C
10064 #define IPCC_SCR_CH3C_Pos         IPCC_C1SCR_CH3C_Pos
10065 #define IPCC_SCR_CH3C_Msk         IPCC_C1SCR_CH3C_Msk
10066 #define IPCC_SCR_CH3C             IPCC_C1SCR_CH3C
10067 #define IPCC_SCR_CH4C_Pos         IPCC_C1SCR_CH4C_Pos
10068 #define IPCC_SCR_CH4C_Msk         IPCC_C1SCR_CH4C_Msk
10069 #define IPCC_SCR_CH4C             IPCC_C1SCR_CH4C
10070 #define IPCC_SCR_CH5C_Pos         IPCC_C1SCR_CH5C_Pos
10071 #define IPCC_SCR_CH5C_Msk         IPCC_C1SCR_CH5C_Msk
10072 #define IPCC_SCR_CH5C             IPCC_C1SCR_CH5C
10073 #define IPCC_SCR_CH6C_Pos         IPCC_C1SCR_CH6C_Pos
10074 #define IPCC_SCR_CH6C_Msk         IPCC_C1SCR_CH6C_Msk
10075 #define IPCC_SCR_CH6C             IPCC_C1SCR_CH6C
10076 
10077 #define IPCC_SCR_CH1S_Pos         IPCC_C1SCR_CH1S_Pos
10078 #define IPCC_SCR_CH1S_Msk         IPCC_C1SCR_CH1S_Msk
10079 #define IPCC_SCR_CH1S             IPCC_C1SCR_CH1S
10080 #define IPCC_SCR_CH2S_Pos         IPCC_C1SCR_CH2S_Pos
10081 #define IPCC_SCR_CH2S_Msk         IPCC_C1SCR_CH2S_Msk
10082 #define IPCC_SCR_CH2S             IPCC_C1SCR_CH2S
10083 #define IPCC_SCR_CH3S_Pos         IPCC_C1SCR_CH3S_Pos
10084 #define IPCC_SCR_CH3S_Msk         IPCC_C1SCR_CH3S_Msk
10085 #define IPCC_SCR_CH3S             IPCC_C1SCR_CH3S
10086 #define IPCC_SCR_CH4S_Pos         IPCC_C1SCR_CH4S_Pos
10087 #define IPCC_SCR_CH4S_Msk         IPCC_C1SCR_CH4S_Msk
10088 #define IPCC_SCR_CH4S             IPCC_C1SCR_CH4S
10089 #define IPCC_SCR_CH5S_Pos         IPCC_C1SCR_CH5S_Pos
10090 #define IPCC_SCR_CH5S_Msk         IPCC_C1SCR_CH5S_Msk
10091 #define IPCC_SCR_CH5S             IPCC_C1SCR_CH5S
10092 #define IPCC_SCR_CH6S_Pos         IPCC_C1SCR_CH6S_Pos
10093 #define IPCC_SCR_CH6S_Msk         IPCC_C1SCR_CH6S_Msk
10094 #define IPCC_SCR_CH6S             IPCC_C1SCR_CH6S
10095 
10096 /**********************  Bit definition for IPCC_C1TOC2SR register  ***************/
10097 #define IPCC_SR_CH1F_Pos          IPCC_C1TOC2SR_CH1F_Pos
10098 #define IPCC_SR_CH1F_Msk          IPCC_C1TOC2SR_CH1F_Msk
10099 #define IPCC_SR_CH1F              IPCC_C1TOC2SR_CH1F
10100 #define IPCC_SR_CH2F_Pos          IPCC_C1TOC2SR_CH2F_Pos
10101 #define IPCC_SR_CH2F_Msk          IPCC_C1TOC2SR_CH2F_Msk
10102 #define IPCC_SR_CH2F              IPCC_C1TOC2SR_CH2F
10103 #define IPCC_SR_CH3F_Pos          IPCC_C1TOC2SR_CH3F_Pos
10104 #define IPCC_SR_CH3F_Msk          IPCC_C1TOC2SR_CH3F_Msk
10105 #define IPCC_SR_CH3F              IPCC_C1TOC2SR_CH3F
10106 #define IPCC_SR_CH4F_Pos          IPCC_C1TOC2SR_CH4F_Pos
10107 #define IPCC_SR_CH4F_Msk          IPCC_C1TOC2SR_CH4F_Msk
10108 #define IPCC_SR_CH4F              IPCC_C1TOC2SR_CH4F
10109 #define IPCC_SR_CH5F_Pos          IPCC_C1TOC2SR_CH5F_Pos
10110 #define IPCC_SR_CH5F_Msk          IPCC_C1TOC2SR_CH5F_Msk
10111 #define IPCC_SR_CH5F              IPCC_C1TOC2SR_CH5F
10112 #define IPCC_SR_CH6F_Pos          IPCC_C1TOC2SR_CH6F_Pos
10113 #define IPCC_SR_CH6F_Msk          IPCC_C1TOC2SR_CH6F_Msk
10114 #define IPCC_SR_CH6F              IPCC_C1TOC2SR_CH6F
10115 
10116 /******************** Number of IPCC channels ******************************/
10117 #define IPCC_CHANNEL_NUMBER       6U
10118 
10119 /******************************************************************************/
10120 /*                                                                            */
10121 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
10122 /*                                                                            */
10123 /******************************************************************************/
10124 /******************  Bit definition for USART_CR1 register  *******************/
10125 #define USART_CR1_UE_Pos                (0U)
10126 #define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */
10127 #define USART_CR1_UE                    USART_CR1_UE_Msk                        /*!< USART Enable */
10128 #define USART_CR1_UESM_Pos              (1U)
10129 #define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)           /*!< 0x00000002 */
10130 #define USART_CR1_UESM                  USART_CR1_UESM_Msk                      /*!< USART Enable in STOP Mode */
10131 #define USART_CR1_RE_Pos                (2U)
10132 #define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)             /*!< 0x00000004 */
10133 #define USART_CR1_RE                    USART_CR1_RE_Msk                        /*!< Receiver Enable */
10134 #define USART_CR1_TE_Pos                (3U)
10135 #define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)             /*!< 0x00000008 */
10136 #define USART_CR1_TE                    USART_CR1_TE_Msk                        /*!< Transmitter Enable */
10137 #define USART_CR1_IDLEIE_Pos            (4U)
10138 #define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)         /*!< 0x00000010 */
10139 #define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                    /*!< IDLE Interrupt Enable */
10140 #define USART_CR1_RXNEIE_Pos            (5U)
10141 #define USART_CR1_RXNEIE_Msk            (0x1UL << USART_CR1_RXNEIE_Pos)         /*!< 0x00000020 */
10142 #define USART_CR1_RXNEIE                USART_CR1_RXNEIE_Msk                    /*!< RXNE Interrupt Enable */
10143 #define USART_CR1_RXNEIE_RXFNEIE_Pos    USART_CR1_RXNEIE_Pos
10144 #define USART_CR1_RXNEIE_RXFNEIE_Msk    USART_CR1_RXNEIE_Msk                    /*!< 0x00000020 */
10145 #define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_Msk                    /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
10146 #define USART_CR1_TCIE_Pos              (6U)
10147 #define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)           /*!< 0x00000040 */
10148 #define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                      /*!< Transmission Complete Interrupt Enable */
10149 #define USART_CR1_TXEIE_Pos             (7U)
10150 #define USART_CR1_TXEIE_Msk             (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
10151 #define USART_CR1_TXEIE                 USART_CR1_TXEIE_Msk                     /*!< TXE Interrupt Enable */
10152 #define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)
10153 #define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
10154 #define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE                         /*!< TXE and TX FIFO Not Full Interrupt Enable */
10155 #define USART_CR1_PEIE_Pos              (8U)
10156 #define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)           /*!< 0x00000100 */
10157 #define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                      /*!< PE Interrupt Enable */
10158 #define USART_CR1_PS_Pos                (9U)
10159 #define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)             /*!< 0x00000200 */
10160 #define USART_CR1_PS                    USART_CR1_PS_Msk                        /*!< Parity Selection */
10161 #define USART_CR1_PCE_Pos               (10U)
10162 #define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)            /*!< 0x00000400 */
10163 #define USART_CR1_PCE                   USART_CR1_PCE_Msk                       /*!< Parity Control Enable */
10164 #define USART_CR1_WAKE_Pos              (11U)
10165 #define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)           /*!< 0x00000800 */
10166 #define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                      /*!< Receiver Wakeup method */
10167 #define USART_CR1_M0_Pos                (12U)
10168 #define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)             /*!< 0x00001000 */
10169 #define USART_CR1_M0                    USART_CR1_M0_Msk                        /*!< Word length - Bit 0 */
10170 #define USART_CR1_MME_Pos               (13U)
10171 #define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)            /*!< 0x00002000 */
10172 #define USART_CR1_MME                   USART_CR1_MME_Msk                       /*!< Mute Mode Enable */
10173 #define USART_CR1_CMIE_Pos              (14U)
10174 #define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)           /*!< 0x00004000 */
10175 #define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                      /*!< Character match interrupt enable */
10176 #define USART_CR1_OVER8_Pos             (15U)
10177 #define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)          /*!< 0x00008000 */
10178 #define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                     /*!< Oversampling by 8-bit or 16-bit mode */
10179 #define USART_CR1_DEDT_Pos              (16U)
10180 #define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)          /*!< 0x001F0000 */
10181 #define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                      /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
10182 #define USART_CR1_DEDT_0                (0x01U << USART_CR1_DEDT_Pos)           /*!< 0x00010000 */
10183 #define USART_CR1_DEDT_1                (0x02U << USART_CR1_DEDT_Pos)           /*!< 0x00020000 */
10184 #define USART_CR1_DEDT_2                (0x04U << USART_CR1_DEDT_Pos)           /*!< 0x00040000 */
10185 #define USART_CR1_DEDT_3                (0x08U << USART_CR1_DEDT_Pos)           /*!< 0x00080000 */
10186 #define USART_CR1_DEDT_4                (0x10U << USART_CR1_DEDT_Pos)           /*!< 0x00100000 */
10187 #define USART_CR1_DEAT_Pos              (21U)
10188 #define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)          /*!< 0x03E00000 */
10189 #define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                      /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
10190 #define USART_CR1_DEAT_0                (0x01U << USART_CR1_DEAT_Pos)           /*!< 0x00200000 */
10191 #define USART_CR1_DEAT_1                (0x02U << USART_CR1_DEAT_Pos)           /*!< 0x00400000 */
10192 #define USART_CR1_DEAT_2                (0x04U << USART_CR1_DEAT_Pos)           /*!< 0x00800000 */
10193 #define USART_CR1_DEAT_3                (0x08U << USART_CR1_DEAT_Pos)           /*!< 0x01000000 */
10194 #define USART_CR1_DEAT_4                (0x10U << USART_CR1_DEAT_Pos)           /*!< 0x02000000 */
10195 #define USART_CR1_RTOIE_Pos             (26U)
10196 #define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)          /*!< 0x04000000 */
10197 #define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                     /*!< Receive Time Out Interrupt Enable */
10198 #define USART_CR1_EOBIE_Pos             (27U)
10199 #define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)          /*!< 0x08000000 */
10200 #define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                     /*!< End of Block Interrupt Enable */
10201 #define USART_CR1_M1_Pos                (28U)
10202 #define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)             /*!< 0x10000000 */
10203 #define USART_CR1_M1                    USART_CR1_M1_Msk                        /*!< Word length - Bit 1 */
10204 #define USART_CR1_M                     (uint32_t)(USART_CR1_M1 | USART_CR1_M0) /*!< Word length */
10205 #define USART_CR1_FIFOEN_Pos            (29U)
10206 #define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)         /*!< 0x20000000 */
10207 #define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                    /*!< FIFO mode enable */
10208 #define USART_CR1_TXFEIE_Pos            (30U)
10209 #define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)         /*!< 0x40000000 */
10210 #define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                    /*!< TX FIFO Empty Interrupt Enable */
10211 #define USART_CR1_RXFFIE_Pos            (31U)
10212 #define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)         /*!< 0x80000000 */
10213 #define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                    /*!< RX FIFO Full Interrupt Enable */
10214 
10215 /******************  Bit definition for USART_CR2 register  *******************/
10216 #define USART_CR2_SLVEN_Pos             (0U)
10217 #define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)          /*!< 0x00000001 */
10218 #define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                     /*!< Synchronous Slave mode enable */
10219 #define USART_CR2_DIS_NSS_Pos           (3U)
10220 #define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)        /*!< 0x00000008 */
10221 #define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                   /*!< Slave Select (NSS) pin management */
10222 #define USART_CR2_ADDM7_Pos             (4U)
10223 #define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)          /*!< 0x00000010 */
10224 #define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                     /*!< 7-bit or 4-bit Address Detection */
10225 #define USART_CR2_LBDL_Pos              (5U)
10226 #define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)           /*!< 0x00000020 */
10227 #define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                      /*!< LIN Break Detection Length */
10228 #define USART_CR2_LBDIE_Pos             (6U)
10229 #define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)          /*!< 0x00000040 */
10230 #define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                     /*!< LIN Break Detection Interrupt Enable */
10231 #define USART_CR2_LBCL_Pos              (8U)
10232 #define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)           /*!< 0x00000100 */
10233 #define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                      /*!< Last Bit Clock pulse */
10234 #define USART_CR2_CPHA_Pos              (9U)
10235 #define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)           /*!< 0x00000200 */
10236 #define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                      /*!< Clock Phase */
10237 #define USART_CR2_CPOL_Pos              (10U)
10238 #define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)           /*!< 0x00000400 */
10239 #define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                      /*!< Clock Polarity */
10240 #define USART_CR2_CLKEN_Pos             (11U)
10241 #define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)          /*!< 0x00000800 */
10242 #define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                     /*!< Clock Enable */
10243 #define USART_CR2_STOP_Pos              (12U)
10244 #define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)           /*!< 0x00003000 */
10245 #define USART_CR2_STOP                  USART_CR2_STOP_Msk                      /*!< STOP[1:0] bits (STOP bits) */
10246 #define USART_CR2_STOP_0                (0x1U << USART_CR2_STOP_Pos)            /*!< 0x00001000 */
10247 #define USART_CR2_STOP_1                (0x2U << USART_CR2_STOP_Pos)            /*!< 0x00002000 */
10248 #define USART_CR2_LINEN_Pos             (14U)
10249 #define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)          /*!< 0x00004000 */
10250 #define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                     /*!< LIN mode enable */
10251 #define USART_CR2_SWAP_Pos              (15U)
10252 #define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)           /*!< 0x00008000 */
10253 #define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                      /*!< SWAP TX/RX pins */
10254 #define USART_CR2_RXINV_Pos             (16U)
10255 #define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)          /*!< 0x00010000 */
10256 #define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                     /*!< RX pin active level inversion */
10257 #define USART_CR2_TXINV_Pos             (17U)
10258 #define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)          /*!< 0x00020000 */
10259 #define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                     /*!< TX pin active level inversion */
10260 #define USART_CR2_DATAINV_Pos           (18U)
10261 #define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)        /*!< 0x00040000 */
10262 #define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                   /*!< Binary data inversion */
10263 #define USART_CR2_MSBFIRST_Pos          (19U)
10264 #define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)       /*!< 0x00080000 */
10265 #define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                  /*!< Most Significant Bit First */
10266 #define USART_CR2_ABREN_Pos             (20U)
10267 #define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)          /*!< 0x00100000 */
10268 #define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                     /*!< Auto Baud-Rate Enable*/
10269 #define USART_CR2_ABRMODE_Pos           (21U)
10270 #define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00600000 */
10271 #define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                   /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
10272 #define USART_CR2_ABRMODE_0             (0x1U << USART_CR2_ABRMODE_Pos)         /*!< 0x00200000 */
10273 #define USART_CR2_ABRMODE_1             (0x2U << USART_CR2_ABRMODE_Pos)         /*!< 0x00400000 */
10274 #define USART_CR2_RTOEN_Pos             (23U)
10275 #define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)          /*!< 0x00800000 */
10276 #define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                     /*!< Receiver Time-Out enable */
10277 #define USART_CR2_ADD_Pos               (24U)
10278 #define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)           /*!< 0xFF000000 */
10279 #define USART_CR2_ADD                   USART_CR2_ADD_Msk                       /*!< Address of the USART node */
10280 
10281 /******************  Bit definition for USART_CR3 register  *******************/
10282 #define USART_CR3_EIE_Pos               (0U)
10283 #define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)            /*!< 0x00000001 */
10284 #define USART_CR3_EIE                   USART_CR3_EIE_Msk                       /*!< Error Interrupt Enable */
10285 #define USART_CR3_IREN_Pos              (1U)
10286 #define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)           /*!< 0x00000002 */
10287 #define USART_CR3_IREN                  USART_CR3_IREN_Msk                      /*!< IrDA mode Enable */
10288 #define USART_CR3_IRLP_Pos              (2U)
10289 #define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)           /*!< 0x00000004 */
10290 #define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                      /*!< IrDA Low-Power */
10291 #define USART_CR3_HDSEL_Pos             (3U)
10292 #define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)          /*!< 0x00000008 */
10293 #define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                     /*!< Half-Duplex Selection */
10294 #define USART_CR3_NACK_Pos              (4U)
10295 #define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)           /*!< 0x00000010 */
10296 #define USART_CR3_NACK                  USART_CR3_NACK_Msk                      /*!< SmartCard NACK enable */
10297 #define USART_CR3_SCEN_Pos              (5U)
10298 #define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)           /*!< 0x00000020 */
10299 #define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                      /*!< SmartCard mode enable */
10300 #define USART_CR3_DMAR_Pos              (6U)
10301 #define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)           /*!< 0x00000040 */
10302 #define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                      /*!< DMA Enable Receiver */
10303 #define USART_CR3_DMAT_Pos              (7U)
10304 #define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)           /*!< 0x00000080 */
10305 #define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                      /*!< DMA Enable Transmitter */
10306 #define USART_CR3_RTSE_Pos              (8U)
10307 #define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)           /*!< 0x00000100 */
10308 #define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                      /*!< RTS Enable */
10309 #define USART_CR3_CTSE_Pos              (9U)
10310 #define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)           /*!< 0x00000200 */
10311 #define USART_CR3_CTSE                  USART_CR3_CTSE_Msk
10312 #define USART_CR3_CTSIE_Pos             (10U)
10313 #define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)          /*!< 0x00000400 */
10314 #define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                     /*!< CTS Interrupt Enable */
10315 #define USART_CR3_ONEBIT_Pos            (11U)
10316 #define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)         /*!< 0x00000800 */
10317 #define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                    /*!< One sample bit method enable */
10318 #define USART_CR3_OVRDIS_Pos            (12U)
10319 #define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)         /*!< 0x00001000 */
10320 #define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                    /*!< Overrun Disable */
10321 #define USART_CR3_DDRE_Pos              (13U)
10322 #define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)           /*!< 0x00002000 */
10323 #define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                      /*!< DMA Disable on Reception Error */
10324 #define USART_CR3_DEM_Pos               (14U)
10325 #define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)            /*!< 0x00004000 */
10326 #define USART_CR3_DEM                   USART_CR3_DEM_Msk                       /*!< Driver Enable Mode */
10327 #define USART_CR3_DEP_Pos               (15U)
10328 #define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)            /*!< 0x00008000 */
10329 #define USART_CR3_DEP                   USART_CR3_DEP_Msk                       /*!< Driver Enable Polarity Selection */
10330 #define USART_CR3_SCARCNT_Pos           (17U)
10331 #define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)        /*!< 0x000E0000 */
10332 #define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                   /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
10333 #define USART_CR3_SCARCNT_0             (0x1U << USART_CR3_SCARCNT_Pos)         /*!< 0x00020000 */
10334 #define USART_CR3_SCARCNT_1             (0x2U << USART_CR3_SCARCNT_Pos)         /*!< 0x00040000 */
10335 #define USART_CR3_SCARCNT_2             (0x4U << USART_CR3_SCARCNT_Pos)         /*!< 0x00080000 */
10336 #define USART_CR3_WUS_Pos               (20U)
10337 #define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)            /*!< 0x00300000 */
10338 #define USART_CR3_WUS                   USART_CR3_WUS_Msk                       /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
10339 #define USART_CR3_WUS_0                 (0x1U << USART_CR3_WUS_Pos)             /*!< 0x00100000 */
10340 #define USART_CR3_WUS_1                 (0x2U << USART_CR3_WUS_Pos)             /*!< 0x00200000 */
10341 #define USART_CR3_WUFIE_Pos             (22U)
10342 #define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)          /*!< 0x00400000 */
10343 #define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                     /*!< Wake Up Interrupt Enable */
10344 #define USART_CR3_TXFTIE_Pos            (23U)
10345 #define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)         /*!< 0x00800000 */
10346 #define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                    /*!< TX FIFO Threshold Interrupt Enable */
10347 #define USART_CR3_TCBGTIE_Pos           (24U)
10348 #define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)        /*!< 0x01000000 */
10349 #define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                   /*!< Transmission Complete Before Guard Time Interrupt Enable */
10350 #define USART_CR3_RXFTCFG_Pos           (25U)
10351 #define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x0E000000 */
10352 #define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                   /*!< RX FIFO Threshold Configuration */
10353 #define USART_CR3_RXFTCFG_0             (0x1U << USART_CR3_RXFTCFG_Pos)         /*!< 0x02000000 */
10354 #define USART_CR3_RXFTCFG_1             (0x2U << USART_CR3_RXFTCFG_Pos)         /*!< 0x04000000 */
10355 #define USART_CR3_RXFTCFG_2             (0x4U << USART_CR3_RXFTCFG_Pos)         /*!< 0x08000000 */
10356 #define USART_CR3_RXFTIE_Pos            (28U)
10357 #define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)         /*!< 0x10000000 */
10358 #define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                    /*!< RX FIFO Threshold Interrupt Enable */
10359 #define USART_CR3_TXFTCFG_Pos           (29U)
10360 #define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)        /*!< 0xE0000000 */
10361 #define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                   /*!< TX FIFO Threshold configuration */
10362 #define USART_CR3_TXFTCFG_0             (0x1U << USART_CR3_TXFTCFG_Pos)         /*!< 0x20000000 */
10363 #define USART_CR3_TXFTCFG_1             (0x2U << USART_CR3_TXFTCFG_Pos)         /*!< 0x40000000 */
10364 #define USART_CR3_TXFTCFG_2             (0x4U << USART_CR3_TXFTCFG_Pos)         /*!< 0x80000000 */
10365 
10366 /******************  Bit definition for USART_BRR register  *******************/
10367 #define USART_BRR_BRR                   ((uint16_t)0xFFFF)                      /*!< USART  Baud rate register [15:0] */
10368 
10369 /******************  Bit definition for USART_GTPR register  ******************/
10370 #define USART_GTPR_PSC_Pos              (0U)
10371 #define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)          /*!< 0x000000FF */
10372 #define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                      /*!< PSC[7:0] bits (Prescaler value) */
10373 #define USART_GTPR_GT_Pos               (8U)
10374 #define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)           /*!< 0x0000FF00 */
10375 #define USART_GTPR_GT                   USART_GTPR_GT_Msk                       /*!< GT[7:0] bits (Guard time value) */
10376 
10377 /*******************  Bit definition for USART_RTOR register  *****************/
10378 #define USART_RTOR_RTO_Pos              (0U)
10379 #define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)      /*!< 0x00FFFFFF */
10380 #define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                      /*!< Receiver Timeout Value */
10381 #define USART_RTOR_BLEN_Pos             (24U)
10382 #define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)         /*!< 0xFF000000 */
10383 #define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                     /*!< Block Length */
10384 
10385 /*******************  Bit definition for USART_RQR register  ******************/
10386 #define USART_RQR_ABRRQ_Pos             (0U)
10387 #define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)          /*!< 0x00000001 */
10388 #define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                     /*!< Auto-Baud Rate Request */
10389 #define USART_RQR_SBKRQ_Pos             (1U)
10390 #define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)          /*!< 0x00000002 */
10391 #define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                     /*!< Send Break Request */
10392 #define USART_RQR_MMRQ_Pos              (2U)
10393 #define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)           /*!< 0x00000004 */
10394 #define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                      /*!< Mute Mode Request */
10395 #define USART_RQR_RXFRQ_Pos             (3U)
10396 #define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)          /*!< 0x00000008 */
10397 #define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                     /*!< Receive Data flush Request */
10398 #define USART_RQR_TXFRQ_Pos             (4U)
10399 #define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)          /*!< 0x00000010 */
10400 #define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                     /*!< Transmit Data flush Request */
10401 
10402 /*******************  Bit definition for USART_ISR register  ******************/
10403 #define USART_ISR_PE_Pos                (0U)
10404 #define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)             /*!< 0x00000001 */
10405 #define USART_ISR_PE                    USART_ISR_PE_Msk                        /*!< Parity Error */
10406 #define USART_ISR_FE_Pos                (1U)
10407 #define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)             /*!< 0x00000002 */
10408 #define USART_ISR_FE                    USART_ISR_FE_Msk                        /*!< Framing Error */
10409 #define USART_ISR_NE_Pos                (2U)
10410 #define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)             /*!< 0x00000004 */
10411 #define USART_ISR_NE                    USART_ISR_NE_Msk                        /*!< START bit Noise Error detection Flag */
10412 #define USART_ISR_ORE_Pos               (3U)
10413 #define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)            /*!< 0x00000008 */
10414 #define USART_ISR_ORE                   USART_ISR_ORE_Msk                       /*!< OverRun Error */
10415 #define USART_ISR_IDLE_Pos              (4U)
10416 #define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)           /*!< 0x00000010 */
10417 #define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                      /*!< IDLE line detected */
10418 #define USART_ISR_RXNE_Pos              (5U)
10419 #define USART_ISR_RXNE_Msk              (0x1UL << USART_ISR_RXNE_Pos)           /*!< 0x00000020 */
10420 #define USART_ISR_RXNE                  USART_ISR_RXNE_Msk                      /*!< Read Data Register Not Empty */
10421 #define USART_ISR_RXNE_RXFNE_Pos        USART_ISR_RXNE_Pos
10422 #define USART_ISR_RXNE_RXFNE_Msk        USART_ISR_RXNE_Msk                      /*!< 0x00000020 */
10423 #define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_Msk                      /*!< Read Data Register or RX FIFO Not Empty */
10424 #define USART_ISR_TC_Pos                (6U)
10425 #define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)             /*!< 0x00000040 */
10426 #define USART_ISR_TC                    USART_ISR_TC_Msk                        /*!< Transmission Complete */
10427 #define USART_ISR_TXE_Pos               (7U)
10428 #define USART_ISR_TXE_Msk               (0x1UL << USART_ISR_TXE_Pos)            /*!< 0x00000080 */
10429 #define USART_ISR_TXE                   USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty */
10430 #define USART_ISR_TXE_TXFNF_Pos         USART_ISR_TXE_Pos
10431 #define USART_ISR_TXE_TXFNF_Msk         USART_ISR_TXE_Msk                       /*!< 0x00000080 */
10432 #define USART_ISR_TXE_TXFNF             USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
10433 #define USART_ISR_LBDF_Pos              (8U)
10434 #define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)           /*!< 0x00000100 */
10435 #define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                      /*!< LIN Break Detection Flag */
10436 #define USART_ISR_CTSIF_Pos             (9U)
10437 #define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)          /*!< 0x00000200 */
10438 #define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                     /*!< CTS interrupt Flag */
10439 #define USART_ISR_CTS_Pos               (10U)
10440 #define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)            /*!< 0x00000400 */
10441 #define USART_ISR_CTS                   USART_ISR_CTS_Msk                       /*!< CTS Flag */
10442 #define USART_ISR_RTOF_Pos              (11U)
10443 #define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)           /*!< 0x00000800 */
10444 #define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                      /*!< Receiver Timeout */
10445 #define USART_ISR_EOBF_Pos              (12U)
10446 #define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)           /*!< 0x00001000 */
10447 #define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                      /*!< End Of Block Flag */
10448 #define USART_ISR_UDR_Pos               (13U)
10449 #define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)            /*!< 0x00002000 */
10450 #define USART_ISR_UDR                   USART_ISR_UDR_Msk                       /*!< SPI Slave Underrun error Flag */
10451 #define USART_ISR_ABRE_Pos              (14U)
10452 #define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)           /*!< 0x00004000 */
10453 #define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                      /*!< Auto-Baud Rate Error */
10454 #define USART_ISR_ABRF_Pos              (15U)
10455 #define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)           /*!< 0x00008000 */
10456 #define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                      /*!< Auto-Baud Rate Flag */
10457 #define USART_ISR_BUSY_Pos              (16U)
10458 #define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)           /*!< 0x00010000 */
10459 #define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                      /*!< Busy Flag */
10460 #define USART_ISR_CMF_Pos               (17U)
10461 #define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)            /*!< 0x00020000 */
10462 #define USART_ISR_CMF                   USART_ISR_CMF_Msk                       /*!< Character Match Flag */
10463 #define USART_ISR_SBKF_Pos              (18U)
10464 #define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)           /*!< 0x00040000 */
10465 #define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                      /*!< Send Break Flag */
10466 #define USART_ISR_RWU_Pos               (19U)
10467 #define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)            /*!< 0x00080000 */
10468 #define USART_ISR_RWU                   USART_ISR_RWU_Msk                       /*!< Receive Wake Up from mute mode Flag */
10469 #define USART_ISR_WUF_Pos               (20U)
10470 #define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)            /*!< 0x00100000 */
10471 #define USART_ISR_WUF                   USART_ISR_WUF_Msk                       /*!< Wake Up from stop mode Flag */
10472 #define USART_ISR_TEACK_Pos             (21U)
10473 #define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)          /*!< 0x00200000 */
10474 #define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                     /*!< Transmit Enable Acknowledge Flag */
10475 #define USART_ISR_REACK_Pos             (22U)
10476 #define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)          /*!< 0x00400000 */
10477 #define USART_ISR_REACK                 USART_ISR_REACK_Msk                     /*!< Receive Enable Acknowledge Flag */
10478 #define USART_ISR_TXFE_Pos              (23U)
10479 #define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)           /*!< 0x00800000 */
10480 #define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                      /*!< TX FIFO Empty Flag */
10481 #define USART_ISR_RXFF_Pos              (24U)
10482 #define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)           /*!< 0x01000000 */
10483 #define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                      /*!< RX FIFO Full Flag */
10484 #define USART_ISR_TCBGT_Pos             (25U)
10485 #define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)          /*!< 0x02000000 */
10486 #define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                     /*!< Transmission Complete Before Guard Time completion */
10487 #define USART_ISR_RXFT_Pos              (26U)
10488 #define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)           /*!< 0x04000000 */
10489 #define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                      /*!< RX FIFO Threshold Flag */
10490 #define USART_ISR_TXFT_Pos              (27U)
10491 #define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)           /*!< 0x08000000 */
10492 #define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                      /*!< TX FIFO Threshold Flag */
10493 
10494 /*******************  Bit definition for USART_ICR register  ******************/
10495 #define USART_ICR_PECF_Pos              (0U)
10496 #define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)           /*!< 0x00000001 */
10497 #define USART_ICR_PECF                  USART_ICR_PECF_Msk                      /*!< Parity Error Clear Flag */
10498 #define USART_ICR_FECF_Pos              (1U)
10499 #define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)           /*!< 0x00000002 */
10500 #define USART_ICR_FECF                  USART_ICR_FECF_Msk                      /*!< Framing Error Clear Flag */
10501 #define USART_ICR_NECF_Pos              (2U)
10502 #define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)           /*!< 0x00000004 */
10503 #define USART_ICR_NECF                  USART_ICR_NECF_Msk                      /*!< Noise Error detected Clear Flag */
10504 #define USART_ICR_ORECF_Pos             (3U)
10505 #define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)          /*!< 0x00000008 */
10506 #define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                     /*!< OverRun Error Clear Flag */
10507 #define USART_ICR_IDLECF_Pos            (4U)
10508 #define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)         /*!< 0x00000010 */
10509 #define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                    /*!< IDLE line detected Clear Flag */
10510 #define USART_ICR_TXFECF_Pos            (5U)
10511 #define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)         /*!< 0x00000020 */
10512 #define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                    /*!< TX FIFO Empty Clear Flag */
10513 #define USART_ICR_TCCF_Pos              (6U)
10514 #define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)           /*!< 0x00000040 */
10515 #define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                      /*!< Transmission Complete Clear Flag */
10516 #define USART_ICR_TCBGTCF_Pos           (7U)
10517 #define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)        /*!< 0x00000080 */
10518 #define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                   /*!< Transmission Complete Before Guard Time Clear Flag */
10519 #define USART_ICR_LBDCF_Pos             (8U)
10520 #define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)          /*!< 0x00000100 */
10521 #define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                     /*!< LIN Break Detection Clear Flag */
10522 #define USART_ICR_CTSCF_Pos             (9U)
10523 #define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)          /*!< 0x00000200 */
10524 #define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                     /*!< CTS Interrupt Clear Flag */
10525 #define USART_ICR_RTOCF_Pos             (11U)
10526 #define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)          /*!< 0x00000800 */
10527 #define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                     /*!< Receiver Time Out Clear Flag */
10528 #define USART_ICR_EOBCF_Pos             (12U)
10529 #define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)          /*!< 0x00001000 */
10530 #define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                     /*!< End Of Block Clear Flag */
10531 #define USART_ICR_UDRCF_Pos             (13U)
10532 #define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)          /*!< 0x00002000 */
10533 #define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                     /*!< SPI Slave Underrun Clear Flag */
10534 #define USART_ICR_CMCF_Pos              (17U)
10535 #define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)           /*!< 0x00020000 */
10536 #define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                      /*!< Character Match Clear Flag */
10537 #define USART_ICR_WUCF_Pos              (20U)
10538 #define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)           /*!< 0x00100000 */
10539 #define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                      /*!< Wake Up from stop mode Clear Flag */
10540 
10541 /*******************  Bit definition for USART_RDR register  ******************/
10542 #define USART_RDR_RDR_Pos               (0U)
10543 #define USART_RDR_RDR_Msk               (0x01FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */
10544 #define USART_RDR_RDR                   USART_RDR_RDR_Msk                       /*!< RDR[8:0] bits (Receive Data value) */
10545 
10546 /*******************  Bit definition for USART_TDR register  ******************/
10547 #define USART_TDR_TDR_Pos               (0U)
10548 #define USART_TDR_TDR_Msk               (0x01FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */
10549 #define USART_TDR_TDR                   USART_TDR_TDR_Msk                       /*!< TDR[8:0] bits (Transmit Data value) */
10550 
10551 /*******************  Bit definition for USART_PRESC register  ******************/
10552 #define USART_PRESC_PRESCALER_Pos       (0U)
10553 #define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)    /*!< 0x0000000F */
10554 #define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk               /*!< PRESCALER[3:0] bits (Clock prescaler) */
10555 #define USART_PRESC_PRESCALER_0         (0x1U << USART_PRESC_PRESCALER_Pos)     /*!< 0x00000001 */
10556 #define USART_PRESC_PRESCALER_1         (0x2U << USART_PRESC_PRESCALER_Pos)     /*!< 0x00000002 */
10557 #define USART_PRESC_PRESCALER_2         (0x4U << USART_PRESC_PRESCALER_Pos)     /*!< 0x00000004 */
10558 #define USART_PRESC_PRESCALER_3         (0x8U << USART_PRESC_PRESCALER_Pos)     /*!< 0x00000008 */
10559 
10560 /******************************************************************************/
10561 /*                                                                            */
10562 /*                            Window WATCHDOG                                 */
10563 /*                                                                            */
10564 /******************************************************************************/
10565 /*******************  Bit definition for WWDG_CR register  ********************/
10566 #define WWDG_CR_T_Pos           (0U)
10567 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
10568 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
10569 #define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
10570 #define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
10571 #define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
10572 #define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
10573 #define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
10574 #define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
10575 #define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
10576 
10577 #define WWDG_CR_WDGA_Pos        (7U)
10578 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
10579 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
10580 
10581 /*******************  Bit definition for WWDG_CFR register  *******************/
10582 #define WWDG_CFR_W_Pos          (0U)
10583 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
10584 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
10585 #define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
10586 #define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
10587 #define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
10588 #define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
10589 #define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
10590 #define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
10591 #define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
10592 
10593 #define WWDG_CFR_WDGTB_Pos      (11U)
10594 #define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
10595 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
10596 #define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */
10597 #define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */
10598 #define WWDG_CFR_WDGTB_2        (0x4U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */
10599 
10600 #define WWDG_CFR_EWI_Pos        (9U)
10601 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
10602 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
10603 
10604 /*******************  Bit definition for WWDG_SR register  ********************/
10605 #define WWDG_SR_EWIF_Pos        (0U)
10606 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
10607 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
10608 
10609 /******************************************************************************/
10610 /*                                                                            */
10611 /*                                Debug MCU                                   */
10612 /*                                                                            */
10613 /******************************************************************************/
10614 /********************  Bit definition for DBGMCU_IDCODE register  *************/
10615 #define DBGMCU_IDCODE_DEV_ID_Pos                          (0U)
10616 #define DBGMCU_IDCODE_DEV_ID_Msk                          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
10617 #define DBGMCU_IDCODE_DEV_ID                              DBGMCU_IDCODE_DEV_ID_Msk
10618 #define DBGMCU_IDCODE_REV_ID_Pos                          (16U)
10619 #define DBGMCU_IDCODE_REV_ID_Msk                          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
10620 #define DBGMCU_IDCODE_REV_ID                              DBGMCU_IDCODE_REV_ID_Msk
10621 
10622 /********************  Bit definition for DBGMCU_CR register  *****************/
10623 #define DBGMCU_CR_DBG_SLEEP_Pos                           (0U)
10624 #define DBGMCU_CR_DBG_SLEEP_Msk                           (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)  /*!< 0x00000001 */
10625 #define DBGMCU_CR_DBG_SLEEP                               DBGMCU_CR_DBG_SLEEP_Msk
10626 #define DBGMCU_CR_DBG_STOP_Pos                            (1U)
10627 #define DBGMCU_CR_DBG_STOP_Msk                            (0x1UL << DBGMCU_CR_DBG_STOP_Pos)   /*!< 0x00000002 */
10628 #define DBGMCU_CR_DBG_STOP                                DBGMCU_CR_DBG_STOP_Msk
10629 #define DBGMCU_CR_DBG_STANDBY_Pos                         (2U)
10630 #define DBGMCU_CR_DBG_STANDBY_Msk                         (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
10631 #define DBGMCU_CR_DBG_STANDBY                             DBGMCU_CR_DBG_STANDBY_Msk
10632 #define DBGMCU_CR_TRACE_IOEN_Pos                          (5U)
10633 #define DBGMCU_CR_TRACE_IOEN_Msk                          (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
10634 #define DBGMCU_CR_TRACE_IOEN                              DBGMCU_CR_TRACE_IOEN_Msk
10635 #define DBGMCU_CR_TRGOEN_Pos                              (28U)
10636 #define DBGMCU_CR_TRGOEN_Msk                              (0x1UL << DBGMCU_CR_TRGOEN_Pos)      /*!< 0x10000000 */
10637 #define DBGMCU_CR_TRGOEN                                  DBGMCU_CR_TRGOEN_Msk
10638 
10639 /********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
10640 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos                 (0U)
10641 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)  /*!< 0x00000001 */
10642 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP                     DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
10643 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos                  (10U)
10644 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk                  (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)   /*!< 0x00000400 */
10645 #define DBGMCU_APB1FZR1_DBG_RTC_STOP                      DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
10646 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos                 (11U)
10647 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)  /*!< 0x00000800 */
10648 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP                     DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
10649 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos                 (12U)
10650 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)  /*!< 0x00001000 */
10651 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP                     DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
10652 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos                 (21U)
10653 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)  /*!< 0x00200000 */
10654 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP                     DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
10655 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos               (31U)
10656 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk               (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
10657 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP                   DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
10658 
10659 /********************  Bit definition for DBGMCU_C2APB1FZR1 register  ***********/
10660 #define DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Pos               (0U)
10661 #define DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Msk               (0x1UL << DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Pos)  /*!< 0x00000001 */
10662 #define DBGMCU_C2APB1FZR1_DBG_TIM2_STOP                   DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Msk
10663 #define DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Pos                (10U)
10664 #define DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Msk                (0x1UL << DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Pos)   /*!< 0x00000400 */
10665 #define DBGMCU_C2APB1FZR1_DBG_RTC_STOP                    DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Msk
10666 #define DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Pos               (12U)
10667 #define DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Msk               (0x1UL << DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Pos)  /*!< 0x00001000 */
10668 #define DBGMCU_C2APB1FZR1_DBG_IWDG_STOP                   DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Msk
10669 #define DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Pos               (21U)
10670 #define DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Msk               (0x1UL << DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Pos)  /*!< 0x00200000 */
10671 #define DBGMCU_C2APB1FZR1_DBG_I2C1_STOP                   DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Msk
10672 #define DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Pos             (31U)
10673 #define DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Msk             (0x1UL << DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
10674 #define DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP                 DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Msk
10675 
10676 /********************  Bit definition for DBGMCU_APB1FZR2 register  ***********/
10677 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos               (5U)
10678 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk               (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
10679 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP                   DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
10680 
10681 /********************  Bit definition for DBGMCU_C2APB1FZR2 register  ***********/
10682 #define DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Pos             (5U)
10683 #define DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Msk             (0x1UL << DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
10684 #define DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP                 DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Msk
10685 
10686 /********************  Bit definition for DBGMCU_APB2FZR register  ************/
10687 #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos                  (11U)
10688 #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk                  (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) /*!< 0x000000800 */
10689 #define DBGMCU_APB2FZR_DBG_TIM1_STOP                      DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk
10690 
10691 /********************  Bit definition for DBGMCU_C2APB2FZR register  ************/
10692 #define DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Pos                (11U)
10693 #define DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Msk                (0x1UL << DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Pos) /*!< 0x000000800 */
10694 #define DBGMCU_C2APB2FZR_DBG_TIM1_STOP                    DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Msk
10695 
10696 /** @addtogroup Exported_macros
10697   * @{
10698   */
10699 
10700 
10701 /*********************** UART Instances : Asynchronous mode *******************/
10702 #define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10703 
10704 /*********************** UART Instances : FIFO mode ***************************/
10705 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10706                                          ((INSTANCE) == LPUART1))
10707 
10708 /*********************** UART Instances : SPI Slave mode **********************/
10709 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10710 
10711 /*********************** USART Instances : Synchronous mode *******************/
10712 #define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10713 
10714 /*********************** USART Instances : Auto Baud Rate detection ***********/
10715 
10716 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10717 
10718 /*********************** UART Instances : Half-Duplex mode ********************/
10719 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
10720                                                  ((INSTANCE) == LPUART1))
10721 
10722 /*********************** UART Instances : LIN mode ****************************/
10723 #define IS_UART_LIN_INSTANCE(INSTANCE)    ((INSTANCE) == USART1)
10724 
10725 /*********************** UART Instances : Wake-up from Stop mode **************/
10726 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
10727                                                       ((INSTANCE) == LPUART1))
10728 
10729 /*********************** UART Instances : Hardware Flow control ***************/
10730 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10731                                            ((INSTANCE) == LPUART1))
10732 
10733 /*********************** UART Instances : Smard card mode *********************/
10734 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10735 
10736 /*********************** UART Instances : Driver Enable ***********************/
10737 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1)|| \
10738                                                   ((INSTANCE) == LPUART1))
10739 
10740 /*********************** UART Instances : IRDA mode ***************************/
10741 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10742 
10743 /******************** LPUART Instance *****************************************/
10744 #define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
10745 
10746 /******************************* ADC Instances ********************************/
10747 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
10748 
10749 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
10750 
10751 /******************************* AES Instances ********************************/
10752 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES2)
10753 
10754 /******************************** COMP Instances ******************************/
10755 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1))
10756 
10757 #define IS_COMP_COMMON_INSTANCE(INSTANCE) (0U)
10758 
10759 /******************** COMP Instances with window mode capability **************/
10760 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (0U)
10761 
10762 /******************************* CRC Instances ********************************/
10763 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
10764 
10765 /******************************** DMA Instances *******************************/
10766 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
10767                                        ((INSTANCE) == DMA1_Channel2) || \
10768                                        ((INSTANCE) == DMA1_Channel3) || \
10769                                        ((INSTANCE) == DMA1_Channel4) || \
10770                                        ((INSTANCE) == DMA1_Channel5) || \
10771                                        ((INSTANCE) == DMA1_Channel6) || \
10772                                        ((INSTANCE) == DMA1_Channel7))
10773 
10774 /******************************** DMAMUX Instances ****************************/
10775 #define IS_DMAMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMAMUX1)
10776 
10777 #define IS_DMAMUX_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
10778                                                       ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
10779                                                       ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
10780                                                       ((INSTANCE) == DMAMUX1_RequestGenerator3))
10781 
10782 /******************************* GPIO Instances *******************************/
10783 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
10784                                         ((INSTANCE) == GPIOB) || \
10785                                         ((INSTANCE) == GPIOC) || \
10786                                         ((INSTANCE) == GPIOE) || \
10787                                         ((INSTANCE) == GPIOH))
10788 
10789 /******************************* GPIO AF Instances ****************************/
10790 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
10791 
10792 /**************************** GPIO Lock Instances *****************************/
10793 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
10794 
10795 /******************************** I2C Instances *******************************/
10796 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
10797 
10798 /****************** I2C Instances : wakeup capability from stop modes *********/
10799 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
10800 
10801 /******************************* SMBUS Instances ******************************/
10802 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
10803 
10804 /******************************* IPCC Instances ********************************/
10805 #define IS_IPCC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IPCC)
10806 
10807 /******************************** HSEM Instances *******************************/
10808 #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
10809 
10810 #define HSEM_CPU1_COREID        (0x00000004UL)/* Semaphore Core ID */
10811 #define HSEM_CPU2_COREID        (0x00000008UL)/* Semaphore Core ID */
10812 
10813 #define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/
10814 #define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */
10815 
10816 #define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */
10817 #define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */
10818 
10819 #define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */
10820 #define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */
10821 
10822 /******************************** PKA Instances *******************************/
10823 #define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA)
10824 
10825 /******************************* RNG Instances ********************************/
10826 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
10827 
10828 /****************************** RTC Instances *********************************/
10829 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
10830 
10831 /******************************** SPI Instances *******************************/
10832 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
10833 
10834 /****************** LPTIM Instances : All supported instances *****************/
10835 #define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
10836                                          ((INSTANCE) == LPTIM2))
10837 
10838 /****************** LPTIM Instances : Encoder mode ****************************/
10839 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
10840 
10841 /****************** TIM Instances : All supported instances *******************/
10842 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
10843                                          ((INSTANCE) == TIM2))
10844 
10845 /****************************** IWDG Instances ********************************/
10846 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
10847 
10848 /****************************** WWDG Instances ********************************/
10849 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
10850 
10851 /****************** TIM Instances : supporting 32 bits counter ****************/
10852 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
10853 
10854 /****************** TIM Instances : supporting the break function *************/
10855 #define IS_TIM_BREAK_INSTANCE(INSTANCE)  ((INSTANCE) == TIM1)
10856 
10857 /************** TIM Instances : supporting Break source selection *************/
10858 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE)  ((INSTANCE) == TIM1)
10859 
10860 /****************** TIM Instances : supporting 2 break inputs *****************/
10861 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
10862 
10863 /************* TIM Instances : at least 1 capture/compare channel *************/
10864 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
10865                                          ((INSTANCE) == TIM2))
10866 
10867 /************ TIM Instances : at least 2 capture/compare channels *************/
10868 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
10869                                          ((INSTANCE) == TIM2))
10870 
10871 /************ TIM Instances : at least 3 capture/compare channels *************/
10872 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
10873                                          ((INSTANCE) == TIM2))
10874 
10875 /************ TIM Instances : at least 4 capture/compare channels *************/
10876 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
10877                                          ((INSTANCE) == TIM2))
10878 
10879 /****************** TIM Instances : at least 5 capture/compare channels *******/
10880 #define IS_TIM_CC5_INSTANCE(INSTANCE)      ((INSTANCE) == TIM1)
10881 
10882 /****************** TIM Instances : at least 6 capture/compare channels *******/
10883 #define IS_TIM_CC6_INSTANCE(INSTANCE)      ((INSTANCE) == TIM1)
10884 
10885 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
10886 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
10887 
10888 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
10889 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
10890                                             ((INSTANCE) == TIM2))
10891 
10892 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
10893 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
10894                                             ((INSTANCE) == TIM2))
10895 
10896 /******************** TIM Instances : DMA burst feature ***********************/
10897 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
10898                                             ((INSTANCE) == TIM2))
10899 
10900 /******************* TIM Instances : Timer input selection ********************/
10901 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
10902                                          ((INSTANCE) == TIM2))
10903 
10904 /******************* TIM Instances : output(s) available **********************/
10905 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
10906   ((((INSTANCE) == TIM1) &&                  \
10907     (((CHANNEL) == TIM_CHANNEL_1) ||          \
10908      ((CHANNEL) == TIM_CHANNEL_2) ||          \
10909      ((CHANNEL) == TIM_CHANNEL_3) ||          \
10910      ((CHANNEL) == TIM_CHANNEL_4) ||          \
10911      ((CHANNEL) == TIM_CHANNEL_5) ||          \
10912      ((CHANNEL) == TIM_CHANNEL_6)))           \
10913    ||                                        \
10914    (((INSTANCE) == TIM2) &&                  \
10915     (((CHANNEL) == TIM_CHANNEL_1) ||          \
10916      ((CHANNEL) == TIM_CHANNEL_2) ||          \
10917      ((CHANNEL) == TIM_CHANNEL_3) ||          \
10918      ((CHANNEL) == TIM_CHANNEL_4))))
10919 
10920 /****************** TIM Instances : supporting complementary output(s) ********/
10921 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
10922   (((INSTANCE) == TIM1) &&                    \
10923    (((CHANNEL) == TIM_CHANNEL_1) ||           \
10924     ((CHANNEL) == TIM_CHANNEL_2) ||           \
10925     ((CHANNEL) == TIM_CHANNEL_3)))
10926 
10927 /****************** TIM Instances : supporting clock division *****************/
10928 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
10929                                                     ((INSTANCE) == TIM2))
10930 
10931 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
10932 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10933                                                         ((INSTANCE) == TIM2))
10934 
10935 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
10936 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10937                                                         ((INSTANCE) == TIM2))
10938 
10939 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
10940 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
10941                                                         ((INSTANCE) == TIM2))
10942 
10943 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
10944 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
10945                                                         ((INSTANCE) == TIM2))
10946 
10947 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
10948 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
10949 
10950 /****************** TIM Instances : supporting commutation event generation ***/
10951 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
10952 
10953 /****************** TIM Instances : supporting counting mode selection ********/
10954 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
10955                                                         ((INSTANCE) == TIM2))
10956 
10957 /****************** TIM Instances : supporting encoder interface **************/
10958 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
10959                                                       ((INSTANCE) == TIM2))
10960 
10961 /****************** TIM Instances : supporting Hall sensor interface **********/
10962 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
10963                                                          ((INSTANCE) == TIM2))
10964 
10965 /**************** TIM Instances : external trigger input available ************/
10966 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
10967                                             ((INSTANCE) == TIM2))
10968 
10969 /************* TIM Instances : supporting ETR source selection ***************/
10970 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
10971                                              ((INSTANCE) == TIM2))
10972 
10973 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
10974 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
10975                                             ((INSTANCE) == TIM2))
10976 
10977 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
10978 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
10979                                             ((INSTANCE) == TIM2))
10980 
10981 /****************** TIM Instances : supporting OCxREF clear *******************/
10982 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
10983                                                        ((INSTANCE) == TIM2))
10984 
10985 /****************** TIM Instances : remapping capability **********************/
10986 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
10987                                             ((INSTANCE) == TIM2))
10988 
10989 /****************** TIM Instances : supporting repetition counter *************/
10990 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  ((INSTANCE) == TIM1)
10991 
10992 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
10993 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
10994 
10995 /******************* TIM Instances : Timer input XOR function *****************/
10996 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
10997                                             ((INSTANCE) == TIM2))
10998 
10999 /************ TIM Instances : Advanced timers  ********************************/
11000 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
11001 
11002 /****************************** TSC Instances *********************************/
11003 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
11004 
11005 /**
11006   * @}
11007   */
11008 
11009 /**
11010   * @}
11011  */
11012 
11013 /**
11014   * @}
11015   */
11016 
11017 #ifdef __cplusplus
11018 }
11019 #endif /* __cplusplus */
11020 
11021 #endif /* __STM32WB15xx_H */
11022 
11023 /**
11024   * @}
11025   */
11026 
11027 /**
11028   * @}
11029 */
11030