1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32wbxx_ll_rcc.h"
22 #ifdef USE_FULL_ASSERT
23 #include "stm32_assert.h"
24 #else
25 #define assert_param(expr) ((void)0U)
26 #endif /* USE_FULL_ASSERT */
27
28 /** @addtogroup STM32WBxx_LL_Driver
29 * @{
30 */
31
32 #if defined(RCC)
33
34 /** @addtogroup RCC_LL
35 * @{
36 */
37
38 /* Private types -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /* Private constants ---------------------------------------------------------*/
41 /* Private macros ------------------------------------------------------------*/
42 /** @addtogroup RCC_LL_Private_Macros
43 * @{
44 */
45 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USART1_CLKSOURCE)
46
47 #if defined(LPUART1)
48 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)
49 #endif /* LPUART1 */
50
51 #if defined(I2C3)
52 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
53 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
54 #else
55 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
56 #endif /* I2C3 */
57
58 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
59 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))
60
61 #if defined(SAI1)
62 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
63 #endif /* SAI1 */
64
65 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
66
67 #define IS_LL_RCC_CLK48_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CLK48_CLKSOURCE))
68
69 #if defined(USB)
70 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
71 #endif /* USB */
72
73 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
74
75 /**
76 * @}
77 */
78
79 /* Private function prototypes -----------------------------------------------*/
80 /** @defgroup RCC_LL_Private_Functions RCC Private functions
81 * @{
82 */
83 static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
84 #if defined(SAI1)
85 static uint32_t RCC_PLL_GetFreqDomain_SAI(void);
86 #endif /* SAI1 */
87 static uint32_t RCC_PLL_GetFreqDomain_ADC(void);
88 static uint32_t RCC_PLL_GetFreqDomain_48M(void);
89
90 #if defined(SAI1)
91 static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void);
92 static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);
93 static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
94 #endif /* SAI1 */
95
96
97 static uint32_t RCC_GetSystemClockFreq(void);
98
99
100 static uint32_t RCC_GetHCLK1ClockFreq(uint32_t SYSCLK_Frequency);
101 static uint32_t RCC_GetHCLK2ClockFreq(uint32_t SYSCLK_Frequency);
102 static uint32_t RCC_GetHCLK4ClockFreq(uint32_t SYSCLK_Frequency);
103 static uint32_t RCC_GetHCLK5ClockFreq(void);
104
105
106 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
107 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
108 /**
109 * @}
110 */
111
112
113 /* Exported functions --------------------------------------------------------*/
114 /** @addtogroup RCC_LL_Exported_Functions
115 * @{
116 */
117
118 /** @addtogroup RCC_LL_EF_Init
119 * @{
120 */
121
122 /**
123 * @brief Reset the RCC clock to the default reset state.
124 * @note The default reset state of the clock configuration is given below:
125 * - MSI ON and used as system clock source
126 * - HSE, HSI, HSI48, PLL and PLLSAI1 Source OFF
127 * - CPU1, CPU2, AHB4, APB1 and APB2 prescaler set to 1.
128 * - CSS, MCO OFF
129 * - All interrupts disabled
130 * @note This function doesn't modify the configuration of the
131 * - Peripheral clocks
132 * - LSI, LSE and RTC clocks
133 * @retval An ErrorStatus enumeration value:
134 * - SUCCESS: RCC registers are de-initialized
135 * - ERROR: not applicable
136 */
LL_RCC_DeInit(void)137 ErrorStatus LL_RCC_DeInit(void)
138 {
139 uint32_t vl_mask;
140
141 /* Set MSION bit */
142 LL_RCC_MSI_Enable();
143
144 /* Insure MSIRDY bit is set before writing default MSIRANGE value */
145 while (LL_RCC_MSI_IsReady() == 0U)
146 {}
147
148 /* Set MSIRANGE default value */
149 LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
150
151 /* Set MSITRIM bits to the reset value*/
152 LL_RCC_MSI_SetCalibTrimming(0);
153
154 /* Set HSITRIM bits to the reset value*/
155 LL_RCC_HSI_SetCalibTrimming(0x40U);
156
157 /* Reset CFGR register */
158 LL_RCC_WriteReg(CFGR, 0x00070000U); /* MSI selected as System Clock and all prescaler to not divided */
159
160 /* Wait for MSI oscillator used as system clock */
161 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSI)
162 {}
163
164 /* Write new mask in CR register */
165 LL_RCC_WriteReg(CR, 0x00000061);
166
167 /* Wait for PLL READY bit to be reset */
168 while (LL_RCC_PLL_IsReady() != 0U)
169 {}
170
171 /* Reset PLLCFGR register */
172 LL_RCC_WriteReg(PLLCFGR, 0x22041000U);
173
174 #if defined(SAI1)
175 /* Wait for PLLSAI READY bit to be reset */
176 while (LL_RCC_PLLSAI1_IsReady() != 0U)
177 {}
178
179 /* Reset PLLSAI1CFGR register */
180 LL_RCC_WriteReg(PLLSAI1CFGR, 0x22041000U);
181 #endif /* SAI1 */
182
183 /* Disable all interrupts */
184 LL_RCC_WriteReg(CIER, 0x00000000U);
185
186 /* Clear all interrupt flags */
187 vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC |
188 RCC_CICR_PLLRDYC | RCC_CICR_CSSC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC;
189
190 #if defined(SAI1)
191 vl_mask |= RCC_CICR_PLLSAI1RDYC;
192 #endif /* SAI1 */
193
194 #if defined(RCC_HSI48_SUPPORT)
195 vl_mask |= RCC_CICR_HSI48RDYC;
196 #endif /* RCC_HSI48_SUPPORT */
197
198 LL_RCC_WriteReg(CICR, vl_mask);
199
200 /* Clear reset flags */
201 LL_RCC_ClearResetFlags();
202
203 #if defined(RCC_SMPS_SUPPORT)
204 /* SMPS reset */
205 LL_RCC_WriteReg(SMPSCR, 0x00000301U); /* MSI default clock source */
206 #endif /* RCC_SMPS_SUPPORT */
207
208 /* RF Wakeup Clock Source selection */
209 LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_NONE);
210
211 #if defined(RCC_HSI48_SUPPORT)
212 /* HSI48 reset */
213 LL_RCC_HSI48_Disable();
214 #endif /* RCC_HSI48_SUPPORT */
215
216 /* HSECR register write unlock & then reset*/
217 LL_RCC_WriteReg(HSECR, HSE_CONTROL_UNLOCK_KEY);
218 LL_RCC_WriteReg(HSECR, LL_RCC_HSE_CURRENTMAX_3); /* HSEGMC set to default value 011, current max limit 1.13 mA/V */
219
220 /* EXTCFGR reset*/
221 LL_RCC_WriteReg(EXTCFGR, 0x00030000U);
222
223 return SUCCESS;
224 }
225
226 /**
227 * @}
228 */
229
230 /** @addtogroup RCC_LL_EF_Get_Freq
231 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
232 * and different peripheral clocks available on the device.
233 * @note If SYSCLK source is MSI, function returns values based on MSI values(*)
234 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
235 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
236 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
237 * or HSI_VALUE(**) or MSI values(*) multiplied/divided by the PLL factors.
238 * @note (*) MSI values are retrieved thanks to __LL_RCC_CALC_MSI_FREQ macro
239 * @note (**) HSI_VALUE is a constant defined in this file (default value
240 * 16 MHz) but the real value may vary depending on the variations
241 * in voltage and temperature.
242 * @note (***) HSE_VALUE is a constant defined in this file (default value
243 * 32 MHz), user has to ensure that HSE_VALUE is same as the real
244 * frequency of the crystal used. Otherwise, this function may
245 * have wrong result.
246 * @note The result of this function could be incorrect when using fractional
247 * value for HSE crystal.
248 * @note This function can be used by the user application to compute the
249 * baud-rate for the communication peripherals or configure other parameters.
250 * @{
251 */
252
253 /**
254 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
255 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
256 * must be called to update structure fields. Otherwise, any
257 * configuration based on this function will be incorrect.
258 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
259 * @retval None
260 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)261 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
262 {
263 /* Get SYSCLK frequency */
264 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
265
266 /* HCLK1 clock frequency */
267 RCC_Clocks->HCLK1_Frequency = RCC_GetHCLK1ClockFreq(RCC_Clocks->SYSCLK_Frequency);
268
269 /* HCLK2 clock frequency */
270 RCC_Clocks->HCLK2_Frequency = RCC_GetHCLK2ClockFreq(RCC_Clocks->SYSCLK_Frequency);
271
272 /* HCLK4 clock frequency */
273 RCC_Clocks->HCLK4_Frequency = RCC_GetHCLK4ClockFreq(RCC_Clocks->SYSCLK_Frequency);
274
275 /* HCLK5 clock frequency */
276 RCC_Clocks->HCLK5_Frequency = RCC_GetHCLK5ClockFreq();
277
278 /* PCLK1 clock frequency */
279 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK1_Frequency);
280
281 /* PCLK2 clock frequency */
282 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK1_Frequency);
283 }
284
285 #if defined(RCC_SMPS_SUPPORT)
286 /**
287 * @brief Return SMPS clock frequency
288 * @note This function is only applicable when CPU runs,
289 * When waking up from Standby mode and powering on the VCODE supply, the HSI is
290 * selected as SMPS Step Down converter clock, independent from the selection in
291 * SMPSSEL.
292 * @retval SMPS clock frequency (in Hz)
293 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
294 */
LL_RCC_GetSMPSClockFreq(void)295 uint32_t LL_RCC_GetSMPSClockFreq(void)
296 {
297 uint32_t smps_frequency;
298 uint32_t smps_prescaler_index = ((LL_RCC_GetSMPSPrescaler()) >> RCC_SMPSCR_SMPSDIV_Pos);
299 uint32_t smpsClockSource = LL_RCC_GetSMPSClockSource();
300
301 if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSI) /* SMPS Clock source is HSI Osc. */
302 {
303 if (LL_RCC_HSI_IsReady() == 1U)
304 {
305 smps_frequency = HSI_VALUE / SmpsPrescalerTable[smps_prescaler_index][0];
306 }
307 else
308 {
309 smps_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
310 }
311 }
312 else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSE) /* SMPS Clock source is HSE Osc. */
313 {
314 if (LL_RCC_HSE_IsReady() == 1U)
315 {
316 smps_frequency = HSE_VALUE / SmpsPrescalerTable[smps_prescaler_index][5];
317 }
318 else
319 {
320 smps_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
321 }
322 }
323 else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_MSI) /* SMPS Clock source is MSI Osc. */
324 {
325 uint32_t msiRange = LL_RCC_MSI_GetRange();
326
327 if (msiRange == LL_RCC_MSIRANGE_8)
328 {
329 smps_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_8) / SmpsPrescalerTable[smps_prescaler_index][4];
330 }
331 else if (msiRange == LL_RCC_MSIRANGE_9)
332 {
333 smps_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_9) / SmpsPrescalerTable[smps_prescaler_index][3];
334 }
335 else if (msiRange == LL_RCC_MSIRANGE_10)
336 {
337 smps_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_10) / SmpsPrescalerTable[smps_prescaler_index][2];
338 }
339 else if (msiRange == LL_RCC_MSIRANGE_11)
340 {
341 smps_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_11) / SmpsPrescalerTable[smps_prescaler_index][1];
342 }
343 else
344 {
345 smps_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
346 }
347 }
348 else /* SMPS has no Clock */
349 {
350 smps_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
351 }
352
353 if (smps_frequency != LL_RCC_PERIPH_FREQUENCY_NO)
354 {
355 /* Systematic div by 2 */
356 smps_frequency = smps_frequency >> 1U;
357 }
358
359 return smps_frequency;
360 }
361 #endif /* RCC_SMPS_SUPPORT */
362
363 /**
364 * @brief Return USARTx clock frequency
365 * @param USARTxSource This parameter can be one of the following values:
366 * @arg @ref LL_RCC_USART1_CLKSOURCE
367 * @retval USART clock frequency (in Hz)
368 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
369 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)370 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
371 {
372 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
373
374 /* Check parameter */
375 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
376
377 /* USART1CLK clock frequency */
378 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
379 {
380 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
381 usart_frequency = RCC_GetSystemClockFreq();
382 break;
383
384 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
385 if (LL_RCC_HSI_IsReady() == 1U)
386 {
387 usart_frequency = HSI_VALUE;
388 }
389 break;
390
391 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
392 if (LL_RCC_LSE_IsReady() == 1U)
393 {
394 usart_frequency = LSE_VALUE;
395 }
396 break;
397
398 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
399 default:
400 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLK1ClockFreq(RCC_GetSystemClockFreq()));
401 break;
402 }
403 return usart_frequency;
404 }
405
406 /**
407 * @brief Return I2Cx clock frequency
408 * @param I2CxSource This parameter can be one of the following values:
409 * @arg @ref LL_RCC_I2C1_CLKSOURCE
410 * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
411 * @note (*) Value not defined for all devices
412 * @retval I2C clock frequency (in Hz)
413 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
414 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)415 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
416 {
417 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
418
419 /* Check parameter */
420 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
421
422 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
423 {
424 /* I2C1 CLK clock frequency */
425 switch (LL_RCC_GetI2CClockSource(I2CxSource))
426 {
427 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
428 i2c_frequency = RCC_GetSystemClockFreq();
429 break;
430
431 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
432 if (LL_RCC_HSI_IsReady() == 1U)
433 {
434 i2c_frequency = HSI_VALUE;
435 }
436 break;
437
438 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
439 default:
440 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLK1ClockFreq(RCC_GetSystemClockFreq()));
441 break;
442 }
443 }
444 #if defined(I2C3)
445 else
446 {
447 /* I2C3 CLK clock frequency */
448 switch (LL_RCC_GetI2CClockSource(I2CxSource))
449 {
450 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
451 i2c_frequency = RCC_GetSystemClockFreq();
452 break;
453
454 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
455 if (LL_RCC_HSI_IsReady() == 1U)
456 {
457 i2c_frequency = HSI_VALUE;
458 }
459 break;
460
461 case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
462 default:
463 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLK1ClockFreq(RCC_GetSystemClockFreq()));
464 break;
465 }
466 }
467 #endif /* I2C3 */
468
469 return i2c_frequency;
470 }
471
472 #if defined(LPUART1)
473 /**
474 * @brief Return LPUARTx clock frequency
475 * @param LPUARTxSource This parameter can be one of the following values:
476 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
477 * @retval LPUART clock frequency (in Hz)
478 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
479 */
LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)480 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
481 {
482 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
483
484 /* Check parameter */
485 assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
486
487 /* LPUART1CLK clock frequency */
488 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
489 {
490 case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
491 lpuart_frequency = RCC_GetSystemClockFreq();
492 break;
493
494 case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
495 if (LL_RCC_HSI_IsReady() == 1U)
496 {
497 lpuart_frequency = HSI_VALUE;
498 }
499 break;
500
501 case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
502 if (LL_RCC_LSE_IsReady() == 1U)
503 {
504 lpuart_frequency = LSE_VALUE;
505 }
506 break;
507
508 case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */
509 default:
510 lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLK1ClockFreq(RCC_GetSystemClockFreq()));
511 break;
512 }
513
514 return lpuart_frequency;
515 }
516 #endif /* LPUART1 */
517
518 /**
519 * @brief Return LPTIMx clock frequency
520 * @param LPTIMxSource This parameter can be one of the following values:
521 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
522 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
523 * @retval LPTIM clock frequency (in Hz)
524 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
525 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)526 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
527 {
528 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
529 uint32_t temp = LL_RCC_LSI2_IsReady();
530
531 /* Check parameter */
532 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
533
534 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
535 {
536 /* LPTIM1CLK clock frequency */
537 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
538 {
539 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
540 if ((LL_RCC_LSI1_IsReady() == 1UL) || (temp == 1UL))
541 {
542 lptim_frequency = LSI_VALUE;
543 }
544 break;
545
546 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
547 if (LL_RCC_HSI_IsReady() == 1U)
548 {
549 lptim_frequency = HSI_VALUE;
550 }
551 break;
552
553 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
554 if (LL_RCC_LSE_IsReady() == 1U)
555 {
556 lptim_frequency = LSE_VALUE;
557 }
558 break;
559
560 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
561 default:
562 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLK1ClockFreq(RCC_GetSystemClockFreq()));
563 break;
564 }
565 }
566 else
567 {
568 /* LPTIM2CLK clock frequency */
569 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
570 {
571 case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */
572 if ((LL_RCC_LSI1_IsReady() == 1UL) || (temp == 1UL))
573 {
574 lptim_frequency = LSI_VALUE;
575 }
576 break;
577
578 case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */
579 if (LL_RCC_HSI_IsReady() == 1U)
580 {
581 lptim_frequency = HSI_VALUE;
582 }
583 break;
584
585 case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */
586 if (LL_RCC_LSE_IsReady() == 1U)
587 {
588 lptim_frequency = LSE_VALUE;
589 }
590 break;
591
592 case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */
593 default:
594 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLK1ClockFreq(RCC_GetSystemClockFreq()));
595 break;
596 }
597 }
598
599 return lptim_frequency;
600 }
601
602 #if defined(SAI1)
603 /**
604 * @brief Return SAIx clock frequency
605 * @param SAIxSource This parameter can be one of the following values:
606 * @arg @ref LL_RCC_SAI1_CLKSOURCE
607 *
608 * @retval SAI clock frequency (in Hz)
609 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
610 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
611 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)612 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
613 {
614 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
615
616 /* Check parameter */
617 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
618
619 switch (LL_RCC_GetSAIClockSource(SAIxSource))
620 {
621 case LL_RCC_SAI1_CLKSOURCE_HSI: /* HSI clock used as SAI1 clock source */
622 if (LL_RCC_HSI_IsReady() == 1U)
623 {
624 sai_frequency = HSI_VALUE;
625 }
626 break;
627
628 case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */
629 if (LL_RCC_PLLSAI1_IsReady() == 1U)
630 {
631 if (LL_RCC_PLLSAI1_IsEnabledDomain_SAI() == 1U)
632 {
633 sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
634 }
635 }
636 break;
637
638 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
639 if (LL_RCC_PLL_IsReady() == 1U)
640 {
641 if (LL_RCC_PLL_IsEnabledDomain_SAI() == 1U)
642 {
643 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
644 }
645 }
646 break;
647
648 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
649 default:
650 sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
651 break;
652 }
653 return sai_frequency;
654 }
655 #endif /* SAI1 */
656
657 /**
658 * @brief Return CLK48x clock frequency
659 * @param CLK48xSource This parameter can be one of the following values:
660 * @arg @ref LL_RCC_CLK48_CLKSOURCE
661 * @retval USB clock frequency (in Hz)
662 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI48) or PLLs (PLL or PLLSAI1)
663 * is not ready
664 */
LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource)665 uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource)
666 {
667 uint32_t clk48_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
668
669 /* Check parameter */
670 assert_param(IS_LL_RCC_CLK48_CLKSOURCE(CLK48xSource));
671
672 /* CLK48CLK clock frequency */
673 switch (LL_RCC_GetCLK48ClockSource(CLK48xSource))
674 {
675 #if defined(SAI1)
676 case LL_RCC_CLK48_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as CLK48 clock source */
677 if (LL_RCC_PLLSAI1_IsReady() == 1U)
678 {
679 if (LL_RCC_PLLSAI1_IsEnabledDomain_48M() == 1U)
680 {
681 clk48_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
682 }
683 }
684 break;
685 #endif /* SAI1 */
686
687 case LL_RCC_CLK48_CLKSOURCE_PLL: /* PLL clock used as CLK48 clock source */
688 if (LL_RCC_PLL_IsReady() == 1U)
689 {
690 if (LL_RCC_PLL_IsEnabledDomain_48M() == 1U)
691 {
692 clk48_frequency = RCC_PLL_GetFreqDomain_48M();
693 }
694 }
695 break;
696
697 case LL_RCC_CLK48_CLKSOURCE_MSI: /* MSI clock used as CLK48 clock source */
698 if (LL_RCC_MSI_IsReady() == 1U)
699 {
700 clk48_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
701 }
702 break;
703
704 #if defined(RCC_HSI48_SUPPORT)
705 case LL_RCC_CLK48_CLKSOURCE_HSI48: /* HSI48 clock used as CLK48 clock source */
706 default:
707 if (LL_RCC_HSI48_IsReady() == 1U)
708 {
709 clk48_frequency = HSI48_VALUE;
710 }
711 break;
712 #else
713 default:
714 /* Nothing to do */
715 break;
716 #endif /* RCC_HSI48_SUPPORT */
717 }
718
719 return clk48_frequency;
720 }
721
722 #if defined(USB)
723 /**
724 * @brief Return USBx clock frequency
725 * @param USBxSource This parameter can be one of the following values:
726 * @arg @ref LL_RCC_CLK48_CLKSOURCE
727 * @retval USB clock frequency (in Hz)
728 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI48) or PLLs (PLL or PLLSAI1)
729 * is not ready
730 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)731 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
732 {
733 return LL_RCC_GetCLK48ClockFreq(USBxSource);
734 }
735 #endif /* USB */
736
737 /**
738 * @brief Return RNGx clock frequency
739 * @param RNGxSource This parameter can be one of the following values:
740 * @arg @ref LL_RCC_RNG_CLKSOURCE
741 * @retval RNG clock frequency (in Hz)
742 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI48) or PLLs (PLL or PLLSAI1)
743 * is not ready
744 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)745 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
746 {
747 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
748 uint32_t rngClockSource = LL_RCC_GetRNGClockSource(RNGxSource);
749
750 /* Check parameter */
751 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
752
753 /* RNGCLK clock frequency */
754 if (rngClockSource == LL_RCC_RNG_CLKSOURCE_LSI) /* LSI clock used as RNG clock source */
755 {
756 const uint32_t temp_lsi1Status = LL_RCC_LSI1_IsReady();
757 const uint32_t temp_lsi2Status = LL_RCC_LSI2_IsReady();
758 if ((temp_lsi1Status == 1U) || (temp_lsi2Status == 1U))
759 {
760 rng_frequency = LSI_VALUE;
761 }
762 }
763 else if (rngClockSource == LL_RCC_RNG_CLKSOURCE_LSE) /* LSE clock used as RNG clock source */
764 {
765 if (LL_RCC_LSE_IsReady() == 1U)
766 {
767 rng_frequency = LSE_VALUE;
768 }
769 }
770 else /* CLK48 clock used as RNG clock source */
771 {
772 /* Systematic Div by 3 */
773 rng_frequency = LL_RCC_GetCLK48ClockFreq(LL_RCC_CLK48_CLKSOURCE) / 3U;
774 }
775 return rng_frequency;
776 }
777
778 /**
779 * @brief Return ADCx clock frequency
780 * @param ADCxSource This parameter can be one of the following values:
781 * @arg @ref LL_RCC_ADC_CLKSOURCE
782 * @retval ADC clock frequency (in Hz)
783 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
784 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
785 */
LL_RCC_GetADCClockFreq(uint32_t ADCxSource)786 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
787 {
788 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
789
790 /* Check parameter */
791 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
792
793 /* ADCCLK clock frequency */
794 switch (LL_RCC_GetADCClockSource(ADCxSource))
795 {
796 #if defined(SAI1)
797 case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */
798 if (LL_RCC_PLLSAI1_IsReady() == 1U)
799 {
800 if (LL_RCC_PLLSAI1_IsEnabledDomain_ADC() == 1U)
801 {
802 adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC();
803 }
804 }
805 break;
806 #endif /* SAI1 */
807
808 case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */
809 adc_frequency = RCC_GetSystemClockFreq();
810 break;
811
812 case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as ADC clock source */
813 if (LL_RCC_PLL_IsReady() == 1U)
814 {
815 if (LL_RCC_PLL_IsEnabledDomain_ADC() == 1U)
816 {
817 adc_frequency = RCC_PLL_GetFreqDomain_ADC();
818 }
819 }
820 break;
821
822 case LL_RCC_ADC_CLKSOURCE_NONE: /* No clock used as ADC clock source */
823 default:
824 adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
825 break;
826 }
827
828 return adc_frequency;
829 }
830
831 /**
832 * @brief Return RTC & LCD clock frequency
833 * @retval RTC clock frequency (in Hz)
834 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready
835 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
836 */
LL_RCC_GetRTCClockFreq(void)837 uint32_t LL_RCC_GetRTCClockFreq(void)
838 {
839 uint32_t rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
840 uint32_t temp = LL_RCC_LSI2_IsReady();
841
842 /* RTCCLK clock frequency */
843 switch (LL_RCC_GetRTCClockSource())
844 {
845 case LL_RCC_RTC_CLKSOURCE_LSE: /* LSE clock used as RTC clock source */
846 if (LL_RCC_LSE_IsReady() == 1U)
847 {
848 rtc_frequency = LSE_VALUE;
849 }
850 break;
851
852 case LL_RCC_RTC_CLKSOURCE_LSI: /* LSI clock used as RTC clock source */
853
854 if ((LL_RCC_LSI1_IsReady() == 1UL) || (temp == 1UL))
855 {
856 rtc_frequency = LSI_VALUE;
857 }
858 break;
859
860 case LL_RCC_RTC_CLKSOURCE_HSE_DIV32: /* HSE clock used as ADC clock source */
861 rtc_frequency = HSE_VALUE / 32U;
862 break;
863
864 case LL_RCC_RTC_CLKSOURCE_NONE: /* No clock used as RTC clock source */
865 default:
866 rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
867 break;
868 }
869
870 return rtc_frequency;
871 }
872
873 /**
874 * @brief Return RF Wakeup clock frequency
875 * @retval RFWKP clock frequency (in Hz)
876 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready
877 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
878 */
LL_RCC_GetRFWKPClockFreq(void)879 uint32_t LL_RCC_GetRFWKPClockFreq(void)
880 {
881 uint32_t rfwkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
882
883 /* RTCCLK clock frequency */
884 switch (LL_RCC_GetRFWKPClockSource())
885 {
886 case LL_RCC_RFWKP_CLKSOURCE_LSE: /* LSE clock used as RF Wakeup clock source */
887 if (LL_RCC_LSE_IsReady() == 1U)
888 {
889 rfwkp_frequency = LSE_VALUE;
890 }
891 break;
892
893 case LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024: /* HSE clock used as RF Wakeup clock source */
894 rfwkp_frequency = HSE_VALUE / 1024U;
895 break;
896
897 case LL_RCC_RFWKP_CLKSOURCE_NONE: /* No clock used as RF Wakeup clock source */
898 default:
899 rfwkp_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
900 break;
901 }
902
903 return rfwkp_frequency;
904 }
905
906 /**
907 * @}
908 */
909
910 /**
911 * @}
912 */
913
914 /** @addtogroup RCC_LL_Private_Functions
915 * @{
916 */
917
918 /**
919 * @brief Return SYSTEM clock (SYSCLK) frequency
920 * @retval SYSTEM clock frequency (in Hz)
921 */
RCC_GetSystemClockFreq(void)922 static uint32_t RCC_GetSystemClockFreq(void)
923 {
924 uint32_t frequency;
925
926 /* Get SYSCLK source -------------------------------------------------------*/
927 switch (LL_RCC_GetSysClkSource())
928 {
929 case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
930 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
931 break;
932
933 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
934 frequency = HSI_VALUE;
935 break;
936
937 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
938 if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
939 {
940 frequency = HSE_VALUE / 2U;
941 }
942 else
943 {
944 frequency = HSE_VALUE;
945 }
946 break;
947
948 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
949 frequency = RCC_PLL_GetFreqDomain_SYS();
950 break;
951
952 default:
953 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
954 break;
955 }
956
957 return frequency;
958 }
959
960 /**
961 * @brief Return HCLK1 clock frequency
962 * @param SYSCLK_Frequency SYSCLK clock frequency
963 * @retval HCLK1 clock frequency (in Hz)
964 */
RCC_GetHCLK1ClockFreq(uint32_t SYSCLK_Frequency)965 static uint32_t RCC_GetHCLK1ClockFreq(uint32_t SYSCLK_Frequency)
966 {
967 /* HCLK clock frequency */
968 return __LL_RCC_CALC_HCLK1_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
969 }
970
971 /**
972 * @brief Return HCLK2 clock frequency
973 * @param SYSCLK_Frequency SYSCLK clock frequency
974 * @retval HCLK2 clock frequency (in Hz)
975 */
RCC_GetHCLK2ClockFreq(uint32_t SYSCLK_Frequency)976 static uint32_t RCC_GetHCLK2ClockFreq(uint32_t SYSCLK_Frequency)
977 {
978 /* HCLK clock frequency */
979 return __LL_RCC_CALC_HCLK2_FREQ(SYSCLK_Frequency, LL_C2_RCC_GetAHBPrescaler());
980 }
981
982 /**
983 * @brief Return HCLK clock frequency
984 * @param SYSCLK_Frequency SYSCLK clock frequency
985 * @retval HCLK4 clock frequency (in Hz)
986 */
RCC_GetHCLK4ClockFreq(uint32_t SYSCLK_Frequency)987 static uint32_t RCC_GetHCLK4ClockFreq(uint32_t SYSCLK_Frequency)
988 {
989 /* HCLK clock frequency */
990 return __LL_RCC_CALC_HCLK4_FREQ(SYSCLK_Frequency, LL_RCC_GetAHB4Prescaler());
991 }
992
993 /**
994 * @brief Return HCLK5 clock frequency
995 * @retval HCLK5 clock frequency (in Hz)
996 */
RCC_GetHCLK5ClockFreq(void)997 static uint32_t RCC_GetHCLK5ClockFreq(void)
998 {
999 uint32_t frequency;
1000
1001 /* Get SYSCLK source -------------------------------------------------------*/
1002 switch (LL_RCC_GetRFClockSource())
1003 {
1004 case LL_RCC_RF_CLKSOURCE_HSI: /* HSI used as system clock source */
1005 frequency = HSI_VALUE;
1006 break;
1007
1008 case LL_RCC_RF_CLKSOURCE_HSE_DIV2: /* HSE Div2 used as system clock source */
1009 frequency = HSE_VALUE / 2U;
1010 break;
1011
1012 default:
1013 frequency = HSI_VALUE;
1014 break;
1015 }
1016
1017 return frequency;
1018 }
1019
1020 /**
1021 * @brief Return PCLK1 clock frequency
1022 * @param HCLK_Frequency HCLK clock frequency
1023 * @retval PCLK1 clock frequency (in Hz)
1024 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1025 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1026 {
1027 /* PCLK1 clock frequency */
1028 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1029 }
1030
1031 /**
1032 * @brief Return PCLK2 clock frequency
1033 * @param HCLK_Frequency HCLK clock frequency
1034 * @retval PCLK2 clock frequency (in Hz)
1035 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)1036 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1037 {
1038 /* PCLK2 clock frequency */
1039 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1040 }
1041
1042 /**
1043 * @brief Return PLL clock (PLLRCLK) frequency used for system domain
1044 * @retval PLLRCLK clock frequency (in Hz)
1045 */
RCC_PLL_GetFreqDomain_SYS(void)1046 static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
1047 {
1048 uint32_t pllinputfreq;
1049 uint32_t pllsource;
1050
1051 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLN
1052 SYSCLK = PLL_VCO / PLLR
1053 */
1054 pllsource = LL_RCC_PLL_GetMainSource();
1055
1056 switch (pllsource)
1057 {
1058 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1059 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
1060 break;
1061
1062 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1063 pllinputfreq = HSI_VALUE;
1064 break;
1065
1066 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1067 if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
1068 {
1069 pllinputfreq = HSE_VALUE / 2U;
1070 }
1071 else
1072 {
1073 pllinputfreq = HSE_VALUE;
1074 }
1075 break;
1076
1077 default:
1078 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
1079 break;
1080 }
1081 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1082 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1083 }
1084
1085 #if defined(SAI1)
1086 /**
1087 * @brief Return PLL clock (PLLPCLK) frequency used for SAI domain
1088 * @retval PLLPCLK clock frequency (in Hz)
1089 */
RCC_PLL_GetFreqDomain_SAI(void)1090 static uint32_t RCC_PLL_GetFreqDomain_SAI(void)
1091 {
1092 uint32_t pllinputfreq;
1093 uint32_t pllsource;
1094
1095 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI Value / PLLM) * PLLN
1096 SAI Domain clock = PLL_VCO / PLLP
1097 */
1098 pllsource = LL_RCC_PLL_GetMainSource();
1099
1100 switch (pllsource)
1101 {
1102 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1103 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
1104 break;
1105
1106 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1107 pllinputfreq = HSI_VALUE;
1108 break;
1109
1110 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1111 if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
1112 {
1113 pllinputfreq = HSE_VALUE / 2U;
1114 }
1115 else
1116 {
1117 pllinputfreq = HSE_VALUE;
1118 }
1119 break;
1120
1121 default:
1122 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
1123 break;
1124 }
1125 return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1126 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1127 }
1128 #endif /* SAI1 */
1129
1130 /**
1131 * @brief Return PLL clock (PLLPCLK) frequency used for ADC domain
1132 * @retval PLLPCLK clock frequency (in Hz)
1133 */
RCC_PLL_GetFreqDomain_ADC(void)1134 static uint32_t RCC_PLL_GetFreqDomain_ADC(void)
1135 {
1136 uint32_t pllinputfreq;
1137 uint32_t pllsource;
1138
1139 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI Value / PLLM) * PLLN
1140 SAI Domain clock = PLL_VCO / PLLP
1141 */
1142 pllsource = LL_RCC_PLL_GetMainSource();
1143
1144 switch (pllsource)
1145 {
1146 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1147 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
1148 break;
1149
1150 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1151 pllinputfreq = HSI_VALUE;
1152 break;
1153
1154 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1155 if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
1156 {
1157 pllinputfreq = HSE_VALUE / 2U;
1158 }
1159 else
1160 {
1161 pllinputfreq = HSE_VALUE;
1162 }
1163
1164 break;
1165
1166 default:
1167 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
1168 break;
1169 }
1170 return __LL_RCC_CALC_PLLCLK_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1171 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1172 }
1173
1174 /**
1175 * @brief Return PLL clock (PLLQCLK) frequency used for 48 MHz domain
1176 * @retval PLLQCLK clock frequency (in Hz)
1177 */
RCC_PLL_GetFreqDomain_48M(void)1178 static uint32_t RCC_PLL_GetFreqDomain_48M(void)
1179 {
1180 uint32_t pllinputfreq;
1181 uint32_t pllsource;
1182
1183 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLN
1184 48M Domain clock = PLL_VCO / PLLQ
1185 */
1186 pllsource = LL_RCC_PLL_GetMainSource();
1187
1188 switch (pllsource)
1189 {
1190 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1191 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
1192 break;
1193
1194 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1195 pllinputfreq = HSI_VALUE;
1196 break;
1197
1198 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1199 if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
1200 {
1201 pllinputfreq = HSE_VALUE / 2U;
1202 }
1203 else
1204 {
1205 pllinputfreq = HSE_VALUE;
1206 }
1207
1208 break;
1209
1210 default:
1211 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
1212 break;
1213 }
1214 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1215 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1216 }
1217
1218 #if defined(SAI1)
1219 /**
1220 * @brief Return PLLSAI1 clock (PLLSAI1PCLK) frequency used for SAI domain
1221 * @retval PLLSAI1PCLK clock frequency (in Hz)
1222 */
RCC_PLLSAI1_GetFreqDomain_SAI(void)1223 static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)
1224 {
1225 uint32_t pllinputfreq;
1226 uint32_t pllsource;
1227
1228 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLSAI1N */
1229 /* SAI Domain clock = PLLSAI1_VCO / PLLSAI1P */
1230 pllsource = LL_RCC_PLL_GetMainSource();
1231
1232 switch (pllsource)
1233 {
1234 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
1235 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
1236 break;
1237
1238 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
1239 pllinputfreq = HSI_VALUE;
1240 break;
1241
1242 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
1243 if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
1244 {
1245 pllinputfreq = HSE_VALUE / 2U;
1246 }
1247 else
1248 {
1249 pllinputfreq = HSE_VALUE;
1250 }
1251
1252 break;
1253
1254 default:
1255 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
1256 break;
1257 }
1258 return __LL_RCC_CALC_PLLSAI1_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1259 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP());
1260 }
1261
1262 /**
1263 * @brief Return PLLSAI1 clock (PLLSAI1QCLK) frequency used for 48Mhz domain
1264 * @retval PLLSAI1QCLK clock frequency (in Hz)
1265 */
RCC_PLLSAI1_GetFreqDomain_48M(void)1266 static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)
1267 {
1268 uint32_t pllinputfreq;
1269 uint32_t pllsource;
1270
1271 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLSAI1N */
1272 /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1Q */
1273 pllsource = LL_RCC_PLL_GetMainSource();
1274
1275 switch (pllsource)
1276 {
1277 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
1278 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
1279 break;
1280
1281 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
1282 pllinputfreq = HSI_VALUE;
1283 break;
1284
1285 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
1286 if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
1287 {
1288 pllinputfreq = HSE_VALUE / 2U;
1289 }
1290 else
1291 {
1292 pllinputfreq = HSE_VALUE;
1293 }
1294 break;
1295
1296 default:
1297 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
1298 break;
1299 }
1300 return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1301 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ());
1302 }
1303
1304 /**
1305 * @brief Return PLLSAI1 clock (PLLSAI1RCLK) frequency used for ADC domain
1306 * @retval PLLSAI1RCLK clock frequency (in Hz)
1307 */
RCC_PLLSAI1_GetFreqDomain_ADC(void)1308 static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
1309 {
1310 uint32_t pllinputfreq;
1311 uint32_t pllsource;
1312
1313 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLSAI1N */
1314 /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1R */
1315 pllsource = LL_RCC_PLL_GetMainSource();
1316
1317 switch (pllsource)
1318 {
1319 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
1320 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
1321 break;
1322
1323 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
1324 pllinputfreq = HSI_VALUE;
1325 break;
1326
1327 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
1328 if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
1329 {
1330 pllinputfreq = HSE_VALUE / 2U;
1331 }
1332 else
1333 {
1334 pllinputfreq = HSE_VALUE;
1335 }
1336 break;
1337
1338 default:
1339 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
1340 break;
1341 }
1342 return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1343 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR());
1344 }
1345 #endif /* SAI1 */
1346
1347 /**
1348 * @}
1349 */
1350
1351 /**
1352 * @}
1353 */
1354
1355 #endif /* RCC */
1356
1357 /**
1358 * @}
1359 */
1360
1361 #endif /* USE_FULL_LL_DRIVER */
1362
