1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32wbxx_ll_dma.h"
22 #include "stm32wbxx_ll_bus.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif /* USE_FULL_ASSERT */
28
29 /** @addtogroup STM32WBxx_LL_Driver
30 * @{
31 */
32
33 #if defined (DMA1) || defined (DMA2)
34
35 /** @defgroup DMA_LL DMA
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43 /** @addtogroup DMA_LL_Private_Macros
44 * @{
45 */
46 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
47 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
48 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
49
50 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
51 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
52
53 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
54 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
55
56 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
57 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
58
59 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
60 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
61 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
62
63 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
64 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
65 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
66
67 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
68
69 #define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= 40U)
70
71 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
72 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
73 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
74 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
75
76 #if defined (DMA2)
77 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
78 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
79 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
80 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
81 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
82 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
83 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
84 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
85 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
86 (((INSTANCE) == DMA2) && \
87 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
88 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
89 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
90 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
91 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
92 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
93 ((CHANNEL) == LL_DMA_CHANNEL_7))))
94 #else
95 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
96 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
97 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
98 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
99 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
100 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
101 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
102 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
103 (((INSTANCE) == DMA2) && \
104 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
105 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
106 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
107 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
108 ((CHANNEL) == LL_DMA_CHANNEL_5))))
109 #endif /* DMA2_Channel6 && DMA2_Channel7*/
110 #else
111 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
112 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
113 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
114 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
115 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
116 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
117 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
118 ((CHANNEL) == LL_DMA_CHANNEL_7))))
119 #endif /* DMA2 */
120 /**
121 * @}
122 */
123
124 /* Private function prototypes -----------------------------------------------*/
125
126 /* Exported functions --------------------------------------------------------*/
127 /** @addtogroup DMA_LL_Exported_Functions
128 * @{
129 */
130
131 /** @addtogroup DMA_LL_EF_Init
132 * @{
133 */
134
135 /**
136 * @brief De-initialize the DMA registers to their default reset values.
137 * @param DMAx DMAx Instance
138 * @param Channel This parameter can be one of the following values:
139 * @arg @ref LL_DMA_CHANNEL_1
140 * @arg @ref LL_DMA_CHANNEL_2
141 * @arg @ref LL_DMA_CHANNEL_3
142 * @arg @ref LL_DMA_CHANNEL_4
143 * @arg @ref LL_DMA_CHANNEL_5
144 * @arg @ref LL_DMA_CHANNEL_6
145 * @arg @ref LL_DMA_CHANNEL_7
146 * @arg @ref LL_DMA_CHANNEL_ALL
147 * @retval ErrorStatus
148 * - SUCCESS: DMA registers are de-initialized
149 * - ERROR: DMA registers are not de-initialized
150 */
LL_DMA_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)151 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
152 {
153 DMA_Channel_TypeDef *tmp;
154 ErrorStatus status = SUCCESS;
155
156 /* Check the DMA Instance DMAx and Channel parameters*/
157 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
158
159 if (Channel == LL_DMA_CHANNEL_ALL)
160 {
161 if (DMAx == DMA1)
162 {
163 /* Force reset of DMA clock */
164 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
165
166 /* Release reset of DMA clock */
167 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
168 }
169 #if defined(DMA2)
170 else if (DMAx == DMA2)
171 {
172 /* Force reset of DMA clock */
173 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
174
175 /* Release reset of DMA clock */
176 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
177 }
178 #endif /* DMA2 */
179 else
180 {
181 status = ERROR;
182 }
183 }
184 else
185 {
186 tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
187
188 /* Reset DMAx_Channely control register */
189 WRITE_REG(tmp->CCR, 0U);
190
191 /* Reset DMAx_Channely remaining bytes register */
192 WRITE_REG(tmp->CNDTR, 0U);
193
194 /* Reset DMAx_Channely peripheral address register */
195 WRITE_REG(tmp->CPAR, 0U);
196
197 /* Reset DMAx_Channely memory address register */
198 WRITE_REG(tmp->CMAR, 0U);
199
200 /* Reset Request register field for DMAx Channel */
201 LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM);
202
203 if (Channel == LL_DMA_CHANNEL_1)
204 {
205 /* Reset interrupt pending bits for DMAx Channel1 */
206 LL_DMA_ClearFlag_GI1(DMAx);
207 }
208 else if (Channel == LL_DMA_CHANNEL_2)
209 {
210 /* Reset interrupt pending bits for DMAx Channel2 */
211 LL_DMA_ClearFlag_GI2(DMAx);
212 }
213 else if (Channel == LL_DMA_CHANNEL_3)
214 {
215 /* Reset interrupt pending bits for DMAx Channel3 */
216 LL_DMA_ClearFlag_GI3(DMAx);
217 }
218 else if (Channel == LL_DMA_CHANNEL_4)
219 {
220 /* Reset interrupt pending bits for DMAx Channel4 */
221 LL_DMA_ClearFlag_GI4(DMAx);
222 }
223 else if (Channel == LL_DMA_CHANNEL_5)
224 {
225 /* Reset interrupt pending bits for DMAx Channel5 */
226 LL_DMA_ClearFlag_GI5(DMAx);
227 }
228 else if (Channel == LL_DMA_CHANNEL_6)
229 {
230 /* Reset interrupt pending bits for DMAx Channel6 */
231 LL_DMA_ClearFlag_GI6(DMAx);
232 }
233 else if (Channel == LL_DMA_CHANNEL_7)
234 {
235 /* Reset interrupt pending bits for DMAx Channel7 */
236 LL_DMA_ClearFlag_GI7(DMAx);
237 }
238 else
239 {
240 status = ERROR;
241 }
242 }
243
244 return status;
245 }
246
247 /**
248 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
249 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
250 * @arg @ref __LL_DMA_GET_INSTANCE
251 * @arg @ref __LL_DMA_GET_CHANNEL
252 * @param DMAx DMAx Instance
253 * @param Channel This parameter can be one of the following values:
254 * @arg @ref LL_DMA_CHANNEL_1
255 * @arg @ref LL_DMA_CHANNEL_2
256 * @arg @ref LL_DMA_CHANNEL_3
257 * @arg @ref LL_DMA_CHANNEL_4
258 * @arg @ref LL_DMA_CHANNEL_5
259 * @arg @ref LL_DMA_CHANNEL_6
260 * @arg @ref LL_DMA_CHANNEL_7
261 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
262 * @retval ErrorStatus
263 * - SUCCESS: DMA registers are initialized
264 * - ERROR: Not applicable
265 */
LL_DMA_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitTypeDef * DMA_InitStruct)266 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
267 {
268 /* Check the DMA Instance DMAx and Channel parameters*/
269 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
270
271 /* Check the DMA parameters from DMA_InitStruct */
272 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
273 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
274 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
275 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
276 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
277 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
278 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
279 assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
280 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
281
282 /*---------------------------- DMAx CCR Configuration ------------------------
283 * Configure DMAx_Channely: data transfer direction, data transfer mode,
284 * peripheral and memory increment mode,
285 * data size alignment and priority level with parameters :
286 * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
287 * - Mode: DMA_CCR_CIRC bit
288 * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
289 * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
290 * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
291 * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
292 * - Priority: DMA_CCR_PL[1:0] bits
293 */
294 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
295 DMA_InitStruct->Mode | \
296 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
297 DMA_InitStruct->MemoryOrM2MDstIncMode | \
298 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
299 DMA_InitStruct->MemoryOrM2MDstDataSize | \
300 DMA_InitStruct->Priority);
301
302 /*-------------------------- DMAx CMAR Configuration -------------------------
303 * Configure the memory or destination base address with parameter :
304 * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
305 */
306 LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
307
308 /*-------------------------- DMAx CPAR Configuration -------------------------
309 * Configure the peripheral or source base address with parameter :
310 * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
311 */
312 LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
313
314 /*--------------------------- DMAx CNDTR Configuration -----------------------
315 * Configure the peripheral base address with parameter :
316 * - NbData: DMA_CNDTR_NDT[15:0] bits
317 */
318 LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
319
320 /*--------------------------- DMAMUXx CCR Configuration ----------------------
321 * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
322 * - PeriphRequest: DMA_CxCR[7:0] bits
323 */
324 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
325
326 return SUCCESS;
327 }
328
329 /**
330 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
331 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
332 * @retval None
333 */
LL_DMA_StructInit(LL_DMA_InitTypeDef * DMA_InitStruct)334 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
335 {
336 /* Set DMA_InitStruct fields to default values */
337 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
338 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
339 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
340 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
341 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
342 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
343 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
344 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
345 DMA_InitStruct->NbData = 0x00000000U;
346 DMA_InitStruct->PeriphRequest = LL_DMAMUX_REQ_MEM2MEM;
347 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
348 }
349
350 /**
351 * @}
352 */
353
354 /**
355 * @}
356 */
357
358 /**
359 * @}
360 */
361
362 #endif /* DMA1 || DMA2 */
363
364 /**
365 * @}
366 */
367
368 #endif /* USE_FULL_LL_DRIVER */
369
