1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32wbxx_ll_adc.h"
22 #include "stm32wbxx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32WBxx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* APB prescaler 16, ADC prescaler 4. */
62 /* - ADC clock from asynchronous clock (PLLSAI) with prescaler 1, */
63 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
64 /* CPU clock frequency max 72MHz, PLLSAI freq min 26MHz: ratio 4. */
65 /* Unit: CPU cycles. */
66 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
67 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
68 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
69 #if defined(ADC_SUPPORT_2_5_MSPS)
70 /* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles */
71 /* after the channel configuration has been changed. */
72 /* Driver timeout is approximated to 6 CPU cycles. */
73 #define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
74 #endif /* ADC_SUPPORT_2_5_MSPS */
75
76 /**
77 * @}
78 */
79
80 /* Private macros ------------------------------------------------------------*/
81
82 /** @addtogroup ADC_LL_Private_Macros
83 * @{
84 */
85
86 /* Check of parameters for configuration of ADC hierarchical scope: */
87 /* common to several ADC instances. */
88 #if defined(ADC_SUPPORT_2_5_MSPS)
89 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
90 ( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
98 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
99 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
100 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
101 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
102 )
103 #else
104 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
105 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
106 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
107 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
108 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
109 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
110 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
111 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
112 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
113 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
114 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
115 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
116 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
117 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
118 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
119 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
120 )
121 #endif /* ADC_SUPPORT_2_5_MSPS */
122
123 /* Check of parameters for configuration of ADC hierarchical scope: */
124 /* ADC instance. */
125 #if defined(ADC_SUPPORT_2_5_MSPS)
126 #define IS_LL_ADC_CLOCK(__CLOCK__) \
127 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
128 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
129 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
130 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
131 )
132
133 #endif /* ADC_SUPPORT_2_5_MSPS */
134 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
135 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
136 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
137 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
138 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
139 )
140
141 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
142 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
143 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
144 )
145
146 #if defined(ADC_SUPPORT_2_5_MSPS)
147 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
148 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
149 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
150 || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
151 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
152 )
153 #else
154 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
155 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
156 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
157 )
158 #endif /* ADC_SUPPORT_2_5_MSPS */
159 /* Check of parameters for configuration of ADC hierarchical scope: */
160 /* ADC group regular */
161 #if defined(ADC_SUPPORT_2_5_MSPS)
162 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
163 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
164 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
165 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
166 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
167 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
168 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
169 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
170 )
171 #else
172 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
173 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
174 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
175 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
176 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
177 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
178 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
179 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
180 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
181 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
182 )
183 #endif /* ADC_SUPPORT_2_5_MSPS */
184
185 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
186 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
187 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
188 )
189
190 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
191 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
192 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
193 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
194 )
195
196 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
197 ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
198 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
199 )
200
201 #if defined(ADC_SUPPORT_2_5_MSPS)
202 #define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
203 ( ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
204 || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
205 )
206 #endif /* ADC_SUPPORT_2_5_MSPS */
207
208 #if defined(ADC_SUPPORT_2_5_MSPS)
209 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
210 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
211 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
212 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
213 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
214 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
215 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
216 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
217 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
218 )
219 #else
220 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
221 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
222 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
223 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
224 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
225 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
226 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
227 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
228 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
229 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
230 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
231 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
232 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
233 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
234 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
235 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
236 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
237 )
238 #endif /* ADC_SUPPORT_2_5_MSPS */
239 #if defined(ADC_SUPPORT_2_5_MSPS)
240 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
241 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
242 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
243 )
244 #else
245 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
246 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
247 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
248 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
249 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
250 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
251 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
252 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
253 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
254 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
255 )
256 #endif /* ADC_SUPPORT_2_5_MSPS */
257 /* Check of parameters for configuration of ADC hierarchical scope: */
258 /* ADC group injected */
259 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
260 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
261 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
262 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
263 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
264 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
265 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
266 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
267 )
268
269 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
270 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
271 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
272 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
273 )
274
275 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
276 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
277 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
278 )
279
280 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
281 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
282 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
283 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
284 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
285 )
286
287 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
288 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
289 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
290 )
291
292 /**
293 * @}
294 */
295
296
297 /* Private function prototypes -----------------------------------------------*/
298
299 /* Exported functions --------------------------------------------------------*/
300 /** @addtogroup ADC_LL_Exported_Functions
301 * @{
302 */
303
304 /** @addtogroup ADC_LL_EF_Init
305 * @{
306 */
307
308 /**
309 * @brief De-initialize registers of all ADC instances belonging to
310 * the same ADC common instance to their default reset values.
311 * @note This function is performing a hard reset, using high level
312 * clock source RCC ADC reset.
313 * @param ADCxy_COMMON ADC common instance
314 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
315 * @retval An ErrorStatus enumeration value:
316 * - SUCCESS: ADC common registers are de-initialized
317 * - ERROR: not applicable
318 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)319 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
320 {
321 /* Check the parameters */
322 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
323
324 /* Prevent unused argument compilation warning */
325 (void)(ADCxy_COMMON);
326
327 #if defined(ADC_SUPPORT_2_5_MSPS)
328 /* Force reset of ADC clock (core clock) */
329 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
330
331 /* Release reset of ADC clock (core clock) */
332 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
333 #else
334 /* Force reset of ADC clock (core clock) */
335 LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
336
337 /* Release reset of ADC clock (core clock) */
338 LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC);
339 #endif /* ADC_SUPPORT_2_5_MSPS */
340
341 return SUCCESS;
342 }
343
344 /**
345 * @brief Initialize some features of ADC common parameters
346 * (all ADC instances belonging to the same ADC common instance)
347 * and multimode (for devices with several ADC instances available).
348 * @note The setting of ADC common parameters is conditioned to
349 * ADC instances state:
350 * All ADC instances belonging to the same ADC common instance
351 * must be disabled.
352 * @param ADCxy_COMMON ADC common instance
353 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
354 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
355 * @retval An ErrorStatus enumeration value:
356 * - SUCCESS: ADC common registers are initialized
357 * - ERROR: ADC common registers are not initialized
358 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,const LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)359 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
360 {
361 ErrorStatus status = SUCCESS;
362
363 /* Check the parameters */
364 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
365 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
366
367 /* Note: Hardware constraint (refer to description of functions */
368 /* "LL_ADC_SetCommonXXX()": */
369 /* On this STM32 series, setting of these features is conditioned to */
370 /* ADC state: */
371 /* All ADC instances of the ADC common group must be disabled. */
372 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
373 {
374 /* Configuration of ADC hierarchical scope: */
375 /* - common to several ADC */
376 /* (all ADC instances belonging to the same ADC common instance) */
377 /* - Set ADC clock (conversion clock) */
378 #if defined(ADC_MULTIMODE_SUPPORT)
379 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
380 {
381 MODIFY_REG(ADCxy_COMMON->CCR,
382 ADC_CCR_CKMODE
383 | ADC_CCR_PRESC
384 | ADC_CCR_DUAL
385 | ADC_CCR_MDMA
386 | ADC_CCR_DELAY
387 ,
388 ADC_CommonInitStruct->CommonClock
389 | ADC_CommonInitStruct->Multimode
390 | ADC_CommonInitStruct->MultiDMATransfer
391 | ADC_CommonInitStruct->MultiTwoSamplingDelay
392 );
393 }
394 else
395 {
396 MODIFY_REG(ADCxy_COMMON->CCR,
397 ADC_CCR_CKMODE
398 | ADC_CCR_PRESC
399 | ADC_CCR_DUAL
400 | ADC_CCR_MDMA
401 | ADC_CCR_DELAY
402 ,
403 ADC_CommonInitStruct->CommonClock
404 | LL_ADC_MULTI_INDEPENDENT
405 );
406 }
407 #else
408 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
409 #endif
410 }
411 else
412 {
413 /* Initialization error: One or several ADC instances belonging to */
414 /* the same ADC common instance are not disabled. */
415 status = ERROR;
416 }
417
418 return status;
419 }
420
421 /**
422 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
423 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
424 * whose fields will be set to default values.
425 * @retval None
426 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)427 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
428 {
429 /* Set ADC_CommonInitStruct fields to default values */
430 /* Set fields of ADC common */
431 /* (all ADC instances belonging to the same ADC common instance) */
432 #if defined(ADC_SUPPORT_2_5_MSPS)
433 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
434 #else
435 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
436 #endif /* ADC_SUPPORT_2_5_MSPS */
437
438 }
439
440 /**
441 * @brief De-initialize registers of the selected ADC instance
442 * to their default reset values.
443 * @note To reset all ADC instances quickly (perform a hard reset),
444 * use function @ref LL_ADC_CommonDeInit().
445 * @note If this functions returns error status, it means that ADC instance
446 * is in an unknown state.
447 * In this case, perform a hard reset using high level
448 * clock source RCC ADC reset.
449 * Refer to function @ref LL_ADC_CommonDeInit().
450 * @param ADCx ADC instance
451 * @retval An ErrorStatus enumeration value:
452 * - SUCCESS: ADC registers are de-initialized
453 * - ERROR: ADC registers are not de-initialized
454 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)455 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
456 {
457 ErrorStatus status = SUCCESS;
458
459 __IO uint32_t timeout_cpu_cycles = 0UL;
460
461 /* Check the parameters */
462 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
463
464 /* Disable ADC instance if not already disabled. */
465 if (LL_ADC_IsEnabled(ADCx) == 1UL)
466 {
467 /* Set ADC group regular trigger source to SW start to ensure to not */
468 /* have an external trigger event occurring during the conversion stop */
469 /* ADC disable process. */
470 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
471
472 /* Stop potential ADC conversion on going on ADC group regular. */
473 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
474 {
475 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
476 {
477 LL_ADC_REG_StopConversion(ADCx);
478 }
479 }
480
481 #if !defined(ADC_SUPPORT_2_5_MSPS)
482 /* Set ADC group injected trigger source to SW start to ensure to not */
483 /* have an external trigger event occurring during the conversion stop */
484 /* ADC disable process. */
485 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
486
487 /* Stop potential ADC conversion on going on ADC group injected. */
488 if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
489 {
490 if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
491 {
492 LL_ADC_INJ_StopConversion(ADCx);
493 }
494 }
495
496 /* Wait for ADC conversions are effectively stopped */
497 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
498 while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
499 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
500 {
501 timeout_cpu_cycles--;
502 if (timeout_cpu_cycles == 0UL)
503 {
504 /* Time-out error */
505 status = ERROR;
506 break;
507 }
508 }
509 #else
510 /* Wait for ADC conversions are effectively stopped */
511 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
512 while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
513 {
514 timeout_cpu_cycles--;
515 if(timeout_cpu_cycles == 0UL)
516 {
517 /* Time-out error */
518 status = ERROR;
519 break;
520 }
521 }
522 #endif /* !ADC_SUPPORT_2_5_MSPS */
523
524 #if !defined(ADC_SUPPORT_2_5_MSPS)
525 /* Flush group injected contexts queue (register JSQR): */
526 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
527 /* contexts queue is maintained with the last active context). */
528 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
529
530 #endif /* !ADC_SUPPORT_2_5_MSPS */
531 /* Disable the ADC instance */
532 LL_ADC_Disable(ADCx);
533
534 /* Wait for ADC instance is effectively disabled */
535 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
536 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
537 {
538 timeout_cpu_cycles--;
539 if (timeout_cpu_cycles == 0UL)
540 {
541 /* Time-out error */
542 status = ERROR;
543 break;
544 }
545 }
546 }
547
548 /* Check whether ADC state is compliant with expected state */
549 #if defined(ADC_SUPPORT_2_5_MSPS)
550 if (READ_BIT(ADCx->CR,
551 (ADC_CR_ADSTP | ADC_CR_ADSTART
552 | ADC_CR_ADDIS | ADC_CR_ADEN )
553 )
554 == 0UL)
555 #else
556 if (READ_BIT(ADCx->CR,
557 (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
558 | ADC_CR_ADDIS | ADC_CR_ADEN)
559 )
560 == 0UL)
561 #endif /* ADC_SUPPORT_2_5_MSPS */
562 {
563 /* ========== Reset ADC registers ========== */
564 /* Reset register IER */
565 CLEAR_BIT(ADCx->IER,
566 (LL_ADC_IT_ADRDY
567 | LL_ADC_IT_EOC
568 | LL_ADC_IT_EOS
569 | LL_ADC_IT_OVR
570 | LL_ADC_IT_EOSMP
571 #if !defined(ADC_SUPPORT_2_5_MSPS)
572 | LL_ADC_IT_JEOC
573 | LL_ADC_IT_JEOS
574 | LL_ADC_IT_JQOVF
575 #endif /* !ADC_SUPPORT_2_5_MSPS */
576 | LL_ADC_IT_AWD1
577 | LL_ADC_IT_AWD2
578 | LL_ADC_IT_AWD3
579 #if defined(ADC_SUPPORT_2_5_MSPS)
580 | LL_ADC_IT_CCRDY
581 #endif /* ADC_SUPPORT_2_5_MSPS */
582 )
583 );
584
585 /* Reset register ISR */
586 SET_BIT(ADCx->ISR,
587 (LL_ADC_FLAG_ADRDY
588 | LL_ADC_FLAG_EOC
589 | LL_ADC_FLAG_EOS
590 | LL_ADC_FLAG_OVR
591 | LL_ADC_FLAG_EOSMP
592 #if !defined(ADC_SUPPORT_2_5_MSPS)
593 | LL_ADC_FLAG_JEOC
594 | LL_ADC_FLAG_JEOS
595 | LL_ADC_FLAG_JQOVF
596 #endif /* !ADC_SUPPORT_2_5_MSPS */
597 | LL_ADC_FLAG_AWD1
598 | LL_ADC_FLAG_AWD2
599 | LL_ADC_FLAG_AWD3
600 #if defined(ADC_SUPPORT_2_5_MSPS)
601 | LL_ADC_FLAG_CCRDY
602 #endif /* ADC_SUPPORT_2_5_MSPS */
603 )
604 );
605
606 #if defined(ADC_SUPPORT_2_5_MSPS)
607 /* Reset register CR */
608 /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
609 /* "read-set": no direct reset applicable. */
610 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
611 #else
612 /* Reset register CR */
613 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
614 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
615 /* access mode "read-set": no direct reset applicable. */
616 /* - Reset Calibration mode to default setting (single ended). */
617 /* - Disable ADC internal voltage regulator. */
618 /* - Enable ADC deep power down. */
619 /* Note: ADC internal voltage regulator disable and ADC deep power */
620 /* down enable are conditioned to ADC state disabled: */
621 /* already done above. */
622 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
623 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
624 #endif /* ADC_SUPPORT_2_5_MSPS */
625
626 #if defined(ADC_SUPPORT_2_5_MSPS)
627 /* Reset register CFGR1 */
628 CLEAR_BIT(ADCx->CFGR1,
629 ( ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
630 | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
631 | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
632 | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN )
633 );
634
635 /* Reset register SMPR */
636 CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
637
638 /* Reset register TR */
639 MODIFY_REG(ADCx->TR, ADC_TR_HT | ADC_TR_LT, ADC_TR_HT);
640
641 /* Reset register CHSELR */
642 CLEAR_BIT(ADCx->CHSELR,
643 ( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
644 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
645 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
646 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
647 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
648 );
649
650 /* Wait for ADC channel configuration ready */
651 timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
652 while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
653 {
654 timeout_cpu_cycles--;
655 if(timeout_cpu_cycles == 0UL)
656 {
657 /* Time-out error */
658 status = ERROR;
659 break;
660 }
661 }
662
663 /* Clear flag ADC channel configuration ready */
664 LL_ADC_ClearFlag_CCRDY(ADCx);
665
666 /* Reset register DR */
667 /* bits in access mode read only, no direct reset applicable */
668
669 /* Reset register CALFACT */
670 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
671
672 /* Reset register CFGR2 */
673 /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
674 /* already done above. */
675 /* Note: Register reset last due to selection of asynchronous clock, */
676 /* ADC clock then depends of configuration clock source at system */
677 /* level. */
678 CLEAR_BIT(ADCx->CFGR2,
679 ( ADC_CFGR2_CKMODE
680 | ADC_CFGR2_LFTRIG )
681 );
682
683 #else
684 /* Reset register CFGR */
685 MODIFY_REG(ADCx->CFGR,
686 (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
687 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
688 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
689 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
690 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
691 | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN),
692 ADC_CFGR_JQDIS
693 );
694
695 /* Reset register CFGR2 */
696 CLEAR_BIT(ADCx->CFGR2,
697 (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
698 | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
699 );
700
701
702 /* Reset register SMPR1 */
703 CLEAR_BIT(ADCx->SMPR1,
704 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
705 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
706 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
707 );
708
709 /* Reset register SMPR2 */
710 CLEAR_BIT(ADCx->SMPR2,
711 (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
712 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
713 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
714 );
715
716 /* Reset register TR1 */
717 MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
718
719 /* Reset register TR2 */
720 MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
721
722 /* Reset register TR3 */
723 MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
724
725 /* Reset register SQR1 */
726 CLEAR_BIT(ADCx->SQR1,
727 (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
728 | ADC_SQR1_SQ1 | ADC_SQR1_L)
729 );
730
731 /* Reset register SQR2 */
732 CLEAR_BIT(ADCx->SQR2,
733 (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
734 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
735 );
736
737 /* Reset register SQR3 */
738 CLEAR_BIT(ADCx->SQR3,
739 (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
740 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
741 );
742
743 /* Reset register SQR4 */
744 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
745
746 /* Reset register JSQR */
747 CLEAR_BIT(ADCx->JSQR,
748 (ADC_JSQR_JL
749 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
750 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
751 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
752 );
753
754 /* Reset register DR */
755 /* Note: bits in access mode read only, no direct reset applicable */
756
757 /* Reset register OFR1 */
758 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
759 /* Reset register OFR2 */
760 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
761 /* Reset register OFR3 */
762 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
763 /* Reset register OFR4 */
764 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
765
766 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
767 /* Note: bits in access mode read only, no direct reset applicable */
768
769 /* Reset register AWD2CR */
770 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
771
772 /* Reset register AWD3CR */
773 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
774
775 /* Reset register DIFSEL */
776 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
777
778 /* Reset register CALFACT */
779 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
780 #endif /* ADC_SUPPORT_2_5_MSPS */
781 }
782 else
783 {
784 /* ADC instance is in an unknown state */
785 /* Need to performing a hard reset of ADC instance, using high level */
786 /* clock source RCC ADC reset. */
787 /* Caution: On this STM32 series, if several ADC instances are available */
788 /* on the selected device, RCC ADC reset will reset */
789 /* all ADC instances belonging to the common ADC instance. */
790 status = ERROR;
791 }
792
793 return status;
794 }
795
796 /**
797 * @brief Initialize some features of ADC instance.
798 * @note These parameters have an impact on ADC scope: ADC instance.
799 * Affects both group regular and group injected (availability
800 * of ADC group injected depends on STM32 families).
801 * Refer to corresponding unitary functions into
802 * @ref ADC_LL_EF_Configuration_ADC_Instance .
803 * @note The setting of these parameters by function @ref LL_ADC_Init()
804 * is conditioned to ADC state:
805 * ADC instance must be disabled.
806 * This condition is applied to all ADC features, for efficiency
807 * and compatibility over all STM32 families. However, the different
808 * features can be set under different ADC state conditions
809 * (setting possible with ADC enabled without conversion on going,
810 * ADC enabled with conversion on going, ...)
811 * Each feature can be updated afterwards with a unitary function
812 * and potentially with ADC in a different state than disabled,
813 * refer to description of each function for setting
814 * conditioned to ADC state.
815 * @note After using this function, some other features must be configured
816 * using LL unitary functions.
817 * The minimum configuration remaining to be done is:
818 * - Set ADC group regular or group injected sequencer:
819 * map channel on the selected sequencer rank.
820 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
821 * - Set ADC channel sampling time
822 * Refer to function LL_ADC_SetChannelSamplingTime();
823 * @param ADCx ADC instance
824 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
825 * @retval An ErrorStatus enumeration value:
826 * - SUCCESS: ADC registers are initialized
827 * - ERROR: ADC registers are not initialized
828 */
LL_ADC_Init(ADC_TypeDef * ADCx,const LL_ADC_InitTypeDef * ADC_InitStruct)829 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *ADC_InitStruct)
830 {
831 ErrorStatus status = SUCCESS;
832
833 /* Check the parameters */
834 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
835
836 #if defined(ADC_SUPPORT_2_5_MSPS)
837 assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
838 #endif /* ADC_SUPPORT_2_5_MSPS */
839 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
840 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
841 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
842
843 /* Note: Hardware constraint (refer to description of this function): */
844 /* ADC instance must be disabled. */
845 if (LL_ADC_IsEnabled(ADCx) == 0UL)
846 {
847 /* Configuration of ADC hierarchical scope: */
848 /* - ADC instance */
849 /* - Set ADC data resolution */
850 /* - Set ADC conversion data alignment */
851 /* - Set ADC low power mode */
852 #if defined(ADC_SUPPORT_2_5_MSPS)
853 MODIFY_REG(ADCx->CFGR1,
854 ADC_CFGR1_RES
855 | ADC_CFGR1_ALIGN
856 | ADC_CFGR1_WAIT
857 | ADC_CFGR1_AUTOFF
858 ,
859 ADC_InitStruct->Resolution
860 | ADC_InitStruct->DataAlignment
861 | ADC_InitStruct->LowPowerMode
862 );
863
864 MODIFY_REG(ADCx->CFGR2,
865 ADC_CFGR2_CKMODE
866 ,
867 ADC_InitStruct->Clock
868 );
869 #else
870 MODIFY_REG(ADCx->CFGR,
871 ADC_CFGR_RES
872 | ADC_CFGR_ALIGN
873 | ADC_CFGR_AUTDLY
874 ,
875 ADC_InitStruct->Resolution
876 | ADC_InitStruct->DataAlignment
877 | ADC_InitStruct->LowPowerMode
878 );
879 #endif /* ADC_SUPPORT_2_5_MSPS */
880 }
881 else
882 {
883 /* Initialization error: ADC instance is not disabled. */
884 status = ERROR;
885 }
886 return status;
887 }
888
889 /**
890 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
891 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
892 * whose fields will be set to default values.
893 * @retval None
894 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * ADC_InitStruct)895 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
896 {
897 /* Set ADC_InitStruct fields to default values */
898 /* Set fields of ADC instance */
899 #if defined(ADC_SUPPORT_2_5_MSPS)
900 ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
901 #endif /* ADC_SUPPORT_2_5_MSPS */
902 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
903 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
904 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
905
906 }
907
908 /**
909 * @brief Initialize some features of ADC group regular.
910 * @note These parameters have an impact on ADC scope: ADC group regular.
911 * Refer to corresponding unitary functions into
912 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
913 * (functions with prefix "REG").
914 * @note The setting of these parameters by function @ref LL_ADC_Init()
915 * is conditioned to ADC state:
916 * ADC instance must be disabled.
917 * This condition is applied to all ADC features, for efficiency
918 * and compatibility over all STM32 families. However, the different
919 * features can be set under different ADC state conditions
920 * (setting possible with ADC enabled without conversion on going,
921 * ADC enabled with conversion on going, ...)
922 * Each feature can be updated afterwards with a unitary function
923 * and potentially with ADC in a different state than disabled,
924 * refer to description of each function for setting
925 * conditioned to ADC state.
926 * @note On devices STM32WB10xx, STM32WB15xx, STM32WB1Mxx: Before using this function,
927 * ADC group regular sequencer must be configured: refer to function
928 * @ref LL_ADC_REG_SetSequencerConfigurable().
929 * @note After using this function, other features must be configured
930 * using LL unitary functions.
931 * The minimum configuration remaining to be done is:
932 * - Set ADC group regular or group injected sequencer:
933 * map channel on the selected sequencer rank.
934 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
935 * - Set ADC channel sampling time
936 * Refer to function LL_ADC_SetChannelSamplingTime();
937 * @param ADCx ADC instance
938 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
939 * @retval An ErrorStatus enumeration value:
940 * - SUCCESS: ADC registers are initialized
941 * - ERROR: ADC registers are not initialized
942 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,const LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)943 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
944 {
945 ErrorStatus status = SUCCESS;
946
947 /* Check the parameters */
948 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
949 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
950 #if defined(ADC_SUPPORT_2_5_MSPS)
951 if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
952 {
953 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
954 }
955 if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
956 || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
957 )
958 {
959 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
960
961 /* ADC group regular continuous mode and discontinuous mode */
962 /* can not be enabled simultenaeously */
963 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
964 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
965 }
966 #else
967 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
968 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
969 {
970 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
971
972 /* ADC group regular continuous mode and discontinuous mode */
973 /* can not be enabled simultenaeously */
974 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
975 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
976 }
977 #endif /* ADC_SUPPORT_2_5_MSPS */
978 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
979 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
980 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
981
982 /* Note: Hardware constraint (refer to description of this function): */
983 /* ADC instance must be disabled. */
984 if (LL_ADC_IsEnabled(ADCx) == 0UL)
985 {
986 /* Configuration of ADC hierarchical scope: */
987 /* - ADC group regular */
988 /* - Set ADC group regular trigger source */
989 /* - Set ADC group regular sequencer length */
990 /* - Set ADC group regular sequencer discontinuous mode */
991 /* - Set ADC group regular continuous mode */
992 /* - Set ADC group regular conversion data transfer: no transfer or */
993 /* transfer by DMA, and DMA requests mode */
994 /* - Set ADC group regular overrun behavior */
995 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
996 /* setting of trigger source to SW start. */
997 #if defined(ADC_SUPPORT_2_5_MSPS)
998 if( (LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
999 || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1000 )
1001 {
1002 /* Case of sequencer mode fixed
1003 or sequencer length >= 2 ranks with sequencer mode fully configurable:
1004 discontinuous mode configured */
1005 MODIFY_REG(ADCx->CFGR1,
1006 ADC_CFGR1_EXTSEL
1007 | ADC_CFGR1_EXTEN
1008 | ADC_CFGR1_DISCEN
1009 | ADC_CFGR1_CONT
1010 | ADC_CFGR1_DMAEN
1011 | ADC_CFGR1_DMACFG
1012 | ADC_CFGR1_OVRMOD
1013 ,
1014 ADC_REG_InitStruct->TriggerSource
1015 | ADC_REG_InitStruct->SequencerDiscont
1016 | ADC_REG_InitStruct->ContinuousMode
1017 | ADC_REG_InitStruct->DMATransfer
1018 | ADC_REG_InitStruct->Overrun
1019 );
1020 }
1021 else
1022 {
1023 /* Case of sequencer mode fully configurable
1024 and sequencer length 1 rank (sequencer disabled):
1025 discontinuous mode discarded (fixed to disable) */
1026 MODIFY_REG(ADCx->CFGR1,
1027 ADC_CFGR1_EXTSEL
1028 | ADC_CFGR1_EXTEN
1029 | ADC_CFGR1_DISCEN
1030 | ADC_CFGR1_CONT
1031 | ADC_CFGR1_DMAEN
1032 | ADC_CFGR1_DMACFG
1033 | ADC_CFGR1_OVRMOD
1034 ,
1035 ADC_REG_InitStruct->TriggerSource
1036 | LL_ADC_REG_SEQ_DISCONT_DISABLE
1037 | ADC_REG_InitStruct->ContinuousMode
1038 | ADC_REG_InitStruct->DMATransfer
1039 | ADC_REG_InitStruct->Overrun
1040 );
1041 }
1042 #else
1043 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1044 {
1045 MODIFY_REG(ADCx->CFGR,
1046 ADC_CFGR_EXTSEL
1047 | ADC_CFGR_EXTEN
1048 | ADC_CFGR_DISCEN
1049 | ADC_CFGR_DISCNUM
1050 | ADC_CFGR_CONT
1051 | ADC_CFGR_DMAEN
1052 | ADC_CFGR_DMACFG
1053 | ADC_CFGR_OVRMOD
1054 ,
1055 ADC_REG_InitStruct->TriggerSource
1056 | ADC_REG_InitStruct->SequencerDiscont
1057 | ADC_REG_InitStruct->ContinuousMode
1058 | ADC_REG_InitStruct->DMATransfer
1059 | ADC_REG_InitStruct->Overrun
1060 );
1061 }
1062 else
1063 {
1064 MODIFY_REG(ADCx->CFGR,
1065 ADC_CFGR_EXTSEL
1066 | ADC_CFGR_EXTEN
1067 | ADC_CFGR_DISCEN
1068 | ADC_CFGR_DISCNUM
1069 | ADC_CFGR_CONT
1070 | ADC_CFGR_DMAEN
1071 | ADC_CFGR_DMACFG
1072 | ADC_CFGR_OVRMOD
1073 ,
1074 ADC_REG_InitStruct->TriggerSource
1075 | LL_ADC_REG_SEQ_DISCONT_DISABLE
1076 | ADC_REG_InitStruct->ContinuousMode
1077 | ADC_REG_InitStruct->DMATransfer
1078 | ADC_REG_InitStruct->Overrun
1079 );
1080 }
1081 #endif /* ADC_SUPPORT_2_5_MSPS */
1082
1083 /* Set ADC group regular sequencer length and scan direction */
1084 #if defined(ADC_SUPPORT_2_5_MSPS)
1085 if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
1086 {
1087 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
1088 }
1089 #else
1090 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
1091 #endif /* ADC_SUPPORT_2_5_MSPS */
1092 }
1093 else
1094 {
1095 /* Initialization error: ADC instance is not disabled. */
1096 status = ERROR;
1097 }
1098 return status;
1099 }
1100
1101 /**
1102 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
1103 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1104 * whose fields will be set to default values.
1105 * @retval None
1106 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)1107 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
1108 {
1109 /* Set ADC_REG_InitStruct fields to default values */
1110 /* Set fields of ADC group regular */
1111 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
1112 /* setting of trigger source to SW start. */
1113 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
1114 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
1115 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
1116 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
1117 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
1118 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
1119 }
1120
1121 #if defined(ADC_SUPPORT_2_5_MSPS)
1122 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
1123 #else
1124 /**
1125 * @brief Initialize some features of ADC group injected.
1126 * @note These parameters have an impact on ADC scope: ADC group injected.
1127 * Refer to corresponding unitary functions into
1128 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1129 * (functions with prefix "INJ").
1130 * @note The setting of these parameters by function @ref LL_ADC_Init()
1131 * is conditioned to ADC state:
1132 * ADC instance must be disabled.
1133 * This condition is applied to all ADC features, for efficiency
1134 * and compatibility over all STM32 families. However, the different
1135 * features can be set under different ADC state conditions
1136 * (setting possible with ADC enabled without conversion on going,
1137 * ADC enabled with conversion on going, ...)
1138 * Each feature can be updated afterwards with a unitary function
1139 * and potentially with ADC in a different state than disabled,
1140 * refer to description of each function for setting
1141 * conditioned to ADC state.
1142 * @note After using this function, other features must be configured
1143 * using LL unitary functions.
1144 * The minimum configuration remaining to be done is:
1145 * - Set ADC group injected sequencer:
1146 * map channel on the selected sequencer rank.
1147 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
1148 * - Set ADC channel sampling time
1149 * Refer to function LL_ADC_SetChannelSamplingTime();
1150 * @note Caution if feature ADC group injected contexts queue is enabled
1151 * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
1152 * using successively several times this function will appear as
1153 * having no effect.
1154 * To set several features of ADC group injected, use
1155 * function @ref LL_ADC_INJ_ConfigQueueContext().
1156 * @param ADCx ADC instance
1157 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1158 * @retval An ErrorStatus enumeration value:
1159 * - SUCCESS: ADC registers are initialized
1160 * - ERROR: ADC registers are not initialized
1161 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,const LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)1162 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1163 {
1164 ErrorStatus status = SUCCESS;
1165
1166 /* Check the parameters */
1167 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1168 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
1169 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
1170 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
1171 {
1172 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
1173 }
1174 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
1175
1176 /* Note: Hardware constraint (refer to description of this function): */
1177 /* ADC instance must be disabled. */
1178 if (LL_ADC_IsEnabled(ADCx) == 0UL)
1179 {
1180 /* Configuration of ADC hierarchical scope: */
1181 /* - ADC group injected */
1182 /* - Set ADC group injected trigger source */
1183 /* - Set ADC group injected sequencer length */
1184 /* - Set ADC group injected sequencer discontinuous mode */
1185 /* - Set ADC group injected conversion trigger: independent or */
1186 /* from ADC group regular */
1187 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
1188 /* setting of trigger source to SW start. */
1189 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1190 {
1191 MODIFY_REG(ADCx->CFGR,
1192 ADC_CFGR_JDISCEN
1193 | ADC_CFGR_JAUTO
1194 ,
1195 ADC_INJ_InitStruct->SequencerDiscont
1196 | ADC_INJ_InitStruct->TrigAuto
1197 );
1198 }
1199 else
1200 {
1201 MODIFY_REG(ADCx->CFGR,
1202 ADC_CFGR_JDISCEN
1203 | ADC_CFGR_JAUTO
1204 ,
1205 LL_ADC_REG_SEQ_DISCONT_DISABLE
1206 | ADC_INJ_InitStruct->TrigAuto
1207 );
1208 }
1209
1210 MODIFY_REG(ADCx->JSQR,
1211 ADC_JSQR_JEXTSEL
1212 | ADC_JSQR_JEXTEN
1213 | ADC_JSQR_JL
1214 ,
1215 ADC_INJ_InitStruct->TriggerSource
1216 | ADC_INJ_InitStruct->SequencerLength
1217 );
1218 }
1219 else
1220 {
1221 /* Initialization error: ADC instance is not disabled. */
1222 status = ERROR;
1223 }
1224 return status;
1225 }
1226
1227 /**
1228 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1229 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1230 * whose fields will be set to default values.
1231 * @retval None
1232 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)1233 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1234 {
1235 /* Set ADC_INJ_InitStruct fields to default values */
1236 /* Set fields of ADC group injected */
1237 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1238 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1239 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1240 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1241 }
1242
1243 #endif
1244 /**
1245 * @}
1246 */
1247
1248 /**
1249 * @}
1250 */
1251
1252 /**
1253 * @}
1254 */
1255
1256 #endif /* ADC1 */
1257
1258 /**
1259 * @}
1260 */
1261
1262 #endif /* USE_FULL_LL_DRIVER */
1263
