1 /**
2 ******************************************************************************
3 * @file stm32wbxx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization/de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2019 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 */
23
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32wbxx_hal.h"
26
27 /** @addtogroup STM32WBxx_HAL_Driver
28 * @{
29 */
30
31 /** @addtogroup PWR
32 * @{
33 */
34
35 #ifdef HAL_PWR_MODULE_ENABLED
36
37 /* Private typedef -----------------------------------------------------------*/
38 /* Private define ------------------------------------------------------------*/
39 /* Private macro -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /** @addtogroup PWR_Private_Defines
43 * @{
44 */
45
46 /** @defgroup PWR_Register_Reset_Values PWR Register Reset Values
47 * @{
48 */
49 /* Definitions of PWR registers reset value */
50 #define PWR_CR1_RESET_VALUE (0x00000200U)
51 #define PWR_CR2_RESET_VALUE (0x00000000U)
52 #define PWR_CR3_RESET_VALUE (0x00008000U)
53 #define PWR_CR4_RESET_VALUE (0x00000000U)
54 #define PWR_CR5_RESET_VALUE (0x00004204U)
55 #define PWR_PUCRA_RESET_VALUE (0x00000000U)
56 #define PWR_PDCRA_RESET_VALUE (0x00000000U)
57 #define PWR_PUCRB_RESET_VALUE (0x00000000U)
58 #define PWR_PDCRB_RESET_VALUE (0x00000000U)
59 #define PWR_PUCRC_RESET_VALUE (0x00000000U)
60 #define PWR_PDCRC_RESET_VALUE (0x00000000U)
61 #define PWR_PUCRD_RESET_VALUE (0x00000000U)
62 #define PWR_PDCRD_RESET_VALUE (0x00000000U)
63 #define PWR_PUCRE_RESET_VALUE (0x00000000U)
64 #define PWR_PDCRE_RESET_VALUE (0x00000000U)
65 #define PWR_PUCRH_RESET_VALUE (0x00000000U)
66 #define PWR_PDCRH_RESET_VALUE (0x00000000U)
67 #define PWR_C2CR1_RESET_VALUE (0x00000000U)
68 #define PWR_C2CR3_RESET_VALUE (0x00008000U)
69 /**
70 * @}
71 */
72
73 /**
74 * @}
75 */
76
77 /* Private function prototypes -----------------------------------------------*/
78 /* Exported functions --------------------------------------------------------*/
79 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
80 * @{
81 */
82
83 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
84 * @brief Initialization and de-initialization functions
85 *
86 @verbatim
87 ===============================================================================
88 ##### Initialization and de-initialization functions #####
89 ===============================================================================
90 [..]
91
92 @endverbatim
93 * @{
94 */
95
96 /**
97 * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
98 * @retval None
99 */
HAL_PWR_DeInit(void)100 void HAL_PWR_DeInit(void)
101 {
102 /* Apply reset values to all PWR registers */
103 /* Note: Update of each register required since PWR global reset is not */
104 /* available at RCC level on this STM32 series. */
105 LL_PWR_WriteReg(CR1, PWR_CR1_RESET_VALUE);
106 LL_PWR_WriteReg(CR2, PWR_CR2_RESET_VALUE);
107 LL_PWR_WriteReg(CR3, PWR_CR3_RESET_VALUE);
108 LL_PWR_WriteReg(CR4, PWR_CR4_RESET_VALUE);
109 LL_PWR_WriteReg(CR5, PWR_CR5_RESET_VALUE);
110 LL_PWR_WriteReg(PUCRA, PWR_PUCRA_RESET_VALUE);
111 LL_PWR_WriteReg(PDCRA, PWR_PDCRA_RESET_VALUE);
112 LL_PWR_WriteReg(PUCRB, PWR_PUCRB_RESET_VALUE);
113 LL_PWR_WriteReg(PDCRB, PWR_PDCRB_RESET_VALUE);
114 LL_PWR_WriteReg(PUCRC, PWR_PUCRC_RESET_VALUE);
115 LL_PWR_WriteReg(PDCRC, PWR_PDCRC_RESET_VALUE);
116 #if defined(GPIOD)
117 LL_PWR_WriteReg(PUCRD, PWR_PUCRD_RESET_VALUE);
118 LL_PWR_WriteReg(PDCRD, PWR_PDCRD_RESET_VALUE);
119 #endif /* GPIOD */
120 LL_PWR_WriteReg(PUCRE, PWR_PUCRE_RESET_VALUE);
121 LL_PWR_WriteReg(PDCRE, PWR_PDCRE_RESET_VALUE);
122 LL_PWR_WriteReg(PUCRH, PWR_PUCRH_RESET_VALUE);
123 LL_PWR_WriteReg(PDCRH, PWR_PDCRH_RESET_VALUE);
124 LL_PWR_WriteReg(C2CR1, PWR_C2CR1_RESET_VALUE);
125 LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE);
126
127 /* Clear all flags */
128 LL_PWR_WriteReg(SCR,
129 LL_PWR_SCR_CC2HF
130 | LL_PWR_SCR_CBLEAF
131 | LL_PWR_SCR_CCRPEF
132 #if defined(PWR_CR3_E802A)
133 | LL_PWR_SCR_C802AF
134 | LL_PWR_SCR_C802WUF
135 #endif /* PWR_CR3_E802A */
136 | LL_PWR_SCR_CBLEWUF
137 #if defined(PWR_CR5_SMPSEN)
138 | LL_PWR_SCR_CBORHF
139 | LL_PWR_SCR_CSMPSFBF
140 #endif /* PWR_CR5_SMPSEN */
141 | LL_PWR_SCR_CWUF
142 );
143
144 LL_PWR_WriteReg(EXTSCR,
145 LL_PWR_EXTSCR_CCRPF
146 | LL_PWR_EXTSCR_C2CSSF
147 | LL_PWR_EXTSCR_C1CSSF
148 );
149 }
150
151
152 /**
153 * @brief Enable access to the backup domain
154 * (RTC registers, RTC backup data registers).
155 * @note After reset, the backup domain is protected against
156 * possible unwanted write accesses.
157 * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
158 * In order to set or modify the RTC clock, the backup domain access must be
159 * disabled.
160 * @note LSEON bit that switches on and off the LSE crystal belongs as well to the
161 * back-up domain.
162 * @retval None
163 */
HAL_PWR_EnableBkUpAccess(void)164 void HAL_PWR_EnableBkUpAccess(void)
165 {
166 SET_BIT(PWR->CR1, PWR_CR1_DBP);
167 }
168
169 /**
170 * @brief Disable access to the backup domain
171 * (RTC registers, RTC backup data registers).
172 * @retval None
173 */
HAL_PWR_DisableBkUpAccess(void)174 void HAL_PWR_DisableBkUpAccess(void)
175 {
176 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
177 }
178
179 /**
180 * @}
181 */
182
183
184 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
185 * @brief Low Power modes configuration functions
186 *
187 @verbatim
188
189 ===============================================================================
190 ##### Peripheral Control functions #####
191 ===============================================================================
192
193 [..]
194 *** PVD configuration ***
195 =========================
196 [..]
197 (+) The PVD is used to monitor the VDD power supply by comparing it to a
198 threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
199 (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
200 than the PVD threshold. This event is internally connected to the EXTI
201 line16 and can generate an interrupt if enabled. This is done through
202 __HAL_PVD_EXTI_ENABLE_IT() macro.
203 (+) The PVD is stopped in Standby mode.
204
205 *** WakeUp pin configuration ***
206 ================================
207 [..]
208 (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
209 The polarity of these pins can be set to configure event detection on high
210 level (rising edge) or low level (falling edge).
211
212 *** Low Power modes configuration ***
213 =====================================
214 [..]
215 The devices feature 8 low-power modes:
216
217 (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
218
219 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
220 (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
221
222 (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
223 (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
224 (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
225
226 (+) Standby mode with SRAM2a: all clocks are stopped except LSI and LSE, SRAM2a content preserved, main regulator off, low power regulator on.
227 Note: On devices STM32WB15xx, STM32WB10xx, STM32WB1Mxx retention is extended to SRAM1, SRAM2a, SRAM2b.
228 (+) Standby mode without SRAM2a: all clocks are stopped except LSI and LSE, main and low power regulators off.
229
230 (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
231
232
233 *** Low-power run mode ***
234 ==========================
235 [..]
236 (+) Entry: (from main run mode)
237 (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
238 (+) Exit:
239 (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
240 then can the system clock frequency be increased above 2 MHz.
241
242 *** Sleep mode / Low-power sleep mode ***
243 =========================================
244 [..]
245 (+) Entry:
246 The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
247 in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
248 (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
249 (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
250 In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
251 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
252 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
253
254 (+) WFI Exit:
255 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
256 controller (NVIC) or any wake-up event.
257
258 (+) WFE Exit:
259 (++) Any wake-up event such as an EXTI line configured in event mode.
260
261 [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
262 the MCU is in Low-power Run mode.
263
264 *** Stop 0, Stop 1 and Stop 2 modes ***
265 ===============================
266 [..]
267 (+) Entry:
268 The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
269 (++) HAL_PWREx_EnterSTOP0Mode() for mode 0, HAL_PWREx_EnterSTOP1Mode() for mode 1, HAL_PWREx_EnterSTOP2Mode() for mode 2
270 or for porting reasons HAL_PWR_EnterSTOPMode().
271 Note: Low power Stop2 mode is not available on devices STM32WB15xx, STM32WB10xx, STM32WB1Mxx.
272
273 (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
274 (++) PWR_MAINREGULATOR_ON: Regulator in main mode (STOP0 mode)
275 (++) PWR_LOWPOWERREGULATOR_ON: Regulator in low-power mode (STOP1 mode)
276 (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
277 (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
278 (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
279 (+) WFI Exit:
280 (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
281 (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
282 when programmed in wakeup mode.
283 (+) WFE Exit:
284 (++) Any EXTI Line (Internal or External) configured in Event mode.
285
286 [..]
287 When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
288 depending on the LPR bit setting.
289 When exiting Stop 2 mode, the MCU is in Run mode.
290
291 *** Standby mode ***
292 ====================
293 [..] The Standby mode offers two options:
294 (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
295 SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
296 and Standby circuitry.
297 (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
298 SRAM and register contents are lost except for the RTC registers, RTC backup registers
299 and Standby circuitry.
300
301 (++) Entry:
302 (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
303 SRAM1 and register contents are lost except for registers in the Backup domain and
304 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
305 To enable this feature, the user can resort to HAL_PWREx_EnableBKRAMContentRetention() API
306 to set RRS bit.
307 (++) Exit:
308 (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
309 external reset in NRST pin, IWDG reset.
310 [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
311
312
313 *** Shutdown mode ***
314 ======================
315 [..]
316 In Shutdown mode,
317 voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
318 SRAM and registers contents are lost except for backup domain registers.
319 (+) Entry:
320 The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
321 (+) Exit:
322 (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
323 external reset in NRST pin.
324 [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
325
326
327 *** Auto-wakeup (AWU) from low-power mode ***
328 =============================================
329 [..]
330 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
331 Wakeup event, a tamper event or a time-stamp event, without depending on
332 an external interrupt (Auto-wakeup mode).
333
334 (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
335
336
337 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
338 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
339
340 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
341 is necessary to configure the RTC to detect the tamper or time stamp event using the
342 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
343
344 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
345 configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
346
347 @endverbatim
348 * @{
349 */
350
351 /**
352 * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
353 * @param sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the PVD
354 * configuration information.
355 * @note Refer to the electrical characteristics of your device datasheet for
356 * more details about the voltage thresholds corresponding to each
357 * detection level.
358 * @note If "sConfigPVD->Mode" is set to PVD_MODE_IT,
359 * wake-up target is set by default to wake-up target CPU1.
360 * To select wake-up target to CPU2, additional configuration must be
361 * performed using macro "__HAL_PWR_PVD_EXTIC2_ENABLE_IT()"
362 * (and optionally, to select CPU2 only (not both CPU1 and CPU2):
363 * "__HAL_PWR_PVD_EXTI_DISABLE_IT()").
364 * @retval None
365 */
HAL_PWR_ConfigPVD(PWR_PVDTypeDef * sConfigPVD)366 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
367 {
368 /* Check the parameters */
369 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
370 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
371
372 /* Set PLS bits according to PVDLevel value */
373 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
374
375 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
376
377 /* Note: On STM32WB series, power PVD event is not available on AIEC lines */
378 /* (only interruption is available through AIEC line 16). */
379 __HAL_PWR_PVD_EXTI_DISABLE_IT(); /*CPU1*/
380 __HAL_PWR_PVD_EXTIC2_DISABLE_IT(); /*CPU2*/
381
382 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
383 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
384
385 /* Configure interrupt mode */
386 if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
387 {
388 /* Set CPU1 as wakeup target */
389 __HAL_PWR_PVD_EXTI_ENABLE_IT();
390 }
391
392 /* Configure the edge */
393 if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
394 {
395 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
396 }
397
398 if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
399 {
400 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
401 }
402
403 return HAL_OK;
404 }
405
406 /**
407 * @brief Enables the Power Voltage Detector(PVD).
408 * @retval None
409 */
HAL_PWR_EnablePVD(void)410 void HAL_PWR_EnablePVD(void)
411 {
412 /* Enable the power voltage detector */
413 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
414 }
415
416 /**
417 * @brief Disables the Power Voltage Detector(PVD).
418 * @retval None
419 */
HAL_PWR_DisablePVD(void)420 void HAL_PWR_DisablePVD(void)
421 {
422 /* Disable the power voltage detector */
423 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
424 }
425
426
427 /**
428 * @brief Enable the WakeUp PINx functionality.
429 * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.
430 * This parameter can be one of the following legacy values which set the default polarity
431 * i.e. detection on high level (rising edge):
432 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
433 *
434 * or one of the following value where the user can explicitly specify the enabled pin and
435 * the chosen polarity:
436 * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
437 * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
438 * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
439 * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
440 * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
441 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
442 * @retval None
443 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)444 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
445 {
446 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
447
448 /* Specifies the Wake-Up pin polarity for the event detection
449 (rising or falling edge) */
450 MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
451
452 /* Enable wake-up pin */
453 SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
454 }
455
456 /**
457 * @brief Disable the WakeUp PINx functionality.
458 * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
459 * This parameter can be one of the following values:
460 * @arg PWR_WAKEUP_PIN1: An event on PA0 PIN wakes-up the system from Standby mode.
461 * @arg PWR_WAKEUP_PIN2: An event on PC13 PIN wakes-up the system from Standby mode.
462 * @arg PWR_WAKEUP_PIN3: An event on PC12 PIN wakes-up the system from Standby mode.
463 * @arg PWR_WAKEUP_PIN4: An event on PA2 PIN wakes-up the system from Standby mode.
464 * @arg PWR_WAKEUP_PIN5: An event on PC5 PIN wakes-up the system from Standby mode.
465 * @retval None
466 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)467 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
468 {
469 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
470
471 CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
472 }
473
474 /**
475 * @brief Enter Sleep or Low-power Sleep mode.
476 * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
477 * @param Regulator Specifies the regulator state in Sleep/Low-power Sleep mode.
478 * This parameter can be one of the following values:
479 * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
480 * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
481 * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
482 * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
483 * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
484 * Flash in power-down mode in setting the SLEEP_PD bit in FLASH_ACR register.
485 * Additionally, the clock frequency must be reduced below 2 MHz.
486 * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
487 * be done before calling HAL_PWR_EnterSLEEPMode() API.
488 * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
489 * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
490 * @param SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE instruction.
491 * This parameter can be one of the following values:
492 * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
493 * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
494 * @note When WFI entry is used, tick interrupt have to be disabled if not desired as
495 * the interrupt wake up source.
496 * @retval None
497 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)498 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
499 {
500 /* Check the parameters */
501 assert_param(IS_PWR_REGULATOR(Regulator));
502 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
503
504 /* Set Regulator parameter */
505 if (Regulator == PWR_MAINREGULATOR_ON)
506 {
507 /* If in low-power run mode at this point, exit it */
508 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
509 {
510 if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
511 {
512 return ;
513 }
514 }
515 /* Regulator now in main mode. */
516 }
517 else
518 {
519 /* If in run mode, first move to low-power run mode.
520 The system clock frequency must be below 2 MHz at this point. */
521 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
522 {
523 HAL_PWREx_EnableLowPowerRunMode();
524 }
525 }
526
527 /* Clear SLEEPDEEP bit of Cortex System Control Register */
528 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
529
530 /* Select SLEEP mode entry -------------------------------------------------*/
531 if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
532 {
533 /* Request Wait For Interrupt */
534 __WFI();
535 }
536 else
537 {
538 /* Request Wait For Event */
539 __SEV();
540 __WFE();
541 __WFE();
542 }
543 }
544
545
546 /**
547 * @brief Enter Stop mode
548 * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
549 * on devices where only "Stop mode" is mentioned with main or low power regulator ON.
550 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
551 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
552 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
553 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
554 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
555 * only to the peripheral requesting it.
556 * SRAM1, SRAM2 and register contents are preserved.
557 * The BOR is available.
558 * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
559 * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
560 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
561 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
562 * @note When the voltage regulator operates in low power mode (Stop 1), an additional
563 * startup delay is incurred when waking up.
564 * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
565 * is higher although the startup time is reduced.
566 * @note Case of Stop0 mode with SMPS: Before entering Stop 0 mode with SMPS Step Down converter enabled,
567 * the HSI16 must be kept on by enabling HSI kernel clock (set HSIKERON register bit).
568 * @note According to system power policy, system entering in Stop mode
569 * is depending on other CPU power mode.
570 * @param Regulator Specifies the regulator state in Stop mode.
571 * This parameter can be one of the following values:
572 * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
573 * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
574 * @param STOPEntry Specifies Stop 0, Stop 1 or Stop 2 mode is entered with WFI or WFE instruction.
575 * This parameter can be one of the following values:
576 * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
577 * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
578 * @retval None
579 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)580 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
581 {
582 /* Check the parameters */
583 assert_param(IS_PWR_REGULATOR(Regulator));
584
585 if (Regulator == PWR_LOWPOWERREGULATOR_ON)
586 {
587 HAL_PWREx_EnterSTOP1Mode(STOPEntry);
588 }
589 else
590 {
591 HAL_PWREx_EnterSTOP0Mode(STOPEntry);
592 }
593 }
594
595
596 /**
597 * @brief Enter Standby mode.
598 * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
599 * off. The voltage regulator is disabled, except when BKRAM content is preserved
600 * in which case the regulator is in low-power mode.
601 * SRAM and register contents are lost except for registers in the Backup domain and
602 * Standby circuitry. BKRAM content can be preserved if the bit RRS is set in PWR_CR3 register.
603 * To enable this feature, the user can resort to HAL_PWREx_EnableBKRAMContentRetention() API
604 * to set RRS bit.
605 * The BOR is available.
606 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
607 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
608 * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
609 * same.
610 * These states are effective in Standby mode only if APC bit is set through
611 * HAL_PWREx_EnablePullUpPullDownConfig() API.
612 * @note According to system power policy, system entering in Standby mode
613 * is depending on other CPU power mode.
614 * @retval None
615 */
HAL_PWR_EnterSTANDBYMode(void)616 void HAL_PWR_EnterSTANDBYMode(void)
617 {
618 /* Set Stand-by mode */
619 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY);
620
621 /* Set SLEEPDEEP bit of Cortex System Control Register */
622 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
623
624 /* This option is used to ensure that store operations are completed */
625 #if defined (__CC_ARM)
626 __force_stores();
627 #endif /* __CC_ARM */
628
629 /* Request Wait For Interrupt */
630 __WFI();
631
632 /* Following code is executed after wake up if system did not go to STANDBY
633 mode according to system power policy */
634
635 /* Reset SLEEPDEEP bit of Cortex System Control Register */
636 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
637 }
638
639 /**
640 * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
641 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
642 * re-enters SLEEP mode when an interruption handling is over.
643 * Setting this bit is useful when the processor is expected to run only on
644 * interruptions handling.
645 * @retval None
646 */
HAL_PWR_EnableSleepOnExit(void)647 void HAL_PWR_EnableSleepOnExit(void)
648 {
649 /* Set SLEEPONEXIT bit of Cortex System Control Register */
650 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
651 }
652
653 /**
654 * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
655 * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
656 * re-enters SLEEP mode when an interruption handling is over.
657 * @retval None
658 */
HAL_PWR_DisableSleepOnExit(void)659 void HAL_PWR_DisableSleepOnExit(void)
660 {
661 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
662 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
663 }
664
665
666 /**
667 * @brief Enable CORTEX M4 SEVONPEND bit.
668 * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
669 * WFE to wake up when an interrupt moves from inactive to pended.
670 * @retval None
671 */
HAL_PWR_EnableSEVOnPend(void)672 void HAL_PWR_EnableSEVOnPend(void)
673 {
674 /* Set SEVONPEND bit of Cortex System Control Register */
675 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
676 }
677
678
679 /**
680 * @brief Disable CORTEX M4 SEVONPEND bit.
681 * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
682 * WFE to wake up when an interrupt moves from inactive to pended.
683 * @retval None
684 */
HAL_PWR_DisableSEVOnPend(void)685 void HAL_PWR_DisableSEVOnPend(void)
686 {
687 /* Clear SEVONPEND bit of Cortex System Control Register */
688 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
689 }
690
691
692 /**
693 * @brief PWR PVD interrupt callback
694 * @retval None
695 */
HAL_PWR_PVDCallback(void)696 __weak void HAL_PWR_PVDCallback(void)
697 {
698 /* NOTE : This function should not be modified; when the callback is needed,
699 the HAL_PWR_PVDCallback can be implemented in the user file
700 */
701 }
702
703 /**
704 * @}
705 */
706
707 /**
708 * @}
709 */
710
711 #endif /* HAL_PWR_MODULE_ENABLED */
712 /**
713 * @}
714 */
715
716 /**
717 * @}
718 */
719
720
