1 /**
2 ******************************************************************************
3 * @file stm32wbxx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and Configuration functions
9 * + Peripheral Control functions
10 ******************************************************************************
11 * @attention
12 *
13 * Copyright (c) 2019 STMicroelectronics.
14 * All rights reserved.
15 *
16 * This software is licensed under terms that can be found in the LICENSE file
17 * in the root directory of this software component.
18 * If no LICENSE file comes with this software, it is provided AS-IS.
19 *
20 ******************************************************************************
21 @verbatim
22 ==============================================================================
23 ##### How to use this driver #####
24 ==============================================================================
25 [..]
26 *** How to configure Interrupts using CORTEX HAL driver ***
27 ===========================================================
28 [..]
29 This section provides functions allowing to configure the NVIC interrupts (IRQ).
30 The Cortex M0+ exceptions are managed by CMSIS functions.
31 (#) Enable and Configure the priority of the selected IRQ Channels.
32 The priority can be 0..3.
33
34 -@- Lower priority values gives higher priority.
35 -@- Priority Order:
36 (#@) Lowest priority.
37 (#@) Lowest hardware priority (IRQn position).
38
39 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
40
41 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
42
43 -@- Negative value of IRQn_Type are not allowed.
44
45 *** How to configure Systick using CORTEX HAL driver ***
46 ========================================================
47 [..]
48 Setup SysTick Timer for time base.
49
50 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
51 is a CMSIS function that:
52 (++) Configures the SysTick Reload register with value passed as function parameter.
53 (++) Configures the SysTick IRQ priority to the lowest value (0x03).
54 (++) Resets the SysTick Counter register.
55 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
56 (++) Enables the SysTick Interrupt.
57 (++) Starts the SysTick Counter.
58
59 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
60 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
61 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
62 inside the stm32wbxx_hal_cortex.h file.
63
64 (+) You can change the SysTick IRQ priority by calling the
65 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
66 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
67
68 (+) To adjust the SysTick time base, use the following formula:
69
70 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
71 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
72 (++) Reload Value should not exceed 0xFFFFFF
73
74 @endverbatim
75 ******************************************************************************
76 */
77
78 /* Includes ------------------------------------------------------------------*/
79 #include "stm32wbxx_hal.h"
80
81 /** @addtogroup STM32WBxx_HAL_Driver
82 * @{
83 */
84
85 /** @addtogroup CORTEX
86 * @{
87 */
88
89 #ifdef HAL_CORTEX_MODULE_ENABLED
90
91 /* Private types -------------------------------------------------------------*/
92 /* Private variables ---------------------------------------------------------*/
93 /* Private constants ---------------------------------------------------------*/
94 /* Private macros ------------------------------------------------------------*/
95 /* Private functions ---------------------------------------------------------*/
96 /* Exported functions --------------------------------------------------------*/
97
98 /** @addtogroup CORTEX_Exported_Functions
99 * @{
100 */
101
102
103 /** @addtogroup CORTEX_Exported_Functions_Group1
104 * @brief Initialization and Configuration functions
105 *
106 @verbatim
107 ==============================================================================
108 ##### Initialization and Configuration functions #####
109 ==============================================================================
110 [..]
111 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
112 SysTick functionalities
113
114 @endverbatim
115 * @{
116 */
117
118 /**
119 * @brief Set the priority grouping field (pre-emption priority and subpriority)
120 * using the required unlock sequence.
121 * @param PriorityGroup The priority grouping bits length.
122 * This parameter can be one of the following values:
123 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
124 * 4 bits for subpriority
125 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
126 * 3 bits for subpriority
127 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
128 * 2 bits for subpriority
129 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
130 * 1 bit for subpriority
131 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
132 * 0 bit for subpriority
133 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
134 * The pending IRQ priority will be managed only by the subpriority.
135 * @retval None
136 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)137 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
138 {
139 /* Check the parameters */
140 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
141
142 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
143 NVIC_SetPriorityGrouping(PriorityGroup);
144 }
145
146 /**
147 * @brief Set the priority of an interrupt.
148 * @param IRQn External interrupt number.
149 * This parameter can be an enumerator of IRQn_Type enumeration
150 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
151 * @param PreemptPriority The pre-emption priority for the IRQn channel.
152 * This parameter can be a value between 0 and 15
153 * A lower priority value indicates a higher priority
154 * @param SubPriority the subpriority level for the IRQ channel.
155 * This parameter can be a value between 0 and 15
156 * A lower priority value indicates a higher priority.
157 * @retval None
158 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)159 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
160 {
161 uint32_t prioritygroup;
162
163 /* Check the parameters */
164 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
165 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
166
167 prioritygroup = NVIC_GetPriorityGrouping();
168
169 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
170 }
171
172 /**
173 * @brief Enable a device specific interrupt in the NVIC interrupt controller.
174 * @param IRQn External interrupt number.
175 * This parameter can be an enumerator of IRQn_Type enumeration
176 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
177 * @retval None
178 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)179 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
180 {
181 /* Check the parameters */
182 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
183
184 /* Enable interrupt */
185 NVIC_EnableIRQ(IRQn);
186 }
187
188 /**
189 * @brief Disable a device specific interrupt in the NVIC interrupt controller.
190 * @param IRQn External interrupt number.
191 * This parameter can be an enumerator of IRQn_Type enumeration
192 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
193 * @retval None
194 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)195 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
196 {
197 /* Check the parameters */
198 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
199
200 /* Disable interrupt */
201 NVIC_DisableIRQ(IRQn);
202 }
203
204 /**
205 * @brief Initiate a system reset request to reset the MCU.
206 * @retval None
207 */
HAL_NVIC_SystemReset(void)208 void HAL_NVIC_SystemReset(void)
209 {
210 /* System Reset */
211 NVIC_SystemReset();
212 }
213
214 /**
215 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
216 * Counter is in free running mode to generate periodic interrupts.
217 * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
218 * @retval status: - 0 Function succeeded.
219 * - 1 Function failed.
220 */
HAL_SYSTICK_Config(uint32_t TicksNumb)221 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
222 {
223 return SysTick_Config(TicksNumb);
224 }
225 /**
226 * @}
227 */
228
229 /** @addtogroup CORTEX_Exported_Functions_Group2
230 * @brief Cortex control functions
231 *
232 @verbatim
233 ==============================================================================
234 ##### Peripheral Control functions #####
235 ==============================================================================
236 [..]
237 This subsection provides a set of functions allowing to control the CORTEX
238 (NVIC, SYSTICK, MPU) functionalities.
239
240
241 @endverbatim
242 * @{
243 */
244
245
246 /**
247 * @brief Get the priority grouping field from the NVIC Interrupt Controller.
248 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
249 */
HAL_NVIC_GetPriorityGrouping(void)250 uint32_t HAL_NVIC_GetPriorityGrouping(void)
251 {
252 /* Get the PRIGROUP[10:8] field value */
253 return NVIC_GetPriorityGrouping();
254 }
255
256 /**
257 * @brief Get the priority of an interrupt.
258 * @param IRQn External interrupt number.
259 * This parameter can be an enumerator of IRQn_Type enumeration
260 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
261 * @param PriorityGroup the priority grouping bits length.
262 * This parameter can be one of the following values:
263 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
264 * 4 bits for subpriority
265 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
266 * 3 bits for subpriority
267 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
268 * 2 bits for subpriority
269 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
270 * 1 bit for subpriority
271 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
272 * 0 bit for subpriority
273 * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
274 * @param pSubPriority Pointer on the Subpriority value (starting from 0).
275 * @retval None
276 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)277 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
278 {
279 /* Check the parameters */
280 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
281 /* Get priority for Cortex-M system or device specific interrupts */
282 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
283 }
284
285 /**
286 * @brief Set Pending bit of an external interrupt.
287 * @param IRQn External interrupt number
288 * This parameter can be an enumerator of IRQn_Type enumeration
289 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
290 * @retval None
291 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)292 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
293 {
294 /* Check the parameters */
295 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
296
297 /* Set interrupt pending */
298 NVIC_SetPendingIRQ(IRQn);
299 }
300
301 /**
302 * @brief Get Pending Interrupt (read the pending register in the NVIC
303 * and return the pending bit for the specified interrupt).
304 * @param IRQn External interrupt number.
305 * This parameter can be an enumerator of IRQn_Type enumeration
306 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
307 * @retval status: - 0 Interrupt status is not pending.
308 * - 1 Interrupt status is pending.
309 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)310 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
311 {
312 /* Check the parameters */
313 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
314
315 /* Return 1 if pending else 0 */
316 return NVIC_GetPendingIRQ(IRQn);
317 }
318
319 /**
320 * @brief Clear the pending bit of an external interrupt.
321 * @param IRQn External interrupt number.
322 * This parameter can be an enumerator of IRQn_Type enumeration
323 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
324 * @retval None
325 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)326 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
327 {
328 /* Check the parameters */
329 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
330
331 /* Clear pending interrupt */
332 NVIC_ClearPendingIRQ(IRQn);
333 }
334
335 /**
336 * @brief Configure the SysTick clock source.
337 * @param CLKSource specifies the SysTick clock source.
338 * This parameter can be one of the following values:
339 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
340 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
341 * @retval None
342 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)343 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
344 {
345 /* Check the parameters */
346 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
347 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
348 {
349 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
350 }
351 else
352 {
353 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
354 }
355 }
356
357 /**
358 * @brief Handle SYSTICK interrupt request.
359 * @retval None
360 */
HAL_SYSTICK_IRQHandler(void)361 void HAL_SYSTICK_IRQHandler(void)
362 {
363 HAL_SYSTICK_Callback();
364 }
365
366 /**
367 * @brief SYSTICK callback.
368 * @retval None
369 */
HAL_SYSTICK_Callback(void)370 __weak void HAL_SYSTICK_Callback(void)
371 {
372 /* NOTE : This function should not be modified, when the callback is needed,
373 the HAL_SYSTICK_Callback could be implemented in the user file
374 */
375 }
376
377 #if (__MPU_PRESENT == 1U)
378 /**
379 * @brief Disables the MPU
380 * @retval None
381 */
HAL_MPU_Disable(void)382 void HAL_MPU_Disable(void)
383 {
384 /* Make sure outstanding transfers are done */
385 __DMB();
386
387 /* Disable fault exceptions */
388 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
389
390 /* Disable the MPU and clear the control register*/
391 MPU->CTRL = 0U;
392 }
393
394 /**
395 * @brief Enable the MPU.
396 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
397 * NMI, FAULTMASK and privileged access to the default memory
398 * This parameter can be one of the following values:
399 * @arg MPU_HFNMI_PRIVDEF_NONE
400 * @arg MPU_HARDFAULT_NMI
401 * @arg MPU_PRIVILEGED_DEFAULT
402 * @arg MPU_HFNMI_PRIVDEF
403 * @retval None
404 */
HAL_MPU_Enable(uint32_t MPU_Control)405 void HAL_MPU_Enable(uint32_t MPU_Control)
406 {
407 /* Enable the MPU */
408 MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
409
410 /* Enable fault exceptions */
411 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
412
413 /* Ensure MPU setting take effects */
414 __DSB();
415 __ISB();
416 }
417
418 /**
419 * @brief Initialize and configure the Region and the memory to be protected.
420 * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
421 * the initialization and configuration information.
422 * @retval None
423 */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_Init)424 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
425 {
426 /* Check the parameters */
427 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
428 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
429
430 /* Set the Region number */
431 MPU->RNR = MPU_Init->Number;
432
433 if ((MPU_Init->Enable) != 0U)
434 {
435 /* Check the parameters */
436 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
437 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
438 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
439 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
440 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
441 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
442 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
443 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
444
445 MPU->RBAR = MPU_Init->BaseAddress;
446 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
447 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
448 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
449 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
450 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
451 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
452 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
453 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
454 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
455 }
456 else
457 {
458 MPU->RBAR = 0x00U;
459 MPU->RASR = 0x00U;
460 }
461 }
462 #endif /* __MPU_PRESENT */
463
464 /**
465 * @}
466 */
467
468 /**
469 * @}
470 */
471
472 #endif /* HAL_CORTEX_MODULE_ENABLED */
473 /**
474 * @}
475 */
476
477 /**
478 * @}
479 */
480
