1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32WBxx_LL_TIM_H
21 #define __STM32WBxx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbxx.h"
29
30 /** @addtogroup STM32WBxx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM16) || defined (TIM7)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118 /* Defines used for the bit position in the register and perform offsets */
119 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
120
121 /* Generic bit definitions for TIMx_AF1 register */
122 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
123 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
124
125 /* Remap mask definitions */
126 #define TIMx_OR_RMP_SHIFT 16U
127 #define TIMx_OR_RMP_MASK 0x0000FFFFU
128 #define TIM1_OR_RMP_MASK ((TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT)
129 #define TIM2_OR_RMP_MASK ((TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP) << TIMx_OR_RMP_SHIFT)
130 #if defined(TIM16)
131 #define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
132 #endif /* TIM16 */
133 #if defined(TIM17)
134 #define TIM17_OR_RMP_MASK (TIM17_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
135 #endif /* TIM17 */
136
137 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
138 #define DT_DELAY_1 ((uint8_t)0x7F)
139 #define DT_DELAY_2 ((uint8_t)0x3F)
140 #define DT_DELAY_3 ((uint8_t)0x1F)
141 #define DT_DELAY_4 ((uint8_t)0x1F)
142
143 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
144 #define DT_RANGE_1 ((uint8_t)0x00)
145 #define DT_RANGE_2 ((uint8_t)0x80)
146 #define DT_RANGE_3 ((uint8_t)0xC0)
147 #define DT_RANGE_4 ((uint8_t)0xE0)
148
149 /** Legacy definitions for compatibility purpose
150 @cond 0
151 */
152 /**
153 @endcond
154 */
155
156 /**
157 * @}
158 */
159
160 /* Private macros ------------------------------------------------------------*/
161 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
162 * @{
163 */
164 /** @brief Convert channel id into channel index.
165 * @param __CHANNEL__ This parameter can be one of the following values:
166 * @arg @ref LL_TIM_CHANNEL_CH1
167 * @arg @ref LL_TIM_CHANNEL_CH1N
168 * @arg @ref LL_TIM_CHANNEL_CH2
169 * @arg @ref LL_TIM_CHANNEL_CH2N
170 * @arg @ref LL_TIM_CHANNEL_CH3
171 * @arg @ref LL_TIM_CHANNEL_CH3N
172 * @arg @ref LL_TIM_CHANNEL_CH4
173 * @arg @ref LL_TIM_CHANNEL_CH5
174 * @arg @ref LL_TIM_CHANNEL_CH6
175 * @retval none
176 */
177 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
178 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
179 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
180 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
181 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
182 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
183 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
184 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
185 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
186
187 /** @brief Calculate the deadtime sampling period(in ps).
188 * @param __TIMCLK__ timer input clock frequency (in Hz).
189 * @param __CKD__ This parameter can be one of the following values:
190 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
191 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
192 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
193 * @retval none
194 */
195 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
196 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
197 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
198 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
199 /**
200 * @}
201 */
202
203
204 /* Exported types ------------------------------------------------------------*/
205 #if defined(USE_FULL_LL_DRIVER)
206 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
207 * @{
208 */
209
210 /**
211 * @brief TIM Time Base configuration structure definition.
212 */
213 typedef struct
214 {
215 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
216 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
217
218 This feature can be modified afterwards using unitary function
219 @ref LL_TIM_SetPrescaler().*/
220
221 uint32_t CounterMode; /*!< Specifies the counter mode.
222 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
223
224 This feature can be modified afterwards using unitary function
225 @ref LL_TIM_SetCounterMode().*/
226
227 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
228 Auto-Reload Register at the next update event.
229 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
230 Some timer instances may support 32 bits counters. In that case this parameter must
231 be a number between 0x0000 and 0xFFFFFFFF.
232
233 This feature can be modified afterwards using unitary function
234 @ref LL_TIM_SetAutoReload().*/
235
236 uint32_t ClockDivision; /*!< Specifies the clock division.
237 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
238
239 This feature can be modified afterwards using unitary function
240 @ref LL_TIM_SetClockDivision().*/
241
242 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
243 reaches zero, an update event is generated and counting restarts
244 from the RCR value (N).
245 This means in PWM mode that (N+1) corresponds to:
246 - the number of PWM periods in edge-aligned mode
247 - the number of half PWM period in center-aligned mode
248 GP timers: this parameter must be a number between Min_Data = 0x00 and
249 Max_Data = 0xFF.
250 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
251 Max_Data = 0xFFFF.
252
253 This feature can be modified afterwards using unitary function
254 @ref LL_TIM_SetRepetitionCounter().*/
255 } LL_TIM_InitTypeDef;
256
257 /**
258 * @brief TIM Output Compare configuration structure definition.
259 */
260 typedef struct
261 {
262 uint32_t OCMode; /*!< Specifies the output mode.
263 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
264
265 This feature can be modified afterwards using unitary function
266 @ref LL_TIM_OC_SetMode().*/
267
268 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
269 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
270
271 This feature can be modified afterwards using unitary functions
272 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
273
274 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
275 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
276
277 This feature can be modified afterwards using unitary functions
278 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
279
280 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
281 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
282
283 This feature can be modified afterwards using unitary function
284 LL_TIM_OC_SetCompareCHx (x=1..6).*/
285
286 uint32_t OCPolarity; /*!< Specifies the output polarity.
287 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
288
289 This feature can be modified afterwards using unitary function
290 @ref LL_TIM_OC_SetPolarity().*/
291
292 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
293 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
294
295 This feature can be modified afterwards using unitary function
296 @ref LL_TIM_OC_SetPolarity().*/
297
298
299 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
300 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
301
302 This feature can be modified afterwards using unitary function
303 @ref LL_TIM_OC_SetIdleState().*/
304
305 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
306 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
307
308 This feature can be modified afterwards using unitary function
309 @ref LL_TIM_OC_SetIdleState().*/
310 } LL_TIM_OC_InitTypeDef;
311
312 /**
313 * @brief TIM Input Capture configuration structure definition.
314 */
315
316 typedef struct
317 {
318
319 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
320 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
321
322 This feature can be modified afterwards using unitary function
323 @ref LL_TIM_IC_SetPolarity().*/
324
325 uint32_t ICActiveInput; /*!< Specifies the input.
326 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
327
328 This feature can be modified afterwards using unitary function
329 @ref LL_TIM_IC_SetActiveInput().*/
330
331 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
332 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
333
334 This feature can be modified afterwards using unitary function
335 @ref LL_TIM_IC_SetPrescaler().*/
336
337 uint32_t ICFilter; /*!< Specifies the input capture filter.
338 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
339
340 This feature can be modified afterwards using unitary function
341 @ref LL_TIM_IC_SetFilter().*/
342 } LL_TIM_IC_InitTypeDef;
343
344
345 /**
346 * @brief TIM Encoder interface configuration structure definition.
347 */
348 typedef struct
349 {
350 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
351 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
352
353 This feature can be modified afterwards using unitary function
354 @ref LL_TIM_SetEncoderMode().*/
355
356 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
357 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
358
359 This feature can be modified afterwards using unitary function
360 @ref LL_TIM_IC_SetPolarity().*/
361
362 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
363 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
364
365 This feature can be modified afterwards using unitary function
366 @ref LL_TIM_IC_SetActiveInput().*/
367
368 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
369 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
370
371 This feature can be modified afterwards using unitary function
372 @ref LL_TIM_IC_SetPrescaler().*/
373
374 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
375 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
376
377 This feature can be modified afterwards using unitary function
378 @ref LL_TIM_IC_SetFilter().*/
379
380 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
381 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
382
383 This feature can be modified afterwards using unitary function
384 @ref LL_TIM_IC_SetPolarity().*/
385
386 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
387 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
388
389 This feature can be modified afterwards using unitary function
390 @ref LL_TIM_IC_SetActiveInput().*/
391
392 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
393 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
394
395 This feature can be modified afterwards using unitary function
396 @ref LL_TIM_IC_SetPrescaler().*/
397
398 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
399 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
400
401 This feature can be modified afterwards using unitary function
402 @ref LL_TIM_IC_SetFilter().*/
403
404 } LL_TIM_ENCODER_InitTypeDef;
405
406 /**
407 * @brief TIM Hall sensor interface configuration structure definition.
408 */
409 typedef struct
410 {
411
412 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
413 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
414
415 This feature can be modified afterwards using unitary function
416 @ref LL_TIM_IC_SetPolarity().*/
417
418 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
419 Prescaler must be set to get a maximum counter period longer than the
420 time interval between 2 consecutive changes on the Hall inputs.
421 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
422
423 This feature can be modified afterwards using unitary function
424 @ref LL_TIM_IC_SetPrescaler().*/
425
426 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
427 This parameter can be a value of
428 @ref TIM_LL_EC_IC_FILTER.
429
430 This feature can be modified afterwards using unitary function
431 @ref LL_TIM_IC_SetFilter().*/
432
433 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
434 A positive pulse (TRGO event) is generated with a programmable delay every time
435 a change occurs on the Hall inputs.
436 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
437
438 This feature can be modified afterwards using unitary function
439 @ref LL_TIM_OC_SetCompareCH2().*/
440 } LL_TIM_HALLSENSOR_InitTypeDef;
441
442 /**
443 * @brief BDTR (Break and Dead Time) structure definition
444 */
445 typedef struct
446 {
447 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
448 This parameter can be a value of @ref TIM_LL_EC_OSSR
449
450 This feature can be modified afterwards using unitary function
451 @ref LL_TIM_SetOffStates()
452
453 @note This bit-field cannot be modified as long as LOCK level 2 has been
454 programmed. */
455
456 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
457 This parameter can be a value of @ref TIM_LL_EC_OSSI
458
459 This feature can be modified afterwards using unitary function
460 @ref LL_TIM_SetOffStates()
461
462 @note This bit-field cannot be modified as long as LOCK level 2 has been
463 programmed. */
464
465 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
466 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
467
468 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
469 register has been written, their content is frozen until the next reset.*/
470
471 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
472 switching-on of the outputs.
473 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
474
475 This feature can be modified afterwards using unitary function
476 @ref LL_TIM_OC_SetDeadTime()
477
478 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
479 programmed. */
480
481 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
482 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
483
484 This feature can be modified afterwards using unitary functions
485 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
486
487 @note This bit-field can not be modified as long as LOCK level 1 has been
488 programmed. */
489
490 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
491 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
492
493 This feature can be modified afterwards using unitary function
494 @ref LL_TIM_ConfigBRK()
495
496 @note This bit-field can not be modified as long as LOCK level 1 has been
497 programmed. */
498
499 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
500 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
501
502 This feature can be modified afterwards using unitary function
503 @ref LL_TIM_ConfigBRK()
504
505 @note This bit-field can not be modified as long as LOCK level 1 has been
506 programmed. */
507
508 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
509 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
510
511 This feature can be modified afterwards using unitary functions
512 @ref LL_TIM_ConfigBRK()
513
514 @note Bidirectional break input is only supported by advanced timers instances.
515
516 @note This bit-field can not be modified as long as LOCK level 1 has been
517 programmed. */
518
519 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
520 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
521
522 This feature can be modified afterwards using unitary functions
523 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
524
525 @note This bit-field can not be modified as long as LOCK level 1 has been
526 programmed. */
527
528 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
529 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
530
531 This feature can be modified afterwards using unitary function
532 @ref LL_TIM_ConfigBRK2()
533
534 @note This bit-field can not be modified as long as LOCK level 1 has been
535 programmed. */
536
537 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
538 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
539
540 This feature can be modified afterwards using unitary function
541 @ref LL_TIM_ConfigBRK2()
542
543 @note This bit-field can not be modified as long as LOCK level 1 has been
544 programmed. */
545
546 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
547 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
548
549 This feature can be modified afterwards using unitary functions
550 @ref LL_TIM_ConfigBRK2()
551
552 @note Bidirectional break input is only supported by advanced timers instances.
553
554 @note This bit-field can not be modified as long as LOCK level 1 has been
555 programmed. */
556
557 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
558 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
559
560 This feature can be modified afterwards using unitary functions
561 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
562
563 @note This bit-field can not be modified as long as LOCK level 1 has been
564 programmed. */
565 } LL_TIM_BDTR_InitTypeDef;
566
567 /**
568 * @}
569 */
570 #endif /* USE_FULL_LL_DRIVER */
571
572 /* Exported constants --------------------------------------------------------*/
573 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
574 * @{
575 */
576
577 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
578 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
579 * @{
580 */
581 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
582 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
583 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
584 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
585 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
586 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
587 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
588 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
589 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
590 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
591 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
592 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
593 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
594 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
595 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
596 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
597 /**
598 * @}
599 */
600
601 #if defined(USE_FULL_LL_DRIVER)
602 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
603 * @{
604 */
605 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
606 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
607 /**
608 * @}
609 */
610
611 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
612 * @{
613 */
614 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
615 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
616 /**
617 * @}
618 */
619
620 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
621 * @{
622 */
623 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
624 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
625 /**
626 * @}
627 */
628 #endif /* USE_FULL_LL_DRIVER */
629
630 /** @defgroup TIM_LL_EC_IT IT Defines
631 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
632 * @{
633 */
634 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
635 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
636 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
637 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
638 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
639 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
640 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
641 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
642 /**
643 * @}
644 */
645
646 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
647 * @{
648 */
649 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
650 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
651 /**
652 * @}
653 */
654
655 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
656 * @{
657 */
658 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
659 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
660 /**
661 * @}
662 */
663
664 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
665 * @{
666 */
667 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
668 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
669 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
670 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
671 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
672 /**
673 * @}
674 */
675
676 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
677 * @{
678 */
679 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
680 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
681 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
682 /**
683 * @}
684 */
685
686 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
687 * @{
688 */
689 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
690 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
691 /**
692 * @}
693 */
694
695 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
696 * @{
697 */
698 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
699 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
700 /**
701 * @}
702 */
703
704 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
705 * @{
706 */
707 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
708 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
709 /**
710 * @}
711 */
712
713 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
714 * @{
715 */
716 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
717 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
718 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
719 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
720 /**
721 * @}
722 */
723
724 /** @defgroup TIM_LL_EC_CHANNEL Channel
725 * @{
726 */
727 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
728 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
729 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
730 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
731 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
732 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
733 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
734 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
735 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
736 /**
737 * @}
738 */
739
740 #if defined(USE_FULL_LL_DRIVER)
741 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
742 * @{
743 */
744 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
745 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
746 /**
747 * @}
748 */
749 #endif /* USE_FULL_LL_DRIVER */
750
751 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
752 * @{
753 */
754 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
755 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
756 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
757 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
758 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
759 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
760 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
761 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
762 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
763 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
764 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
765 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
766 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
767 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
768 /**
769 * @}
770 */
771
772 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
773 * @{
774 */
775 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
776 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
777 /**
778 * @}
779 */
780
781 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
782 * @{
783 */
784 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
785 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
786 /**
787 * @}
788 */
789
790 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
791 * @{
792 */
793 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
794 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
795 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
796 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
797 /**
798 * @}
799 */
800
801 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
802 * @{
803 */
804 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
805 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
806 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
807 /**
808 * @}
809 */
810
811 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
812 * @{
813 */
814 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
815 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
816 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
817 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
818 /**
819 * @}
820 */
821
822 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
823 * @{
824 */
825 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
826 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
827 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
828 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
829 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
830 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
831 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
832 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
833 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
834 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
835 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
836 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
837 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
838 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
839 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
840 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
841 /**
842 * @}
843 */
844
845 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
846 * @{
847 */
848 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
849 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
850 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
851 /**
852 * @}
853 */
854
855 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
856 * @{
857 */
858 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
859 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
860 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
861 /**
862 * @}
863 */
864
865 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
866 * @{
867 */
868 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
869 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
870 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
871 /**
872 * @}
873 */
874
875 /** @defgroup TIM_LL_EC_TRGO Trigger Output
876 * @{
877 */
878 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
879 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
880 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
881 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
882 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
883 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
884 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
885 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
886 /**
887 * @}
888 */
889
890 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
891 * @{
892 */
893 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
894 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
895 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
896 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
897 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
898 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
899 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
900 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
901 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
902 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
903 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
904 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
905 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
906 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
907 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
908 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
909 /**
910 * @}
911 */
912
913 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
914 * @{
915 */
916 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
917 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
918 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
919 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
920 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
921 /**
922 * @}
923 */
924
925 /** @defgroup TIM_LL_EC_TS Trigger Selection
926 * @{
927 */
928 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
929 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
930 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
931 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
932 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
933 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
934 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
935 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
936 /**
937 * @}
938 */
939
940 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
941 * @{
942 */
943 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
944 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
945 /**
946 * @}
947 */
948
949 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
950 * @{
951 */
952 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
953 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
954 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
955 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
956 /**
957 * @}
958 */
959
960 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
961 * @{
962 */
963 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
964 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
965 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
966 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
967 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
968 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
969 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
970 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
971 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
972 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
973 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
974 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
975 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
976 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
977 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
978 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
979 /**
980 * @}
981 */
982
983 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
984 * @{
985 */
986 #define LL_TIM_ETRSOURCE_LEGACY 0x00000000U /*!< ETR legacy mode */
987 #if defined(COMP1)
988 #define LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
989 #endif /* COMP1 */
990 #if defined(COMP2)
991 #define LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
992 #endif /* COMP2 */
993 #define LL_TIM_ETRSOURCE_GPIO LL_TIM_ETRSOURCE_LEGACY /*!< ETR input is connected to GPIO through TIMx ETR remapping capability */
994 #define LL_TIM_ETRSOURCE_ADC1_AWD1 LL_TIM_ETRSOURCE_LEGACY /*!< ETR input is connected to ADC1 analog watchdog 1 through TIMx ETR remapping capability */
995 #if defined(ADC_SUPPORT_5_MSPS)
996 #define LL_TIM_ETRSOURCE_ADC1_AWD2 LL_TIM_ETRSOURCE_LEGACY /*!< ETR input is connected to ADC1 analog watchdog 2 through TIMx ETR remapping capability */
997 #define LL_TIM_ETRSOURCE_ADC1_AWD3 LL_TIM_ETRSOURCE_LEGACY /*!< ETR input is connected to ADC1 analog watchdog 3 through TIMx ETR remapping capability */
998 #endif
999 /**
1000 * @}
1001 */
1002
1003 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1004 * @{
1005 */
1006 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1007 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1008 /**
1009 * @}
1010 */
1011
1012 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1013 * @{
1014 */
1015 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1016 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1017 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1018 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1019 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1020 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1021 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1022 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1023 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1024 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1025 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1026 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1027 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1028 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1029 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1030 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1031 /**
1032 * @}
1033 */
1034
1035 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1036 * @{
1037 */
1038 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1039 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1040 /**
1041 * @}
1042 */
1043
1044 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1045 * @{
1046 */
1047 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1048 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1049 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1050 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1051 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1052 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1053 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1054 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1055 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1056 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1057 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1058 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1059 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1060 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1061 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1062 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1063 /**
1064 * @}
1065 */
1066
1067 /** @defgroup TIM_LL_EC_OSSI OSSI
1068 * @{
1069 */
1070 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1071 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1072 /**
1073 * @}
1074 */
1075
1076 /** @defgroup TIM_LL_EC_OSSR OSSR
1077 * @{
1078 */
1079 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1080 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1081 /**
1082 * @}
1083 */
1084
1085 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1086 * @{
1087 */
1088 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1089 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1090 /**
1091 * @}
1092 */
1093
1094 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1095 * @{
1096 */
1097 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1098 #if defined(COMP1)
1099 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1100 #endif /* COMP1 */
1101 #if defined(COMP2)
1102 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1103 #endif /* COMP2 */
1104 /**
1105 * @}
1106 */
1107
1108 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1109 * @{
1110 */
1111 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1112 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1113 /**
1114 * @}
1115 */
1116
1117 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1118 * @{
1119 */
1120 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1121 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1122 /**
1123 * @}
1124 */
1125
1126 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1127 * @{
1128 */
1129 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1130 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1131 /**
1132 * @}
1133 */
1134
1135 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1136 * @{
1137 */
1138 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1139 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1140 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1141 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1142 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1143 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1144 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1145 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1146 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1147 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1148 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1149 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1150 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1151 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1152 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1153 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1154 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1155 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1156 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR register is the DMA base address for DMA burst */
1157 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1158 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1159 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1160 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1161 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1162 /**
1163 * @}
1164 */
1165
1166 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1167 * @{
1168 */
1169 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1170 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1171 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1172 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1173 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1174 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1175 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1176 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1177 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1178 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1179 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1180 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1181 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1182 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1183 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1184 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1185 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1186 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1187 /**
1188 * @}
1189 */
1190
1191 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
1192 * @{
1193 */
1194 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR_RMP_MASK /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
1195 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
1196 #if defined(ADC_SUPPORT_5_MSPS)
1197 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR_ETR_ADC1_RMP_1 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
1198 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR_ETR_ADC1_RMP | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
1199 #endif
1200 /**
1201 * @}
1202 */
1203
1204 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
1205 * @{
1206 */
1207 #define LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR_RMP_MASK /*!< TIM1 input capture 1 is connected to GPIO */
1208 #if defined(COMP1)
1209 #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR_TI1_RMP | TIM1_OR_RMP_MASK) /*!< TIM1 input capture 1 is connected to COMP1 output */
1210 #endif /* COMP1 */
1211 /**
1212 * @}
1213 */
1214
1215 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap
1216 * @{
1217 */
1218 #define LL_TIM_TIM2_ITR1_RMP_NONE TIM2_OR_RMP_MASK /*!< No internal trigger on TIM2_ITR1 */
1219 #if defined(USB)
1220 #define LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR_ITR1_RMP) /*!< TIM2_ITR1 is connected to USB SOF */
1221 #endif /* USB */
1222 /**
1223 * @}
1224 */
1225
1226 /** @defgroup TIM_LL_EC_TIM2_ETR_RMP TIM2 External Trigger Remap
1227 * @{
1228 */
1229 #define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR_RMP_MASK /*!< TIM2_ETR is connected to GPIO */
1230 #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR_ETR_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to LSE */
1231 /**
1232 * @}
1233 */
1234
1235 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
1236 * @{
1237 */
1238 #define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR_RMP_MASK /*!< TIM2 input capture 4 is connected to GPIO */
1239 #if defined(COMP1)
1240 #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR_TI4_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */
1241 #endif /* COMP1 */
1242 #if defined(COMP2)
1243 #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR_TI4_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */
1244 #endif /* COMP2 */
1245 #if defined(COMP1) && defined(COMP2)
1246 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR_TI4_RMP | TIM2_OR_RMP_MASK) /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */
1247 #endif /* COMP1 && COMP2 */
1248 /**
1249 * @}
1250 */
1251
1252 #if defined(TIM16)
1253 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1254 * @{
1255 */
1256 #define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR_RMP_MASK /*!< TIM16 input capture 1 is connected to GPIO */
1257 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSI */
1258 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSE */
1259 #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
1260 /**
1261 * @}
1262 */
1263 #endif /* TIM16 */
1264
1265 #if defined(TIM17)
1266 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1267 * @{
1268 */
1269 #define LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR_RMP_MASK /*!< TIM17 input capture 1 is connected to GPIO */
1270 #define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR_TI1_RMP_0 | TIM17_OR_RMP_MASK) /*!< TIM17 input capture 1 is connected to MSI */
1271 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR_TI1_RMP_1 | TIM17_OR_RMP_MASK) /*!< TIM17 input capture 1 is connected to HSE/32 */
1272 #define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR_TI1_RMP | TIM17_OR_RMP_MASK) /*!< TIM17 input capture 1 is connected to MCO */
1273 /**
1274 * @}
1275 */
1276 #endif /* TIM17 */
1277
1278 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1279 * @{
1280 */
1281 #define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
1282 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
1283 /**
1284 * @}
1285 */
1286
1287 /** Legacy definitions for compatibility purpose
1288 @cond 0
1289 */
1290 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1291 /**
1292 @endcond
1293 */
1294
1295 /**
1296 * @}
1297 */
1298
1299 /* Exported macro ------------------------------------------------------------*/
1300 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1301 * @{
1302 */
1303
1304 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1305 * @{
1306 */
1307 /**
1308 * @brief Write a value in TIM register.
1309 * @param __INSTANCE__ TIM Instance
1310 * @param __REG__ Register to be written
1311 * @param __VALUE__ Value to be written in the register
1312 * @retval None
1313 */
1314 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1315
1316 /**
1317 * @brief Read a value in TIM register.
1318 * @param __INSTANCE__ TIM Instance
1319 * @param __REG__ Register to be read
1320 * @retval Register value
1321 */
1322 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1323 /**
1324 * @}
1325 */
1326
1327 /**
1328 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1329 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1330 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1331 * to TIMx_CNT register bit 31)
1332 * @param __CNT__ Counter value
1333 * @retval UIF status bit
1334 */
1335 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1336 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1337
1338 /**
1339 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1340 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1341 * @param __TIMCLK__ timer input clock frequency (in Hz)
1342 * @param __CKD__ This parameter can be one of the following values:
1343 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1344 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1345 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1346 * @param __DT__ deadtime duration (in ns)
1347 * @retval DTG[0:7]
1348 */
1349 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1350 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1351 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1352 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1353 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1354 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1355 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1356 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1357 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1358 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1359 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1360 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1361 0U)
1362
1363 /**
1364 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1365 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1366 * @param __TIMCLK__ timer input clock frequency (in Hz)
1367 * @param __CNTCLK__ counter clock frequency (in Hz)
1368 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1369 */
1370 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1371 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1372
1373 /**
1374 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1375 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1376 * @param __TIMCLK__ timer input clock frequency (in Hz)
1377 * @param __PSC__ prescaler
1378 * @param __FREQ__ output signal frequency (in Hz)
1379 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1380 */
1381 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1382 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1383
1384 /**
1385 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1386 * active/inactive delay.
1387 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1388 * @param __TIMCLK__ timer input clock frequency (in Hz)
1389 * @param __PSC__ prescaler
1390 * @param __DELAY__ timer output compare active/inactive delay (in us)
1391 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1392 */
1393 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1394 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1395 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1396
1397 /**
1398 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1399 * (when the timer operates in one pulse mode).
1400 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1401 * @param __TIMCLK__ timer input clock frequency (in Hz)
1402 * @param __PSC__ prescaler
1403 * @param __DELAY__ timer output compare active/inactive delay (in us)
1404 * @param __PULSE__ pulse duration (in us)
1405 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1406 */
1407 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1408 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1409 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1410
1411 /**
1412 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1413 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1414 * @param __ICPSC__ This parameter can be one of the following values:
1415 * @arg @ref LL_TIM_ICPSC_DIV1
1416 * @arg @ref LL_TIM_ICPSC_DIV2
1417 * @arg @ref LL_TIM_ICPSC_DIV4
1418 * @arg @ref LL_TIM_ICPSC_DIV8
1419 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1420 */
1421 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1422 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1423
1424
1425 /**
1426 * @}
1427 */
1428
1429 /* Exported functions --------------------------------------------------------*/
1430 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1431 * @{
1432 */
1433
1434 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1435 * @{
1436 */
1437 /**
1438 * @brief Enable timer counter.
1439 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1440 * @param TIMx Timer instance
1441 * @retval None
1442 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1443 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1444 {
1445 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1446 }
1447
1448 /**
1449 * @brief Disable timer counter.
1450 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1451 * @param TIMx Timer instance
1452 * @retval None
1453 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1454 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1455 {
1456 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1457 }
1458
1459 /**
1460 * @brief Indicates whether the timer counter is enabled.
1461 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1462 * @param TIMx Timer instance
1463 * @retval State of bit (1 or 0).
1464 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1465 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1466 {
1467 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1468 }
1469
1470 /**
1471 * @brief Enable update event generation.
1472 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1473 * @param TIMx Timer instance
1474 * @retval None
1475 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1476 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1477 {
1478 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1479 }
1480
1481 /**
1482 * @brief Disable update event generation.
1483 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1484 * @param TIMx Timer instance
1485 * @retval None
1486 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1487 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1488 {
1489 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1490 }
1491
1492 /**
1493 * @brief Indicates whether update event generation is enabled.
1494 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1495 * @param TIMx Timer instance
1496 * @retval Inverted state of bit (0 or 1).
1497 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1498 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1499 {
1500 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1501 }
1502
1503 /**
1504 * @brief Set update event source
1505 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1506 * generate an update interrupt or DMA request if enabled:
1507 * - Counter overflow/underflow
1508 * - Setting the UG bit
1509 * - Update generation through the slave mode controller
1510 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1511 * overflow/underflow generates an update interrupt or DMA request if enabled.
1512 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1513 * @param TIMx Timer instance
1514 * @param UpdateSource This parameter can be one of the following values:
1515 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1516 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1517 * @retval None
1518 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1519 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1520 {
1521 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1522 }
1523
1524 /**
1525 * @brief Get actual event update source
1526 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1527 * @param TIMx Timer instance
1528 * @retval Returned value can be one of the following values:
1529 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1530 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1531 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1532 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1533 {
1534 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1535 }
1536
1537 /**
1538 * @brief Set one pulse mode (one shot v.s. repetitive).
1539 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1540 * @param TIMx Timer instance
1541 * @param OnePulseMode This parameter can be one of the following values:
1542 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1543 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1544 * @retval None
1545 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1546 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1547 {
1548 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1549 }
1550
1551 /**
1552 * @brief Get actual one pulse mode.
1553 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1554 * @param TIMx Timer instance
1555 * @retval Returned value can be one of the following values:
1556 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1557 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1558 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1559 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1560 {
1561 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1562 }
1563
1564 /**
1565 * @brief Set the timer counter counting mode.
1566 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1567 * check whether or not the counter mode selection feature is supported
1568 * by a timer instance.
1569 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1570 * requires a timer reset to avoid unexpected direction
1571 * due to DIR bit readonly in center aligned mode.
1572 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1573 * CR1 CMS LL_TIM_SetCounterMode
1574 * @param TIMx Timer instance
1575 * @param CounterMode This parameter can be one of the following values:
1576 * @arg @ref LL_TIM_COUNTERMODE_UP
1577 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1578 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1579 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1580 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1581 * @retval None
1582 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1583 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1584 {
1585 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1586 }
1587
1588 /**
1589 * @brief Get actual counter mode.
1590 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1591 * check whether or not the counter mode selection feature is supported
1592 * by a timer instance.
1593 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1594 * CR1 CMS LL_TIM_GetCounterMode
1595 * @param TIMx Timer instance
1596 * @retval Returned value can be one of the following values:
1597 * @arg @ref LL_TIM_COUNTERMODE_UP
1598 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1599 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1600 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1601 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1602 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1603 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1604 {
1605 uint32_t counter_mode;
1606
1607 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1608
1609 if (counter_mode == 0U)
1610 {
1611 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1612 }
1613
1614 return counter_mode;
1615 }
1616
1617 /**
1618 * @brief Enable auto-reload (ARR) preload.
1619 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1620 * @param TIMx Timer instance
1621 * @retval None
1622 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1623 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1624 {
1625 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1626 }
1627
1628 /**
1629 * @brief Disable auto-reload (ARR) preload.
1630 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1631 * @param TIMx Timer instance
1632 * @retval None
1633 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1634 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1635 {
1636 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1637 }
1638
1639 /**
1640 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1641 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1642 * @param TIMx Timer instance
1643 * @retval State of bit (1 or 0).
1644 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1645 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1646 {
1647 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1648 }
1649
1650 /**
1651 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1652 * (when supported) and the digital filters.
1653 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1654 * whether or not the clock division feature is supported by the timer
1655 * instance.
1656 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1657 * @param TIMx Timer instance
1658 * @param ClockDivision This parameter can be one of the following values:
1659 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1660 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1661 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1662 * @retval None
1663 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1664 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1665 {
1666 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1667 }
1668
1669 /**
1670 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1671 * generators (when supported) and the digital filters.
1672 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1673 * whether or not the clock division feature is supported by the timer
1674 * instance.
1675 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1676 * @param TIMx Timer instance
1677 * @retval Returned value can be one of the following values:
1678 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1679 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1680 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1681 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1682 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1683 {
1684 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1685 }
1686
1687 /**
1688 * @brief Set the counter value.
1689 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1690 * whether or not a timer instance supports a 32 bits counter.
1691 * @rmtoll CNT CNT LL_TIM_SetCounter
1692 * @param TIMx Timer instance
1693 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1694 * @retval None
1695 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1696 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1697 {
1698 WRITE_REG(TIMx->CNT, Counter);
1699 }
1700
1701 /**
1702 * @brief Get the counter value.
1703 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1704 * whether or not a timer instance supports a 32 bits counter.
1705 * @rmtoll CNT CNT LL_TIM_GetCounter
1706 * @param TIMx Timer instance
1707 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1708 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1709 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1710 {
1711 return (uint32_t)(READ_REG(TIMx->CNT));
1712 }
1713
1714 /**
1715 * @brief Get the current direction of the counter
1716 * @rmtoll CR1 DIR LL_TIM_GetDirection
1717 * @param TIMx Timer instance
1718 * @retval Returned value can be one of the following values:
1719 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1720 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1721 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1722 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1723 {
1724 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1725 }
1726
1727 /**
1728 * @brief Set the prescaler value.
1729 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1730 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1731 * prescaler ratio is taken into account at the next update event.
1732 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1733 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1734 * @param TIMx Timer instance
1735 * @param Prescaler between Min_Data=0 and Max_Data=65535
1736 * @retval None
1737 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1738 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1739 {
1740 WRITE_REG(TIMx->PSC, Prescaler);
1741 }
1742
1743 /**
1744 * @brief Get the prescaler value.
1745 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1746 * @param TIMx Timer instance
1747 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1748 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1749 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1750 {
1751 return (uint32_t)(READ_REG(TIMx->PSC));
1752 }
1753
1754 /**
1755 * @brief Set the auto-reload value.
1756 * @note The counter is blocked while the auto-reload value is null.
1757 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1758 * whether or not a timer instance supports a 32 bits counter.
1759 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1760 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1761 * @param TIMx Timer instance
1762 * @param AutoReload between Min_Data=0 and Max_Data=65535
1763 * @retval None
1764 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1765 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1766 {
1767 WRITE_REG(TIMx->ARR, AutoReload);
1768 }
1769
1770 /**
1771 * @brief Get the auto-reload value.
1772 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1773 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1774 * whether or not a timer instance supports a 32 bits counter.
1775 * @param TIMx Timer instance
1776 * @retval Auto-reload value
1777 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1778 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1779 {
1780 return (uint32_t)(READ_REG(TIMx->ARR));
1781 }
1782
1783 /**
1784 * @brief Set the repetition counter value.
1785 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1786 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1787 * whether or not a timer instance supports a repetition counter.
1788 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1789 * @param TIMx Timer instance
1790 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1791 * @retval None
1792 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1793 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1794 {
1795 WRITE_REG(TIMx->RCR, RepetitionCounter);
1796 }
1797
1798 /**
1799 * @brief Get the repetition counter value.
1800 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1801 * whether or not a timer instance supports a repetition counter.
1802 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1803 * @param TIMx Timer instance
1804 * @retval Repetition counter value
1805 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1806 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1807 {
1808 return (uint32_t)(READ_REG(TIMx->RCR));
1809 }
1810
1811 /**
1812 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1813 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1814 * in an atomic way.
1815 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1816 * @param TIMx Timer instance
1817 * @retval None
1818 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1819 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1820 {
1821 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1822 }
1823
1824 /**
1825 * @brief Disable update interrupt flag (UIF) remapping.
1826 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1827 * @param TIMx Timer instance
1828 * @retval None
1829 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1830 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1831 {
1832 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1833 }
1834
1835 /**
1836 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1837 * @param Counter Counter value
1838 * @retval State of bit (1 or 0).
1839 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1840 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1841 {
1842 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1843 }
1844
1845 /**
1846 * @}
1847 */
1848
1849 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1850 * @{
1851 */
1852 /**
1853 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1854 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1855 * they are updated only when a commutation event (COM) occurs.
1856 * @note Only on channels that have a complementary output.
1857 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1858 * whether or not a timer instance is able to generate a commutation event.
1859 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1860 * @param TIMx Timer instance
1861 * @retval None
1862 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1863 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1864 {
1865 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1866 }
1867
1868 /**
1869 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1870 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1871 * whether or not a timer instance is able to generate a commutation event.
1872 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1873 * @param TIMx Timer instance
1874 * @retval None
1875 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1876 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1877 {
1878 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1879 }
1880
1881 /**
1882 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1883 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1884 * whether or not a timer instance is able to generate a commutation event.
1885 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1886 * @param TIMx Timer instance
1887 * @param CCUpdateSource This parameter can be one of the following values:
1888 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1889 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1890 * @retval None
1891 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1892 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1893 {
1894 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1895 }
1896
1897 /**
1898 * @brief Set the trigger of the capture/compare DMA request.
1899 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1900 * @param TIMx Timer instance
1901 * @param DMAReqTrigger This parameter can be one of the following values:
1902 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1903 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1904 * @retval None
1905 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1906 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1907 {
1908 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1909 }
1910
1911 /**
1912 * @brief Get actual trigger of the capture/compare DMA request.
1913 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1914 * @param TIMx Timer instance
1915 * @retval Returned value can be one of the following values:
1916 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1917 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1918 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1919 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1920 {
1921 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1922 }
1923
1924 /**
1925 * @brief Set the lock level to freeze the
1926 * configuration of several capture/compare parameters.
1927 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1928 * the lock mechanism is supported by a timer instance.
1929 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1930 * @param TIMx Timer instance
1931 * @param LockLevel This parameter can be one of the following values:
1932 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1933 * @arg @ref LL_TIM_LOCKLEVEL_1
1934 * @arg @ref LL_TIM_LOCKLEVEL_2
1935 * @arg @ref LL_TIM_LOCKLEVEL_3
1936 * @retval None
1937 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1938 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1939 {
1940 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1941 }
1942
1943 /**
1944 * @brief Enable capture/compare channels.
1945 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1946 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1947 * CCER CC2E LL_TIM_CC_EnableChannel\n
1948 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1949 * CCER CC3E LL_TIM_CC_EnableChannel\n
1950 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1951 * CCER CC4E LL_TIM_CC_EnableChannel\n
1952 * CCER CC5E LL_TIM_CC_EnableChannel\n
1953 * CCER CC6E LL_TIM_CC_EnableChannel
1954 * @param TIMx Timer instance
1955 * @param Channels This parameter can be a combination of the following values:
1956 * @arg @ref LL_TIM_CHANNEL_CH1
1957 * @arg @ref LL_TIM_CHANNEL_CH1N
1958 * @arg @ref LL_TIM_CHANNEL_CH2
1959 * @arg @ref LL_TIM_CHANNEL_CH2N
1960 * @arg @ref LL_TIM_CHANNEL_CH3
1961 * @arg @ref LL_TIM_CHANNEL_CH3N
1962 * @arg @ref LL_TIM_CHANNEL_CH4
1963 * @arg @ref LL_TIM_CHANNEL_CH5
1964 * @arg @ref LL_TIM_CHANNEL_CH6
1965 * @retval None
1966 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1967 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1968 {
1969 SET_BIT(TIMx->CCER, Channels);
1970 }
1971
1972 /**
1973 * @brief Disable capture/compare channels.
1974 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1975 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1976 * CCER CC2E LL_TIM_CC_DisableChannel\n
1977 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1978 * CCER CC3E LL_TIM_CC_DisableChannel\n
1979 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1980 * CCER CC4E LL_TIM_CC_DisableChannel\n
1981 * CCER CC5E LL_TIM_CC_DisableChannel\n
1982 * CCER CC6E LL_TIM_CC_DisableChannel
1983 * @param TIMx Timer instance
1984 * @param Channels This parameter can be a combination of the following values:
1985 * @arg @ref LL_TIM_CHANNEL_CH1
1986 * @arg @ref LL_TIM_CHANNEL_CH1N
1987 * @arg @ref LL_TIM_CHANNEL_CH2
1988 * @arg @ref LL_TIM_CHANNEL_CH2N
1989 * @arg @ref LL_TIM_CHANNEL_CH3
1990 * @arg @ref LL_TIM_CHANNEL_CH3N
1991 * @arg @ref LL_TIM_CHANNEL_CH4
1992 * @arg @ref LL_TIM_CHANNEL_CH5
1993 * @arg @ref LL_TIM_CHANNEL_CH6
1994 * @retval None
1995 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1996 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1997 {
1998 CLEAR_BIT(TIMx->CCER, Channels);
1999 }
2000
2001 /**
2002 * @brief Indicate whether channel(s) is(are) enabled.
2003 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2004 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2005 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2006 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2007 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2008 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2009 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2010 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2011 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2012 * @param TIMx Timer instance
2013 * @param Channels This parameter can be a combination of the following values:
2014 * @arg @ref LL_TIM_CHANNEL_CH1
2015 * @arg @ref LL_TIM_CHANNEL_CH1N
2016 * @arg @ref LL_TIM_CHANNEL_CH2
2017 * @arg @ref LL_TIM_CHANNEL_CH2N
2018 * @arg @ref LL_TIM_CHANNEL_CH3
2019 * @arg @ref LL_TIM_CHANNEL_CH3N
2020 * @arg @ref LL_TIM_CHANNEL_CH4
2021 * @arg @ref LL_TIM_CHANNEL_CH5
2022 * @arg @ref LL_TIM_CHANNEL_CH6
2023 * @retval State of bit (1 or 0).
2024 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)2025 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2026 {
2027 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2028 }
2029
2030 /**
2031 * @}
2032 */
2033
2034 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2035 * @{
2036 */
2037 /**
2038 * @brief Configure an output channel.
2039 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2040 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2041 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2042 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2043 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2044 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2045 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2046 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2047 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2048 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2049 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2050 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2051 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2052 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2053 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2054 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2055 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2056 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2057 * @param TIMx Timer instance
2058 * @param Channel This parameter can be one of the following values:
2059 * @arg @ref LL_TIM_CHANNEL_CH1
2060 * @arg @ref LL_TIM_CHANNEL_CH2
2061 * @arg @ref LL_TIM_CHANNEL_CH3
2062 * @arg @ref LL_TIM_CHANNEL_CH4
2063 * @arg @ref LL_TIM_CHANNEL_CH5
2064 * @arg @ref LL_TIM_CHANNEL_CH6
2065 * @param Configuration This parameter must be a combination of all the following values:
2066 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2067 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2068 * @retval None
2069 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2070 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2071 {
2072 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2073 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2074 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2075 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2076 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2077 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2078 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2079 }
2080
2081 /**
2082 * @brief Define the behavior of the output reference signal OCxREF from which
2083 * OCx and OCxN (when relevant) are derived.
2084 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2085 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2086 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2087 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2088 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2089 * CCMR3 OC6M LL_TIM_OC_SetMode
2090 * @param TIMx Timer instance
2091 * @param Channel This parameter can be one of the following values:
2092 * @arg @ref LL_TIM_CHANNEL_CH1
2093 * @arg @ref LL_TIM_CHANNEL_CH2
2094 * @arg @ref LL_TIM_CHANNEL_CH3
2095 * @arg @ref LL_TIM_CHANNEL_CH4
2096 * @arg @ref LL_TIM_CHANNEL_CH5
2097 * @arg @ref LL_TIM_CHANNEL_CH6
2098 * @param Mode This parameter can be one of the following values:
2099 * @arg @ref LL_TIM_OCMODE_FROZEN
2100 * @arg @ref LL_TIM_OCMODE_ACTIVE
2101 * @arg @ref LL_TIM_OCMODE_INACTIVE
2102 * @arg @ref LL_TIM_OCMODE_TOGGLE
2103 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2104 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2105 * @arg @ref LL_TIM_OCMODE_PWM1
2106 * @arg @ref LL_TIM_OCMODE_PWM2
2107 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2108 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2109 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2110 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2111 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2112 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2113 * @retval None
2114 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2115 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2116 {
2117 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2118 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2119 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2120 }
2121
2122 /**
2123 * @brief Get the output compare mode of an output channel.
2124 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2125 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2126 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2127 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2128 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2129 * CCMR3 OC6M LL_TIM_OC_GetMode
2130 * @param TIMx Timer instance
2131 * @param Channel This parameter can be one of the following values:
2132 * @arg @ref LL_TIM_CHANNEL_CH1
2133 * @arg @ref LL_TIM_CHANNEL_CH2
2134 * @arg @ref LL_TIM_CHANNEL_CH3
2135 * @arg @ref LL_TIM_CHANNEL_CH4
2136 * @arg @ref LL_TIM_CHANNEL_CH5
2137 * @arg @ref LL_TIM_CHANNEL_CH6
2138 * @retval Returned value can be one of the following values:
2139 * @arg @ref LL_TIM_OCMODE_FROZEN
2140 * @arg @ref LL_TIM_OCMODE_ACTIVE
2141 * @arg @ref LL_TIM_OCMODE_INACTIVE
2142 * @arg @ref LL_TIM_OCMODE_TOGGLE
2143 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2144 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2145 * @arg @ref LL_TIM_OCMODE_PWM1
2146 * @arg @ref LL_TIM_OCMODE_PWM2
2147 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2148 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2149 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2150 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2151 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2152 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2153 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2154 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2155 {
2156 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2157 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2158 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2159 }
2160
2161 /**
2162 * @brief Set the polarity of an output channel.
2163 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2164 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2165 * CCER CC2P LL_TIM_OC_SetPolarity\n
2166 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2167 * CCER CC3P LL_TIM_OC_SetPolarity\n
2168 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2169 * CCER CC4P LL_TIM_OC_SetPolarity\n
2170 * CCER CC5P LL_TIM_OC_SetPolarity\n
2171 * CCER CC6P LL_TIM_OC_SetPolarity
2172 * @param TIMx Timer instance
2173 * @param Channel This parameter can be one of the following values:
2174 * @arg @ref LL_TIM_CHANNEL_CH1
2175 * @arg @ref LL_TIM_CHANNEL_CH1N
2176 * @arg @ref LL_TIM_CHANNEL_CH2
2177 * @arg @ref LL_TIM_CHANNEL_CH2N
2178 * @arg @ref LL_TIM_CHANNEL_CH3
2179 * @arg @ref LL_TIM_CHANNEL_CH3N
2180 * @arg @ref LL_TIM_CHANNEL_CH4
2181 * @arg @ref LL_TIM_CHANNEL_CH5
2182 * @arg @ref LL_TIM_CHANNEL_CH6
2183 * @param Polarity This parameter can be one of the following values:
2184 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2185 * @arg @ref LL_TIM_OCPOLARITY_LOW
2186 * @retval None
2187 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2188 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2189 {
2190 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2191 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2192 }
2193
2194 /**
2195 * @brief Get the polarity of an output channel.
2196 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2197 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2198 * CCER CC2P LL_TIM_OC_GetPolarity\n
2199 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2200 * CCER CC3P LL_TIM_OC_GetPolarity\n
2201 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2202 * CCER CC4P LL_TIM_OC_GetPolarity\n
2203 * CCER CC5P LL_TIM_OC_GetPolarity\n
2204 * CCER CC6P LL_TIM_OC_GetPolarity
2205 * @param TIMx Timer instance
2206 * @param Channel This parameter can be one of the following values:
2207 * @arg @ref LL_TIM_CHANNEL_CH1
2208 * @arg @ref LL_TIM_CHANNEL_CH1N
2209 * @arg @ref LL_TIM_CHANNEL_CH2
2210 * @arg @ref LL_TIM_CHANNEL_CH2N
2211 * @arg @ref LL_TIM_CHANNEL_CH3
2212 * @arg @ref LL_TIM_CHANNEL_CH3N
2213 * @arg @ref LL_TIM_CHANNEL_CH4
2214 * @arg @ref LL_TIM_CHANNEL_CH5
2215 * @arg @ref LL_TIM_CHANNEL_CH6
2216 * @retval Returned value can be one of the following values:
2217 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2218 * @arg @ref LL_TIM_OCPOLARITY_LOW
2219 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2220 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2221 {
2222 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2223 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2224 }
2225
2226 /**
2227 * @brief Set the IDLE state of an output channel
2228 * @note This function is significant only for the timer instances
2229 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2230 * can be used to check whether or not a timer instance provides
2231 * a break input.
2232 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2233 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2234 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2235 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2236 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2237 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2238 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2239 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2240 * CR2 OIS6 LL_TIM_OC_SetIdleState
2241 * @param TIMx Timer instance
2242 * @param Channel This parameter can be one of the following values:
2243 * @arg @ref LL_TIM_CHANNEL_CH1
2244 * @arg @ref LL_TIM_CHANNEL_CH1N
2245 * @arg @ref LL_TIM_CHANNEL_CH2
2246 * @arg @ref LL_TIM_CHANNEL_CH2N
2247 * @arg @ref LL_TIM_CHANNEL_CH3
2248 * @arg @ref LL_TIM_CHANNEL_CH3N
2249 * @arg @ref LL_TIM_CHANNEL_CH4
2250 * @arg @ref LL_TIM_CHANNEL_CH5
2251 * @arg @ref LL_TIM_CHANNEL_CH6
2252 * @param IdleState This parameter can be one of the following values:
2253 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2254 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2255 * @retval None
2256 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2257 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2258 {
2259 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2260 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2261 }
2262
2263 /**
2264 * @brief Get the IDLE state of an output channel
2265 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2266 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2267 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2268 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2269 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2270 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2271 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2272 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2273 * CR2 OIS6 LL_TIM_OC_GetIdleState
2274 * @param TIMx Timer instance
2275 * @param Channel This parameter can be one of the following values:
2276 * @arg @ref LL_TIM_CHANNEL_CH1
2277 * @arg @ref LL_TIM_CHANNEL_CH1N
2278 * @arg @ref LL_TIM_CHANNEL_CH2
2279 * @arg @ref LL_TIM_CHANNEL_CH2N
2280 * @arg @ref LL_TIM_CHANNEL_CH3
2281 * @arg @ref LL_TIM_CHANNEL_CH3N
2282 * @arg @ref LL_TIM_CHANNEL_CH4
2283 * @arg @ref LL_TIM_CHANNEL_CH5
2284 * @arg @ref LL_TIM_CHANNEL_CH6
2285 * @retval Returned value can be one of the following values:
2286 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2287 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2288 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2289 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2290 {
2291 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2292 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2293 }
2294
2295 /**
2296 * @brief Enable fast mode for the output channel.
2297 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2298 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2299 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2300 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2301 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2302 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2303 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2304 * @param TIMx Timer instance
2305 * @param Channel This parameter can be one of the following values:
2306 * @arg @ref LL_TIM_CHANNEL_CH1
2307 * @arg @ref LL_TIM_CHANNEL_CH2
2308 * @arg @ref LL_TIM_CHANNEL_CH3
2309 * @arg @ref LL_TIM_CHANNEL_CH4
2310 * @arg @ref LL_TIM_CHANNEL_CH5
2311 * @arg @ref LL_TIM_CHANNEL_CH6
2312 * @retval None
2313 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2314 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2315 {
2316 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2317 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2318 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2319
2320 }
2321
2322 /**
2323 * @brief Disable fast mode for the output channel.
2324 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2325 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2326 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2327 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2328 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2329 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2330 * @param TIMx Timer instance
2331 * @param Channel This parameter can be one of the following values:
2332 * @arg @ref LL_TIM_CHANNEL_CH1
2333 * @arg @ref LL_TIM_CHANNEL_CH2
2334 * @arg @ref LL_TIM_CHANNEL_CH3
2335 * @arg @ref LL_TIM_CHANNEL_CH4
2336 * @arg @ref LL_TIM_CHANNEL_CH5
2337 * @arg @ref LL_TIM_CHANNEL_CH6
2338 * @retval None
2339 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2340 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2341 {
2342 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2343 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2344 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2345
2346 }
2347
2348 /**
2349 * @brief Indicates whether fast mode is enabled for the output channel.
2350 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2351 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2352 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2353 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2354 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2355 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2356 * @param TIMx Timer instance
2357 * @param Channel This parameter can be one of the following values:
2358 * @arg @ref LL_TIM_CHANNEL_CH1
2359 * @arg @ref LL_TIM_CHANNEL_CH2
2360 * @arg @ref LL_TIM_CHANNEL_CH3
2361 * @arg @ref LL_TIM_CHANNEL_CH4
2362 * @arg @ref LL_TIM_CHANNEL_CH5
2363 * @arg @ref LL_TIM_CHANNEL_CH6
2364 * @retval State of bit (1 or 0).
2365 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2366 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2367 {
2368 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2369 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2370 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2371 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2372 }
2373
2374 /**
2375 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2376 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2377 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2378 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2379 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2380 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2381 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2382 * @param TIMx Timer instance
2383 * @param Channel This parameter can be one of the following values:
2384 * @arg @ref LL_TIM_CHANNEL_CH1
2385 * @arg @ref LL_TIM_CHANNEL_CH2
2386 * @arg @ref LL_TIM_CHANNEL_CH3
2387 * @arg @ref LL_TIM_CHANNEL_CH4
2388 * @arg @ref LL_TIM_CHANNEL_CH5
2389 * @arg @ref LL_TIM_CHANNEL_CH6
2390 * @retval None
2391 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2392 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2393 {
2394 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2395 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2396 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2397 }
2398
2399 /**
2400 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2401 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2402 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2403 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2404 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2405 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2406 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2407 * @param TIMx Timer instance
2408 * @param Channel This parameter can be one of the following values:
2409 * @arg @ref LL_TIM_CHANNEL_CH1
2410 * @arg @ref LL_TIM_CHANNEL_CH2
2411 * @arg @ref LL_TIM_CHANNEL_CH3
2412 * @arg @ref LL_TIM_CHANNEL_CH4
2413 * @arg @ref LL_TIM_CHANNEL_CH5
2414 * @arg @ref LL_TIM_CHANNEL_CH6
2415 * @retval None
2416 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2417 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2418 {
2419 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2420 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2421 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2422 }
2423
2424 /**
2425 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2426 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2427 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2428 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2429 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2430 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2431 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2432 * @param TIMx Timer instance
2433 * @param Channel This parameter can be one of the following values:
2434 * @arg @ref LL_TIM_CHANNEL_CH1
2435 * @arg @ref LL_TIM_CHANNEL_CH2
2436 * @arg @ref LL_TIM_CHANNEL_CH3
2437 * @arg @ref LL_TIM_CHANNEL_CH4
2438 * @arg @ref LL_TIM_CHANNEL_CH5
2439 * @arg @ref LL_TIM_CHANNEL_CH6
2440 * @retval State of bit (1 or 0).
2441 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2442 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2443 {
2444 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2445 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2446 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2447 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2448 }
2449
2450 /**
2451 * @brief Enable clearing the output channel on an external event.
2452 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2453 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2454 * or not a timer instance can clear the OCxREF signal on an external event.
2455 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2456 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2457 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2458 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2459 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2460 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2461 * @param TIMx Timer instance
2462 * @param Channel This parameter can be one of the following values:
2463 * @arg @ref LL_TIM_CHANNEL_CH1
2464 * @arg @ref LL_TIM_CHANNEL_CH2
2465 * @arg @ref LL_TIM_CHANNEL_CH3
2466 * @arg @ref LL_TIM_CHANNEL_CH4
2467 * @arg @ref LL_TIM_CHANNEL_CH5
2468 * @arg @ref LL_TIM_CHANNEL_CH6
2469 * @retval None
2470 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2471 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2472 {
2473 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2474 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2475 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2476 }
2477
2478 /**
2479 * @brief Disable clearing the output channel on an external event.
2480 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2481 * or not a timer instance can clear the OCxREF signal on an external event.
2482 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2483 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2484 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2485 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2486 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2487 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2488 * @param TIMx Timer instance
2489 * @param Channel This parameter can be one of the following values:
2490 * @arg @ref LL_TIM_CHANNEL_CH1
2491 * @arg @ref LL_TIM_CHANNEL_CH2
2492 * @arg @ref LL_TIM_CHANNEL_CH3
2493 * @arg @ref LL_TIM_CHANNEL_CH4
2494 * @arg @ref LL_TIM_CHANNEL_CH5
2495 * @arg @ref LL_TIM_CHANNEL_CH6
2496 * @retval None
2497 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2498 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2499 {
2500 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2501 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2502 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2503 }
2504
2505 /**
2506 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2507 * @note This function enables clearing the output channel on an external event.
2508 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2509 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2510 * or not a timer instance can clear the OCxREF signal on an external event.
2511 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2512 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2513 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2514 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2515 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2516 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2517 * @param TIMx Timer instance
2518 * @param Channel This parameter can be one of the following values:
2519 * @arg @ref LL_TIM_CHANNEL_CH1
2520 * @arg @ref LL_TIM_CHANNEL_CH2
2521 * @arg @ref LL_TIM_CHANNEL_CH3
2522 * @arg @ref LL_TIM_CHANNEL_CH4
2523 * @arg @ref LL_TIM_CHANNEL_CH5
2524 * @arg @ref LL_TIM_CHANNEL_CH6
2525 * @retval State of bit (1 or 0).
2526 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2527 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2528 {
2529 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2530 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2531 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2532 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2533 }
2534
2535 /**
2536 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2537 * the Ocx and OCxN signals).
2538 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2539 * dead-time insertion feature is supported by a timer instance.
2540 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2541 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2542 * @param TIMx Timer instance
2543 * @param DeadTime between Min_Data=0 and Max_Data=255
2544 * @retval None
2545 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2546 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2547 {
2548 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2549 }
2550
2551 /**
2552 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2553 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2554 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2555 * whether or not a timer instance supports a 32 bits counter.
2556 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2557 * output channel 1 is supported by a timer instance.
2558 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2559 * @param TIMx Timer instance
2560 * @param CompareValue between Min_Data=0 and Max_Data=65535
2561 * @retval None
2562 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2563 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2564 {
2565 WRITE_REG(TIMx->CCR1, CompareValue);
2566 }
2567
2568 /**
2569 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2570 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2571 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2572 * whether or not a timer instance supports a 32 bits counter.
2573 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2574 * output channel 2 is supported by a timer instance.
2575 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2576 * @param TIMx Timer instance
2577 * @param CompareValue between Min_Data=0 and Max_Data=65535
2578 * @retval None
2579 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2580 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2581 {
2582 WRITE_REG(TIMx->CCR2, CompareValue);
2583 }
2584
2585 /**
2586 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2587 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2588 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2589 * whether or not a timer instance supports a 32 bits counter.
2590 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2591 * output channel is supported by a timer instance.
2592 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2593 * @param TIMx Timer instance
2594 * @param CompareValue between Min_Data=0 and Max_Data=65535
2595 * @retval None
2596 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2597 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2598 {
2599 WRITE_REG(TIMx->CCR3, CompareValue);
2600 }
2601
2602 /**
2603 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2604 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2605 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2606 * whether or not a timer instance supports a 32 bits counter.
2607 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2608 * output channel 4 is supported by a timer instance.
2609 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2610 * @param TIMx Timer instance
2611 * @param CompareValue between Min_Data=0 and Max_Data=65535
2612 * @retval None
2613 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2614 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2615 {
2616 WRITE_REG(TIMx->CCR4, CompareValue);
2617 }
2618
2619 /**
2620 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2621 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2622 * output channel 5 is supported by a timer instance.
2623 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2624 * @param TIMx Timer instance
2625 * @param CompareValue between Min_Data=0 and Max_Data=65535
2626 * @retval None
2627 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2628 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2629 {
2630 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2631 }
2632
2633 /**
2634 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2635 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2636 * output channel 6 is supported by a timer instance.
2637 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2638 * @param TIMx Timer instance
2639 * @param CompareValue between Min_Data=0 and Max_Data=65535
2640 * @retval None
2641 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2642 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2643 {
2644 WRITE_REG(TIMx->CCR6, CompareValue);
2645 }
2646
2647 /**
2648 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2649 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2650 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2651 * whether or not a timer instance supports a 32 bits counter.
2652 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2653 * output channel 1 is supported by a timer instance.
2654 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2655 * @param TIMx Timer instance
2656 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2657 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2658 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2659 {
2660 return (uint32_t)(READ_REG(TIMx->CCR1));
2661 }
2662
2663 /**
2664 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2665 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2666 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2667 * whether or not a timer instance supports a 32 bits counter.
2668 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2669 * output channel 2 is supported by a timer instance.
2670 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2671 * @param TIMx Timer instance
2672 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2673 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2674 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2675 {
2676 return (uint32_t)(READ_REG(TIMx->CCR2));
2677 }
2678
2679 /**
2680 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2681 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2682 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2683 * whether or not a timer instance supports a 32 bits counter.
2684 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2685 * output channel 3 is supported by a timer instance.
2686 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2687 * @param TIMx Timer instance
2688 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2689 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2690 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2691 {
2692 return (uint32_t)(READ_REG(TIMx->CCR3));
2693 }
2694
2695 /**
2696 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2697 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2698 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2699 * whether or not a timer instance supports a 32 bits counter.
2700 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2701 * output channel 4 is supported by a timer instance.
2702 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2703 * @param TIMx Timer instance
2704 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2705 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2706 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2707 {
2708 return (uint32_t)(READ_REG(TIMx->CCR4));
2709 }
2710
2711 /**
2712 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2713 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2714 * output channel 5 is supported by a timer instance.
2715 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2716 * @param TIMx Timer instance
2717 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2718 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2719 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2720 {
2721 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2722 }
2723
2724 /**
2725 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2726 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2727 * output channel 6 is supported by a timer instance.
2728 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2729 * @param TIMx Timer instance
2730 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2731 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2732 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2733 {
2734 return (uint32_t)(READ_REG(TIMx->CCR6));
2735 }
2736
2737 /**
2738 * @brief Select on which reference signal the OC5REF is combined to.
2739 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2740 * whether or not a timer instance supports the combined 3-phase PWM mode.
2741 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2742 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2743 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2744 * @param TIMx Timer instance
2745 * @param GroupCH5 This parameter can be a combination of the following values:
2746 * @arg @ref LL_TIM_GROUPCH5_NONE
2747 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2748 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2749 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2750 * @retval None
2751 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2752 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2753 {
2754 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2755 }
2756
2757 /**
2758 * @}
2759 */
2760
2761 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2762 * @{
2763 */
2764 /**
2765 * @brief Configure input channel.
2766 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2767 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2768 * CCMR1 IC1F LL_TIM_IC_Config\n
2769 * CCMR1 CC2S LL_TIM_IC_Config\n
2770 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2771 * CCMR1 IC2F LL_TIM_IC_Config\n
2772 * CCMR2 CC3S LL_TIM_IC_Config\n
2773 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2774 * CCMR2 IC3F LL_TIM_IC_Config\n
2775 * CCMR2 CC4S LL_TIM_IC_Config\n
2776 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2777 * CCMR2 IC4F LL_TIM_IC_Config\n
2778 * CCER CC1P LL_TIM_IC_Config\n
2779 * CCER CC1NP LL_TIM_IC_Config\n
2780 * CCER CC2P LL_TIM_IC_Config\n
2781 * CCER CC2NP LL_TIM_IC_Config\n
2782 * CCER CC3P LL_TIM_IC_Config\n
2783 * CCER CC3NP LL_TIM_IC_Config\n
2784 * CCER CC4P LL_TIM_IC_Config\n
2785 * CCER CC4NP LL_TIM_IC_Config
2786 * @param TIMx Timer instance
2787 * @param Channel This parameter can be one of the following values:
2788 * @arg @ref LL_TIM_CHANNEL_CH1
2789 * @arg @ref LL_TIM_CHANNEL_CH2
2790 * @arg @ref LL_TIM_CHANNEL_CH3
2791 * @arg @ref LL_TIM_CHANNEL_CH4
2792 * @param Configuration This parameter must be a combination of all the following values:
2793 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2794 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2795 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2796 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2797 * @retval None
2798 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2799 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2800 {
2801 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2802 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2803 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2804 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2805 << SHIFT_TAB_ICxx[iChannel]);
2806 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2807 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2808 }
2809
2810 /**
2811 * @brief Set the active input.
2812 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2813 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2814 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2815 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2816 * @param TIMx Timer instance
2817 * @param Channel This parameter can be one of the following values:
2818 * @arg @ref LL_TIM_CHANNEL_CH1
2819 * @arg @ref LL_TIM_CHANNEL_CH2
2820 * @arg @ref LL_TIM_CHANNEL_CH3
2821 * @arg @ref LL_TIM_CHANNEL_CH4
2822 * @param ICActiveInput This parameter can be one of the following values:
2823 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2824 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2825 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2826 * @retval None
2827 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2828 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2829 {
2830 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2831 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2832 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2833 }
2834
2835 /**
2836 * @brief Get the current active input.
2837 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2838 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2839 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2840 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2841 * @param TIMx Timer instance
2842 * @param Channel This parameter can be one of the following values:
2843 * @arg @ref LL_TIM_CHANNEL_CH1
2844 * @arg @ref LL_TIM_CHANNEL_CH2
2845 * @arg @ref LL_TIM_CHANNEL_CH3
2846 * @arg @ref LL_TIM_CHANNEL_CH4
2847 * @retval Returned value can be one of the following values:
2848 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2849 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2850 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2851 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2852 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2853 {
2854 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2855 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2856 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2857 }
2858
2859 /**
2860 * @brief Set the prescaler of input channel.
2861 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2862 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2863 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2864 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2865 * @param TIMx Timer instance
2866 * @param Channel This parameter can be one of the following values:
2867 * @arg @ref LL_TIM_CHANNEL_CH1
2868 * @arg @ref LL_TIM_CHANNEL_CH2
2869 * @arg @ref LL_TIM_CHANNEL_CH3
2870 * @arg @ref LL_TIM_CHANNEL_CH4
2871 * @param ICPrescaler This parameter can be one of the following values:
2872 * @arg @ref LL_TIM_ICPSC_DIV1
2873 * @arg @ref LL_TIM_ICPSC_DIV2
2874 * @arg @ref LL_TIM_ICPSC_DIV4
2875 * @arg @ref LL_TIM_ICPSC_DIV8
2876 * @retval None
2877 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2878 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2879 {
2880 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2881 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2882 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2883 }
2884
2885 /**
2886 * @brief Get the current prescaler value acting on an input channel.
2887 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2888 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2889 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2890 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2891 * @param TIMx Timer instance
2892 * @param Channel This parameter can be one of the following values:
2893 * @arg @ref LL_TIM_CHANNEL_CH1
2894 * @arg @ref LL_TIM_CHANNEL_CH2
2895 * @arg @ref LL_TIM_CHANNEL_CH3
2896 * @arg @ref LL_TIM_CHANNEL_CH4
2897 * @retval Returned value can be one of the following values:
2898 * @arg @ref LL_TIM_ICPSC_DIV1
2899 * @arg @ref LL_TIM_ICPSC_DIV2
2900 * @arg @ref LL_TIM_ICPSC_DIV4
2901 * @arg @ref LL_TIM_ICPSC_DIV8
2902 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2903 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2904 {
2905 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2906 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2907 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2908 }
2909
2910 /**
2911 * @brief Set the input filter duration.
2912 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2913 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2914 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2915 * CCMR2 IC4F LL_TIM_IC_SetFilter
2916 * @param TIMx Timer instance
2917 * @param Channel This parameter can be one of the following values:
2918 * @arg @ref LL_TIM_CHANNEL_CH1
2919 * @arg @ref LL_TIM_CHANNEL_CH2
2920 * @arg @ref LL_TIM_CHANNEL_CH3
2921 * @arg @ref LL_TIM_CHANNEL_CH4
2922 * @param ICFilter This parameter can be one of the following values:
2923 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2924 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2925 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2926 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2927 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2928 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2929 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2930 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2931 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2932 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2933 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2934 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2935 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2936 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2937 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2938 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2939 * @retval None
2940 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2941 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2942 {
2943 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2944 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2945 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2946 }
2947
2948 /**
2949 * @brief Get the input filter duration.
2950 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2951 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2952 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2953 * CCMR2 IC4F LL_TIM_IC_GetFilter
2954 * @param TIMx Timer instance
2955 * @param Channel This parameter can be one of the following values:
2956 * @arg @ref LL_TIM_CHANNEL_CH1
2957 * @arg @ref LL_TIM_CHANNEL_CH2
2958 * @arg @ref LL_TIM_CHANNEL_CH3
2959 * @arg @ref LL_TIM_CHANNEL_CH4
2960 * @retval Returned value can be one of the following values:
2961 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2962 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2963 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2964 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2965 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2966 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2967 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2968 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2969 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2970 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2971 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2972 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2973 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2974 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2975 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2976 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2977 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)2978 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
2979 {
2980 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2981 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2982 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2983 }
2984
2985 /**
2986 * @brief Set the input channel polarity.
2987 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2988 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2989 * CCER CC2P LL_TIM_IC_SetPolarity\n
2990 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2991 * CCER CC3P LL_TIM_IC_SetPolarity\n
2992 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2993 * CCER CC4P LL_TIM_IC_SetPolarity\n
2994 * CCER CC4NP LL_TIM_IC_SetPolarity
2995 * @param TIMx Timer instance
2996 * @param Channel This parameter can be one of the following values:
2997 * @arg @ref LL_TIM_CHANNEL_CH1
2998 * @arg @ref LL_TIM_CHANNEL_CH2
2999 * @arg @ref LL_TIM_CHANNEL_CH3
3000 * @arg @ref LL_TIM_CHANNEL_CH4
3001 * @param ICPolarity This parameter can be one of the following values:
3002 * @arg @ref LL_TIM_IC_POLARITY_RISING
3003 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3004 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3005 * @retval None
3006 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3007 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3008 {
3009 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3010 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3011 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3012 }
3013
3014 /**
3015 * @brief Get the current input channel polarity.
3016 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3017 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3018 * CCER CC2P LL_TIM_IC_GetPolarity\n
3019 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3020 * CCER CC3P LL_TIM_IC_GetPolarity\n
3021 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3022 * CCER CC4P LL_TIM_IC_GetPolarity\n
3023 * CCER CC4NP LL_TIM_IC_GetPolarity
3024 * @param TIMx Timer instance
3025 * @param Channel This parameter can be one of the following values:
3026 * @arg @ref LL_TIM_CHANNEL_CH1
3027 * @arg @ref LL_TIM_CHANNEL_CH2
3028 * @arg @ref LL_TIM_CHANNEL_CH3
3029 * @arg @ref LL_TIM_CHANNEL_CH4
3030 * @retval Returned value can be one of the following values:
3031 * @arg @ref LL_TIM_IC_POLARITY_RISING
3032 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3033 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3034 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3035 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3036 {
3037 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3038 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3039 SHIFT_TAB_CCxP[iChannel]);
3040 }
3041
3042 /**
3043 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3044 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3045 * a timer instance provides an XOR input.
3046 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3047 * @param TIMx Timer instance
3048 * @retval None
3049 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3050 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3051 {
3052 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3053 }
3054
3055 /**
3056 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3057 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3058 * a timer instance provides an XOR input.
3059 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3060 * @param TIMx Timer instance
3061 * @retval None
3062 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3063 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3064 {
3065 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3066 }
3067
3068 /**
3069 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3070 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3071 * a timer instance provides an XOR input.
3072 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3073 * @param TIMx Timer instance
3074 * @retval State of bit (1 or 0).
3075 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3076 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3077 {
3078 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3079 }
3080
3081 /**
3082 * @brief Get captured value for input channel 1.
3083 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3084 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3085 * whether or not a timer instance supports a 32 bits counter.
3086 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3087 * input channel 1 is supported by a timer instance.
3088 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3089 * @param TIMx Timer instance
3090 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3091 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3092 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3093 {
3094 return (uint32_t)(READ_REG(TIMx->CCR1));
3095 }
3096
3097 /**
3098 * @brief Get captured value for input channel 2.
3099 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3100 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3101 * whether or not a timer instance supports a 32 bits counter.
3102 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3103 * input channel 2 is supported by a timer instance.
3104 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3105 * @param TIMx Timer instance
3106 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3107 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3108 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3109 {
3110 return (uint32_t)(READ_REG(TIMx->CCR2));
3111 }
3112
3113 /**
3114 * @brief Get captured value for input channel 3.
3115 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3116 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3117 * whether or not a timer instance supports a 32 bits counter.
3118 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3119 * input channel 3 is supported by a timer instance.
3120 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3121 * @param TIMx Timer instance
3122 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3123 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3124 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3125 {
3126 return (uint32_t)(READ_REG(TIMx->CCR3));
3127 }
3128
3129 /**
3130 * @brief Get captured value for input channel 4.
3131 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3132 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3133 * whether or not a timer instance supports a 32 bits counter.
3134 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3135 * input channel 4 is supported by a timer instance.
3136 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3137 * @param TIMx Timer instance
3138 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3139 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3140 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3141 {
3142 return (uint32_t)(READ_REG(TIMx->CCR4));
3143 }
3144
3145 /**
3146 * @}
3147 */
3148
3149 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3150 * @{
3151 */
3152 /**
3153 * @brief Enable external clock mode 2.
3154 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3155 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3156 * whether or not a timer instance supports external clock mode2.
3157 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3158 * @param TIMx Timer instance
3159 * @retval None
3160 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3161 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3162 {
3163 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3164 }
3165
3166 /**
3167 * @brief Disable external clock mode 2.
3168 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3169 * whether or not a timer instance supports external clock mode2.
3170 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3171 * @param TIMx Timer instance
3172 * @retval None
3173 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3174 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3175 {
3176 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3177 }
3178
3179 /**
3180 * @brief Indicate whether external clock mode 2 is enabled.
3181 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3182 * whether or not a timer instance supports external clock mode2.
3183 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3184 * @param TIMx Timer instance
3185 * @retval State of bit (1 or 0).
3186 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3187 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3188 {
3189 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3190 }
3191
3192 /**
3193 * @brief Set the clock source of the counter clock.
3194 * @note when selected clock source is external clock mode 1, the timer input
3195 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3196 * function. This timer input must be configured by calling
3197 * the @ref LL_TIM_IC_Config() function.
3198 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3199 * whether or not a timer instance supports external clock mode1.
3200 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3201 * whether or not a timer instance supports external clock mode2.
3202 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3203 * SMCR ECE LL_TIM_SetClockSource
3204 * @param TIMx Timer instance
3205 * @param ClockSource This parameter can be one of the following values:
3206 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3207 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3208 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3209 * @retval None
3210 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3211 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3212 {
3213 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3214 }
3215
3216 /**
3217 * @brief Set the encoder interface mode.
3218 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3219 * whether or not a timer instance supports the encoder mode.
3220 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3221 * @param TIMx Timer instance
3222 * @param EncoderMode This parameter can be one of the following values:
3223 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3224 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3225 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3226 * @retval None
3227 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3228 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3229 {
3230 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3231 }
3232
3233 /**
3234 * @}
3235 */
3236
3237 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3238 * @{
3239 */
3240 /**
3241 * @brief Set the trigger output (TRGO) used for timer synchronization .
3242 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3243 * whether or not a timer instance can operate as a master timer.
3244 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3245 * @param TIMx Timer instance
3246 * @param TimerSynchronization This parameter can be one of the following values:
3247 * @arg @ref LL_TIM_TRGO_RESET
3248 * @arg @ref LL_TIM_TRGO_ENABLE
3249 * @arg @ref LL_TIM_TRGO_UPDATE
3250 * @arg @ref LL_TIM_TRGO_CC1IF
3251 * @arg @ref LL_TIM_TRGO_OC1REF
3252 * @arg @ref LL_TIM_TRGO_OC2REF
3253 * @arg @ref LL_TIM_TRGO_OC3REF
3254 * @arg @ref LL_TIM_TRGO_OC4REF
3255 * @retval None
3256 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3257 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3258 {
3259 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3260 }
3261
3262 /**
3263 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3264 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3265 * whether or not a timer instance can be used for ADC synchronization.
3266 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3267 * @param TIMx Timer Instance
3268 * @param ADCSynchronization This parameter can be one of the following values:
3269 * @arg @ref LL_TIM_TRGO2_RESET
3270 * @arg @ref LL_TIM_TRGO2_ENABLE
3271 * @arg @ref LL_TIM_TRGO2_UPDATE
3272 * @arg @ref LL_TIM_TRGO2_CC1F
3273 * @arg @ref LL_TIM_TRGO2_OC1
3274 * @arg @ref LL_TIM_TRGO2_OC2
3275 * @arg @ref LL_TIM_TRGO2_OC3
3276 * @arg @ref LL_TIM_TRGO2_OC4
3277 * @arg @ref LL_TIM_TRGO2_OC5
3278 * @arg @ref LL_TIM_TRGO2_OC6
3279 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3280 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3281 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3282 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3283 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3284 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3285 * @retval None
3286 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3287 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3288 {
3289 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3290 }
3291
3292 /**
3293 * @brief Set the synchronization mode of a slave timer.
3294 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3295 * a timer instance can operate as a slave timer.
3296 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3297 * @param TIMx Timer instance
3298 * @param SlaveMode This parameter can be one of the following values:
3299 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3300 * @arg @ref LL_TIM_SLAVEMODE_RESET
3301 * @arg @ref LL_TIM_SLAVEMODE_GATED
3302 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3303 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3304 * @retval None
3305 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3306 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3307 {
3308 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3309 }
3310
3311 /**
3312 * @brief Set the selects the trigger input to be used to synchronize the counter.
3313 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3314 * a timer instance can operate as a slave timer.
3315 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3316 * @param TIMx Timer instance
3317 * @param TriggerInput This parameter can be one of the following values:
3318 * @arg @ref LL_TIM_TS_ITR0
3319 * @arg @ref LL_TIM_TS_ITR1
3320 * @arg @ref LL_TIM_TS_ITR2
3321 * @arg @ref LL_TIM_TS_ITR3
3322 * @arg @ref LL_TIM_TS_TI1F_ED
3323 * @arg @ref LL_TIM_TS_TI1FP1
3324 * @arg @ref LL_TIM_TS_TI2FP2
3325 * @arg @ref LL_TIM_TS_ETRF
3326 * @retval None
3327 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3328 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3329 {
3330 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3331 }
3332
3333 /**
3334 * @brief Enable the Master/Slave mode.
3335 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3336 * a timer instance can operate as a slave timer.
3337 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3338 * @param TIMx Timer instance
3339 * @retval None
3340 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3341 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3342 {
3343 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3344 }
3345
3346 /**
3347 * @brief Disable the Master/Slave mode.
3348 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3349 * a timer instance can operate as a slave timer.
3350 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3351 * @param TIMx Timer instance
3352 * @retval None
3353 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3354 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3355 {
3356 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3357 }
3358
3359 /**
3360 * @brief Indicates whether the Master/Slave mode is enabled.
3361 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3362 * a timer instance can operate as a slave timer.
3363 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3364 * @param TIMx Timer instance
3365 * @retval State of bit (1 or 0).
3366 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3367 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3368 {
3369 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3370 }
3371
3372 /**
3373 * @brief Configure the external trigger (ETR) input.
3374 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3375 * a timer instance provides an external trigger input.
3376 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3377 * SMCR ETPS LL_TIM_ConfigETR\n
3378 * SMCR ETF LL_TIM_ConfigETR
3379 * @param TIMx Timer instance
3380 * @param ETRPolarity This parameter can be one of the following values:
3381 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3382 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3383 * @param ETRPrescaler This parameter can be one of the following values:
3384 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3385 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3386 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3387 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3388 * @param ETRFilter This parameter can be one of the following values:
3389 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3390 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3391 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3392 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3393 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3394 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3395 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3396 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3397 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3398 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3399 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3400 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3401 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3402 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3403 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3404 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3405 * @retval None
3406 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3407 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3408 uint32_t ETRFilter)
3409 {
3410 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3411 }
3412
3413 /**
3414 * @brief Select the external trigger (ETR) input source.
3415 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3416 * not a timer instance supports ETR source selection.
3417 * @note When this function is called with LL_TIM_ETRSOURCE_GPIO,
3418 * LL_TIM_ETRSOURCE_ADC1_AWD1, LL_TIM_ETRSOURCE_ADC1_AWD2 or
3419 * LL_TIM_ETRSOURCE_ADC1_AWD3, ETR source relies on TIMx ETR remapping
3420 * capability configured through the function @ref LL_TIM_SetRemap().
3421 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3422 * @param TIMx Timer instance
3423 * @param ETRSource This parameter can be one of the following values:
3424 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3425 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1
3426 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2 (*)
3427 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3 (*)
3428 * @arg @ref LL_TIM_ETRSOURCE_COMP1 (*)
3429 * @arg @ref LL_TIM_ETRSOURCE_COMP2 (*)
3430 *
3431 * (*) Value not defined in all devices. \n
3432 * @retval None
3433 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3434 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3435 {
3436 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3437 }
3438
3439 /**
3440 * @}
3441 */
3442
3443 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3444 * @{
3445 */
3446 /**
3447 * @brief Enable the break function.
3448 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3449 * a timer instance provides a break input.
3450 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3451 * @param TIMx Timer instance
3452 * @retval None
3453 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3454 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3455 {
3456 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3457 }
3458
3459 /**
3460 * @brief Disable the break function.
3461 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3462 * @param TIMx Timer instance
3463 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3464 * a timer instance provides a break input.
3465 * @retval None
3466 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3467 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3468 {
3469 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3470 }
3471
3472 /**
3473 * @brief Configure the break input.
3474 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3475 * a timer instance provides a break input.
3476 * @note Bidirectional mode is only supported by advanced timer instances.
3477 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3478 * a timer instance is an advanced-control timer.
3479 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
3480 * in input mode and in open drain output mode. Any active Break event will
3481 * assert a low logic level on the Break input to indicate an internal break
3482 * event to external devices.
3483 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
3484 * LL_TIM_BREAK_AFMODE_INPUT.
3485 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3486 * BDTR BKF LL_TIM_ConfigBRK\n
3487 * BDTR BKBID LL_TIM_ConfigBRK
3488 * @param TIMx Timer instance
3489 * @param BreakPolarity This parameter can be one of the following values:
3490 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3491 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3492 * @param BreakFilter This parameter can be one of the following values:
3493 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3494 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3495 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3496 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3497 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3498 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3499 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3500 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3501 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3502 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3503 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3504 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3505 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3506 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3507 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3508 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3509 * @param BreakAFMode This parameter can be one of the following values:
3510 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3511 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3512 * @retval None
3513 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)3514 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
3515 uint32_t BreakAFMode)
3516 {
3517 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
3518 }
3519
3520 /**
3521 * @brief Disarm the break input (when it operates in bidirectional mode).
3522 * @note The break input can be disarmed only when it is configured in
3523 * bidirectional mode and when when MOE is reset.
3524 * @note Purpose is to be able to have the input voltage back to high-state,
3525 * whatever the time constant on the output .
3526 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3527 * @param TIMx Timer instance
3528 * @retval None
3529 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)3530 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
3531 {
3532 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3533 }
3534
3535 /**
3536 * @brief Re-arm the break input (when it operates in bidirectional mode).
3537 * @note The Break input is automatically armed as soon as MOE bit is set.
3538 * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
3539 * @param TIMx Timer instance
3540 * @retval None
3541 */
LL_TIM_ReArmBRK(TIM_TypeDef * TIMx)3542 __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
3543 {
3544 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3545 }
3546
3547 /**
3548 * @brief Enable the break 2 function.
3549 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3550 * a timer instance provides a second break input.
3551 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3552 * @param TIMx Timer instance
3553 * @retval None
3554 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3555 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3556 {
3557 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3558 }
3559
3560 /**
3561 * @brief Disable the break 2 function.
3562 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3563 * a timer instance provides a second break input.
3564 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3565 * @param TIMx Timer instance
3566 * @retval None
3567 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3568 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3569 {
3570 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3571 }
3572
3573 /**
3574 * @brief Configure the break 2 input.
3575 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3576 * a timer instance provides a second break input.
3577 * @note Bidirectional mode is only supported by advanced timer instances.
3578 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3579 * a timer instance is an advanced-control timer.
3580 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
3581 * in input mode and in open drain output mode. Any active Break event will
3582 * assert a low logic level on the Break 2 input to indicate an internal break
3583 * event to external devices.
3584 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
3585 * LL_TIM_BREAK2_AFMODE_INPUT.
3586 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3587 * BDTR BK2F LL_TIM_ConfigBRK2\n
3588 * BDTR BK2BID LL_TIM_ConfigBRK2
3589 * @param TIMx Timer instance
3590 * @param Break2Polarity This parameter can be one of the following values:
3591 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3592 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3593 * @param Break2Filter This parameter can be one of the following values:
3594 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3595 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3596 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3597 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3598 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3599 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3600 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3601 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3602 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3603 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3604 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3605 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3606 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3607 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3608 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3609 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3610 * @param Break2AFMode This parameter can be one of the following values:
3611 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
3612 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
3613 * @retval None
3614 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)3615 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
3616 uint32_t Break2AFMode)
3617 {
3618 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
3619 }
3620
3621 /**
3622 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
3623 * @note The break 2 input can be disarmed only when it is configured in
3624 * bidirectional mode and when when MOE is reset.
3625 * @note Purpose is to be able to have the input voltage back to high-state,
3626 * whatever the time constant on the output.
3627 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
3628 * @param TIMx Timer instance
3629 * @retval None
3630 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)3631 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
3632 {
3633 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3634 }
3635
3636 /**
3637 * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
3638 * @note The Break 2 input is automatically armed as soon as MOE bit is set.
3639 * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
3640 * @param TIMx Timer instance
3641 * @retval None
3642 */
LL_TIM_ReArmBRK2(TIM_TypeDef * TIMx)3643 __STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
3644 {
3645 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3646 }
3647
3648 /**
3649 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3650 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3651 * a timer instance provides a break input.
3652 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3653 * BDTR OSSR LL_TIM_SetOffStates
3654 * @param TIMx Timer instance
3655 * @param OffStateIdle This parameter can be one of the following values:
3656 * @arg @ref LL_TIM_OSSI_DISABLE
3657 * @arg @ref LL_TIM_OSSI_ENABLE
3658 * @param OffStateRun This parameter can be one of the following values:
3659 * @arg @ref LL_TIM_OSSR_DISABLE
3660 * @arg @ref LL_TIM_OSSR_ENABLE
3661 * @retval None
3662 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3663 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3664 {
3665 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3666 }
3667
3668 /**
3669 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3670 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3671 * a timer instance provides a break input.
3672 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3673 * @param TIMx Timer instance
3674 * @retval None
3675 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3676 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3677 {
3678 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3679 }
3680
3681 /**
3682 * @brief Disable automatic output (MOE can be set only by software).
3683 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3684 * a timer instance provides a break input.
3685 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3686 * @param TIMx Timer instance
3687 * @retval None
3688 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3689 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3690 {
3691 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3692 }
3693
3694 /**
3695 * @brief Indicate whether automatic output is enabled.
3696 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3697 * a timer instance provides a break input.
3698 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3699 * @param TIMx Timer instance
3700 * @retval State of bit (1 or 0).
3701 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3702 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3703 {
3704 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3705 }
3706
3707 /**
3708 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3709 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3710 * software and is reset in case of break or break2 event
3711 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3712 * a timer instance provides a break input.
3713 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3714 * @param TIMx Timer instance
3715 * @retval None
3716 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3717 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3718 {
3719 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3720 }
3721
3722 /**
3723 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3724 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3725 * software and is reset in case of break or break2 event.
3726 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3727 * a timer instance provides a break input.
3728 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3729 * @param TIMx Timer instance
3730 * @retval None
3731 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3732 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3733 {
3734 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3735 }
3736
3737 /**
3738 * @brief Indicates whether outputs are enabled.
3739 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3740 * a timer instance provides a break input.
3741 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3742 * @param TIMx Timer instance
3743 * @retval State of bit (1 or 0).
3744 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3745 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3746 {
3747 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3748 }
3749
3750 /**
3751 * @brief Enable the signals connected to the designated timer break input.
3752 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3753 * or not a timer instance allows for break input selection.
3754 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3755 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
3756 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
3757 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3758 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3759 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource
3760 * @param TIMx Timer instance
3761 * @param BreakInput This parameter can be one of the following values:
3762 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3763 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3764 * @param Source This parameter can be one of the following values:
3765 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3766 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
3767 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
3768 *
3769 * (*) Value not defined in all devices.
3770 * @retval None
3771 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3772 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3773 {
3774 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3775 SET_BIT(*pReg, Source);
3776 }
3777
3778 /**
3779 * @brief Disable the signals connected to the designated timer break input.
3780 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3781 * or not a timer instance allows for break input selection.
3782 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3783 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
3784 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
3785 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3786 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3787 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource
3788 * @param TIMx Timer instance
3789 * @param BreakInput This parameter can be one of the following values:
3790 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3791 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3792 * @param Source This parameter can be one of the following values:
3793 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3794 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
3795 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
3796 *
3797 * (*) Value not defined in all devices.
3798 * @retval None
3799 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3800 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3801 {
3802 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3803 CLEAR_BIT(*pReg, Source);
3804 }
3805
3806 /**
3807 * @brief Set the polarity of the break signal for the timer break input.
3808 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3809 * or not a timer instance allows for break input selection.
3810 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3811 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
3812 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
3813 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3814 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
3815 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
3816 * @param TIMx Timer instance
3817 * @param BreakInput This parameter can be one of the following values:
3818 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3819 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3820 * @param Source This parameter can be one of the following values:
3821 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3822 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
3823 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
3824 * @param Polarity This parameter can be one of the following values:
3825 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3826 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3827 *
3828 * (*) Value not defined in all devices.
3829 * @retval None
3830 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3831 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3832 uint32_t Polarity)
3833 {
3834 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3835 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3836 }
3837 /**
3838 * @}
3839 */
3840
3841 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3842 * @{
3843 */
3844 /**
3845 * @brief Configures the timer DMA burst feature.
3846 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3847 * not a timer instance supports the DMA burst mode.
3848 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3849 * DCR DBA LL_TIM_ConfigDMABurst
3850 * @param TIMx Timer instance
3851 * @param DMABurstBaseAddress This parameter can be one of the following values:
3852 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3853 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3854 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3855 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3856 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3857 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3858 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3859 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3860 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3861 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3862 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3863 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3864 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3865 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3866 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3867 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3868 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3869 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3870 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
3871 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3872 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3873 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3874 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
3875 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
3876 * @param DMABurstLength This parameter can be one of the following values:
3877 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3878 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3879 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3880 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3881 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3882 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3883 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3884 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3885 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3886 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3887 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3888 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3889 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3890 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3891 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3892 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3893 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3894 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3895 * @retval None
3896 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3897 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3898 {
3899 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3900 }
3901
3902 /**
3903 * @}
3904 */
3905
3906 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3907 * @{
3908 */
3909 /**
3910 * @brief Remap TIM inputs (input channel, internal/external triggers).
3911 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3912 * a some timer inputs can be remapped.
3913 * @rmtoll TIM1_OR ETR_ADC1_RMP LL_TIM_SetRemap\n
3914 * TIM1_OR TI1_RMP LL_TIM_SetRemap\n
3915 * TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
3916 * TIM2_OR TI4_RMP LL_TIM_SetRemap\n
3917 * TIM2_OR TI1_RMP LL_TIM_SetRemap\n
3918 * TIM16_OR TI1_RMP LL_TIM_SetRemap (***)\n
3919 * TIM17_OR TI1_RMP LL_TIM_SetRemap (***)
3920 * @param TIMx Timer instance
3921 * @param Remap Remap param depends on the TIMx. Description available only
3922 * in CHM version of the User Manual (not in .pdf).
3923 * Otherwise see Reference Manual description of OR registers.
3924 *
3925 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3926 *
3927 * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
3928 *
3929 * . . ADC1_RMP can be one of the following values
3930 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
3931 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
3932 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (**)
3933 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (**)
3934 *
3935 * . . TI1_RMP can be one of the following values
3936 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
3937 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 (**)
3938 *
3939 * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
3940 *
3941 * ITR1_RMP can be one of the following values
3942 * @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE
3943 * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF (**)
3944 *
3945 * . . ETR1_RMP can be one of the following values
3946 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
3947 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
3948 *
3949 * . . TI4_RMP can be one of the following values
3950 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
3951 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 (**)
3952 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 (**)
3953 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (**)
3954 *
3955 * TIM16: one of the following values (*)
3956 *
3957 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
3958 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
3959 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
3960 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
3961 *
3962 * TIM17: one of the following values (*)
3963 *
3964 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
3965 * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
3966 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
3967 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
3968 *
3969 * (*) Timer instance not available on all devices \n
3970 * (**) Value not defined in all devices.
3971 * (***) Register not available in all devices.
3972 * @retval None
3973 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3974 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3975 {
3976 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3977 }
3978
3979 /**
3980 * @}
3981 */
3982
3983 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
3984 * @{
3985 */
3986 /**
3987 * @brief Set the OCREF clear input source
3988 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
3989 * @note This function can only be used in Output compare and PWM modes.
3990 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
3991 * @param TIMx Timer instance
3992 * @param OCRefClearInputSource This parameter can be one of the following values:
3993 * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
3994 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
3995 * @retval None
3996 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)3997 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
3998 {
3999 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
4000 }
4001 /**
4002 * @}
4003 */
4004
4005 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4006 * @{
4007 */
4008 /**
4009 * @brief Clear the update interrupt flag (UIF).
4010 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4011 * @param TIMx Timer instance
4012 * @retval None
4013 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4014 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4015 {
4016 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4017 }
4018
4019 /**
4020 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4021 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4022 * @param TIMx Timer instance
4023 * @retval State of bit (1 or 0).
4024 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)4025 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
4026 {
4027 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4028 }
4029
4030 /**
4031 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4032 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4033 * @param TIMx Timer instance
4034 * @retval None
4035 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4036 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4037 {
4038 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4039 }
4040
4041 /**
4042 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4043 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4044 * @param TIMx Timer instance
4045 * @retval State of bit (1 or 0).
4046 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)4047 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
4048 {
4049 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4050 }
4051
4052 /**
4053 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4054 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4055 * @param TIMx Timer instance
4056 * @retval None
4057 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4058 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4059 {
4060 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4061 }
4062
4063 /**
4064 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4065 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4066 * @param TIMx Timer instance
4067 * @retval State of bit (1 or 0).
4068 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)4069 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4070 {
4071 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4072 }
4073
4074 /**
4075 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4076 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4077 * @param TIMx Timer instance
4078 * @retval None
4079 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4080 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4081 {
4082 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4083 }
4084
4085 /**
4086 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4087 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4088 * @param TIMx Timer instance
4089 * @retval State of bit (1 or 0).
4090 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)4091 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4092 {
4093 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4094 }
4095
4096 /**
4097 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4098 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4099 * @param TIMx Timer instance
4100 * @retval None
4101 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4102 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4103 {
4104 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4105 }
4106
4107 /**
4108 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4109 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4110 * @param TIMx Timer instance
4111 * @retval State of bit (1 or 0).
4112 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4113 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4114 {
4115 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4116 }
4117
4118 /**
4119 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4120 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4121 * @param TIMx Timer instance
4122 * @retval None
4123 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4124 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4125 {
4126 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4127 }
4128
4129 /**
4130 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4131 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4132 * @param TIMx Timer instance
4133 * @retval State of bit (1 or 0).
4134 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4135 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4136 {
4137 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4138 }
4139
4140 /**
4141 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4142 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4143 * @param TIMx Timer instance
4144 * @retval None
4145 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4146 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4147 {
4148 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4149 }
4150
4151 /**
4152 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4153 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4154 * @param TIMx Timer instance
4155 * @retval State of bit (1 or 0).
4156 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4157 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4158 {
4159 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4160 }
4161
4162 /**
4163 * @brief Clear the commutation interrupt flag (COMIF).
4164 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4165 * @param TIMx Timer instance
4166 * @retval None
4167 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4168 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4169 {
4170 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4171 }
4172
4173 /**
4174 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4175 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4176 * @param TIMx Timer instance
4177 * @retval State of bit (1 or 0).
4178 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)4179 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4180 {
4181 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4182 }
4183
4184 /**
4185 * @brief Clear the trigger interrupt flag (TIF).
4186 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4187 * @param TIMx Timer instance
4188 * @retval None
4189 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4190 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4191 {
4192 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4193 }
4194
4195 /**
4196 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4197 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4198 * @param TIMx Timer instance
4199 * @retval State of bit (1 or 0).
4200 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)4201 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
4202 {
4203 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4204 }
4205
4206 /**
4207 * @brief Clear the break interrupt flag (BIF).
4208 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4209 * @param TIMx Timer instance
4210 * @retval None
4211 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4212 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4213 {
4214 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4215 }
4216
4217 /**
4218 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4219 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4220 * @param TIMx Timer instance
4221 * @retval State of bit (1 or 0).
4222 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)4223 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
4224 {
4225 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4226 }
4227
4228 /**
4229 * @brief Clear the break 2 interrupt flag (B2IF).
4230 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4231 * @param TIMx Timer instance
4232 * @retval None
4233 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4234 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4235 {
4236 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4237 }
4238
4239 /**
4240 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4241 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4242 * @param TIMx Timer instance
4243 * @retval State of bit (1 or 0).
4244 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)4245 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
4246 {
4247 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4248 }
4249
4250 /**
4251 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4252 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4253 * @param TIMx Timer instance
4254 * @retval None
4255 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4256 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4257 {
4258 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4259 }
4260
4261 /**
4262 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
4263 * (Capture/Compare 1 interrupt is pending).
4264 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4265 * @param TIMx Timer instance
4266 * @retval State of bit (1 or 0).
4267 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)4268 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
4269 {
4270 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4271 }
4272
4273 /**
4274 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4275 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4276 * @param TIMx Timer instance
4277 * @retval None
4278 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4279 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4280 {
4281 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4282 }
4283
4284 /**
4285 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
4286 * (Capture/Compare 2 over-capture interrupt is pending).
4287 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4288 * @param TIMx Timer instance
4289 * @retval State of bit (1 or 0).
4290 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)4291 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4292 {
4293 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4294 }
4295
4296 /**
4297 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4298 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4299 * @param TIMx Timer instance
4300 * @retval None
4301 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4302 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4303 {
4304 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4305 }
4306
4307 /**
4308 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4309 * (Capture/Compare 3 over-capture interrupt is pending).
4310 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4311 * @param TIMx Timer instance
4312 * @retval State of bit (1 or 0).
4313 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4314 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4315 {
4316 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4317 }
4318
4319 /**
4320 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4321 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4322 * @param TIMx Timer instance
4323 * @retval None
4324 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4325 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4326 {
4327 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4328 }
4329
4330 /**
4331 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4332 * (Capture/Compare 4 over-capture interrupt is pending).
4333 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4334 * @param TIMx Timer instance
4335 * @retval State of bit (1 or 0).
4336 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4337 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4338 {
4339 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4340 }
4341
4342 /**
4343 * @brief Clear the system break interrupt flag (SBIF).
4344 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4345 * @param TIMx Timer instance
4346 * @retval None
4347 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4348 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4349 {
4350 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4351 }
4352
4353 /**
4354 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4355 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4356 * @param TIMx Timer instance
4357 * @retval State of bit (1 or 0).
4358 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)4359 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
4360 {
4361 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4362 }
4363
4364 /**
4365 * @}
4366 */
4367
4368 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4369 * @{
4370 */
4371 /**
4372 * @brief Enable update interrupt (UIE).
4373 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4374 * @param TIMx Timer instance
4375 * @retval None
4376 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4377 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4378 {
4379 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4380 }
4381
4382 /**
4383 * @brief Disable update interrupt (UIE).
4384 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4385 * @param TIMx Timer instance
4386 * @retval None
4387 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4388 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4389 {
4390 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4391 }
4392
4393 /**
4394 * @brief Indicates whether the update interrupt (UIE) is enabled.
4395 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4396 * @param TIMx Timer instance
4397 * @retval State of bit (1 or 0).
4398 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4399 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4400 {
4401 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4402 }
4403
4404 /**
4405 * @brief Enable capture/compare 1 interrupt (CC1IE).
4406 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4407 * @param TIMx Timer instance
4408 * @retval None
4409 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4410 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4411 {
4412 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4413 }
4414
4415 /**
4416 * @brief Disable capture/compare 1 interrupt (CC1IE).
4417 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4418 * @param TIMx Timer instance
4419 * @retval None
4420 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4421 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4422 {
4423 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4424 }
4425
4426 /**
4427 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4428 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4429 * @param TIMx Timer instance
4430 * @retval State of bit (1 or 0).
4431 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4432 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4433 {
4434 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4435 }
4436
4437 /**
4438 * @brief Enable capture/compare 2 interrupt (CC2IE).
4439 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4440 * @param TIMx Timer instance
4441 * @retval None
4442 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4443 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4444 {
4445 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4446 }
4447
4448 /**
4449 * @brief Disable capture/compare 2 interrupt (CC2IE).
4450 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4451 * @param TIMx Timer instance
4452 * @retval None
4453 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4454 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4455 {
4456 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4457 }
4458
4459 /**
4460 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4461 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4462 * @param TIMx Timer instance
4463 * @retval State of bit (1 or 0).
4464 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4465 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4466 {
4467 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4468 }
4469
4470 /**
4471 * @brief Enable capture/compare 3 interrupt (CC3IE).
4472 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4473 * @param TIMx Timer instance
4474 * @retval None
4475 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4476 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4477 {
4478 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4479 }
4480
4481 /**
4482 * @brief Disable capture/compare 3 interrupt (CC3IE).
4483 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4484 * @param TIMx Timer instance
4485 * @retval None
4486 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4487 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4488 {
4489 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4490 }
4491
4492 /**
4493 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4494 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4495 * @param TIMx Timer instance
4496 * @retval State of bit (1 or 0).
4497 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4498 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4499 {
4500 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4501 }
4502
4503 /**
4504 * @brief Enable capture/compare 4 interrupt (CC4IE).
4505 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4506 * @param TIMx Timer instance
4507 * @retval None
4508 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4509 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4510 {
4511 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4512 }
4513
4514 /**
4515 * @brief Disable capture/compare 4 interrupt (CC4IE).
4516 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4517 * @param TIMx Timer instance
4518 * @retval None
4519 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4520 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4521 {
4522 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4523 }
4524
4525 /**
4526 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4527 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4528 * @param TIMx Timer instance
4529 * @retval State of bit (1 or 0).
4530 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4531 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4532 {
4533 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4534 }
4535
4536 /**
4537 * @brief Enable commutation interrupt (COMIE).
4538 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4539 * @param TIMx Timer instance
4540 * @retval None
4541 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4542 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4543 {
4544 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4545 }
4546
4547 /**
4548 * @brief Disable commutation interrupt (COMIE).
4549 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4550 * @param TIMx Timer instance
4551 * @retval None
4552 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4553 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4554 {
4555 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4556 }
4557
4558 /**
4559 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4560 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4561 * @param TIMx Timer instance
4562 * @retval State of bit (1 or 0).
4563 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4564 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4565 {
4566 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4567 }
4568
4569 /**
4570 * @brief Enable trigger interrupt (TIE).
4571 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4572 * @param TIMx Timer instance
4573 * @retval None
4574 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4575 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4576 {
4577 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4578 }
4579
4580 /**
4581 * @brief Disable trigger interrupt (TIE).
4582 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4583 * @param TIMx Timer instance
4584 * @retval None
4585 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4586 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4587 {
4588 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4589 }
4590
4591 /**
4592 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4593 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4594 * @param TIMx Timer instance
4595 * @retval State of bit (1 or 0).
4596 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4597 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4598 {
4599 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4600 }
4601
4602 /**
4603 * @brief Enable break interrupt (BIE).
4604 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4605 * @param TIMx Timer instance
4606 * @retval None
4607 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4608 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4609 {
4610 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4611 }
4612
4613 /**
4614 * @brief Disable break interrupt (BIE).
4615 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4616 * @param TIMx Timer instance
4617 * @retval None
4618 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4619 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4620 {
4621 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4622 }
4623
4624 /**
4625 * @brief Indicates whether the break interrupt (BIE) is enabled.
4626 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4627 * @param TIMx Timer instance
4628 * @retval State of bit (1 or 0).
4629 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4630 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4631 {
4632 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4633 }
4634
4635 /**
4636 * @}
4637 */
4638
4639 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4640 * @{
4641 */
4642 /**
4643 * @brief Enable update DMA request (UDE).
4644 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4645 * @param TIMx Timer instance
4646 * @retval None
4647 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4648 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4649 {
4650 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4651 }
4652
4653 /**
4654 * @brief Disable update DMA request (UDE).
4655 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4656 * @param TIMx Timer instance
4657 * @retval None
4658 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4659 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4660 {
4661 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4662 }
4663
4664 /**
4665 * @brief Indicates whether the update DMA request (UDE) is enabled.
4666 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4667 * @param TIMx Timer instance
4668 * @retval State of bit (1 or 0).
4669 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4670 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4671 {
4672 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4673 }
4674
4675 /**
4676 * @brief Enable capture/compare 1 DMA request (CC1DE).
4677 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4678 * @param TIMx Timer instance
4679 * @retval None
4680 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4681 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4682 {
4683 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4684 }
4685
4686 /**
4687 * @brief Disable capture/compare 1 DMA request (CC1DE).
4688 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4689 * @param TIMx Timer instance
4690 * @retval None
4691 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4692 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4693 {
4694 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4695 }
4696
4697 /**
4698 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4699 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4700 * @param TIMx Timer instance
4701 * @retval State of bit (1 or 0).
4702 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4703 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4704 {
4705 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4706 }
4707
4708 /**
4709 * @brief Enable capture/compare 2 DMA request (CC2DE).
4710 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4711 * @param TIMx Timer instance
4712 * @retval None
4713 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4714 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4715 {
4716 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4717 }
4718
4719 /**
4720 * @brief Disable capture/compare 2 DMA request (CC2DE).
4721 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4722 * @param TIMx Timer instance
4723 * @retval None
4724 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4725 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4726 {
4727 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4728 }
4729
4730 /**
4731 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4732 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4733 * @param TIMx Timer instance
4734 * @retval State of bit (1 or 0).
4735 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4736 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4737 {
4738 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4739 }
4740
4741 /**
4742 * @brief Enable capture/compare 3 DMA request (CC3DE).
4743 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4744 * @param TIMx Timer instance
4745 * @retval None
4746 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4747 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4748 {
4749 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4750 }
4751
4752 /**
4753 * @brief Disable capture/compare 3 DMA request (CC3DE).
4754 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4755 * @param TIMx Timer instance
4756 * @retval None
4757 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4758 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4759 {
4760 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4761 }
4762
4763 /**
4764 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4765 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4766 * @param TIMx Timer instance
4767 * @retval State of bit (1 or 0).
4768 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)4769 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4770 {
4771 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4772 }
4773
4774 /**
4775 * @brief Enable capture/compare 4 DMA request (CC4DE).
4776 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4777 * @param TIMx Timer instance
4778 * @retval None
4779 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4780 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4781 {
4782 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4783 }
4784
4785 /**
4786 * @brief Disable capture/compare 4 DMA request (CC4DE).
4787 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4788 * @param TIMx Timer instance
4789 * @retval None
4790 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4791 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4792 {
4793 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4794 }
4795
4796 /**
4797 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4798 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4799 * @param TIMx Timer instance
4800 * @retval State of bit (1 or 0).
4801 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)4802 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4803 {
4804 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4805 }
4806
4807 /**
4808 * @brief Enable commutation DMA request (COMDE).
4809 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4810 * @param TIMx Timer instance
4811 * @retval None
4812 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4813 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4814 {
4815 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4816 }
4817
4818 /**
4819 * @brief Disable commutation DMA request (COMDE).
4820 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4821 * @param TIMx Timer instance
4822 * @retval None
4823 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4824 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4825 {
4826 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4827 }
4828
4829 /**
4830 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4831 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4832 * @param TIMx Timer instance
4833 * @retval State of bit (1 or 0).
4834 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)4835 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
4836 {
4837 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4838 }
4839
4840 /**
4841 * @brief Enable trigger interrupt (TDE).
4842 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4843 * @param TIMx Timer instance
4844 * @retval None
4845 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4846 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4847 {
4848 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4849 }
4850
4851 /**
4852 * @brief Disable trigger interrupt (TDE).
4853 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4854 * @param TIMx Timer instance
4855 * @retval None
4856 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4857 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4858 {
4859 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4860 }
4861
4862 /**
4863 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4864 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4865 * @param TIMx Timer instance
4866 * @retval State of bit (1 or 0).
4867 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)4868 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
4869 {
4870 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4871 }
4872
4873 /**
4874 * @}
4875 */
4876
4877 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4878 * @{
4879 */
4880 /**
4881 * @brief Generate an update event.
4882 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4883 * @param TIMx Timer instance
4884 * @retval None
4885 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4886 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4887 {
4888 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4889 }
4890
4891 /**
4892 * @brief Generate Capture/Compare 1 event.
4893 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4894 * @param TIMx Timer instance
4895 * @retval None
4896 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4897 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4898 {
4899 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4900 }
4901
4902 /**
4903 * @brief Generate Capture/Compare 2 event.
4904 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4905 * @param TIMx Timer instance
4906 * @retval None
4907 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4908 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4909 {
4910 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4911 }
4912
4913 /**
4914 * @brief Generate Capture/Compare 3 event.
4915 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4916 * @param TIMx Timer instance
4917 * @retval None
4918 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4919 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4920 {
4921 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4922 }
4923
4924 /**
4925 * @brief Generate Capture/Compare 4 event.
4926 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4927 * @param TIMx Timer instance
4928 * @retval None
4929 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4930 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4931 {
4932 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4933 }
4934
4935 /**
4936 * @brief Generate commutation event.
4937 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4938 * @param TIMx Timer instance
4939 * @retval None
4940 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4941 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4942 {
4943 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4944 }
4945
4946 /**
4947 * @brief Generate trigger event.
4948 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4949 * @param TIMx Timer instance
4950 * @retval None
4951 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4952 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4953 {
4954 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4955 }
4956
4957 /**
4958 * @brief Generate break event.
4959 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4960 * @param TIMx Timer instance
4961 * @retval None
4962 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4963 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4964 {
4965 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4966 }
4967
4968 /**
4969 * @brief Generate break 2 event.
4970 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4971 * @param TIMx Timer instance
4972 * @retval None
4973 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)4974 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4975 {
4976 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4977 }
4978
4979 /**
4980 * @}
4981 */
4982
4983 #if defined(USE_FULL_LL_DRIVER)
4984 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4985 * @{
4986 */
4987
4988 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
4989 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4990 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
4991 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4992 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4993 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4994 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4995 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4996 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4997 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4998 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4999 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5000 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5001 /**
5002 * @}
5003 */
5004 #endif /* USE_FULL_LL_DRIVER */
5005
5006 /**
5007 * @}
5008 */
5009
5010 /**
5011 * @}
5012 */
5013
5014 #endif /* TIM1 || TIM2 || TIM16 || TIM17 */
5015
5016 /**
5017 * @}
5018 */
5019
5020 #ifdef __cplusplus
5021 }
5022 #endif
5023
5024 #endif /* __STM32WBxx_LL_TIM_H */
5025
