1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBxx_LL_RCC_H
21 #define STM32WBxx_LL_RCC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbxx.h"
29
30 /** @addtogroup STM32WBxx_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35
36 /** @defgroup RCC_LL RCC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
43 * @{
44 */
45
46 #define HSE_CONTROL_UNLOCK_KEY 0xCAFECAFEU
47
48 /**
49 * @}
50 */
51
52 /* Private constants ---------------------------------------------------------*/
53 /* Private macros ------------------------------------------------------------*/
54 #if defined(USE_FULL_LL_DRIVER)
55 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
56 * @{
57 */
58 /**
59 * @}
60 */
61 #endif /* USE_FULL_LL_DRIVER */
62
63 /* Exported types ------------------------------------------------------------*/
64 #if defined(USE_FULL_LL_DRIVER)
65 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
66 * @{
67 */
68
69 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
70 * @{
71 */
72
73 /**
74 * @brief RCC Clocks Frequency Structure
75 */
76 typedef struct
77 {
78 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
79 uint32_t HCLK1_Frequency; /*!< HCLK1 clock frequency */
80 uint32_t HCLK2_Frequency; /*!< HCLK2 clock frequency */
81 uint32_t HCLK4_Frequency; /*!< HCLK4 clock frequency */
82 uint32_t HCLK5_Frequency; /*!< HCLK5 clock frequency */
83 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
84 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
85 } LL_RCC_ClocksTypeDef;
86
87 /**
88 * @}
89 */
90
91 /**
92 * @}
93 */
94 #endif /* USE_FULL_LL_DRIVER */
95
96 /* Exported constants --------------------------------------------------------*/
97 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
98 * @{
99 */
100
101 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
102 * @brief Defines used to adapt values of different oscillators
103 * @note These values could be modified in the user environment according to
104 * HW set-up.
105 * @{
106 */
107 #if !defined (HSE_VALUE)
108 #define HSE_VALUE 32000000U /*!< Value of the HSE oscillator in Hz */
109 #endif /* !HSE_VALUE */
110
111 #if !defined (HSI_VALUE)
112 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
113 #endif /* !HSI_VALUE */
114
115 #if !defined (LSE_VALUE)
116 #if defined(STM32WB5Mxx)
117 #define LSE_VALUE 32774U /*!< Value of the LSE oscillator in Hz */
118 #else
119 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
120 #endif /* STM32WB5Mxx */
121 #endif /* !LSE_VALUE */
122
123 #if !defined (LSI_VALUE)
124 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
125 #endif /* !LSI_VALUE */
126
127 #if defined(RCC_HSI48_SUPPORT)
128 #if !defined (HSI48_VALUE)
129 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
130 #endif /* !HSI48_VALUE */
131 #endif /* RCC_HSI48_SUPPORT */
132
133 /**
134 * @}
135 */
136
137 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
138 * @brief Flags defines which can be used with LL_RCC_WriteReg function
139 * @{
140 */
141 #define LL_RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC /*!< LSI1 Ready Interrupt Clear */
142 #define LL_RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC /*!< LSI1 Ready Interrupt Clear */
143 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
144 #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */
145 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
146 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
147 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
148 #if defined(RCC_HSI48_SUPPORT)
149 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
150 #endif /* RCC_HSI48_SUPPORT */
151 #if defined(SAI1)
152 #define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */
153 #endif /* SAI1 */
154 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
155 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
156 /**
157 * @}
158 */
159
160 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
161 * @brief Flags defines which can be used with LL_RCC_ReadReg function
162 * @{
163 */
164 #define LL_RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */
165 #define LL_RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */
166 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
167 #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
168 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
169 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
170 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
171 #if defined(RCC_HSI48_SUPPORT)
172 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
173 #endif /* RCC_HSI48_SUPPORT */
174 #if defined(SAI1)
175 #define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
176 #endif /* SAI1 */
177 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
178 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
179 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
180 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
181 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
182 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
183 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
184 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
185 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
186 /**
187 * @}
188 */
189
190 /** @defgroup RCC_LL_EC_IT IT Defines
191 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
192 * @{
193 */
194 #define LL_RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE /*!< LSI1 Ready Interrupt Enable */
195 #define LL_RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE /*!< LSI Ready Interrupt Enable */
196 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
197 #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */
198 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
199 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
200 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
201 #if defined(RCC_HSI48_SUPPORT)
202 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
203 #endif /* RCC_HSI48_SUPPORT */
204 #if defined(SAI1)
205 #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */
206 #endif /* SAI1 */
207 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
208 /**
209 * @}
210 */
211
212 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
213 * @{
214 */
215 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
216 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
217 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
218 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
219 /**
220 * @}
221 */
222
223 /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
224 * @{
225 */
226 #define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
227 #define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
228 #define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
229 #define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
230 #define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
231 #define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
232 #define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
233 #define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
234 #define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
235 #define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
236 #define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
237 #define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
238 /**
239 * @}
240 */
241
242
243 /** @defgroup RCC_LL_EC_HSE_CURRENT_CONTROL HSE current control max limits
244 * @{
245 */
246 #define LL_RCC_HSE_CURRENTMAX_0 0x000000000U /*!< HSE current control max limit = 0.18 ma/V*/
247 #define LL_RCC_HSE_CURRENTMAX_1 RCC_HSECR_HSEGMC0 /*!< HSE current control max limit = 0.57 ma/V*/
248 #define LL_RCC_HSE_CURRENTMAX_2 RCC_HSECR_HSEGMC1 /*!< HSE current control max limit = 0.78 ma/V*/
249 #define LL_RCC_HSE_CURRENTMAX_3 (RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 1.13 ma/V*/
250 #define LL_RCC_HSE_CURRENTMAX_4 RCC_HSECR_HSEGMC2 /*!< HSE current control max limit = 0.61 ma/V*/
251 #define LL_RCC_HSE_CURRENTMAX_5 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 1.65 ma/V*/
252 #define LL_RCC_HSE_CURRENTMAX_6 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1) /*!< HSE current control max limit = 2.12 ma/V*/
253 #define LL_RCC_HSE_CURRENTMAX_7 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 2.84 ma/V*/
254 /**
255 * @}
256 */
257
258 /** @defgroup RCC_LL_EC_HSE_SENSE_AMPLIFIER HSE sense amplifier threshold
259 * @{
260 */
261 #define LL_RCC_HSEAMPTHRESHOLD_1_2 (0x000000000U) /*!< HSE sense amplifier bias current factor = 1/2*/
262 #define LL_RCC_HSEAMPTHRESHOLD_3_4 RCC_HSECR_HSES /*!< HSE sense amplifier bias current factor = 3/4*/
263 /**
264 * @}
265 */
266
267 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
268 * @{
269 */
270 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
271 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
272 /**
273 * @}
274 */
275
276 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
277 * @{
278 */
279 #define LL_RCC_SYS_CLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */
280 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */
281 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */
282 #define LL_RCC_SYS_CLKSOURCE_PLL (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< PLL selection as system clock */
283 /**
284 * @}
285 */
286
287 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
288 * @{
289 */
290 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */
291 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */
292 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */
293 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< PLL used as system clock */
294 /**
295 * @}
296 */
297
298 /** @defgroup RCC_LL_EC_RF_CLKSOURCE_STATUS RF system clock switch status
299 * @{
300 */
301 #define LL_RCC_RF_CLKSOURCE_HSI 0x00000000U /*!< HSI used as RF system clock */
302 #define LL_RCC_RF_CLKSOURCE_HSE_DIV2 RCC_EXTCFGR_RFCSS /*!< HSE divided by 2 used as RF system clock */
303 /**
304 * @}
305 */
306
307 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
308 * @{
309 */
310 #define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */
311 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */
312 #define LL_RCC_SYSCLK_DIV_3 RCC_CFGR_HPRE_0 /*!< SYSCLK divided by 3 */
313 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */
314 #define LL_RCC_SYSCLK_DIV_5 RCC_CFGR_HPRE_1 /*!< SYSCLK divided by 5 */
315 #define LL_RCC_SYSCLK_DIV_6 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 6 */
316 #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */
317 #define LL_RCC_SYSCLK_DIV_10 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 10 */
318 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */
319 #define LL_RCC_SYSCLK_DIV_32 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 32 */
320 #define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */
321 #define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */
322 #define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */
323 #define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */
324 /**
325 * @}
326 */
327
328 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
329 * @{
330 */
331 #define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK1 not divided */
332 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_2 /*!< HCLK1 divided by 2 */
333 #define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 4 */
334 #define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1) /*!< HCLK1 divided by 8 */
335 #define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 16 */
336 /**
337 * @}
338 */
339
340 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
341 * @{
342 */
343 #define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK1 not divided */
344 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_2 /*!< HCLK1 divided by 2 */
345 #define LL_RCC_APB2_DIV_4 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 4 */
346 #define LL_RCC_APB2_DIV_8 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1) /*!< HCLK1 divided by 8 */
347 #define LL_RCC_APB2_DIV_16 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 16 */
348 /**
349 * @}
350 */
351
352 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
353 * @{
354 */
355 #define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */
356 #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
357 /**
358 * @}
359 */
360
361 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
362 * @{
363 */
364 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
365 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
366 #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
367 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
368 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE after stabilization selection as MCO1 source */
369 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
370 #define LL_RCC_MCO1SOURCE_LSI1 (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI1 selection as MCO1 source */
371 #define LL_RCC_MCO1SOURCE_LSI2 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI2 selection as MCO1 source */
372 #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_3 /*!< LSE selection as MCO1 source */
373 #if defined(RCC_HSI48_SUPPORT)
374 #define LL_RCC_MCO1SOURCE_HSI48 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_3) /*!< HSI48 selection as MCO1 source */
375 #endif /* RCC_HSI48_SUPPORT */
376 #define LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB (RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3) /*!< HSE before stabilization selection as MCO1 source */
377 /**
378 * @}
379 */
380
381 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
382 * @{
383 */
384 #define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO not divided */
385 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */
386 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */
387 #define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */
388 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */
389 /**
390 * @}
391 */
392
393 #if defined(RCC_SMPS_SUPPORT)
394 /** @defgroup RCC_LL_EC_SMPS_CLKSOURCE SMPS clock switch
395 * @{
396 */
397 #define LL_RCC_SMPS_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as SMPS clock */
398 #define LL_RCC_SMPS_CLKSOURCE_MSI RCC_SMPSCR_SMPSSEL_0 /*!< MSI selection as SMPS clock */
399 #define LL_RCC_SMPS_CLKSOURCE_HSE RCC_SMPSCR_SMPSSEL_1 /*!< HSE selection as SMPS clock */
400 /**
401 * @}
402 */
403
404 /** @defgroup RCC_LL_EC_SMPS_CLKSOURCE_STATUS SMPS clock switch status
405 * @{
406 */
407 #define LL_RCC_SMPS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as SMPS clock */
408 #define LL_RCC_SMPS_CLKSOURCE_STATUS_MSI RCC_SMPSCR_SMPSSWS_0 /*!< MSI used as SMPS clock */
409 #define LL_RCC_SMPS_CLKSOURCE_STATUS_HSE RCC_SMPSCR_SMPSSWS_1 /*!< HSE used as SMPS clock */
410 #define LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK (RCC_SMPSCR_SMPSSWS_0|RCC_SMPSCR_SMPSSWS_1) /*!< No Clock used as SMPS clock */
411 /**
412 * @}
413 */
414
415 /** @defgroup RCC_LL_EC_SMPS_DIV SMPS prescaler
416 * @{
417 */
418 #define LL_RCC_SMPS_DIV_0 (0x00000000U) /*!< SMPS clock division 0 */
419 #define LL_RCC_SMPS_DIV_1 RCC_SMPSCR_SMPSDIV_0 /*!< SMPS clock division 1 */
420 #define LL_RCC_SMPS_DIV_2 RCC_SMPSCR_SMPSDIV_1 /*!< SMPS clock division 2 */
421 #define LL_RCC_SMPS_DIV_3 (RCC_SMPSCR_SMPSDIV_0|RCC_SMPSCR_SMPSDIV_1) /*!< SMPS clock division 3 */
422 /**
423 * @}
424 */
425 #endif /* RCC_SMPS_SUPPORT */
426
427 #if defined(USE_FULL_LL_DRIVER)
428 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
429 * @{
430 */
431 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
432 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
433 /**
434 * @}
435 */
436 #endif /* USE_FULL_LL_DRIVER */
437
438 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE USART1 CLKSOURCE
439 * @{
440 */
441 #define LL_RCC_USART1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 selected as USART1 clock */
442 #define LL_RCC_USART1_CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 /*!< SYSCLK selected as USART1 clock */
443 #define LL_RCC_USART1_CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 /*!< HSI selected as USART1 clock */
444 #define LL_RCC_USART1_CLKSOURCE_LSE RCC_CCIPR_USART1SEL /*!< LSE selected as USART1 clock */
445 /**
446 * @}
447 */
448
449 #if defined(LPUART1)
450 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE LPUART1 CLKSOURCE
451 * @{
452 */
453 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 selected as LPUART1 clock */
454 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYCLK selected as LPUART1 clock */
455 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI selected as LPUART1 clock */
456 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE selected as LPUART1 clock */
457 /**
458 * @}
459 */
460 #endif /* LPUART1 */
461
462 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE I2Cx CLKSOURCE
463 * @{
464 */
465 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C1 clock */
466 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4)) /*!< SYSCLK selected as I2C1 clock */
467 #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4)) /*!< HSI selected as I2C1 clock */
468 #if defined(I2C3)
469 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C3 clock */
470 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4)) /*!< SYSCLK selected as I2C3 clock */
471 #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4)) /*!< HSI selected as I2C3 clock */
472 #endif /* I2C3 */
473 /**
474 * @}
475 */
476
477 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE LPTIMx CLKSOURCE
478 * @{
479 */
480 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM1 clock */
481 #define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16)) /*!< LSI selected as LPTIM1 clock */
482 #define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16)) /*!< HSI selected as LPTIM1 clock */
483 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16)) /*!< LSE selected as LPTIM1 clock */
484 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM2 clock */
485 #define LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16)) /*!< LSI selected as LPTIM2 clock */
486 #define LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16)) /*!< HSI selected as LPTIM2 clock */
487 #define LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16)) /*!< LSE selected as LPTIM2 clock */
488 /**
489 * @}
490 */
491
492 #if defined(SAI1)
493 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE SAI1 CLKSOURCE
494 * @{
495 */
496 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 0x00000000U /*!< PLLSAI1 selected as SAI1 clock */
497 #define LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 /*!< PLL selected as SAI1 clock */
498 #define LL_RCC_SAI1_CLKSOURCE_HSI RCC_CCIPR_SAI1SEL_1 /*!< HSI selected as SAI1 clock */
499 #define LL_RCC_SAI1_CLKSOURCE_PIN RCC_CCIPR_SAI1SEL /*!< External input selected as SAI1 clock */
500 /**
501 * @}
502 */
503 #endif /* SAI1 */
504
505 /** @defgroup RCC_LL_EC_CLK48_CLKSOURCE CLK48 CLKSOURCE
506 * @{
507 */
508 #if defined(RCC_HSI48_SUPPORT)
509 #define LL_RCC_CLK48_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 selected as CLK48 clock */
510 #endif /* RCC_HSI48_SUPPORT */
511 #if defined(SAI1)
512 #define LL_RCC_CLK48_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 selected as CLK48 clock */
513 #endif /* SAI1 */
514 #define LL_RCC_CLK48_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL selected as CLK48 clock */
515 #define LL_RCC_CLK48_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI selected as CLK48 clock */
516 /**
517 * @}
518 */
519
520 /** @defgroup RCC_LL_EC_USB_CLKSOURCE USB CLKSOURCE
521 * @{
522 */
523 #if defined(RCC_HSI48_SUPPORT)
524 #define LL_RCC_USB_CLKSOURCE_HSI48 LL_RCC_CLK48_CLKSOURCE_HSI48 /*!< HSI48 selected as USB clock */
525 #endif /* RCC_HSI48_SUPPORT */
526 #if defined(SAI1)
527 #define LL_RCC_USB_CLKSOURCE_PLLSAI1 LL_RCC_CLK48_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 selected as USB clock */
528 #endif /* SAI1 */
529 #define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CLK48_CLKSOURCE_PLL /*!< PLL selected as USB clock */
530 #define LL_RCC_USB_CLKSOURCE_MSI LL_RCC_CLK48_CLKSOURCE_MSI /*!< MSI selected as USB clock */
531 /**
532 * @}
533 */
534
535 /** @defgroup RCC_LL_EC_ADC_CLKSRC ADC CLKSRC
536 * @{
537 */
538 #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as ADC clock*/
539 #if defined(STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
540 #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 selected as ADC clock*/
541 #elif defined (STM32WB15xx) || defined(STM32WB1Mxx)
542 #define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_0 /*!< HSI selected as ADC clock */
543 #endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx */
544 #define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock */
545 #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock */
546 /**
547 * @}
548 */
549
550 /** @defgroup RCC_LL_EC_RNG_CLKSRC RNG CLKSRC
551 * @{
552 */
553 #define LL_RCC_RNG_CLKSOURCE_CLK48 0x00000000U /*!< CLK48 divided by 3 selected as RNG Clock */
554 #define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0 /*!< LSI selected as ADC clock */
555 #define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1 /*!< LSE selected as ADC clock */
556 /**
557 * @}
558 */
559
560
561 /** @defgroup RCC_LL_EC_USART1 USART1
562 * @{
563 */
564 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 clock source selection bits */
565 /**
566 * @}
567 */
568
569 #if defined(LPUART1)
570 /** @defgroup RCC_LL_EC_LPUART1 LPUART1
571 * @{
572 */
573 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 clock source selection bits */
574 /**
575 * @}
576 */
577 #endif /* LPUART1 */
578
579 /** @defgroup RCC_LL_EC_I2C1 I2C1
580 * @{
581 */
582 #define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 clock source selection bits */
583 #define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL /*!< I2C3 clock source selection bits */
584 /**
585 * @}
586 */
587
588 /** @defgroup RCC_LL_EC_LPTIM1 LPTIM1
589 * @{
590 */
591 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 clock source selection bits */
592 #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 clock source selection bits */
593 /**
594 * @}
595 */
596
597 #if defined(SAI1)
598 /** @defgroup RCC_LL_EC_SAI1 SAI1
599 * @{
600 */
601 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 clock source selection bits */
602 /**
603 * @}
604 */
605 #endif /* SAI1 */
606
607 /** @defgroup RCC_LL_EC_CLK48 CLK48
608 * @{
609 */
610 #define LL_RCC_CLK48_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< CLK48 clock source selection bits */
611 /**
612 * @}
613 */
614
615 /** @defgroup RCC_LL_EC_USB USB
616 * @{
617 */
618 #define LL_RCC_USB_CLKSOURCE LL_RCC_CLK48_CLKSOURCE /*!< USB clock source selection bits */
619 /**
620 * @}
621 */
622
623 /** @defgroup RCC_LL_EC_RNG RNG
624 * @{
625 */
626 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL /*!< RNG clock source selection bits */
627 /**
628 * @}
629 */
630
631 /** @defgroup RCC_LL_EC_ADC ADC
632 * @{
633 */
634 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC clock source selection bits */
635 /**
636 * @}
637 */
638
639
640 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
641 * @{
642 */
643 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
644 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
645 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
646 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
647
648 /**
649 * @}
650 */
651
652 /** @defgroup RCC_LL_EC_RFWKP_CLKSOURCE RF Wakeup clock source selection
653 * @{
654 */
655 #define LL_RCC_RFWKP_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RF Wakeup clock */
656 #define LL_RCC_RFWKP_CLKSOURCE_LSE RCC_CSR_RFWKPSEL_0 /*!< LSE oscillator clock used as RF Wakeup clock */
657 #if defined(STM32WB15xx) || defined(STM32WB10xx)
658 #define LL_RCC_RFWKP_CLKSOURCE_LSI RCC_CSR_RFWKPSEL_1 /*!< LSI oscillator clock used as RF Wakeup clock */
659 #endif /* STM32WB15xx || STM32WB10xx */
660 #define LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 RCC_CSR_RFWKPSEL /*!< HSE oscillator clock divided by 1024 used as RF Wakeup clock */
661
662 /**
663 * @}
664 */
665
666
667 /** @defgroup RCC_LL_EC_PLLSOURCE PLL and PLLSAI1 entry clock source
668 * @{
669 */
670 #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
671 #define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as PLL entry clock source */
672 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI clock selected as PLL entry clock source */
673 #define LL_RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0) /*!< HSE clock selected as PLL entry clock source */
674 /**
675 * @}
676 */
677
678 /** @defgroup RCC_LL_EC_PLLM_DIV PLL and PLLSAI1 division factor
679 * @{
680 */
681 #define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL and PLLSAI1 division factor by 1 */
682 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLSAI1 division factor by 2 */
683 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLSAI1 division factor by 3 */
684 #define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL and PLLSAI1 division factor by 4 */
685 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLSAI1 division factor by 5 */
686 #define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL and PLLSAI1 division factor by 6 */
687 #define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL and PLLSAI1 division factor by 7 */
688 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< PLL and PLLSAI1 division factor by 8 */
689 /**
690 * @}
691 */
692
693 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
694 * @{
695 */
696 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
697 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
698 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
699 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
700 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
701 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
702 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
703 /**
704 * @}
705 */
706
707 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
708 * @{
709 */
710 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */
711 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */
712 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */
713 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */
714 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */
715 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */
716 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */
717 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */
718 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */
719 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */
720 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */
721 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */
722 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */
723 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */
724 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 16 */
725 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */
726 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */
727 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */
728 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */
729 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */
730 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */
731 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */
732 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 24 */
733 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */
734 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */
735 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27 */
736 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 28 */
737 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */
738 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 30 */
739 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 31 */
740 #define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 32 */
741 /**
742 * @}
743 */
744
745 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
746 * @{
747 */
748 #define LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 2 */
749 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 3 */
750 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
751 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 5 */
752 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 6 */
753 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 7 */
754 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
755 /**
756 * @}
757 */
758
759
760 #if defined(SAI1)
761 /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLQ)
762 * @{
763 */
764 #define LL_RCC_PLLSAI1Q_DIV_2 (RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */
765 #define LL_RCC_PLLSAI1Q_DIV_3 (RCC_PLLSAI1CFGR_PLLQ_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 3 */
766 #define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */
767 #define LL_RCC_PLLSAI1Q_DIV_5 (RCC_PLLSAI1CFGR_PLLQ_2) /*!< PLLSAI1 division factor for PLLSAI1Q output by 5 */
768 #define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */
769 #define LL_RCC_PLLSAI1Q_DIV_7 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 7 */
770 #define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */
771 /**
772 * @}
773 */
774
775 /** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLP)
776 * @{
777 */
778 #define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */
779 #define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */
780 #define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */
781 #define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */
782 #define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */
783 #define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */
784 #define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */
785 #define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */
786 #define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */
787 #define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */
788 #define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */
789 #define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */
790 #define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */
791 #define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */
792 #define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 16 */
793 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */
794 #define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */
795 #define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */
796 #define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */
797 #define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */
798 #define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */
799 #define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */
800 #define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 24 */
801 #define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */
802 #define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */
803 #define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27*/
804 #define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 28 */
805 #define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */
806 #define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 30 */
807 #define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 31 */
808 #define LL_RCC_PLLSAI1P_DIV_32 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 32 */
809 /**
810 * @}
811 */
812
813 /** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLR)
814 * @{
815 */
816 #define LL_RCC_PLLSAI1R_DIV_2 (RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */
817 #define LL_RCC_PLLSAI1R_DIV_3 (RCC_PLLSAI1CFGR_PLLR_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 3 */
818 #define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */
819 #define LL_RCC_PLLSAI1R_DIV_5 (RCC_PLLSAI1CFGR_PLLR_2) /*!< PLLSAI1 division factor for PLLSAI1R output by 5 */
820 #define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */
821 #define LL_RCC_PLLSAI1R_DIV_7 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 7 */
822 #define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */
823 /**
824 * @}
825 */
826 #endif /* SAI1 */
827
828 /**
829 * @}
830 */
831
832 /* Exported macro ------------------------------------------------------------*/
833 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
834 * @{
835 */
836
837 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
838 * @{
839 */
840
841 /**
842 * @brief Write a value in RCC register
843 * @param __REG__ Register to be written
844 * @param __VALUE__ Value to be written in the register
845 * @retval None
846 */
847 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
848
849 /**
850 * @brief Read a value in RCC register
851 * @param __REG__ Register to be read
852 * @retval Register value
853 */
854 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
855 /**
856 * @}
857 */
858
859 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
860 * @{
861 */
862
863 /**
864 * @brief Helper macro to calculate the PLLRCLK frequency on system domain
865 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
866 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
867 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
868 * @param __PLLM__ This parameter can be one of the following values:
869 * @arg @ref LL_RCC_PLLM_DIV_1
870 * @arg @ref LL_RCC_PLLM_DIV_2
871 * @arg @ref LL_RCC_PLLM_DIV_3
872 * @arg @ref LL_RCC_PLLM_DIV_4
873 * @arg @ref LL_RCC_PLLM_DIV_5
874 * @arg @ref LL_RCC_PLLM_DIV_6
875 * @arg @ref LL_RCC_PLLM_DIV_7
876 * @arg @ref LL_RCC_PLLM_DIV_8
877 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
878 * @param __PLLR__ This parameter can be one of the following values:
879 * @arg @ref LL_RCC_PLLR_DIV_2
880 * @arg @ref LL_RCC_PLLR_DIV_3
881 * @arg @ref LL_RCC_PLLR_DIV_4
882 * @arg @ref LL_RCC_PLLR_DIV_5
883 * @arg @ref LL_RCC_PLLR_DIV_6
884 * @arg @ref LL_RCC_PLLR_DIV_7
885 * @arg @ref LL_RCC_PLLR_DIV_8
886 * @retval PLL clock frequency (in Hz)
887 */
888 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
889 (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U))
890
891 #if defined(SAI1)
892 /**
893 * @brief Helper macro to calculate the PLLPCLK frequency used on SAI domain
894 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
895 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
896 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
897 * @param __PLLM__ This parameter can be one of the following values:
898 * @arg @ref LL_RCC_PLLM_DIV_1
899 * @arg @ref LL_RCC_PLLM_DIV_2
900 * @arg @ref LL_RCC_PLLM_DIV_3
901 * @arg @ref LL_RCC_PLLM_DIV_4
902 * @arg @ref LL_RCC_PLLM_DIV_5
903 * @arg @ref LL_RCC_PLLM_DIV_6
904 * @arg @ref LL_RCC_PLLM_DIV_7
905 * @arg @ref LL_RCC_PLLM_DIV_8
906 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
907 * @param __PLLP__ This parameter can be one of the following values:
908 * @arg @ref LL_RCC_PLLP_DIV_2
909 * @arg @ref LL_RCC_PLLP_DIV_3
910 * @arg @ref LL_RCC_PLLP_DIV_4
911 * @arg @ref LL_RCC_PLLP_DIV_5
912 * @arg @ref LL_RCC_PLLP_DIV_6
913 * @arg @ref LL_RCC_PLLP_DIV_7
914 * @arg @ref LL_RCC_PLLP_DIV_8
915 * @arg @ref LL_RCC_PLLP_DIV_9
916 * @arg @ref LL_RCC_PLLP_DIV_10
917 * @arg @ref LL_RCC_PLLP_DIV_11
918 * @arg @ref LL_RCC_PLLP_DIV_12
919 * @arg @ref LL_RCC_PLLP_DIV_13
920 * @arg @ref LL_RCC_PLLP_DIV_14
921 * @arg @ref LL_RCC_PLLP_DIV_15
922 * @arg @ref LL_RCC_PLLP_DIV_16
923 * @arg @ref LL_RCC_PLLP_DIV_17
924 * @arg @ref LL_RCC_PLLP_DIV_18
925 * @arg @ref LL_RCC_PLLP_DIV_19
926 * @arg @ref LL_RCC_PLLP_DIV_20
927 * @arg @ref LL_RCC_PLLP_DIV_21
928 * @arg @ref LL_RCC_PLLP_DIV_22
929 * @arg @ref LL_RCC_PLLP_DIV_23
930 * @arg @ref LL_RCC_PLLP_DIV_24
931 * @arg @ref LL_RCC_PLLP_DIV_25
932 * @arg @ref LL_RCC_PLLP_DIV_26
933 * @arg @ref LL_RCC_PLLP_DIV_27
934 * @arg @ref LL_RCC_PLLP_DIV_28
935 * @arg @ref LL_RCC_PLLP_DIV_29
936 * @arg @ref LL_RCC_PLLP_DIV_30
937 * @arg @ref LL_RCC_PLLP_DIV_31
938 * @retval PLL clock frequency (in Hz)
939 */
940 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U))/ \
941 (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
942 #endif /* SAI1 */
943
944 /**
945 * @brief Helper macro to calculate the PLLPCLK frequency used on ADC domain
946 * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
947 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
948 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
949 * @param __PLLM__ This parameter can be one of the following values:
950 * @arg @ref LL_RCC_PLLM_DIV_1
951 * @arg @ref LL_RCC_PLLM_DIV_2
952 * @arg @ref LL_RCC_PLLM_DIV_3
953 * @arg @ref LL_RCC_PLLM_DIV_4
954 * @arg @ref LL_RCC_PLLM_DIV_5
955 * @arg @ref LL_RCC_PLLM_DIV_6
956 * @arg @ref LL_RCC_PLLM_DIV_7
957 * @arg @ref LL_RCC_PLLM_DIV_8
958 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
959 * @param __PLLP__ This parameter can be one of the following values:
960 * @arg @ref LL_RCC_PLLP_DIV_2
961 * @arg @ref LL_RCC_PLLP_DIV_3
962 * @arg @ref LL_RCC_PLLP_DIV_4
963 * @arg @ref LL_RCC_PLLP_DIV_5
964 * @arg @ref LL_RCC_PLLP_DIV_6
965 * @arg @ref LL_RCC_PLLP_DIV_7
966 * @arg @ref LL_RCC_PLLP_DIV_8
967 * @arg @ref LL_RCC_PLLP_DIV_9
968 * @arg @ref LL_RCC_PLLP_DIV_10
969 * @arg @ref LL_RCC_PLLP_DIV_11
970 * @arg @ref LL_RCC_PLLP_DIV_12
971 * @arg @ref LL_RCC_PLLP_DIV_13
972 * @arg @ref LL_RCC_PLLP_DIV_14
973 * @arg @ref LL_RCC_PLLP_DIV_15
974 * @arg @ref LL_RCC_PLLP_DIV_16
975 * @arg @ref LL_RCC_PLLP_DIV_17
976 * @arg @ref LL_RCC_PLLP_DIV_18
977 * @arg @ref LL_RCC_PLLP_DIV_19
978 * @arg @ref LL_RCC_PLLP_DIV_20
979 * @arg @ref LL_RCC_PLLP_DIV_21
980 * @arg @ref LL_RCC_PLLP_DIV_22
981 * @arg @ref LL_RCC_PLLP_DIV_23
982 * @arg @ref LL_RCC_PLLP_DIV_24
983 * @arg @ref LL_RCC_PLLP_DIV_25
984 * @arg @ref LL_RCC_PLLP_DIV_26
985 * @arg @ref LL_RCC_PLLP_DIV_27
986 * @arg @ref LL_RCC_PLLP_DIV_28
987 * @arg @ref LL_RCC_PLLP_DIV_29
988 * @arg @ref LL_RCC_PLLP_DIV_30
989 * @arg @ref LL_RCC_PLLP_DIV_31
990 * @arg @ref LL_RCC_PLLP_DIV_32
991 * @retval PLL clock frequency (in Hz)
992 */
993 #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
994 (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
995
996
997 /**
998 * @brief Helper macro to calculate the PLLQCLK frequency used on 48M domain
999 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1000 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1001 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1002 * @param __PLLM__ This parameter can be one of the following values:
1003 * @arg @ref LL_RCC_PLLM_DIV_1
1004 * @arg @ref LL_RCC_PLLM_DIV_2
1005 * @arg @ref LL_RCC_PLLM_DIV_3
1006 * @arg @ref LL_RCC_PLLM_DIV_4
1007 * @arg @ref LL_RCC_PLLM_DIV_5
1008 * @arg @ref LL_RCC_PLLM_DIV_6
1009 * @arg @ref LL_RCC_PLLM_DIV_7
1010 * @arg @ref LL_RCC_PLLM_DIV_8
1011 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
1012 * @param __PLLQ__ This parameter can be one of the following values:
1013 * @arg @ref LL_RCC_PLLQ_DIV_2
1014 * @arg @ref LL_RCC_PLLQ_DIV_3
1015 * @arg @ref LL_RCC_PLLQ_DIV_4
1016 * @arg @ref LL_RCC_PLLQ_DIV_5
1017 * @arg @ref LL_RCC_PLLQ_DIV_6
1018 * @arg @ref LL_RCC_PLLQ_DIV_7
1019 * @arg @ref LL_RCC_PLLQ_DIV_8
1020 * @retval PLL clock frequency (in Hz)
1021 */
1022 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1023 (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
1024
1025 #if defined(SAI1)
1026 /**
1027 * @brief Helper macro to calculate the PLLSAI1PCLK frequency used for SAI domain
1028 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1029 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
1030 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1031 * @param __PLLM__ This parameter can be one of the following values:
1032 * @arg @ref LL_RCC_PLLM_DIV_1
1033 * @arg @ref LL_RCC_PLLM_DIV_2
1034 * @arg @ref LL_RCC_PLLM_DIV_3
1035 * @arg @ref LL_RCC_PLLM_DIV_4
1036 * @arg @ref LL_RCC_PLLM_DIV_5
1037 * @arg @ref LL_RCC_PLLM_DIV_6
1038 * @arg @ref LL_RCC_PLLM_DIV_7
1039 * @arg @ref LL_RCC_PLLM_DIV_8
1040 * @param __PLLSAI1N__ Between 6 and 127
1041 * @param __PLLSAI1P__ This parameter can be one of the following values:
1042 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
1043 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
1044 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
1045 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
1046 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
1047 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
1048 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
1049 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
1050 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
1051 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
1052 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
1053 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
1054 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
1055 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
1056 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
1057 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
1058 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
1059 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
1060 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
1061 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
1062 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
1063 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
1064 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
1065 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
1066 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
1067 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
1068 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
1069 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
1070 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
1071 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
1072 * @arg @ref LL_RCC_PLLSAI1P_DIV_32
1073 * @retval PLLSAI1 clock frequency (in Hz)
1074 */
1075 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
1076 ((__INPUTFREQ__) * (__PLLSAI1N__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1077 (((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLP_Pos) + 1U))
1078
1079 /**
1080 * @brief Helper macro to calculate the PLLSAI1QCLK frequency used on 48M domain
1081 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1082 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
1083 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1084 * @param __PLLM__ This parameter can be one of the following values:
1085 * @arg @ref LL_RCC_PLLM_DIV_1
1086 * @arg @ref LL_RCC_PLLM_DIV_2
1087 * @arg @ref LL_RCC_PLLM_DIV_3
1088 * @arg @ref LL_RCC_PLLM_DIV_4
1089 * @arg @ref LL_RCC_PLLM_DIV_5
1090 * @arg @ref LL_RCC_PLLM_DIV_6
1091 * @arg @ref LL_RCC_PLLM_DIV_7
1092 * @arg @ref LL_RCC_PLLM_DIV_8
1093 * @param __PLLSAI1N__ Between 6 and 127
1094 * @param __PLLSAI1Q__ This parameter can be one of the following values:
1095 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
1096 * @arg @ref LL_RCC_PLLSAI1Q_DIV_3
1097 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
1098 * @arg @ref LL_RCC_PLLSAI1Q_DIV_5
1099 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
1100 * @arg @ref LL_RCC_PLLSAI1Q_DIV_7
1101 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
1102 * @retval PLLSAI1 clock frequency (in Hz)
1103 */
1104 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \
1105 ((__INPUTFREQ__) * (__PLLSAI1N__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1106 (((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLQ_Pos) + 1U))
1107
1108 /**
1109 * @brief Helper macro to calculate the PLLSAI1RCLK frequency used on ADC domain
1110 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1111 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
1112 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1113 * @param __PLLM__ This parameter can be one of the following values:
1114 * @arg @ref LL_RCC_PLLM_DIV_1
1115 * @arg @ref LL_RCC_PLLM_DIV_2
1116 * @arg @ref LL_RCC_PLLM_DIV_3
1117 * @arg @ref LL_RCC_PLLM_DIV_4
1118 * @arg @ref LL_RCC_PLLM_DIV_5
1119 * @arg @ref LL_RCC_PLLM_DIV_6
1120 * @arg @ref LL_RCC_PLLM_DIV_7
1121 * @arg @ref LL_RCC_PLLM_DIV_8
1122 * @param __PLLSAI1N__ Between 6 and 127
1123 * @param __PLLSAI1R__ This parameter can be one of the following values:
1124 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
1125 * @arg @ref LL_RCC_PLLSAI1R_DIV_3
1126 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
1127 * @arg @ref LL_RCC_PLLSAI1R_DIV_5
1128 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
1129 * @arg @ref LL_RCC_PLLSAI1R_DIV_7
1130 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
1131 * @retval PLLSAI1 clock frequency (in Hz)
1132 */
1133 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \
1134 ((__INPUTFREQ__) * (__PLLSAI1N__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1135 (((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLR_Pos) + 1U))
1136 #endif /* SAI1 */
1137
1138 /**
1139 * @brief Helper macro to calculate the HCLK1 frequency
1140 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
1141 * @param __CPU1PRESCALER__ This parameter can be one of the following values:
1142 * @arg @ref LL_RCC_SYSCLK_DIV_1
1143 * @arg @ref LL_RCC_SYSCLK_DIV_2
1144 * @arg @ref LL_RCC_SYSCLK_DIV_3
1145 * @arg @ref LL_RCC_SYSCLK_DIV_4
1146 * @arg @ref LL_RCC_SYSCLK_DIV_5
1147 * @arg @ref LL_RCC_SYSCLK_DIV_6
1148 * @arg @ref LL_RCC_SYSCLK_DIV_8
1149 * @arg @ref LL_RCC_SYSCLK_DIV_10
1150 * @arg @ref LL_RCC_SYSCLK_DIV_16
1151 * @arg @ref LL_RCC_SYSCLK_DIV_32
1152 * @arg @ref LL_RCC_SYSCLK_DIV_64
1153 * @arg @ref LL_RCC_SYSCLK_DIV_128
1154 * @arg @ref LL_RCC_SYSCLK_DIV_256
1155 * @arg @ref LL_RCC_SYSCLK_DIV_512
1156 * @retval HCLK1 clock frequency (in Hz)
1157 */
1158 #define __LL_RCC_CALC_HCLK1_FREQ(__SYSCLKFREQ__,__CPU1PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU1PRESCALER__)\
1159 & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
1160
1161 /**
1162 * @brief Helper macro to calculate the HCLK2 frequency
1163 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
1164 * @param __CPU2PRESCALER__ This parameter can be one of the following values:
1165 * @arg @ref LL_RCC_SYSCLK_DIV_1
1166 * @arg @ref LL_RCC_SYSCLK_DIV_2
1167 * @arg @ref LL_RCC_SYSCLK_DIV_3
1168 * @arg @ref LL_RCC_SYSCLK_DIV_4
1169 * @arg @ref LL_RCC_SYSCLK_DIV_5
1170 * @arg @ref LL_RCC_SYSCLK_DIV_6
1171 * @arg @ref LL_RCC_SYSCLK_DIV_8
1172 * @arg @ref LL_RCC_SYSCLK_DIV_10
1173 * @arg @ref LL_RCC_SYSCLK_DIV_16
1174 * @arg @ref LL_RCC_SYSCLK_DIV_32
1175 * @arg @ref LL_RCC_SYSCLK_DIV_64
1176 * @arg @ref LL_RCC_SYSCLK_DIV_128
1177 * @arg @ref LL_RCC_SYSCLK_DIV_256
1178 * @arg @ref LL_RCC_SYSCLK_DIV_512
1179 * @retval HCLK2 clock frequency (in Hz)
1180 */
1181 #define __LL_RCC_CALC_HCLK2_FREQ(__SYSCLKFREQ__, __CPU2PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU2PRESCALER__)\
1182 & RCC_EXTCFGR_C2HPRE) >> RCC_EXTCFGR_C2HPRE_Pos])
1183
1184 /**
1185 * @brief Helper macro to calculate the HCLK4 frequency
1186 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
1187 * @param __AHB4PRESCALER__ This parameter can be one of the following values:
1188 * @arg @ref LL_RCC_SYSCLK_DIV_1
1189 * @arg @ref LL_RCC_SYSCLK_DIV_2
1190 * @arg @ref LL_RCC_SYSCLK_DIV_3
1191 * @arg @ref LL_RCC_SYSCLK_DIV_4
1192 * @arg @ref LL_RCC_SYSCLK_DIV_5
1193 * @arg @ref LL_RCC_SYSCLK_DIV_6
1194 * @arg @ref LL_RCC_SYSCLK_DIV_8
1195 * @arg @ref LL_RCC_SYSCLK_DIV_10
1196 * @arg @ref LL_RCC_SYSCLK_DIV_16
1197 * @arg @ref LL_RCC_SYSCLK_DIV_32
1198 * @arg @ref LL_RCC_SYSCLK_DIV_64
1199 * @arg @ref LL_RCC_SYSCLK_DIV_128
1200 * @arg @ref LL_RCC_SYSCLK_DIV_256
1201 * @arg @ref LL_RCC_SYSCLK_DIV_512
1202 * @retval HCLK4 clock frequency (in Hz)
1203 */
1204 #define __LL_RCC_CALC_HCLK4_FREQ(__SYSCLKFREQ__, __AHB4PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[(((__AHB4PRESCALER__) >> 4U)\
1205 & RCC_EXTCFGR_SHDHPRE) >> RCC_EXTCFGR_SHDHPRE_Pos])
1206
1207
1208 /**
1209 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1210 * @param __HCLKFREQ__ HCLK frequency
1211 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1212 * @arg @ref LL_RCC_APB1_DIV_1
1213 * @arg @ref LL_RCC_APB1_DIV_2
1214 * @arg @ref LL_RCC_APB1_DIV_4
1215 * @arg @ref LL_RCC_APB1_DIV_8
1216 * @arg @ref LL_RCC_APB1_DIV_16
1217 * @retval PCLK1 clock frequency (in Hz)
1218 */
1219 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(((__APB1PRESCALER__)\
1220 & RCC_CFGR_PPRE1_Msk) >> RCC_CFGR_PPRE1_Pos)] & 31U))
1221
1222 /**
1223 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
1224 * @param __HCLKFREQ__ HCLK frequency
1225 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1226 * @arg @ref LL_RCC_APB2_DIV_1
1227 * @arg @ref LL_RCC_APB2_DIV_2
1228 * @arg @ref LL_RCC_APB2_DIV_4
1229 * @arg @ref LL_RCC_APB2_DIV_8
1230 * @arg @ref LL_RCC_APB2_DIV_16
1231 * @retval PCLK2 clock frequency (in Hz)
1232 */
1233 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(((__APB2PRESCALER__)\
1234 & RCC_CFGR_PPRE2_Msk) >> RCC_CFGR_PPRE2_Pos)] & 31U))
1235
1236 /**
1237 * @brief Helper macro to calculate the MSI frequency (in Hz)
1238 * @note __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange()
1239 * @param __MSIRANGE__ This parameter can be one of the following values:
1240 * @arg @ref LL_RCC_MSIRANGE_0
1241 * @arg @ref LL_RCC_MSIRANGE_1
1242 * @arg @ref LL_RCC_MSIRANGE_2
1243 * @arg @ref LL_RCC_MSIRANGE_3
1244 * @arg @ref LL_RCC_MSIRANGE_4
1245 * @arg @ref LL_RCC_MSIRANGE_5
1246 * @arg @ref LL_RCC_MSIRANGE_6
1247 * @arg @ref LL_RCC_MSIRANGE_7
1248 * @arg @ref LL_RCC_MSIRANGE_8
1249 * @arg @ref LL_RCC_MSIRANGE_9
1250 * @arg @ref LL_RCC_MSIRANGE_10
1251 * @arg @ref LL_RCC_MSIRANGE_11
1252 * @retval MSI clock frequency (in Hz)
1253 */
1254 #define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) MSIRangeTable[((__MSIRANGE__)\
1255 & RCC_CR_MSIRANGE_Msk) >> RCC_CR_MSIRANGE_Pos]
1256 /**
1257 * @}
1258 */
1259
1260 /**
1261 * @}
1262 */
1263
1264 /* Exported functions --------------------------------------------------------*/
1265 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1266 * @{
1267 */
1268
1269 /** @defgroup RCC_LL_EF_HSE HSE
1270 * @{
1271 */
1272
1273 /**
1274 * @brief Enable HSE sysclk and pll prescaler division by 2
1275 * @rmtoll CR HSEPRE LL_RCC_HSE_EnableDiv2
1276 * @retval None
1277 */
LL_RCC_HSE_EnableDiv2(void)1278 __STATIC_INLINE void LL_RCC_HSE_EnableDiv2(void)
1279 {
1280 SET_BIT(RCC->CR, RCC_CR_HSEPRE);
1281 }
1282
1283 /**
1284 * @brief Disable HSE sysclk and pll prescaler
1285 * @rmtoll CR HSEPRE LL_RCC_HSE_DisableDiv2
1286 * @retval None
1287 */
LL_RCC_HSE_DisableDiv2(void)1288 __STATIC_INLINE void LL_RCC_HSE_DisableDiv2(void)
1289 {
1290 CLEAR_BIT(RCC->CR, RCC_CR_HSEPRE);
1291 }
1292
1293 /**
1294 * @brief Get HSE sysclk and pll prescaler
1295 * @rmtoll CR HSEPRE LL_RCC_HSE_IsEnabledDiv2
1296 * @retval None
1297 */
LL_RCC_HSE_IsEnabledDiv2(void)1298 __STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabledDiv2(void)
1299 {
1300 return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL);
1301 }
1302
1303 /**
1304 * @brief Enable the Clock Security System.
1305 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
1306 * @retval None
1307 */
LL_RCC_HSE_EnableCSS(void)1308 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1309 {
1310 SET_BIT(RCC->CR, RCC_CR_CSSON);
1311 }
1312
1313 /**
1314 * @brief Enable HSE crystal oscillator (HSE ON)
1315 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1316 * @retval None
1317 */
LL_RCC_HSE_Enable(void)1318 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1319 {
1320 SET_BIT(RCC->CR, RCC_CR_HSEON);
1321 }
1322
1323 /**
1324 * @brief Disable HSE crystal oscillator (HSE ON)
1325 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1326 * @retval None
1327 */
LL_RCC_HSE_Disable(void)1328 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1329 {
1330 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1331 }
1332
1333 /**
1334 * @brief Check if HSE oscillator Ready
1335 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1336 * @retval State of bit (1 or 0).
1337 */
LL_RCC_HSE_IsReady(void)1338 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1339 {
1340 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
1341 }
1342
1343 /**
1344 * @brief Check if HSE clock control register is locked or not
1345 * @rmtoll HSECR UNLOCKED LL_RCC_HSE_IsClockControlLocked
1346 * @retval State of bit (1 or 0).
1347 */
LL_RCC_HSE_IsClockControlLocked(void)1348 __STATIC_INLINE uint32_t LL_RCC_HSE_IsClockControlLocked(void)
1349 {
1350 return ((READ_BIT(RCC->HSECR, RCC_HSECR_UNLOCKED) != (RCC_HSECR_UNLOCKED)) ? 1UL : 0UL);
1351 }
1352
1353 /**
1354 * @brief Set HSE capacitor tuning
1355 * @rmtoll HSECR HSETUNE LL_RCC_HSE_SetCapacitorTuning
1356 * @param Value Between Min_Data = 0 and Max_Data = 63
1357 * @retval None
1358 */
LL_RCC_HSE_SetCapacitorTuning(uint32_t Value)1359 __STATIC_INLINE void LL_RCC_HSE_SetCapacitorTuning(uint32_t Value)
1360 {
1361 WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY);
1362 MODIFY_REG(RCC->HSECR, RCC_HSECR_HSETUNE, Value << RCC_HSECR_HSETUNE_Pos);
1363 }
1364
1365 /**
1366 * @brief Get HSE capacitor tuning
1367 * @rmtoll HSECR HSETUNE LL_RCC_HSE_GetCapacitorTuning
1368 * @retval Between Min_Data = 0 and Max_Data = 63
1369 */
LL_RCC_HSE_GetCapacitorTuning(void)1370 __STATIC_INLINE uint32_t LL_RCC_HSE_GetCapacitorTuning(void)
1371 {
1372 return (uint32_t)(READ_BIT(RCC->HSECR, RCC_HSECR_HSETUNE) >> RCC_HSECR_HSETUNE_Pos);
1373 }
1374
1375 /**
1376 * @brief Set HSE current control
1377 * @rmtoll HSECR HSEGMC LL_RCC_HSE_SetCurrentControl
1378 * @param CurrentMax This parameter can be one of the following values:
1379 * @arg @ref LL_RCC_HSE_CURRENTMAX_0
1380 * @arg @ref LL_RCC_HSE_CURRENTMAX_1
1381 * @arg @ref LL_RCC_HSE_CURRENTMAX_2
1382 * @arg @ref LL_RCC_HSE_CURRENTMAX_3
1383 * @arg @ref LL_RCC_HSE_CURRENTMAX_4
1384 * @arg @ref LL_RCC_HSE_CURRENTMAX_5
1385 * @arg @ref LL_RCC_HSE_CURRENTMAX_6
1386 * @arg @ref LL_RCC_HSE_CURRENTMAX_7
1387 */
LL_RCC_HSE_SetCurrentControl(uint32_t CurrentMax)1388 __STATIC_INLINE void LL_RCC_HSE_SetCurrentControl(uint32_t CurrentMax)
1389 {
1390 WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY);
1391 MODIFY_REG(RCC->HSECR, RCC_HSECR_HSEGMC, CurrentMax);
1392 }
1393
1394 /**
1395 * @brief Get HSE current control
1396 * @rmtoll HSECR HSEGMC LL_RCC_HSE_GetCurrentControl
1397 * @retval Returned value can be one of the following values:
1398 * @arg @ref LL_RCC_HSE_CURRENTMAX_0
1399 * @arg @ref LL_RCC_HSE_CURRENTMAX_1
1400 * @arg @ref LL_RCC_HSE_CURRENTMAX_2
1401 * @arg @ref LL_RCC_HSE_CURRENTMAX_3
1402 * @arg @ref LL_RCC_HSE_CURRENTMAX_4
1403 * @arg @ref LL_RCC_HSE_CURRENTMAX_5
1404 * @arg @ref LL_RCC_HSE_CURRENTMAX_6
1405 * @arg @ref LL_RCC_HSE_CURRENTMAX_7
1406 */
LL_RCC_HSE_GetCurrentControl(void)1407 __STATIC_INLINE uint32_t LL_RCC_HSE_GetCurrentControl(void)
1408 {
1409 return (uint32_t)(READ_BIT(RCC->HSECR, RCC_HSECR_HSEGMC));
1410 }
1411
1412 /**
1413 * @brief Set HSE sense amplifier threshold
1414 * @rmtoll HSECR HSES LL_RCC_HSE_SetSenseAmplifier
1415 * @param SenseAmplifier This parameter can be one of the following values:
1416 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_1_2
1417 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_3_4
1418 */
LL_RCC_HSE_SetSenseAmplifier(uint32_t SenseAmplifier)1419 __STATIC_INLINE void LL_RCC_HSE_SetSenseAmplifier(uint32_t SenseAmplifier)
1420 {
1421 WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY);
1422 MODIFY_REG(RCC->HSECR, RCC_HSECR_HSES, SenseAmplifier);
1423 }
1424
1425 /**
1426 * @brief Get HSE current control
1427 * @rmtoll HSECR HSES LL_RCC_HSE_GetSenseAmplifier
1428 * @retval Returned value can be one of the following values:
1429 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_1_2
1430 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_3_4
1431 */
LL_RCC_HSE_GetSenseAmplifier(void)1432 __STATIC_INLINE uint32_t LL_RCC_HSE_GetSenseAmplifier(void)
1433 {
1434 return (uint32_t)(READ_BIT(RCC->HSECR, RCC_HSECR_HSES));
1435 }
1436 /**
1437 * @}
1438 */
1439
1440 /** @defgroup RCC_LL_EF_HSI HSI
1441 * @{
1442 */
1443
1444 /**
1445 * @brief Enable HSI even in stop mode
1446 * @note HSI oscillator is forced ON even in Stop mode
1447 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
1448 * @retval None
1449 */
LL_RCC_HSI_EnableInStopMode(void)1450 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
1451 {
1452 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
1453 }
1454
1455 /**
1456 * @brief Disable HSI in stop mode
1457 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
1458 * @retval None
1459 */
LL_RCC_HSI_DisableInStopMode(void)1460 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
1461 {
1462 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1463 }
1464
1465 /**
1466 * @brief Check if HSI in stop mode is ready
1467 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
1468 * @retval State of bit (1 or 0).
1469 */
LL_RCC_HSI_IsEnabledInStopMode(void)1470 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
1471 {
1472 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL);
1473 }
1474
1475 /**
1476 * @brief Enable HSI oscillator
1477 * @rmtoll CR HSION LL_RCC_HSI_Enable
1478 * @retval None
1479 */
LL_RCC_HSI_Enable(void)1480 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1481 {
1482 SET_BIT(RCC->CR, RCC_CR_HSION);
1483 }
1484
1485 /**
1486 * @brief Disable HSI oscillator
1487 * @rmtoll CR HSION LL_RCC_HSI_Disable
1488 * @retval None
1489 */
LL_RCC_HSI_Disable(void)1490 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1491 {
1492 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1493 }
1494
1495 /**
1496 * @brief Check if HSI clock is ready
1497 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1498 * @retval State of bit (1 or 0).
1499 */
LL_RCC_HSI_IsReady(void)1500 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1501 {
1502 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
1503 }
1504
1505 /**
1506 * @brief Enable HSI Automatic from stop mode
1507 * @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
1508 * @retval None
1509 */
LL_RCC_HSI_EnableAutoFromStop(void)1510 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
1511 {
1512 SET_BIT(RCC->CR, RCC_CR_HSIASFS);
1513 }
1514
1515 /**
1516 * @brief Disable HSI Automatic from stop mode
1517 * @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
1518 * @retval None
1519 */
LL_RCC_HSI_DisableAutoFromStop(void)1520 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
1521 {
1522 CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
1523 }
1524 /**
1525 * @brief Get HSI Calibration value
1526 * @note When HSITRIM is written, HSICAL is updated with the sum of
1527 * HSITRIM and the factory trim value
1528 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
1529 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
1530 */
LL_RCC_HSI_GetCalibration(void)1531 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1532 {
1533 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
1534 }
1535
1536 /**
1537 * @brief Set HSI Calibration trimming
1538 * @note user-programmable trimming value that is added to the HSICAL
1539 * @note Default value is 64, which, when added to the HSICAL value,
1540 * should trim the HSI to 16 MHz +/- 1 %
1541 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
1542 * @param Value Between Min_Data = 0 and Max_Data = 127
1543 * @retval None
1544 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1545 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1546 {
1547 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
1548 }
1549
1550 /**
1551 * @brief Get HSI Calibration trimming
1552 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
1553 * @retval Between Min_Data = 0 and Max_Data = 127
1554 */
LL_RCC_HSI_GetCalibTrimming(void)1555 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1556 {
1557 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
1558 }
1559
1560 /**
1561 * @}
1562 */
1563
1564 #if defined(RCC_HSI48_SUPPORT)
1565 /** @defgroup RCC_LL_EF_HSI48 HSI48
1566 * @{
1567 */
1568
1569 /**
1570 * @brief Enable HSI48
1571 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
1572 * @retval None
1573 */
LL_RCC_HSI48_Enable(void)1574 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
1575 {
1576 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
1577 }
1578
1579 /**
1580 * @brief Disable HSI48
1581 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
1582 * @retval None
1583 */
LL_RCC_HSI48_Disable(void)1584 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
1585 {
1586 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
1587 }
1588
1589 /**
1590 * @brief Check if HSI48 oscillator Ready
1591 * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
1592 * @retval State of bit (1 or 0).
1593 */
LL_RCC_HSI48_IsReady(void)1594 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
1595 {
1596 return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL);
1597 }
1598
1599 /**
1600 * @brief Get HSI48 Calibration value
1601 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
1602 * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
1603 */
LL_RCC_HSI48_GetCalibration(void)1604 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
1605 {
1606 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
1607 }
1608
1609 /**
1610 * @}
1611 */
1612 #endif /* RCC_HSI48_SUPPORT */
1613
1614 /** @defgroup RCC_LL_EF_LSE LSE
1615 * @{
1616 */
1617
1618 /**
1619 * @brief Enable Low Speed External (LSE) crystal.
1620 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1621 * @retval None
1622 */
LL_RCC_LSE_Enable(void)1623 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1624 {
1625 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1626 }
1627
1628 /**
1629 * @brief Disable Low Speed External (LSE) crystal.
1630 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1631 * @retval None
1632 */
LL_RCC_LSE_Disable(void)1633 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1634 {
1635 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1636 }
1637
1638 /**
1639 * @brief Check if Low Speed External (LSE) crystal has been enabled or not
1640 * @rmtoll BDCR LSEON LL_RCC_LSE_IsEnabled
1641 * @retval State of bit (1 or 0).
1642 */
LL_RCC_LSE_IsEnabled(void)1643 __STATIC_INLINE uint32_t LL_RCC_LSE_IsEnabled(void)
1644 {
1645 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == (RCC_BDCR_LSEON)) ? 1UL : 0UL);
1646 }
1647
1648 /**
1649 * @brief Enable external clock source (LSE bypass).
1650 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1651 * @retval None
1652 */
LL_RCC_LSE_EnableBypass(void)1653 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1654 {
1655 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1656 }
1657
1658 /**
1659 * @brief Disable external clock source (LSE bypass).
1660 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1661 * @retval None
1662 */
LL_RCC_LSE_DisableBypass(void)1663 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1664 {
1665 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1666 }
1667
1668 /**
1669 * @brief Set LSE oscillator drive capability
1670 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1671 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1672 * @param LSEDrive This parameter can be one of the following values:
1673 * @arg @ref LL_RCC_LSEDRIVE_LOW
1674 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1675 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1676 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1677 * @retval None
1678 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1679 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1680 {
1681 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1682 }
1683
1684 /**
1685 * @brief Get LSE oscillator drive capability
1686 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
1687 * @retval Returned value can be one of the following values:
1688 * @arg @ref LL_RCC_LSEDRIVE_LOW
1689 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1690 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1691 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1692 */
LL_RCC_LSE_GetDriveCapability(void)1693 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1694 {
1695 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1696 }
1697
1698 /**
1699 * @brief Enable Clock security system on LSE.
1700 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
1701 * @retval None
1702 */
LL_RCC_LSE_EnableCSS(void)1703 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1704 {
1705 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1706 }
1707
1708 /**
1709 * @brief Disable Clock security system on LSE.
1710 * @note Clock security system can be disabled only after a LSE
1711 * failure detection. In that case it MUST be disabled by software.
1712 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
1713 * @retval None
1714 */
LL_RCC_LSE_DisableCSS(void)1715 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1716 {
1717 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1718 }
1719
1720 /**
1721 * @brief Check if LSE oscillator Ready
1722 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1723 * @retval State of bit (1 or 0).
1724 */
LL_RCC_LSE_IsReady(void)1725 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1726 {
1727 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
1728 }
1729
1730 /**
1731 * @brief Check if CSS on LSE failure Detection
1732 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
1733 * @retval State of bit (1 or 0).
1734 */
LL_RCC_LSE_IsCSSDetected(void)1735 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1736 {
1737 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
1738 }
1739
1740 /**
1741 * @}
1742 */
1743
1744 /** @defgroup RCC_LL_EF_LSI1 LSI1
1745 * @{
1746 */
1747
1748 /**
1749 * @brief Enable LSI1 Oscillator
1750 * @rmtoll CSR LSI1ON LL_RCC_LSI1_Enable
1751 * @retval None
1752 */
LL_RCC_LSI1_Enable(void)1753 __STATIC_INLINE void LL_RCC_LSI1_Enable(void)
1754 {
1755 SET_BIT(RCC->CSR, RCC_CSR_LSI1ON);
1756 }
1757
1758 /**
1759 * @brief Disable LSI1 Oscillator
1760 * @rmtoll CSR LSI1ON LL_RCC_LSI1_Disable
1761 * @retval None
1762 */
LL_RCC_LSI1_Disable(void)1763 __STATIC_INLINE void LL_RCC_LSI1_Disable(void)
1764 {
1765 CLEAR_BIT(RCC->CSR, RCC_CSR_LSI1ON);
1766 }
1767
1768 /**
1769 * @brief Check if LSI1 is Ready
1770 * @rmtoll CSR LSI1RDY LL_RCC_LSI1_IsReady
1771 * @retval State of bit (1 or 0).
1772 */
LL_RCC_LSI1_IsReady(void)1773 __STATIC_INLINE uint32_t LL_RCC_LSI1_IsReady(void)
1774 {
1775 return ((READ_BIT(RCC->CSR, RCC_CSR_LSI1RDY) == (RCC_CSR_LSI1RDY)) ? 1UL : 0UL);
1776 }
1777
1778 /**
1779 * @}
1780 */
1781
1782 /** @defgroup RCC_LL_EF_LSI2 LSI2
1783 * @{
1784 */
1785
1786 /**
1787 * @brief Enable LSI2 Oscillator
1788 * @rmtoll CSR LSI2ON LL_RCC_LSI2_Enable
1789 * @retval None
1790 */
LL_RCC_LSI2_Enable(void)1791 __STATIC_INLINE void LL_RCC_LSI2_Enable(void)
1792 {
1793 SET_BIT(RCC->CSR, RCC_CSR_LSI2ON);
1794 }
1795
1796 /**
1797 * @brief Disable LSI2 Oscillator
1798 * @rmtoll CSR LSI2ON LL_RCC_LSI2_Disable
1799 * @retval None
1800 */
LL_RCC_LSI2_Disable(void)1801 __STATIC_INLINE void LL_RCC_LSI2_Disable(void)
1802 {
1803 CLEAR_BIT(RCC->CSR, RCC_CSR_LSI2ON);
1804 }
1805
1806 /**
1807 * @brief Check if LSI2 is Ready
1808 * @rmtoll CSR LSI2RDY LL_RCC_LSI2_IsReady
1809 * @retval State of bit (1 or 0).
1810 */
LL_RCC_LSI2_IsReady(void)1811 __STATIC_INLINE uint32_t LL_RCC_LSI2_IsReady(void)
1812 {
1813 return ((READ_BIT(RCC->CSR, RCC_CSR_LSI2RDY) == (RCC_CSR_LSI2RDY)) ? 1UL : 0UL);
1814 }
1815
1816 /**
1817 * @brief Set LSI2 trimming value
1818 * @rmtoll CSR LSI2TRIM LL_RCC_LSI2_SetTrimming
1819 * @param Value Between Min_Data = 0 and Max_Data = 15
1820 * @retval None
1821 */
LL_RCC_LSI2_SetTrimming(uint32_t Value)1822 __STATIC_INLINE void LL_RCC_LSI2_SetTrimming(uint32_t Value)
1823 {
1824 MODIFY_REG(RCC->CSR, RCC_CSR_LSI2TRIM, Value << RCC_CSR_LSI2TRIM_Pos);
1825 }
1826
1827 /**
1828 * @brief Get LSI2 trimming value
1829 * @rmtoll CSR LSI2TRIM LL_RCC_LSI2_GetTrimming
1830 * @retval Between Min_Data = 0 and Max_Data = 12
1831 */
LL_RCC_LSI2_GetTrimming(void)1832 __STATIC_INLINE uint32_t LL_RCC_LSI2_GetTrimming(void)
1833 {
1834 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_LSI2TRIM) >> RCC_CSR_LSI2TRIM_Pos);
1835 }
1836
1837 /**
1838 * @}
1839 */
1840
1841 /** @defgroup RCC_LL_EF_MSI MSI
1842 * @{
1843 */
1844
1845 /**
1846 * @brief Enable MSI oscillator
1847 * @rmtoll CR MSION LL_RCC_MSI_Enable
1848 * @retval None
1849 */
LL_RCC_MSI_Enable(void)1850 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
1851 {
1852 SET_BIT(RCC->CR, RCC_CR_MSION);
1853 }
1854
1855 /**
1856 * @brief Disable MSI oscillator
1857 * @rmtoll CR MSION LL_RCC_MSI_Disable
1858 * @retval None
1859 */
LL_RCC_MSI_Disable(void)1860 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
1861 {
1862 CLEAR_BIT(RCC->CR, RCC_CR_MSION);
1863 }
1864
1865 /**
1866 * @brief Check if MSI oscillator Ready
1867 * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
1868 * @retval State of bit (1 or 0).
1869 */
LL_RCC_MSI_IsReady(void)1870 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
1871 {
1872 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL);
1873 }
1874
1875 /**
1876 * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
1877 * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
1878 * and ready (LSERDY set by hardware)
1879 * @note hardware protection to avoid enabling MSIPLLEN if LSE is not
1880 * ready
1881 * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
1882 * @retval None
1883 */
LL_RCC_MSI_EnablePLLMode(void)1884 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
1885 {
1886 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
1887 }
1888
1889 /**
1890 * @brief Disable MSI-PLL mode
1891 * @note cleared by hardware when LSE is disabled (LSEON = 0) or when
1892 * the Clock Security System on LSE detects a LSE failure
1893 * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
1894 * @retval None
1895 */
LL_RCC_MSI_DisablePLLMode(void)1896 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
1897 {
1898 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
1899 }
1900
1901
1902 /**
1903 * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
1904 * @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
1905 * @param Range This parameter can be one of the following values:
1906 * @arg @ref LL_RCC_MSIRANGE_0
1907 * @arg @ref LL_RCC_MSIRANGE_1
1908 * @arg @ref LL_RCC_MSIRANGE_2
1909 * @arg @ref LL_RCC_MSIRANGE_3
1910 * @arg @ref LL_RCC_MSIRANGE_4
1911 * @arg @ref LL_RCC_MSIRANGE_5
1912 * @arg @ref LL_RCC_MSIRANGE_6
1913 * @arg @ref LL_RCC_MSIRANGE_7
1914 * @arg @ref LL_RCC_MSIRANGE_8
1915 * @arg @ref LL_RCC_MSIRANGE_9
1916 * @arg @ref LL_RCC_MSIRANGE_10
1917 * @arg @ref LL_RCC_MSIRANGE_11
1918 * @retval None
1919 */
LL_RCC_MSI_SetRange(uint32_t Range)1920 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
1921 {
1922 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
1923 }
1924
1925 /**
1926 * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
1927 * @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
1928 * @retval Returned value can be one of the following values:
1929 * @arg @ref LL_RCC_MSIRANGE_0
1930 * @arg @ref LL_RCC_MSIRANGE_1
1931 * @arg @ref LL_RCC_MSIRANGE_2
1932 * @arg @ref LL_RCC_MSIRANGE_3
1933 * @arg @ref LL_RCC_MSIRANGE_4
1934 * @arg @ref LL_RCC_MSIRANGE_5
1935 * @arg @ref LL_RCC_MSIRANGE_6
1936 * @arg @ref LL_RCC_MSIRANGE_7
1937 * @arg @ref LL_RCC_MSIRANGE_8
1938 * @arg @ref LL_RCC_MSIRANGE_9
1939 * @arg @ref LL_RCC_MSIRANGE_10
1940 * @arg @ref LL_RCC_MSIRANGE_11
1941 */
LL_RCC_MSI_GetRange(void)1942 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
1943 {
1944 uint32_t msiRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE);
1945 if (msiRange > LL_RCC_MSIRANGE_11)
1946 {
1947 msiRange = LL_RCC_MSIRANGE_11;
1948 }
1949 return msiRange;
1950 }
1951
1952
1953 /**
1954 * @brief Get MSI Calibration value
1955 * @note When MSITRIM is written, MSICAL is updated with the sum of
1956 * MSITRIM and the factory trim value
1957 * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
1958 * @retval Between Min_Data = 0 and Max_Data = 255
1959 */
LL_RCC_MSI_GetCalibration(void)1960 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
1961 {
1962 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
1963 }
1964
1965 /**
1966 * @brief Set MSI Calibration trimming
1967 * @note user-programmable trimming value that is added to the MSICAL
1968 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
1969 * @param Value Between Min_Data = 0 and Max_Data = 255
1970 * @retval None
1971 */
LL_RCC_MSI_SetCalibTrimming(uint32_t Value)1972 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
1973 {
1974 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
1975 }
1976
1977 /**
1978 * @brief Get MSI Calibration trimming
1979 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
1980 * @retval Between 0 and 255
1981 */
LL_RCC_MSI_GetCalibTrimming(void)1982 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
1983 {
1984 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
1985 }
1986
1987 /**
1988 * @}
1989 */
1990
1991 /** @defgroup RCC_LL_EF_LSCO LSCO
1992 * @{
1993 */
1994
1995 /**
1996 * @brief Enable Low speed clock
1997 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
1998 * @retval None
1999 */
LL_RCC_LSCO_Enable(void)2000 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
2001 {
2002 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2003 }
2004
2005 /**
2006 * @brief Disable Low speed clock
2007 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
2008 * @retval None
2009 */
LL_RCC_LSCO_Disable(void)2010 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
2011 {
2012 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2013 }
2014
2015 /**
2016 * @brief Configure Low speed clock selection
2017 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
2018 * @param Source This parameter can be one of the following values:
2019 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2020 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2021 * @retval None
2022 */
LL_RCC_LSCO_SetSource(uint32_t Source)2023 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
2024 {
2025 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
2026 }
2027
2028 /**
2029 * @brief Get Low speed clock selection
2030 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
2031 * @retval Returned value can be one of the following values:
2032 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2033 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2034 */
LL_RCC_LSCO_GetSource(void)2035 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
2036 {
2037 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
2038 }
2039
2040 /**
2041 * @}
2042 */
2043
2044 /** @defgroup RCC_LL_EF_System System
2045 * @{
2046 */
2047
2048 /**
2049 * @brief Configure the system clock source
2050 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
2051 * @param Source This parameter can be one of the following values:
2052 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
2053 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2054 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2055 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
2056 * @retval None
2057 */
LL_RCC_SetSysClkSource(uint32_t Source)2058 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2059 {
2060 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
2061 }
2062
2063 /**
2064 * @brief Get the system clock source
2065 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
2066 * @retval Returned value can be one of the following values:
2067 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
2068 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2069 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2070 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
2071 */
LL_RCC_GetSysClkSource(void)2072 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2073 {
2074 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
2075 }
2076
2077 /**
2078 * @brief Get the RF clock source
2079 * @rmtoll EXTCFGR RFCSS LL_RCC_GetRFClockSource
2080 * @retval Returned value can be one of the following values:
2081 * @arg @ref LL_RCC_RF_CLKSOURCE_HSI
2082 * @arg @ref LL_RCC_RF_CLKSOURCE_HSE_DIV2
2083 */
LL_RCC_GetRFClockSource(void)2084 __STATIC_INLINE uint32_t LL_RCC_GetRFClockSource(void)
2085 {
2086 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_RFCSS));
2087 }
2088
2089 /**
2090 * @brief Set RF Wakeup Clock Source
2091 * @rmtoll CSR RFWKPSEL LL_RCC_SetRFWKPClockSource
2092 * @param Source This parameter can be one of the following values:
2093 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_NONE
2094 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSE
2095 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSI (*)
2096 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024
2097 * @note (*) Value not defined for all devices
2098 *
2099 * @retval None
2100 */
LL_RCC_SetRFWKPClockSource(uint32_t Source)2101 __STATIC_INLINE void LL_RCC_SetRFWKPClockSource(uint32_t Source)
2102 {
2103 MODIFY_REG(RCC->CSR, RCC_CSR_RFWKPSEL, Source);
2104 }
2105
2106 /**
2107 * @brief Get RF Wakeup Clock Source
2108 * @rmtoll CSR RFWKPSEL LL_RCC_GetRFWKPClockSource
2109 * @retval Returned value can be one of the following values:
2110 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_NONE
2111 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSE
2112 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSI (*)
2113 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024
2114 * @note (*) Value not defined for all devices
2115 *
2116 */
LL_RCC_GetRFWKPClockSource(void)2117 __STATIC_INLINE uint32_t LL_RCC_GetRFWKPClockSource(void)
2118 {
2119 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RFWKPSEL));
2120 }
2121
2122 /**
2123 * @brief Check if Radio System is reset.
2124 * @rmtoll CSR RFRSTS LL_RCC_IsRFUnderReset
2125 * @retval State of bit (1 or 0).
2126 */
LL_RCC_IsRFUnderReset(void)2127 __STATIC_INLINE uint32_t LL_RCC_IsRFUnderReset(void)
2128 {
2129 return ((READ_BIT(RCC->CSR, RCC_CSR_RFRSTS) == (RCC_CSR_RFRSTS)) ? 1UL : 0UL);
2130 }
2131
2132 /**
2133 * @brief Set AHB prescaler
2134 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
2135 * @param Prescaler This parameter can be one of the following values:
2136 * @arg @ref LL_RCC_SYSCLK_DIV_1
2137 * @arg @ref LL_RCC_SYSCLK_DIV_2
2138 * @arg @ref LL_RCC_SYSCLK_DIV_3
2139 * @arg @ref LL_RCC_SYSCLK_DIV_4
2140 * @arg @ref LL_RCC_SYSCLK_DIV_5
2141 * @arg @ref LL_RCC_SYSCLK_DIV_6
2142 * @arg @ref LL_RCC_SYSCLK_DIV_8
2143 * @arg @ref LL_RCC_SYSCLK_DIV_10
2144 * @arg @ref LL_RCC_SYSCLK_DIV_16
2145 * @arg @ref LL_RCC_SYSCLK_DIV_32
2146 * @arg @ref LL_RCC_SYSCLK_DIV_64
2147 * @arg @ref LL_RCC_SYSCLK_DIV_128
2148 * @arg @ref LL_RCC_SYSCLK_DIV_256
2149 * @arg @ref LL_RCC_SYSCLK_DIV_512
2150 * @retval None
2151 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)2152 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2153 {
2154 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
2155 }
2156
2157 /**
2158 * @brief Set CPU2 AHB prescaler
2159 * @rmtoll EXTCFGR C2HPRE LL_C2_RCC_SetAHBPrescaler
2160 * @param Prescaler This parameter can be one of the following values:
2161 * @arg @ref LL_RCC_SYSCLK_DIV_1
2162 * @arg @ref LL_RCC_SYSCLK_DIV_2
2163 * @arg @ref LL_RCC_SYSCLK_DIV_3
2164 * @arg @ref LL_RCC_SYSCLK_DIV_4
2165 * @arg @ref LL_RCC_SYSCLK_DIV_5
2166 * @arg @ref LL_RCC_SYSCLK_DIV_6
2167 * @arg @ref LL_RCC_SYSCLK_DIV_8
2168 * @arg @ref LL_RCC_SYSCLK_DIV_10
2169 * @arg @ref LL_RCC_SYSCLK_DIV_16
2170 * @arg @ref LL_RCC_SYSCLK_DIV_32
2171 * @arg @ref LL_RCC_SYSCLK_DIV_64
2172 * @arg @ref LL_RCC_SYSCLK_DIV_128
2173 * @arg @ref LL_RCC_SYSCLK_DIV_256
2174 * @arg @ref LL_RCC_SYSCLK_DIV_512
2175 * @retval None
2176 */
LL_C2_RCC_SetAHBPrescaler(uint32_t Prescaler)2177 __STATIC_INLINE void LL_C2_RCC_SetAHBPrescaler(uint32_t Prescaler)
2178 {
2179 MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler);
2180 }
2181
2182 /**
2183 * @brief Set AHB4 prescaler
2184 * @rmtoll EXTCFGR SHDHPRE LL_RCC_SetAHB4Prescaler
2185 * @param Prescaler This parameter can be one of the following values:
2186 * @arg @ref LL_RCC_SYSCLK_DIV_1
2187 * @arg @ref LL_RCC_SYSCLK_DIV_2
2188 * @arg @ref LL_RCC_SYSCLK_DIV_3
2189 * @arg @ref LL_RCC_SYSCLK_DIV_4
2190 * @arg @ref LL_RCC_SYSCLK_DIV_5
2191 * @arg @ref LL_RCC_SYSCLK_DIV_6
2192 * @arg @ref LL_RCC_SYSCLK_DIV_8
2193 * @arg @ref LL_RCC_SYSCLK_DIV_10
2194 * @arg @ref LL_RCC_SYSCLK_DIV_16
2195 * @arg @ref LL_RCC_SYSCLK_DIV_32
2196 * @arg @ref LL_RCC_SYSCLK_DIV_64
2197 * @arg @ref LL_RCC_SYSCLK_DIV_128
2198 * @arg @ref LL_RCC_SYSCLK_DIV_256
2199 * @arg @ref LL_RCC_SYSCLK_DIV_512
2200 * @retval None
2201 */
LL_RCC_SetAHB4Prescaler(uint32_t Prescaler)2202 __STATIC_INLINE void LL_RCC_SetAHB4Prescaler(uint32_t Prescaler)
2203 {
2204 MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4);
2205 }
2206
2207 /**
2208 * @brief Set APB1 prescaler
2209 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
2210 * @param Prescaler This parameter can be one of the following values:
2211 * @arg @ref LL_RCC_APB1_DIV_1
2212 * @arg @ref LL_RCC_APB1_DIV_2
2213 * @arg @ref LL_RCC_APB1_DIV_4
2214 * @arg @ref LL_RCC_APB1_DIV_8
2215 * @arg @ref LL_RCC_APB1_DIV_16
2216 * @retval None
2217 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)2218 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2219 {
2220 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
2221 }
2222
2223 /**
2224 * @brief Set APB2 prescaler
2225 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
2226 * @param Prescaler This parameter can be one of the following values:
2227 * @arg @ref LL_RCC_APB2_DIV_1
2228 * @arg @ref LL_RCC_APB2_DIV_2
2229 * @arg @ref LL_RCC_APB2_DIV_4
2230 * @arg @ref LL_RCC_APB2_DIV_8
2231 * @arg @ref LL_RCC_APB2_DIV_16
2232 * @retval None
2233 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)2234 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2235 {
2236 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
2237 }
2238
2239 /**
2240 * @brief Get AHB prescaler
2241 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
2242 * @retval Returned value can be one of the following values:
2243 * @arg @ref LL_RCC_SYSCLK_DIV_1
2244 * @arg @ref LL_RCC_SYSCLK_DIV_2
2245 * @arg @ref LL_RCC_SYSCLK_DIV_3
2246 * @arg @ref LL_RCC_SYSCLK_DIV_4
2247 * @arg @ref LL_RCC_SYSCLK_DIV_5
2248 * @arg @ref LL_RCC_SYSCLK_DIV_6
2249 * @arg @ref LL_RCC_SYSCLK_DIV_8
2250 * @arg @ref LL_RCC_SYSCLK_DIV_10
2251 * @arg @ref LL_RCC_SYSCLK_DIV_16
2252 * @arg @ref LL_RCC_SYSCLK_DIV_32
2253 * @arg @ref LL_RCC_SYSCLK_DIV_64
2254 * @arg @ref LL_RCC_SYSCLK_DIV_128
2255 * @arg @ref LL_RCC_SYSCLK_DIV_256
2256 * @arg @ref LL_RCC_SYSCLK_DIV_512
2257 */
LL_RCC_GetAHBPrescaler(void)2258 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2259 {
2260 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
2261 }
2262
2263 /**
2264 * @brief Get C2 AHB prescaler
2265 * @rmtoll EXTCFGR C2HPRE LL_C2_RCC_GetAHBPrescaler
2266 * @retval Returned value can be one of the following values:
2267 * @arg @ref LL_RCC_SYSCLK_DIV_1
2268 * @arg @ref LL_RCC_SYSCLK_DIV_2
2269 * @arg @ref LL_RCC_SYSCLK_DIV_3
2270 * @arg @ref LL_RCC_SYSCLK_DIV_4
2271 * @arg @ref LL_RCC_SYSCLK_DIV_5
2272 * @arg @ref LL_RCC_SYSCLK_DIV_6
2273 * @arg @ref LL_RCC_SYSCLK_DIV_8
2274 * @arg @ref LL_RCC_SYSCLK_DIV_10
2275 * @arg @ref LL_RCC_SYSCLK_DIV_16
2276 * @arg @ref LL_RCC_SYSCLK_DIV_32
2277 * @arg @ref LL_RCC_SYSCLK_DIV_64
2278 * @arg @ref LL_RCC_SYSCLK_DIV_128
2279 * @arg @ref LL_RCC_SYSCLK_DIV_256
2280 * @arg @ref LL_RCC_SYSCLK_DIV_512
2281 */
LL_C2_RCC_GetAHBPrescaler(void)2282 __STATIC_INLINE uint32_t LL_C2_RCC_GetAHBPrescaler(void)
2283 {
2284 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE));
2285 }
2286
2287 /**
2288 * @brief Get AHB4 prescaler
2289 * @rmtoll EXTCFGR SHDHPRE LL_RCC_GetAHB4Prescaler
2290 * @retval Returned value can be one of the following values:
2291 * @arg @ref LL_RCC_SYSCLK_DIV_1
2292 * @arg @ref LL_RCC_SYSCLK_DIV_2
2293 * @arg @ref LL_RCC_SYSCLK_DIV_3
2294 * @arg @ref LL_RCC_SYSCLK_DIV_4
2295 * @arg @ref LL_RCC_SYSCLK_DIV_5
2296 * @arg @ref LL_RCC_SYSCLK_DIV_6
2297 * @arg @ref LL_RCC_SYSCLK_DIV_8
2298 * @arg @ref LL_RCC_SYSCLK_DIV_10
2299 * @arg @ref LL_RCC_SYSCLK_DIV_16
2300 * @arg @ref LL_RCC_SYSCLK_DIV_32
2301 * @arg @ref LL_RCC_SYSCLK_DIV_64
2302 * @arg @ref LL_RCC_SYSCLK_DIV_128
2303 * @arg @ref LL_RCC_SYSCLK_DIV_256
2304 * @arg @ref LL_RCC_SYSCLK_DIV_512
2305 */
LL_RCC_GetAHB4Prescaler(void)2306 __STATIC_INLINE uint32_t LL_RCC_GetAHB4Prescaler(void)
2307 {
2308 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4);
2309 }
2310
2311 /**
2312 * @brief Get APB1 prescaler
2313 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
2314 * @retval Returned value can be one of the following values:
2315 * @arg @ref LL_RCC_APB1_DIV_1
2316 * @arg @ref LL_RCC_APB1_DIV_2
2317 * @arg @ref LL_RCC_APB1_DIV_4
2318 * @arg @ref LL_RCC_APB1_DIV_8
2319 * @arg @ref LL_RCC_APB1_DIV_16
2320 */
LL_RCC_GetAPB1Prescaler(void)2321 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2322 {
2323 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
2324 }
2325
2326 /**
2327 * @brief Get APB2 prescaler
2328 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
2329 * @retval Returned value can be one of the following values:
2330 * @arg @ref LL_RCC_APB2_DIV_1
2331 * @arg @ref LL_RCC_APB2_DIV_2
2332 * @arg @ref LL_RCC_APB2_DIV_4
2333 * @arg @ref LL_RCC_APB2_DIV_8
2334 * @arg @ref LL_RCC_APB2_DIV_16
2335 */
LL_RCC_GetAPB2Prescaler(void)2336 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2337 {
2338 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
2339 }
2340
2341 /**
2342 * @brief Set Clock After Wake-Up From Stop mode
2343 * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
2344 * @param Clock This parameter can be one of the following values:
2345 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
2346 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
2347 * @retval None
2348 */
LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)2349 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
2350 {
2351 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
2352 }
2353
2354 /**
2355 * @brief Get Clock After Wake-Up From Stop mode
2356 * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
2357 * @retval Returned value can be one of the following values:
2358 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
2359 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
2360 */
LL_RCC_GetClkAfterWakeFromStop(void)2361 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
2362 {
2363 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
2364 }
2365
2366 /**
2367 * @}
2368 */
2369
2370 #if defined(RCC_SMPS_SUPPORT)
2371 /** @defgroup RCC_LL_EF_SMPS SMPS
2372 * @{
2373 */
2374 /**
2375 * @brief Configure SMPS step down converter clock source
2376 * @rmtoll SMPSCR SMPSSEL LL_RCC_SetSMPSClockSource
2377 * @param SMPSSource This parameter can be one of the following values:
2378 * @arg @ref LL_RCC_SMPS_CLKSOURCE_HSI
2379 * @arg @ref LL_RCC_SMPS_CLKSOURCE_MSI (*)
2380 * @arg @ref LL_RCC_SMPS_CLKSOURCE_HSE
2381 * @note The system must always be configured so as to get a SMPS Step Down
2382 * converter clock frequency between 2 MHz and 8 MHz
2383 * @note (*) The MSI shall only be selected as SMPS Step Down converter
2384 * clock source when a supported SMPS Step Down converter clock
2385 * MSIRANGE is set (LL_RCC_MSIRANGE_8 to LL_RCC_MSIRANGE_11)
2386 * @retval None
2387 */
LL_RCC_SetSMPSClockSource(uint32_t SMPSSource)2388 __STATIC_INLINE void LL_RCC_SetSMPSClockSource(uint32_t SMPSSource)
2389 {
2390 MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSSEL, SMPSSource);
2391 }
2392
2393 /**
2394 * @brief Get the SMPS clock source selection
2395 * @rmtoll SMPSCR SMPSSEL LL_RCC_GetSMPSClockSelection
2396 * @retval Returned value can be one of the following values:
2397 * @arg @ref LL_RCC_SMPS_CLKSOURCE_HSI
2398 * @arg @ref LL_RCC_SMPS_CLKSOURCE_MSI
2399 * @arg @ref LL_RCC_SMPS_CLKSOURCE_HSE
2400 */
LL_RCC_GetSMPSClockSelection(void)2401 __STATIC_INLINE uint32_t LL_RCC_GetSMPSClockSelection(void)
2402 {
2403 return (uint32_t)(READ_BIT(RCC->SMPSCR, RCC_SMPSCR_SMPSSEL));
2404 }
2405
2406
2407 /**
2408 * @brief Get the SMPS clock source
2409 * @rmtoll SMPSCR SMPSSWS LL_RCC_GetSMPSClockSource
2410 * @retval Returned value can be one of the following values:
2411 * @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_HSI
2412 * @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_MSI
2413 * @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_HSE
2414 * @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK
2415 */
LL_RCC_GetSMPSClockSource(void)2416 __STATIC_INLINE uint32_t LL_RCC_GetSMPSClockSource(void)
2417 {
2418 return (uint32_t)(READ_BIT(RCC->SMPSCR, RCC_SMPSCR_SMPSSWS));
2419 }
2420
2421 /**
2422 * @brief Set SMPS prescaler
2423 * @rmtoll SMPSCR SMPSDIV LL_RCC_SetSMPSPrescaler
2424 * @param Prescaler This parameter can be one of the following values:
2425 * @arg @ref LL_RCC_SMPS_DIV_0
2426 * @arg @ref LL_RCC_SMPS_DIV_1
2427 * @arg @ref LL_RCC_SMPS_DIV_2
2428 * @arg @ref LL_RCC_SMPS_DIV_3
2429 * @retval None
2430 */
LL_RCC_SetSMPSPrescaler(uint32_t Prescaler)2431 __STATIC_INLINE void LL_RCC_SetSMPSPrescaler(uint32_t Prescaler)
2432 {
2433 MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSDIV, Prescaler);
2434 }
2435
2436 /**
2437 * @brief Get SMPS prescaler
2438 * @rmtoll SMPSCR SMPSDIV LL_RCC_GetSMPSPrescaler
2439 * @retval Returned value can be one of the following values:
2440 * @arg @ref LL_RCC_SMPS_DIV_0
2441 * @arg @ref LL_RCC_SMPS_DIV_1
2442 * @arg @ref LL_RCC_SMPS_DIV_2
2443 * @arg @ref LL_RCC_SMPS_DIV_3
2444 */
LL_RCC_GetSMPSPrescaler(void)2445 __STATIC_INLINE uint32_t LL_RCC_GetSMPSPrescaler(void)
2446 {
2447 return (uint32_t)(READ_BIT(RCC->SMPSCR, RCC_SMPSCR_SMPSDIV));
2448 }
2449
2450 /**
2451 * @}
2452 */
2453 #endif /* RCC_SMPS_SUPPORT */
2454
2455 /** @defgroup RCC_LL_EF_MCO MCO
2456 * @{
2457 */
2458
2459 /**
2460 * @brief Configure MCOx
2461 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
2462 * CFGR MCOPRE LL_RCC_ConfigMCO
2463 * @param MCOxSource This parameter can be one of the following values:
2464 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
2465 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
2466 * @arg @ref LL_RCC_MCO1SOURCE_MSI
2467 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2468 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2469 * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
2470 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
2471 * @arg @ref LL_RCC_MCO1SOURCE_LSI1
2472 * @arg @ref LL_RCC_MCO1SOURCE_LSI2
2473 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2474 * @arg @ref LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB
2475 * @param MCOxPrescaler This parameter can be one of the following values:
2476 * @arg @ref LL_RCC_MCO1_DIV_1
2477 * @arg @ref LL_RCC_MCO1_DIV_2
2478 * @arg @ref LL_RCC_MCO1_DIV_4
2479 * @arg @ref LL_RCC_MCO1_DIV_8
2480 * @arg @ref LL_RCC_MCO1_DIV_16
2481 * @note (*) Value not defined for all devices
2482 * @retval None
2483 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)2484 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2485 {
2486 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
2487 }
2488
2489 /**
2490 * @}
2491 */
2492
2493 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2494 * @{
2495 */
2496
2497 /**
2498 * @brief Configure USARTx clock source
2499 * @rmtoll CCIPR USART1SEL LL_RCC_SetUSARTClockSource
2500 * @param USARTxSource This parameter can be one of the following values:
2501 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2502 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2503 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2504 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2505 * @retval None
2506 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)2507 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
2508 {
2509 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, USARTxSource);
2510 }
2511
2512 #if defined(LPUART1)
2513 /**
2514 * @brief Configure LPUART1x clock source
2515 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
2516 * @param LPUARTxSource This parameter can be one of the following values:
2517 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
2518 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
2519 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2520 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2521 * @retval None
2522 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)2523 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
2524 {
2525 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
2526 }
2527 #endif /* LPUART1 */
2528
2529 /**
2530 * @brief Configure I2Cx clock source
2531 * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
2532 * @param I2CxSource This parameter can be one of the following values:
2533 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2534 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2535 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2536 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*)
2537 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
2538 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
2539 * @note (*) Value not defined for all devices
2540 * @retval None
2541 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)2542 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
2543 {
2544 MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U));
2545 }
2546
2547 /**
2548 * @brief Configure LPTIMx clock source
2549 * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
2550 * @param LPTIMxSource This parameter can be one of the following values:
2551 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2552 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2553 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2554 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2555 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2556 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2557 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2558 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2559 * @retval None
2560 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)2561 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
2562 {
2563 MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16));
2564 }
2565
2566 #if defined(SAI1)
2567 /**
2568 * @brief Configure SAIx clock source
2569 * @rmtoll CCIPR SAI1SEL LL_RCC_SetSAIClockSource
2570 * @param SAIxSource This parameter can be one of the following values:
2571 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
2572 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
2573 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
2574 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2575 * @retval None
2576 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)2577 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
2578 {
2579 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource);
2580 }
2581 #endif /* SAI1 */
2582
2583 /**
2584 * @brief Configure RNG clock source
2585 * @note In case of CLK48 clock selected, it must be configured first thanks to LL_RCC_SetCLK48ClockSource
2586 * @rmtoll CCIPR RNGSEL LL_RCC_SetRNGClockSource
2587 * @param RNGxSource This parameter can be one of the following values:
2588 * @arg @ref LL_RCC_RNG_CLKSOURCE_CLK48
2589 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
2590 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
2591 * @retval None
2592 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)2593 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
2594 {
2595 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource);
2596 }
2597
2598 /**
2599 * @brief Configure CLK48 clock source
2600 * @rmtoll CCIPR CLK48SEL LL_RCC_SetCLK48ClockSource
2601 * @param CLK48xSource This parameter can be one of the following values:
2602 * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 (*)
2603 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*)
2604 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
2605 * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
2606 * @note (*) Value not defined for all devices
2607 * @retval None
2608 */
LL_RCC_SetCLK48ClockSource(uint32_t CLK48xSource)2609 __STATIC_INLINE void LL_RCC_SetCLK48ClockSource(uint32_t CLK48xSource)
2610 {
2611 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, CLK48xSource);
2612 }
2613
2614 #if defined(USB)
2615 /**
2616 * @brief Configure USB clock source
2617 * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
2618 * @param USBxSource This parameter can be one of the following values:
2619 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
2620 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
2621 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2622 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
2623 * @retval None
2624 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)2625 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
2626 {
2627 LL_RCC_SetCLK48ClockSource(USBxSource);
2628 }
2629 #endif /* USB */
2630
2631 /**
2632 * @brief Configure RNG clock source
2633 * @note Allow to configure the overall RNG Clock source, if CLK48 is selected as RNG
2634 Clock source, the CLK48xSource has to be configured
2635 * @rmtoll CCIPR RNGSEL LL_RCC_ConfigRNGClockSource
2636 * @rmtoll CCIPR CLK48SEL LL_RCC_ConfigRNGClockSource
2637 * @param RNGxSource This parameter can be one of the following values:
2638 * @arg @ref LL_RCC_RNG_CLKSOURCE_CLK48
2639 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
2640 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
2641 * @param CLK48xSource This parameter can be one of the following values:
2642 * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 (*)
2643 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*)
2644 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
2645 * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
2646 * @note (*) Value not defined for all devices
2647 * @retval None
2648 */
LL_RCC_ConfigRNGClockSource(uint32_t RNGxSource,uint32_t CLK48xSource)2649 __STATIC_INLINE void LL_RCC_ConfigRNGClockSource(uint32_t RNGxSource, uint32_t CLK48xSource)
2650 {
2651 if (RNGxSource == LL_RCC_RNG_CLKSOURCE_CLK48)
2652 {
2653 LL_RCC_SetCLK48ClockSource(CLK48xSource);
2654 }
2655 LL_RCC_SetRNGClockSource(RNGxSource);
2656 }
2657
2658
2659 /**
2660 * @brief Configure ADC clock source
2661 * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
2662 * @param ADCxSource This parameter can be one of the following values:
2663 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
2664 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)
2665 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
2666 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2667 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI (*)
2668 * @note (*) Value not defined for all devices
2669 * @retval None
2670 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)2671 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
2672 {
2673 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
2674 }
2675
2676
2677 /**
2678 * @brief Get USARTx clock source
2679 * @rmtoll CCIPR USART1SEL LL_RCC_GetUSARTClockSource
2680 * @param USARTx This parameter can be one of the following values:
2681 * @arg @ref LL_RCC_USART1_CLKSOURCE
2682 * @retval Returned value can be one of the following values:
2683 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2684 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2685 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2686 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2687 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)2688 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
2689 {
2690 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx));
2691 }
2692
2693 #if defined(LPUART1)
2694 /**
2695 * @brief Get LPUARTx clock source
2696 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
2697 * @param LPUARTx This parameter can be one of the following values:
2698 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
2699 * @retval Returned value can be one of the following values:
2700 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
2701 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
2702 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2703 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2704 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)2705 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
2706 {
2707 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
2708 }
2709 #endif /* LPUART1 */
2710
2711 /**
2712 * @brief Get I2Cx clock source
2713 * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
2714 * @param I2Cx This parameter can be one of the following values:
2715 * @arg @ref LL_RCC_I2C1_CLKSOURCE
2716 * @arg @ref LL_RCC_I2C3_CLKSOURCE
2717 * @retval Returned value can be one of the following values:
2718 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2719 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2720 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2721 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*)
2722 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
2723 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
2724 * @note (*) Value not defined for all devices
2725 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)2726 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
2727 {
2728 return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4) | (I2Cx << 4));
2729 }
2730
2731 /**
2732 * @brief Get LPTIMx clock source
2733 * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
2734 * @param LPTIMx This parameter can be one of the following values:
2735 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2736 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
2737 * @retval Returned value can be one of the following values:
2738 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2739 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2740 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2741 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2742 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2743 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2744 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2745 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2746 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)2747 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
2748 {
2749 return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16) | LPTIMx);
2750 }
2751
2752 #if defined(SAI1)
2753 /**
2754 * @brief Get SAIx clock source
2755 * @rmtoll CCIPR SAI1SEL LL_RCC_GetSAIClockSource
2756 * @param SAIx This parameter can be one of the following values:
2757 * @arg @ref LL_RCC_SAI1_CLKSOURCE
2758 * @retval Returned value can be one of the following values:
2759 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
2760 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
2761 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
2762 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2763 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)2764 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
2765 {
2766 return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx));
2767 }
2768 #endif /* SAI1 */
2769
2770 /**
2771 * @brief Get RNGx clock source
2772 * @rmtoll CCIPR RNGSEL LL_RCC_GetRNGClockSource
2773 * @param RNGx This parameter can be one of the following values:
2774 * @arg @ref LL_RCC_RNG_CLKSOURCE
2775 * @retval Returned value can be one of the following values:
2776 * @arg @ref LL_RCC_RNG_CLKSOURCE_CLK48
2777 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
2778 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
2779 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)2780 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
2781 {
2782 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
2783 }
2784
2785 /**
2786 * @brief Get CLK48x clock source
2787 * @rmtoll CCIPR CLK48SEL LL_RCC_GetCLK48ClockSource
2788 * @param CLK48x This parameter can be one of the following values:
2789 * @arg @ref LL_RCC_CLK48_CLKSOURCE
2790 * @retval Returned value can be one of the following values:
2791 * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 (*)
2792 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*)
2793 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
2794 * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
2795 * @note (*) Value not defined for all devices
2796 */
LL_RCC_GetCLK48ClockSource(uint32_t CLK48x)2797 __STATIC_INLINE uint32_t LL_RCC_GetCLK48ClockSource(uint32_t CLK48x)
2798 {
2799 return (uint32_t)(READ_BIT(RCC->CCIPR, CLK48x));
2800 }
2801
2802 #if defined(USB)
2803 /**
2804 * @brief Get USBx clock source
2805 * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
2806 * @param USBx This parameter can be one of the following values:
2807 * @arg @ref LL_RCC_USB_CLKSOURCE
2808 * @retval Returned value can be one of the following values:
2809 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
2810 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
2811 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2812 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
2813 */
LL_RCC_GetUSBClockSource(uint32_t USBx)2814 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
2815 {
2816 return LL_RCC_GetCLK48ClockSource(USBx);
2817 }
2818 #endif /* USB */
2819
2820 /**
2821 * @brief Get ADCx clock source
2822 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
2823 * @param ADCx This parameter can be one of the following values:
2824 * @arg @ref LL_RCC_ADC_CLKSOURCE
2825 * @retval Returned value can be one of the following values:
2826 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
2827 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)
2828 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
2829 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2830 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI (*)
2831 * @note (*) Value not defined for all devices
2832 */
LL_RCC_GetADCClockSource(uint32_t ADCx)2833 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
2834 {
2835 return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
2836 }
2837
2838 /**
2839 * @}
2840 */
2841
2842 /** @defgroup RCC_LL_EF_RTC RTC
2843 * @{
2844 */
2845
2846 /**
2847 * @brief Set RTC Clock Source
2848 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
2849 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
2850 * set). The BDRST bit can be used to reset them.
2851 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
2852 * @param Source This parameter can be one of the following values:
2853 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2854 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2855 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2856 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2857 * @retval None
2858 */
LL_RCC_SetRTCClockSource(uint32_t Source)2859 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2860 {
2861 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
2862 }
2863
2864 /**
2865 * @brief Get RTC Clock Source
2866 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
2867 * @retval Returned value can be one of the following values:
2868 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2869 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2870 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2871 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2872 */
LL_RCC_GetRTCClockSource(void)2873 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2874 {
2875 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
2876 }
2877
2878 /**
2879 * @brief Enable RTC
2880 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
2881 * @retval None
2882 */
LL_RCC_EnableRTC(void)2883 __STATIC_INLINE void LL_RCC_EnableRTC(void)
2884 {
2885 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2886 }
2887
2888 /**
2889 * @brief Disable RTC
2890 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2891 * @retval None
2892 */
LL_RCC_DisableRTC(void)2893 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2894 {
2895 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2896 }
2897
2898 /**
2899 * @brief Check if RTC has been enabled or not
2900 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2901 * @retval State of bit (1 or 0).
2902 */
LL_RCC_IsEnabledRTC(void)2903 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2904 {
2905 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
2906 }
2907
2908 /**
2909 * @brief Force the Backup domain reset
2910 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2911 * @retval None
2912 */
LL_RCC_ForceBackupDomainReset(void)2913 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2914 {
2915 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2916 }
2917
2918 /**
2919 * @brief Release the Backup domain reset
2920 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2921 * @retval None
2922 */
LL_RCC_ReleaseBackupDomainReset(void)2923 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2924 {
2925 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2926 }
2927
2928 /**
2929 * @}
2930 */
2931
2932
2933 /** @defgroup RCC_LL_EF_PLL PLL
2934 * @{
2935 */
2936
2937 /**
2938 * @brief Enable PLL
2939 * @rmtoll CR PLLON LL_RCC_PLL_Enable
2940 * @retval None
2941 */
LL_RCC_PLL_Enable(void)2942 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
2943 {
2944 SET_BIT(RCC->CR, RCC_CR_PLLON);
2945 }
2946
2947 /**
2948 * @brief Disable PLL
2949 * @note Cannot be disabled if the PLL clock is used as the system clock
2950 * @rmtoll CR PLLON LL_RCC_PLL_Disable
2951 * @retval None
2952 */
LL_RCC_PLL_Disable(void)2953 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
2954 {
2955 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
2956 }
2957
2958 /**
2959 * @brief Check if PLL Ready
2960 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
2961 * @retval State of bit (1 or 0).
2962 */
LL_RCC_PLL_IsReady(void)2963 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
2964 {
2965 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
2966 }
2967
2968 /**
2969 * @brief Configure PLL used for SYSCLK Domain
2970 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2971 * PLLSAI1 are disabled
2972 * @note PLLN/PLLR can be written only when PLL is disabled
2973 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2974 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
2975 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
2976 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
2977 * @param Source This parameter can be one of the following values:
2978 * @arg @ref LL_RCC_PLLSOURCE_NONE
2979 * @arg @ref LL_RCC_PLLSOURCE_MSI
2980 * @arg @ref LL_RCC_PLLSOURCE_HSI
2981 * @arg @ref LL_RCC_PLLSOURCE_HSE
2982 * @param PLLM This parameter can be one of the following values:
2983 * @arg @ref LL_RCC_PLLM_DIV_1
2984 * @arg @ref LL_RCC_PLLM_DIV_2
2985 * @arg @ref LL_RCC_PLLM_DIV_3
2986 * @arg @ref LL_RCC_PLLM_DIV_4
2987 * @arg @ref LL_RCC_PLLM_DIV_5
2988 * @arg @ref LL_RCC_PLLM_DIV_6
2989 * @arg @ref LL_RCC_PLLM_DIV_7
2990 * @arg @ref LL_RCC_PLLM_DIV_8
2991 * @param PLLN Between 6 and 127
2992 * @param PLLR This parameter can be one of the following values:
2993 * @arg @ref LL_RCC_PLLR_DIV_2
2994 * @arg @ref LL_RCC_PLLR_DIV_4
2995 * @arg @ref LL_RCC_PLLR_DIV_6
2996 * @arg @ref LL_RCC_PLLR_DIV_8
2997 * @retval None
2998 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)2999 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
3000 {
3001 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
3002 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
3003 }
3004
3005 #if defined(SAI1)
3006 /**
3007 * @brief Configure PLL used for SAI domain clock
3008 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3009 * PLLSAI1 are disabled
3010 * @note PLLN/PLLP can be written only when PLL is disabled
3011 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
3012 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
3013 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
3014 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
3015 * @param Source This parameter can be one of the following values:
3016 * @arg @ref LL_RCC_PLLSOURCE_NONE
3017 * @arg @ref LL_RCC_PLLSOURCE_MSI
3018 * @arg @ref LL_RCC_PLLSOURCE_HSI
3019 * @arg @ref LL_RCC_PLLSOURCE_HSE
3020 * @param PLLM This parameter can be one of the following values:
3021 * @arg @ref LL_RCC_PLLM_DIV_1
3022 * @arg @ref LL_RCC_PLLM_DIV_2
3023 * @arg @ref LL_RCC_PLLM_DIV_3
3024 * @arg @ref LL_RCC_PLLM_DIV_4
3025 * @arg @ref LL_RCC_PLLM_DIV_5
3026 * @arg @ref LL_RCC_PLLM_DIV_6
3027 * @arg @ref LL_RCC_PLLM_DIV_7
3028 * @arg @ref LL_RCC_PLLM_DIV_8
3029 * @param PLLN Between 6 and 127
3030 * @param PLLP This parameter can be one of the following values:
3031 * @arg @ref LL_RCC_PLLP_DIV_2
3032 * @arg @ref LL_RCC_PLLP_DIV_3
3033 * @arg @ref LL_RCC_PLLP_DIV_4
3034 * @arg @ref LL_RCC_PLLP_DIV_5
3035 * @arg @ref LL_RCC_PLLP_DIV_6
3036 * @arg @ref LL_RCC_PLLP_DIV_7
3037 * @arg @ref LL_RCC_PLLP_DIV_8
3038 * @arg @ref LL_RCC_PLLP_DIV_9
3039 * @arg @ref LL_RCC_PLLP_DIV_10
3040 * @arg @ref LL_RCC_PLLP_DIV_11
3041 * @arg @ref LL_RCC_PLLP_DIV_12
3042 * @arg @ref LL_RCC_PLLP_DIV_13
3043 * @arg @ref LL_RCC_PLLP_DIV_14
3044 * @arg @ref LL_RCC_PLLP_DIV_15
3045 * @arg @ref LL_RCC_PLLP_DIV_16
3046 * @arg @ref LL_RCC_PLLP_DIV_17
3047 * @arg @ref LL_RCC_PLLP_DIV_18
3048 * @arg @ref LL_RCC_PLLP_DIV_19
3049 * @arg @ref LL_RCC_PLLP_DIV_20
3050 * @arg @ref LL_RCC_PLLP_DIV_21
3051 * @arg @ref LL_RCC_PLLP_DIV_22
3052 * @arg @ref LL_RCC_PLLP_DIV_23
3053 * @arg @ref LL_RCC_PLLP_DIV_24
3054 * @arg @ref LL_RCC_PLLP_DIV_25
3055 * @arg @ref LL_RCC_PLLP_DIV_26
3056 * @arg @ref LL_RCC_PLLP_DIV_27
3057 * @arg @ref LL_RCC_PLLP_DIV_28
3058 * @arg @ref LL_RCC_PLLP_DIV_29
3059 * @arg @ref LL_RCC_PLLP_DIV_30
3060 * @arg @ref LL_RCC_PLLP_DIV_31
3061 * @arg @ref LL_RCC_PLLP_DIV_32
3062 * @retval None
3063 */
LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3064 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3065 {
3066 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
3067 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
3068 }
3069 #endif /* SAI1 */
3070
3071 /**
3072 * @brief Configure PLL used for ADC domain clock
3073 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3074 * PLLSAI1 are disabled
3075 * @note PLLN/PLLP can be written only when PLL is disabled
3076 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC\n
3077 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC\n
3078 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC\n
3079 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_ADC
3080 * @param Source This parameter can be one of the following values:
3081 * @arg @ref LL_RCC_PLLSOURCE_NONE
3082 * @arg @ref LL_RCC_PLLSOURCE_MSI
3083 * @arg @ref LL_RCC_PLLSOURCE_HSI
3084 * @arg @ref LL_RCC_PLLSOURCE_HSE
3085 * @param PLLM This parameter can be one of the following values:
3086 * @arg @ref LL_RCC_PLLM_DIV_1
3087 * @arg @ref LL_RCC_PLLM_DIV_2
3088 * @arg @ref LL_RCC_PLLM_DIV_3
3089 * @arg @ref LL_RCC_PLLM_DIV_4
3090 * @arg @ref LL_RCC_PLLM_DIV_5
3091 * @arg @ref LL_RCC_PLLM_DIV_6
3092 * @arg @ref LL_RCC_PLLM_DIV_7
3093 * @arg @ref LL_RCC_PLLM_DIV_8
3094 * @param PLLN Between 6 and 127
3095 * @param PLLP This parameter can be one of the following values:
3096 * @arg @ref LL_RCC_PLLP_DIV_2
3097 * @arg @ref LL_RCC_PLLP_DIV_3
3098 * @arg @ref LL_RCC_PLLP_DIV_4
3099 * @arg @ref LL_RCC_PLLP_DIV_5
3100 * @arg @ref LL_RCC_PLLP_DIV_6
3101 * @arg @ref LL_RCC_PLLP_DIV_7
3102 * @arg @ref LL_RCC_PLLP_DIV_8
3103 * @arg @ref LL_RCC_PLLP_DIV_9
3104 * @arg @ref LL_RCC_PLLP_DIV_10
3105 * @arg @ref LL_RCC_PLLP_DIV_11
3106 * @arg @ref LL_RCC_PLLP_DIV_12
3107 * @arg @ref LL_RCC_PLLP_DIV_13
3108 * @arg @ref LL_RCC_PLLP_DIV_14
3109 * @arg @ref LL_RCC_PLLP_DIV_15
3110 * @arg @ref LL_RCC_PLLP_DIV_16
3111 * @arg @ref LL_RCC_PLLP_DIV_17
3112 * @arg @ref LL_RCC_PLLP_DIV_18
3113 * @arg @ref LL_RCC_PLLP_DIV_19
3114 * @arg @ref LL_RCC_PLLP_DIV_20
3115 * @arg @ref LL_RCC_PLLP_DIV_21
3116 * @arg @ref LL_RCC_PLLP_DIV_22
3117 * @arg @ref LL_RCC_PLLP_DIV_23
3118 * @arg @ref LL_RCC_PLLP_DIV_24
3119 * @arg @ref LL_RCC_PLLP_DIV_25
3120 * @arg @ref LL_RCC_PLLP_DIV_26
3121 * @arg @ref LL_RCC_PLLP_DIV_27
3122 * @arg @ref LL_RCC_PLLP_DIV_28
3123 * @arg @ref LL_RCC_PLLP_DIV_29
3124 * @arg @ref LL_RCC_PLLP_DIV_30
3125 * @arg @ref LL_RCC_PLLP_DIV_31
3126 * @arg @ref LL_RCC_PLLP_DIV_32
3127 * @retval None
3128 */
LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3129 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3130 {
3131 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
3132 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
3133 }
3134
3135 /**
3136 * @brief Configure PLL used for 48Mhz domain clock
3137 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3138 * PLLSAI1 are disabled
3139 * @note PLLN/PLLQ can be written only when PLL is disabled
3140 * @note This can be selected for USB, RNG
3141 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
3142 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
3143 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
3144 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
3145 * @param Source This parameter can be one of the following values:
3146 * @arg @ref LL_RCC_PLLSOURCE_NONE
3147 * @arg @ref LL_RCC_PLLSOURCE_MSI
3148 * @arg @ref LL_RCC_PLLSOURCE_HSI
3149 * @arg @ref LL_RCC_PLLSOURCE_HSE
3150 * @param PLLM This parameter can be one of the following values:
3151 * @arg @ref LL_RCC_PLLM_DIV_1
3152 * @arg @ref LL_RCC_PLLM_DIV_2
3153 * @arg @ref LL_RCC_PLLM_DIV_3
3154 * @arg @ref LL_RCC_PLLM_DIV_4
3155 * @arg @ref LL_RCC_PLLM_DIV_5
3156 * @arg @ref LL_RCC_PLLM_DIV_6
3157 * @arg @ref LL_RCC_PLLM_DIV_7
3158 * @arg @ref LL_RCC_PLLM_DIV_8
3159 * @param PLLN Between 6 and 127
3160 * @param PLLQ This parameter can be one of the following values:
3161 * @arg @ref LL_RCC_PLLQ_DIV_2
3162 * @arg @ref LL_RCC_PLLQ_DIV_3
3163 * @arg @ref LL_RCC_PLLQ_DIV_4
3164 * @arg @ref LL_RCC_PLLQ_DIV_5
3165 * @arg @ref LL_RCC_PLLQ_DIV_6
3166 * @arg @ref LL_RCC_PLLQ_DIV_7
3167 * @arg @ref LL_RCC_PLLQ_DIV_8
3168 * @retval None
3169 */
LL_RCC_PLL_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)3170 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
3171 {
3172 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
3173 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
3174 }
3175
3176 /**
3177 * @brief Get Main PLL multiplication factor for VCO
3178 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
3179 * @retval Between 6 and 127
3180 */
LL_RCC_PLL_GetN(void)3181 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
3182 {
3183 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
3184 }
3185
3186 /**
3187 * @brief Get Main PLL division factor for PLLP
3188 * @note used for PLLSAI1CLK (SAI1 clock)
3189 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
3190 * @retval Returned value can be one of the following values:
3191 * @arg @ref LL_RCC_PLLP_DIV_2
3192 * @arg @ref LL_RCC_PLLP_DIV_3
3193 * @arg @ref LL_RCC_PLLP_DIV_4
3194 * @arg @ref LL_RCC_PLLP_DIV_5
3195 * @arg @ref LL_RCC_PLLP_DIV_6
3196 * @arg @ref LL_RCC_PLLP_DIV_7
3197 * @arg @ref LL_RCC_PLLP_DIV_8
3198 * @arg @ref LL_RCC_PLLP_DIV_9
3199 * @arg @ref LL_RCC_PLLP_DIV_10
3200 * @arg @ref LL_RCC_PLLP_DIV_11
3201 * @arg @ref LL_RCC_PLLP_DIV_12
3202 * @arg @ref LL_RCC_PLLP_DIV_13
3203 * @arg @ref LL_RCC_PLLP_DIV_14
3204 * @arg @ref LL_RCC_PLLP_DIV_15
3205 * @arg @ref LL_RCC_PLLP_DIV_16
3206 * @arg @ref LL_RCC_PLLP_DIV_17
3207 * @arg @ref LL_RCC_PLLP_DIV_18
3208 * @arg @ref LL_RCC_PLLP_DIV_19
3209 * @arg @ref LL_RCC_PLLP_DIV_20
3210 * @arg @ref LL_RCC_PLLP_DIV_21
3211 * @arg @ref LL_RCC_PLLP_DIV_22
3212 * @arg @ref LL_RCC_PLLP_DIV_23
3213 * @arg @ref LL_RCC_PLLP_DIV_24
3214 * @arg @ref LL_RCC_PLLP_DIV_25
3215 * @arg @ref LL_RCC_PLLP_DIV_26
3216 * @arg @ref LL_RCC_PLLP_DIV_27
3217 * @arg @ref LL_RCC_PLLP_DIV_28
3218 * @arg @ref LL_RCC_PLLP_DIV_29
3219 * @arg @ref LL_RCC_PLLP_DIV_30
3220 * @arg @ref LL_RCC_PLLP_DIV_31
3221 * @arg @ref LL_RCC_PLLP_DIV_32
3222 */
LL_RCC_PLL_GetP(void)3223 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
3224 {
3225 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
3226 }
3227
3228 /**
3229 * @brief Get Main PLL division factor for PLLQ
3230 * @note used for PLL48MCLK selected for USB, RNG (48 MHz clock)
3231 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
3232 * @retval Returned value can be one of the following values:
3233 * @arg @ref LL_RCC_PLLQ_DIV_2
3234 * @arg @ref LL_RCC_PLLQ_DIV_3
3235 * @arg @ref LL_RCC_PLLQ_DIV_4
3236 * @arg @ref LL_RCC_PLLQ_DIV_5
3237 * @arg @ref LL_RCC_PLLQ_DIV_6
3238 * @arg @ref LL_RCC_PLLQ_DIV_7
3239 * @arg @ref LL_RCC_PLLQ_DIV_8
3240 */
LL_RCC_PLL_GetQ(void)3241 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
3242 {
3243 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
3244 }
3245
3246 /**
3247 * @brief Get Main PLL division factor for PLLR
3248 * @note used for PLLCLK (system clock)
3249 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
3250 * @retval Returned value can be one of the following values:
3251 * @arg @ref LL_RCC_PLLR_DIV_2
3252 * @arg @ref LL_RCC_PLLR_DIV_3
3253 * @arg @ref LL_RCC_PLLR_DIV_4
3254 * @arg @ref LL_RCC_PLLR_DIV_5
3255 * @arg @ref LL_RCC_PLLR_DIV_6
3256 * @arg @ref LL_RCC_PLLR_DIV_7
3257 * @arg @ref LL_RCC_PLLR_DIV_8
3258 */
LL_RCC_PLL_GetR(void)3259 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
3260 {
3261 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
3262 }
3263
3264 /**
3265 * @brief Get Division factor for the main PLL and other PLL
3266 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
3267 * @retval Returned value can be one of the following values:
3268 * @arg @ref LL_RCC_PLLM_DIV_1
3269 * @arg @ref LL_RCC_PLLM_DIV_2
3270 * @arg @ref LL_RCC_PLLM_DIV_3
3271 * @arg @ref LL_RCC_PLLM_DIV_4
3272 * @arg @ref LL_RCC_PLLM_DIV_5
3273 * @arg @ref LL_RCC_PLLM_DIV_6
3274 * @arg @ref LL_RCC_PLLM_DIV_7
3275 * @arg @ref LL_RCC_PLLM_DIV_8
3276 */
LL_RCC_PLL_GetDivider(void)3277 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
3278 {
3279 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
3280 }
3281
3282 #if defined(SAI1)
3283 /**
3284 * @brief Enable PLL output mapped on SAI domain clock
3285 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
3286 * @retval None
3287 */
LL_RCC_PLL_EnableDomain_SAI(void)3288 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
3289 {
3290 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3291 }
3292
3293 /**
3294 * @brief Disable PLL output mapped on SAI domain clock
3295 * @note In order to save power, when the PLLCLK of the PLL is
3296 * not used, should be 0
3297 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
3298 * @retval None
3299 */
LL_RCC_PLL_DisableDomain_SAI(void)3300 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
3301 {
3302 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3303 }
3304 #endif /* SAI1 */
3305
3306 /**
3307 * @brief Check if PLL output mapped on SAI domain clock is enabled
3308 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_SAI
3309 * @retval State of bit (1 or 0).
3310 */
LL_RCC_PLL_IsEnabledDomain_SAI(void)3311 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SAI(void)
3312 {
3313 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
3314 }
3315
3316 /**
3317 * @brief Enable PLL output mapped on ADC domain clock
3318 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC
3319 * @retval None
3320 */
LL_RCC_PLL_EnableDomain_ADC(void)3321 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
3322 {
3323 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3324 }
3325
3326 /**
3327 * @brief Disable PLL output mapped on ADC domain clock
3328 * @note In order to save power, when the PLLCLK of the PLL is
3329 * not used, should be 0
3330 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC
3331 * @retval None
3332 */
LL_RCC_PLL_DisableDomain_ADC(void)3333 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void)
3334 {
3335 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3336 }
3337
3338 /**
3339 * @brief Check if PLL output mapped on ADC domain clock is enabled
3340 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_ADC
3341 * @retval State of bit (1 or 0).
3342 */
LL_RCC_PLL_IsEnabledDomain_ADC(void)3343 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void)
3344 {
3345 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
3346 }
3347
3348 /**
3349 * @brief Enable PLL output mapped on 48MHz domain clock
3350 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
3351 * @retval None
3352 */
LL_RCC_PLL_EnableDomain_48M(void)3353 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
3354 {
3355 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3356 }
3357
3358 /**
3359 * @brief Disable PLL output mapped on 48MHz domain clock
3360 * @note In order to save power, when the PLLCLK of the PLL is
3361 * not used, should be 0
3362 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
3363 * @retval None
3364 */
LL_RCC_PLL_DisableDomain_48M(void)3365 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
3366 {
3367 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3368 }
3369
3370 /**
3371 * @brief Check if PLL output mapped on 48MHz domain clock is enabled
3372 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_48M
3373 * @retval State of bit (1 or 0).
3374 */
LL_RCC_PLL_IsEnabledDomain_48M(void)3375 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void)
3376 {
3377 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
3378 }
3379
3380 /**
3381 * @brief Enable PLL output mapped on SYSCLK domain
3382 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
3383 * @retval None
3384 */
LL_RCC_PLL_EnableDomain_SYS(void)3385 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
3386 {
3387 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
3388 }
3389
3390 /**
3391 * @brief Disable PLL output mapped on SYSCLK domain
3392 * @note Cannot be disabled if the PLL clock is used as the system clock
3393 * @note In order to save power, when the PLLCLK of the PLL is
3394 * not used, Main PLL should be 0
3395 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
3396 * @retval None
3397 */
LL_RCC_PLL_DisableDomain_SYS(void)3398 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
3399 {
3400 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
3401 }
3402
3403 /**
3404 * @brief Check if PLL output mapped on SYSCLK domain clock is enabled
3405 * @rmtoll PLLCFGR RCC_PLLCFGR_PLLREN LL_RCC_PLL_LL_RCC_PLL_IsEnabledDomain_SYSIsEnabledDomain_SYS
3406 * @retval State of bit (1 or 0).
3407 */
LL_RCC_PLL_IsEnabledDomain_SYS(void)3408 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
3409 {
3410 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL);
3411 }
3412
3413 /**
3414 * @}
3415 */
3416
3417 #if defined(SAI1)
3418 /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
3419 * @{
3420 */
3421
3422 /**
3423 * @brief Enable PLLSAI1
3424 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
3425 * @retval None
3426 */
LL_RCC_PLLSAI1_Enable(void)3427 __STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
3428 {
3429 SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
3430 }
3431
3432 /**
3433 * @brief Disable PLLSAI1
3434 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
3435 * @retval None
3436 */
LL_RCC_PLLSAI1_Disable(void)3437 __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
3438 {
3439 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
3440 }
3441
3442 /**
3443 * @brief Check if PLLSAI1 Ready
3444 * @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
3445 * @retval State of bit (1 or 0).
3446 */
LL_RCC_PLLSAI1_IsReady(void)3447 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
3448 {
3449 return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) ? 1UL : 0UL);
3450 }
3451
3452 /**
3453 * @brief Configure PLLSAI1 used for 48Mhz domain clock
3454 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3455 * PLLSAI1 are disabled
3456 * @note PLLN/PLLQ can be written only when PLLSAI1 is disabled
3457 * @note This can be selected for USB, RNG
3458 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
3459 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n
3460 * PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_ConfigDomain_48M\n
3461 * PLLSAI1CFGR PLLQ LL_RCC_PLLSAI1_ConfigDomain_48M
3462 * @param Source This parameter can be one of the following values:
3463 * @arg @ref LL_RCC_PLLSOURCE_NONE
3464 * @arg @ref LL_RCC_PLLSOURCE_MSI
3465 * @arg @ref LL_RCC_PLLSOURCE_HSI
3466 * @arg @ref LL_RCC_PLLSOURCE_HSE
3467 * @param PLLM This parameter can be one of the following values:
3468 * @arg @ref LL_RCC_PLLM_DIV_1
3469 * @arg @ref LL_RCC_PLLM_DIV_2
3470 * @arg @ref LL_RCC_PLLM_DIV_3
3471 * @arg @ref LL_RCC_PLLM_DIV_4
3472 * @arg @ref LL_RCC_PLLM_DIV_5
3473 * @arg @ref LL_RCC_PLLM_DIV_6
3474 * @arg @ref LL_RCC_PLLM_DIV_7
3475 * @arg @ref LL_RCC_PLLM_DIV_8
3476 * @param PLLN Between 6 and 127
3477 * @param PLLQ This parameter can be one of the following values:
3478 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
3479 * @arg @ref LL_RCC_PLLSAI1Q_DIV_3
3480 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
3481 * @arg @ref LL_RCC_PLLSAI1Q_DIV_5
3482 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
3483 * @arg @ref LL_RCC_PLLSAI1Q_DIV_7
3484 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
3485 * @retval None
3486 */
LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)3487 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
3488 {
3489 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
3490 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLQ, (PLLN << RCC_PLLSAI1CFGR_PLLN_Pos) | PLLQ);
3491 }
3492
3493 /**
3494 * @brief Configure PLLSAI1 used for SAI domain clock
3495 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3496 * PLLSAI1 are disabled
3497 * @note PLLN/PLLP can be written only when PLLSAI1 is disabled
3498 * @note This can be selected for SAI1 or SAI2 (*)
3499 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
3500 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
3501 * PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_ConfigDomain_SAI\n
3502 * PLLSAI1CFGR PLLP LL_RCC_PLLSAI1_ConfigDomain_SAI
3503 * @param Source This parameter can be one of the following values:
3504 * @arg @ref LL_RCC_PLLSOURCE_NONE
3505 * @arg @ref LL_RCC_PLLSOURCE_MSI
3506 * @arg @ref LL_RCC_PLLSOURCE_HSI
3507 * @arg @ref LL_RCC_PLLSOURCE_HSE
3508 * @param PLLM This parameter can be one of the following values:
3509 * @arg @ref LL_RCC_PLLM_DIV_1
3510 * @arg @ref LL_RCC_PLLM_DIV_2
3511 * @arg @ref LL_RCC_PLLM_DIV_3
3512 * @arg @ref LL_RCC_PLLM_DIV_4
3513 * @arg @ref LL_RCC_PLLM_DIV_5
3514 * @arg @ref LL_RCC_PLLM_DIV_6
3515 * @arg @ref LL_RCC_PLLM_DIV_7
3516 * @arg @ref LL_RCC_PLLM_DIV_8
3517 * @param PLLN Between 6 and 127
3518 * @param PLLP This parameter can be one of the following values:
3519 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
3520 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
3521 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
3522 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
3523 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
3524 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
3525 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
3526 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
3527 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
3528 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
3529 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
3530 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
3531 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
3532 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
3533 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
3534 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
3535 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
3536 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
3537 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
3538 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
3539 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
3540 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
3541 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
3542 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
3543 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
3544 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
3545 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
3546 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
3547 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
3548 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
3549 * @arg @ref LL_RCC_PLLSAI1P_DIV_32
3550 * @retval None
3551 */
LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3552 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3553 {
3554 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
3555 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLP,
3556 (PLLN << RCC_PLLSAI1CFGR_PLLN_Pos) | PLLP);
3557 }
3558
3559 /**
3560 * @brief Configure PLLSAI1 used for ADC domain clock
3561 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3562 * PLLSAI1 are disabled
3563 * @note PLLN/PLLR can be written only when PLLSAI1 is disabled
3564 * @note This can be selected for ADC
3565 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
3566 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n
3567 * PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_ConfigDomain_ADC\n
3568 * PLLSAI1CFGR PLLR LL_RCC_PLLSAI1_ConfigDomain_ADC
3569 * @param Source This parameter can be one of the following values:
3570 * @arg @ref LL_RCC_PLLSOURCE_NONE
3571 * @arg @ref LL_RCC_PLLSOURCE_MSI
3572 * @arg @ref LL_RCC_PLLSOURCE_HSI
3573 * @arg @ref LL_RCC_PLLSOURCE_HSE
3574 * @param PLLM This parameter can be one of the following values:
3575 * @arg @ref LL_RCC_PLLM_DIV_1
3576 * @arg @ref LL_RCC_PLLM_DIV_2
3577 * @arg @ref LL_RCC_PLLM_DIV_3
3578 * @arg @ref LL_RCC_PLLM_DIV_4
3579 * @arg @ref LL_RCC_PLLM_DIV_5
3580 * @arg @ref LL_RCC_PLLM_DIV_6
3581 * @arg @ref LL_RCC_PLLM_DIV_7
3582 * @arg @ref LL_RCC_PLLM_DIV_8
3583 * @param PLLN Between 6 and 127
3584 * @param PLLR This parameter can be one of the following values:
3585 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
3586 * @arg @ref LL_RCC_PLLSAI1R_DIV_3
3587 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
3588 * @arg @ref LL_RCC_PLLSAI1R_DIV_5
3589 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
3590 * @arg @ref LL_RCC_PLLSAI1R_DIV_7
3591 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
3592 * @retval None
3593 */
LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)3594 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
3595 {
3596 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
3597 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLR, (PLLN << RCC_PLLSAI1CFGR_PLLN_Pos) | PLLR);
3598 }
3599
3600 /**
3601 * @brief Get SAI1PLL multiplication factor for VCO
3602 * @rmtoll PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_GetN
3603 * @retval Between 6 and 127
3604 */
LL_RCC_PLLSAI1_GetN(void)3605 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
3606 {
3607 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN) >> RCC_PLLSAI1CFGR_PLLN_Pos);
3608 }
3609
3610 /**
3611 * @brief Get SAI1PLL division factor for PLLSAI1P
3612 * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
3613 * @rmtoll PLLSAI1CFGR PLLP LL_RCC_PLLSAI1_GetP
3614 * @retval Returned value can be one of the following values:
3615 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
3616 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
3617 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
3618 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
3619 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
3620 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
3621 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
3622 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
3623 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
3624 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
3625 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
3626 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
3627 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
3628 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
3629 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
3630 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
3631 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
3632 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
3633 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
3634 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
3635 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
3636 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
3637 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
3638 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
3639 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
3640 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
3641 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
3642 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
3643 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
3644 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
3645 * @arg @ref LL_RCC_PLLSAI1P_DIV_32
3646 */
LL_RCC_PLLSAI1_GetP(void)3647 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
3648 {
3649 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLP));
3650 }
3651
3652 /**
3653 * @brief Get SAI1PLL division factor for PLLQ
3654 * @note used PLL48M2CLK selected for USB, RNG (48 MHz clock)
3655 * @rmtoll PLLSAI1CFGR PLLQ LL_RCC_PLLSAI1_GetQ
3656 * @retval Returned value can be one of the following values:
3657 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
3658 * @arg @ref LL_RCC_PLLSAI1Q_DIV_3
3659 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
3660 * @arg @ref LL_RCC_PLLSAI1Q_DIV_5
3661 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
3662 * @arg @ref LL_RCC_PLLSAI1Q_DIV_7
3663 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
3664 */
LL_RCC_PLLSAI1_GetQ(void)3665 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
3666 {
3667 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQ));
3668 }
3669
3670 /**
3671 * @brief Get PLLSAI1 division factor for PLLSAIR
3672 * @note used for PLLADC1CLK (ADC clock)
3673 * @rmtoll PLLSAI1CFGR PLLR LL_RCC_PLLSAI1_GetR
3674 * @retval Returned value can be one of the following values:
3675 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
3676 * @arg @ref LL_RCC_PLLSAI1R_DIV_3
3677 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
3678 * @arg @ref LL_RCC_PLLSAI1R_DIV_5
3679 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
3680 * @arg @ref LL_RCC_PLLSAI1R_DIV_7
3681 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
3682 */
LL_RCC_PLLSAI1_GetR(void)3683 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
3684 {
3685 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLR));
3686 }
3687
3688
3689 /**
3690 * @brief Enable PLLSAI1 output mapped on SAI domain clock
3691 * @rmtoll PLLSAI1CFGR PLLPEN LL_RCC_PLLSAI1_EnableDomain_SAI
3692 * @retval None
3693 */
LL_RCC_PLLSAI1_EnableDomain_SAI(void)3694 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
3695 {
3696 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLPEN);
3697 }
3698
3699 /**
3700 * @brief Disable PLLSAI1 output mapped on SAI domain clock
3701 * @note In order to save power, when of the PLLSAI1 is
3702 * not used, should be 0
3703 * @rmtoll PLLSAI1CFGR PLLPEN LL_RCC_PLLSAI1_DisableDomain_SAI
3704 * @retval None
3705 */
LL_RCC_PLLSAI1_DisableDomain_SAI(void)3706 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
3707 {
3708 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLPEN);
3709 }
3710
3711 /**
3712 * @brief Check if PLLSAI1 output mapped on SAI domain clock is enabled
3713 * @rmtoll PLLSAI1CFGR PLLPEN LL_RCC_PLLSAI1_IsEnabledDomain_SAI
3714 * @retval State of bit (1 or 0).
3715 */
LL_RCC_PLLSAI1_IsEnabledDomain_SAI(void)3716 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_SAI(void)
3717 {
3718 return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLPEN) == (RCC_PLLSAI1CFGR_PLLPEN)) ? 1UL : 0UL);
3719 }
3720
3721 /**
3722 * @brief Enable PLLSAI1 output mapped on 48MHz domain clock
3723 * @rmtoll PLLSAI1CFGR PLLQEN LL_RCC_PLLSAI1_EnableDomain_48M
3724 * @retval None
3725 */
LL_RCC_PLLSAI1_EnableDomain_48M(void)3726 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
3727 {
3728 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQEN);
3729 }
3730
3731 /**
3732 * @brief Disable PLLSAI1 output mapped on 48MHz domain clock
3733 * @note In order to save power, when of the PLLSAI1 is
3734 * not used, should be 0
3735 * @rmtoll PLLSAI1CFGR PLLQEN LL_RCC_PLLSAI1_DisableDomain_48M
3736 * @retval None
3737 */
LL_RCC_PLLSAI1_DisableDomain_48M(void)3738 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
3739 {
3740 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQEN);
3741 }
3742
3743 /**
3744 * @brief Check if PLLSAI1 output mapped on 48MHz domain clock is enabled
3745 * @rmtoll PLLSAI1CFGR PLLQEN LL_RCC_PLLSAI1_IsEnabledDomain_48M
3746 * @retval State of bit (1 or 0).
3747 */
LL_RCC_PLLSAI1_IsEnabledDomain_48M(void)3748 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_48M(void)
3749 {
3750 return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQEN) == (RCC_PLLSAI1CFGR_PLLQEN)) ? 1UL : 0UL);
3751 }
3752
3753 /**
3754 * @brief Enable PLLSAI1 output mapped on ADC domain clock
3755 * @rmtoll PLLSAI1CFGR PLLREN LL_RCC_PLLSAI1_EnableDomain_ADC
3756 * @retval None
3757 */
LL_RCC_PLLSAI1_EnableDomain_ADC(void)3758 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
3759 {
3760 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLREN);
3761 }
3762
3763 /**
3764 * @brief Disable PLLSAI1 output mapped on ADC domain clock
3765 * @note In order to save power, when of the PLLSAI1 is
3766 * not used, Main PLLSAI1 should be 0
3767 * @rmtoll PLLSAI1CFGR PLLREN LL_RCC_PLLSAI1_DisableDomain_ADC
3768 * @retval None
3769 */
LL_RCC_PLLSAI1_DisableDomain_ADC(void)3770 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
3771 {
3772 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLREN);
3773 }
3774
3775 /**
3776 * @brief Check if PLLSAI1 output mapped on ADC domain clock is enabled
3777 * @rmtoll PLLSAI1CFGR PLLREN LL_RCC_PLLSAI1_IsEnabledDomain_ADC
3778 * @retval State of bit (1 or 0).
3779 */
LL_RCC_PLLSAI1_IsEnabledDomain_ADC(void)3780 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_ADC(void)
3781 {
3782 return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLREN) == (RCC_PLLSAI1CFGR_PLLREN)) ? 1UL : 0UL);
3783 }
3784 #endif /* SAI1 */
3785
3786 /**
3787 * @}
3788 */
3789
3790
3791
3792 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
3793 * @{
3794 */
3795
3796 /**
3797 * @brief Clear LSI1 ready interrupt flag
3798 * @rmtoll CICR LSI1RDYC LL_RCC_ClearFlag_LSI1RDY
3799 * @retval None
3800 */
LL_RCC_ClearFlag_LSI1RDY(void)3801 __STATIC_INLINE void LL_RCC_ClearFlag_LSI1RDY(void)
3802 {
3803 SET_BIT(RCC->CICR, RCC_CICR_LSI1RDYC);
3804 }
3805
3806 /**
3807 * @brief Clear LSI2 ready interrupt flag
3808 * @rmtoll CICR LSI2RDYC LL_RCC_ClearFlag_LSI2RDY
3809 * @retval None
3810 */
LL_RCC_ClearFlag_LSI2RDY(void)3811 __STATIC_INLINE void LL_RCC_ClearFlag_LSI2RDY(void)
3812 {
3813 SET_BIT(RCC->CICR, RCC_CICR_LSI2RDYC);
3814 }
3815
3816 /**
3817 * @brief Clear LSE ready interrupt flag
3818 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
3819 * @retval None
3820 */
LL_RCC_ClearFlag_LSERDY(void)3821 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
3822 {
3823 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
3824 }
3825
3826 /**
3827 * @brief Clear MSI ready interrupt flag
3828 * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
3829 * @retval None
3830 */
LL_RCC_ClearFlag_MSIRDY(void)3831 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
3832 {
3833 SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
3834 }
3835
3836 /**
3837 * @brief Clear HSI ready interrupt flag
3838 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
3839 * @retval None
3840 */
LL_RCC_ClearFlag_HSIRDY(void)3841 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
3842 {
3843 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
3844 }
3845
3846 /**
3847 * @brief Clear HSE ready interrupt flag
3848 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
3849 * @retval None
3850 */
LL_RCC_ClearFlag_HSERDY(void)3851 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
3852 {
3853 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
3854 }
3855
3856 /**
3857 * @brief Configure PLL clock source
3858 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
3859 * @param PLLSource This parameter can be one of the following values:
3860 * @arg @ref LL_RCC_PLLSOURCE_MSI
3861 * @arg @ref LL_RCC_PLLSOURCE_HSI
3862 * @arg @ref LL_RCC_PLLSOURCE_HSE
3863 * @retval None
3864 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)3865 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
3866 {
3867 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
3868 }
3869
3870 /**
3871 * @brief Get the oscillator used as PLL clock source.
3872 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
3873 * @retval Returned value can be one of the following values:
3874 * @arg @ref LL_RCC_PLLSOURCE_NONE
3875 * @arg @ref LL_RCC_PLLSOURCE_MSI
3876 * @arg @ref LL_RCC_PLLSOURCE_HSI
3877 * @arg @ref LL_RCC_PLLSOURCE_HSE
3878 */
LL_RCC_PLL_GetMainSource(void)3879 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
3880 {
3881 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
3882 }
3883
3884 /**
3885 * @brief Clear PLL ready interrupt flag
3886 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
3887 * @retval None
3888 */
LL_RCC_ClearFlag_PLLRDY(void)3889 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
3890 {
3891 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
3892 }
3893
3894 #if defined(RCC_HSI48_SUPPORT)
3895 /**
3896 * @brief Clear HSI48 ready interrupt flag
3897 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
3898 * @retval None
3899 */
LL_RCC_ClearFlag_HSI48RDY(void)3900 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
3901 {
3902 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
3903 }
3904 #endif /* RCC_HSI48_SUPPORT */
3905
3906 #if defined(SAI1)
3907 /**
3908 * @brief Clear PLLSAI1 ready interrupt flag
3909 * @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
3910 * @retval None
3911 */
LL_RCC_ClearFlag_PLLSAI1RDY(void)3912 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
3913 {
3914 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
3915 }
3916 #endif /* SAI1 */
3917
3918 /**
3919 * @brief Clear Clock security system interrupt flag
3920 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
3921 * @retval None
3922 */
LL_RCC_ClearFlag_HSECSS(void)3923 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
3924 {
3925 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
3926 }
3927
3928 /**
3929 * @brief Clear LSE Clock security system interrupt flag
3930 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
3931 * @retval None
3932 */
LL_RCC_ClearFlag_LSECSS(void)3933 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
3934 {
3935 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
3936 }
3937
3938 /**
3939 * @brief Check if LSI1 ready interrupt occurred or not
3940 * @rmtoll CIFR LSI1RDYF LL_RCC_IsActiveFlag_LSI1RDY
3941 * @retval State of bit (1 or 0).
3942 */
LL_RCC_IsActiveFlag_LSI1RDY(void)3943 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI1RDY(void)
3944 {
3945 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI1RDYF) == (RCC_CIFR_LSI1RDYF)) ? 1UL : 0UL);
3946 }
3947
3948 /**
3949 * @brief Check if LSI2 ready interrupt occurred or not
3950 * @rmtoll CIFR LSI2RDYF LL_RCC_IsActiveFlag_LSI2RDY
3951 * @retval State of bit (1 or 0).
3952 */
LL_RCC_IsActiveFlag_LSI2RDY(void)3953 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI2RDY(void)
3954 {
3955 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI2RDYF) == (RCC_CIFR_LSI2RDYF)) ? 1UL : 0UL);
3956 }
3957
3958 /**
3959 * @brief Check if LSE ready interrupt occurred or not
3960 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
3961 * @retval State of bit (1 or 0).
3962 */
LL_RCC_IsActiveFlag_LSERDY(void)3963 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
3964 {
3965 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
3966 }
3967
3968 /**
3969 * @brief Check if MSI ready interrupt occurred or not
3970 * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
3971 * @retval State of bit (1 or 0).
3972 */
LL_RCC_IsActiveFlag_MSIRDY(void)3973 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
3974 {
3975 return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF)) ? 1UL : 0UL);
3976 }
3977
3978 /**
3979 * @brief Check if HSI ready interrupt occurred or not
3980 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
3981 * @retval State of bit (1 or 0).
3982 */
LL_RCC_IsActiveFlag_HSIRDY(void)3983 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
3984 {
3985 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
3986 }
3987
3988 /**
3989 * @brief Check if HSE ready interrupt occurred or not
3990 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
3991 * @retval State of bit (1 or 0).
3992 */
LL_RCC_IsActiveFlag_HSERDY(void)3993 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
3994 {
3995 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
3996 }
3997
3998 /**
3999 * @brief Check if PLL ready interrupt occurred or not
4000 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
4001 * @retval State of bit (1 or 0).
4002 */
LL_RCC_IsActiveFlag_PLLRDY(void)4003 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
4004 {
4005 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
4006 }
4007
4008 #if defined(RCC_HSI48_SUPPORT)
4009 /**
4010 * @brief Check if HSI48 ready interrupt occurred or not
4011 * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
4012 * @retval State of bit (1 or 0).
4013 */
LL_RCC_IsActiveFlag_HSI48RDY(void)4014 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
4015 {
4016 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
4017 }
4018 #endif /* RCC_HSI48_SUPPORT */
4019
4020 #if defined(SAI1)
4021 /**
4022 * @brief Check if PLLSAI1 ready interrupt occurred or not
4023 * @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
4024 * @retval State of bit (1 or 0).
4025 */
LL_RCC_IsActiveFlag_PLLSAI1RDY(void)4026 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
4027 {
4028 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF)) ? 1UL : 0UL);
4029 }
4030 #endif /* SAI1 */
4031
4032 /**
4033 * @brief Check if Clock security system interrupt occurred or not
4034 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
4035 * @retval State of bit (1 or 0).
4036 */
LL_RCC_IsActiveFlag_HSECSS(void)4037 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
4038 {
4039 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
4040 }
4041
4042 /**
4043 * @brief Check if LSE Clock security system interrupt occurred or not
4044 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
4045 * @retval State of bit (1 or 0).
4046 */
LL_RCC_IsActiveFlag_LSECSS(void)4047 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
4048 {
4049 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
4050 }
4051
4052 /**
4053 * @brief Check if HCLK1 prescaler flag value has been applied or not
4054 * @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE
4055 * @retval State of bit (1 or 0).
4056 */
LL_RCC_IsActiveFlag_HPRE(void)4057 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void)
4058 {
4059 return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL);
4060 }
4061
4062 /**
4063 * @brief Check if HCLK2 prescaler flag value has been applied or not
4064 * @rmtoll EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE
4065 * @retval State of bit (1 or 0).
4066 */
LL_RCC_IsActiveFlag_C2HPRE(void)4067 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void)
4068 {
4069 return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL);
4070 }
4071
4072 /**
4073 * @brief Check if HCLK4 prescaler flag value has been applied or not
4074 * @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE
4075 * @retval State of bit (1 or 0).
4076 */
LL_RCC_IsActiveFlag_SHDHPRE(void)4077 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void)
4078 {
4079 return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL);
4080 }
4081
4082
4083 /**
4084 * @brief Check if PLCK1 prescaler flag value has been applied or not
4085 * @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1
4086 * @retval State of bit (1 or 0).
4087 */
LL_RCC_IsActiveFlag_PPRE1(void)4088 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void)
4089 {
4090 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL);
4091 }
4092
4093 /**
4094 * @brief Check if PLCK2 prescaler flag value has been applied or not
4095 * @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2
4096 * @retval State of bit (1 or 0).
4097 */
LL_RCC_IsActiveFlag_PPRE2(void)4098 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void)
4099 {
4100 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL);
4101 }
4102
4103 /**
4104 * @brief Check if RCC flag Independent Watchdog reset is set or not.
4105 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
4106 * @retval State of bit (1 or 0).
4107 */
LL_RCC_IsActiveFlag_IWDGRST(void)4108 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
4109 {
4110 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
4111 }
4112
4113 /**
4114 * @brief Check if RCC flag Low Power reset is set or not.
4115 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
4116 * @retval State of bit (1 or 0).
4117 */
LL_RCC_IsActiveFlag_LPWRRST(void)4118 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
4119 {
4120 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
4121 }
4122
4123 /**
4124 * @brief Check if RCC flag Option byte reset is set or not.
4125 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
4126 * @retval State of bit (1 or 0).
4127 */
LL_RCC_IsActiveFlag_OBLRST(void)4128 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
4129 {
4130 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
4131 }
4132
4133 /**
4134 * @brief Check if RCC flag Pin reset is set or not.
4135 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
4136 * @retval State of bit (1 or 0).
4137 */
LL_RCC_IsActiveFlag_PINRST(void)4138 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
4139 {
4140 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
4141 }
4142
4143 /**
4144 * @brief Check if RCC flag Software reset is set or not.
4145 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
4146 * @retval State of bit (1 or 0).
4147 */
LL_RCC_IsActiveFlag_SFTRST(void)4148 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
4149 {
4150 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
4151 }
4152
4153 /**
4154 * @brief Check if RCC flag Window Watchdog reset is set or not.
4155 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
4156 * @retval State of bit (1 or 0).
4157 */
LL_RCC_IsActiveFlag_WWDGRST(void)4158 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
4159 {
4160 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
4161 }
4162
4163 /**
4164 * @brief Check if RCC flag BOR reset is set or not.
4165 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
4166 * @retval State of bit (1 or 0).
4167 */
LL_RCC_IsActiveFlag_BORRST(void)4168 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
4169 {
4170 return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)) ? 1UL : 0UL);
4171 }
4172
4173 /**
4174 * @brief Set RMVF bit to clear the reset flags.
4175 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
4176 * @retval None
4177 */
LL_RCC_ClearResetFlags(void)4178 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
4179 {
4180 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
4181 }
4182
4183 /**
4184 * @}
4185 */
4186
4187 /** @defgroup RCC_LL_EF_IT_Management IT Management
4188 * @{
4189 */
4190
4191 /**
4192 * @brief Enable LSI1 ready interrupt
4193 * @rmtoll CIER LSI1RDYIE LL_RCC_EnableIT_LSI1RDY
4194 * @retval None
4195 */
LL_RCC_EnableIT_LSI1RDY(void)4196 __STATIC_INLINE void LL_RCC_EnableIT_LSI1RDY(void)
4197 {
4198 SET_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE);
4199 }
4200
4201 /**
4202 * @brief Enable LSI2 ready interrupt
4203 * @rmtoll CIER LSI2RDYIE LL_RCC_EnableIT_LSI2RDY
4204 * @retval None
4205 */
LL_RCC_EnableIT_LSI2RDY(void)4206 __STATIC_INLINE void LL_RCC_EnableIT_LSI2RDY(void)
4207 {
4208 SET_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE);
4209 }
4210 /**
4211 * @brief Enable LSE ready interrupt
4212 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
4213 * @retval None
4214 */
LL_RCC_EnableIT_LSERDY(void)4215 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
4216 {
4217 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
4218 }
4219
4220 /**
4221 * @brief Enable MSI ready interrupt
4222 * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
4223 * @retval None
4224 */
LL_RCC_EnableIT_MSIRDY(void)4225 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
4226 {
4227 SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
4228 }
4229
4230 /**
4231 * @brief Enable HSI ready interrupt
4232 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
4233 * @retval None
4234 */
LL_RCC_EnableIT_HSIRDY(void)4235 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
4236 {
4237 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
4238 }
4239
4240 /**
4241 * @brief Enable HSE ready interrupt
4242 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
4243 * @retval None
4244 */
LL_RCC_EnableIT_HSERDY(void)4245 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
4246 {
4247 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
4248 }
4249
4250 /**
4251 * @brief Enable PLL ready interrupt
4252 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
4253 * @retval None
4254 */
LL_RCC_EnableIT_PLLRDY(void)4255 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
4256 {
4257 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
4258 }
4259
4260 #if defined(RCC_HSI48_SUPPORT)
4261 /**
4262 * @brief Enable HSI48 ready interrupt
4263 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
4264 * @retval None
4265 */
LL_RCC_EnableIT_HSI48RDY(void)4266 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
4267 {
4268 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
4269 }
4270 #endif /* RCC_HSI48_SUPPORT */
4271
4272 #if defined(SAI1)
4273 /**
4274 * @brief Enable PLLSAI1 ready interrupt
4275 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
4276 * @retval None
4277 */
LL_RCC_EnableIT_PLLSAI1RDY(void)4278 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
4279 {
4280 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
4281 }
4282 #endif /* SAI1 */
4283
4284 /**
4285 * @brief Enable LSE clock security system interrupt
4286 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
4287 * @retval None
4288 */
LL_RCC_EnableIT_LSECSS(void)4289 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
4290 {
4291 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
4292 }
4293
4294 /**
4295 * @brief Disable LSI1 ready interrupt
4296 * @rmtoll CIER LSI1RDYIE LL_RCC_DisableIT_LSI1RDY
4297 * @retval None
4298 */
LL_RCC_DisableIT_LSI1RDY(void)4299 __STATIC_INLINE void LL_RCC_DisableIT_LSI1RDY(void)
4300 {
4301 CLEAR_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE);
4302 }
4303
4304 /**
4305 * @brief Disable LSI2 ready interrupt
4306 * @rmtoll CIER LSI2RDYIE LL_RCC_DisableIT_LSI2RDY
4307 * @retval None
4308 */
LL_RCC_DisableIT_LSI2RDY(void)4309 __STATIC_INLINE void LL_RCC_DisableIT_LSI2RDY(void)
4310 {
4311 CLEAR_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE);
4312 }
4313 /**
4314 * @brief Disable LSE ready interrupt
4315 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
4316 * @retval None
4317 */
LL_RCC_DisableIT_LSERDY(void)4318 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
4319 {
4320 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
4321 }
4322
4323 /**
4324 * @brief Disable MSI ready interrupt
4325 * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
4326 * @retval None
4327 */
LL_RCC_DisableIT_MSIRDY(void)4328 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
4329 {
4330 CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
4331 }
4332
4333 /**
4334 * @brief Disable HSI ready interrupt
4335 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
4336 * @retval None
4337 */
LL_RCC_DisableIT_HSIRDY(void)4338 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
4339 {
4340 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
4341 }
4342
4343 /**
4344 * @brief Disable HSE ready interrupt
4345 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
4346 * @retval None
4347 */
LL_RCC_DisableIT_HSERDY(void)4348 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
4349 {
4350 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
4351 }
4352
4353 /**
4354 * @brief Disable PLL ready interrupt
4355 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
4356 * @retval None
4357 */
LL_RCC_DisableIT_PLLRDY(void)4358 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
4359 {
4360 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
4361 }
4362
4363 #if defined(RCC_HSI48_SUPPORT)
4364 /**
4365 * @brief Disable HSI48 ready interrupt
4366 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
4367 * @retval None
4368 */
LL_RCC_DisableIT_HSI48RDY(void)4369 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
4370 {
4371 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
4372 }
4373 #endif /* RCC_HSI48_SUPPORT */
4374
4375 #if defined(SAI1)
4376 /**
4377 * @brief Disable PLLSAI1 ready interrupt
4378 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
4379 * @retval None
4380 */
LL_RCC_DisableIT_PLLSAI1RDY(void)4381 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
4382 {
4383 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
4384 }
4385 #endif /* SAI1 */
4386
4387 /**
4388 * @brief Disable LSE clock security system interrupt
4389 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
4390 * @retval None
4391 */
LL_RCC_DisableIT_LSECSS(void)4392 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
4393 {
4394 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
4395 }
4396
4397 /**
4398 * @brief Checks if LSI1 ready interrupt source is enabled or disabled.
4399 * @rmtoll CIER LSI1RDYIE LL_RCC_IsEnabledIT_LSI1RDY
4400 * @retval State of bit (1 or 0).
4401 */
LL_RCC_IsEnabledIT_LSI1RDY(void)4402 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI1RDY(void)
4403 {
4404 return ((READ_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE) == (RCC_CIER_LSI1RDYIE)) ? 1UL : 0UL);
4405 }
4406
4407 /**
4408 * @brief Checks if LSI2 ready interrupt source is enabled or disabled.
4409 * @rmtoll CIER LSI2RDYIE LL_RCC_IsEnabledIT_LSI2RDY
4410 * @retval State of bit (1 or 0).
4411 */
LL_RCC_IsEnabledIT_LSI2RDY(void)4412 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI2RDY(void)
4413 {
4414 return ((READ_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE) == (RCC_CIER_LSI2RDYIE)) ? 1UL : 0UL);
4415 }
4416 /**
4417 * @brief Checks if LSE ready interrupt source is enabled or disabled.
4418 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
4419 * @retval State of bit (1 or 0).
4420 */
LL_RCC_IsEnabledIT_LSERDY(void)4421 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
4422 {
4423 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
4424 }
4425
4426 /**
4427 * @brief Checks if MSI ready interrupt source is enabled or disabled.
4428 * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
4429 * @retval State of bit (1 or 0).
4430 */
LL_RCC_IsEnabledIT_MSIRDY(void)4431 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
4432 {
4433 return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE)) ? 1UL : 0UL);
4434 }
4435
4436 /**
4437 * @brief Checks if HSI ready interrupt source is enabled or disabled.
4438 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
4439 * @retval State of bit (1 or 0).
4440 */
LL_RCC_IsEnabledIT_HSIRDY(void)4441 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
4442 {
4443 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
4444 }
4445
4446 /**
4447 * @brief Checks if HSE ready interrupt source is enabled or disabled.
4448 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
4449 * @retval State of bit (1 or 0).
4450 */
LL_RCC_IsEnabledIT_HSERDY(void)4451 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
4452 {
4453 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
4454 }
4455
4456 /**
4457 * @brief Checks if PLL ready interrupt source is enabled or disabled.
4458 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
4459 * @retval State of bit (1 or 0).
4460 */
LL_RCC_IsEnabledIT_PLLRDY(void)4461 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
4462 {
4463 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
4464 }
4465
4466 #if defined(RCC_HSI48_SUPPORT)
4467 /**
4468 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
4469 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
4470 * @retval State of bit (1 or 0).
4471 */
LL_RCC_IsEnabledIT_HSI48RDY(void)4472 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
4473 {
4474 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
4475 }
4476 #endif /* RCC_HSI48_SUPPORT */
4477
4478 #if defined(SAI1)
4479 /**
4480 * @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled.
4481 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
4482 * @retval State of bit (1 or 0).
4483 */
LL_RCC_IsEnabledIT_PLLSAI1RDY(void)4484 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
4485 {
4486 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE)) ? 1UL : 0UL);
4487 }
4488 #endif /* SAI1 */
4489
4490 /**
4491 * @brief Checks if LSECSS interrupt source is enabled or disabled.
4492 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
4493 * @retval State of bit (1 or 0).
4494 */
LL_RCC_IsEnabledIT_LSECSS(void)4495 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
4496 {
4497 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)) ? 1UL : 0UL);
4498 }
4499
4500 /**
4501 * @}
4502 */
4503
4504 #if defined(USE_FULL_LL_DRIVER)
4505 /** @defgroup RCC_LL_EF_Init De-initialization function
4506 * @{
4507 */
4508 ErrorStatus LL_RCC_DeInit(void);
4509 /**
4510 * @}
4511 */
4512
4513 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
4514 * @{
4515 */
4516 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
4517 #if defined(RCC_SMPS_SUPPORT)
4518 uint32_t LL_RCC_GetSMPSClockFreq(void);
4519 #endif /* RCC_SMPS_SUPPORT */
4520 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
4521 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
4522 #if defined(LPUART1)
4523 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
4524 #endif /* LPUART1 */
4525 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
4526 #if defined(SAI1)
4527 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
4528 #endif /* SAI1 */
4529 uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource);
4530 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
4531 #if defined(USB)
4532 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
4533 #endif /* USB */
4534 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
4535 uint32_t LL_RCC_GetRTCClockFreq(void);
4536 uint32_t LL_RCC_GetRFWKPClockFreq(void);
4537 /**
4538 * @}
4539 */
4540 #endif /* USE_FULL_LL_DRIVER */
4541
4542 /**
4543 * @}
4544 */
4545
4546 /**
4547 * @}
4548 */
4549
4550 #endif /* RCC */
4551
4552 /**
4553 * @}
4554 */
4555
4556 #ifdef __cplusplus
4557 }
4558 #endif
4559
4560 #endif /* STM32WBxx_LL_RCC_H */
4561
