1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBxx_LL_PWR_H
21 #define STM32WBxx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbxx.h"
29
30 /** @addtogroup STM32WBxx_LL_Driver
31 * @{
32 */
33
34 #if defined(PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
45 * @{
46 */
47
48 #if defined(PWR_CR5_SMPSEN)
49 /** @defgroup PWR_SMPS_Calibration PWR SMPS calibration
50 * @{
51 */
52 #define SMPS_VOLTAGE_CAL_ADDR ((uint32_t*) (0x1FFF7558UL)) /* SMPS output voltage calibration level corresponding to voltage "SMPS_VOLTAGE_CAL_VOLTAGE_MV" */
53 #define SMPS_VOLTAGE_CAL_POS (8UL) /* SMPS output voltage calibration level bitfield position */
54 #define SMPS_VOLTAGE_CAL (0xFUL << SMPS_VOLTAGE_CAL_POS) /* SMPS output voltage calibration level bitfield mask */
55 #define SMPS_VOLTAGE_CAL_VOLTAGE_MV (1500UL) /* SMPS output voltage calibration value (unit: mV) */
56 #define SMPS_VOLTAGE_BASE_MV (1200UL) /* SMPS output voltage base value (unit: mV) */
57 #define SMPS_VOLTAGE_STEP_MV ( 50UL) /* SMPS output voltage step (unit: mV) */
58 /**
59 * @}
60 */
61 #endif /* PWR_CR5_SMPSEN */
62
63 /**
64 * @}
65 */
66
67 /* Private macros ------------------------------------------------------------*/
68
69 /* Exported types ------------------------------------------------------------*/
70 /* Exported constants --------------------------------------------------------*/
71 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
72 * @{
73 */
74
75 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
76 * @brief Flags defines which can be used with LL_PWR_WriteReg function
77 * @{
78 */
79 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF
80 #if defined(PWR_CR3_EWUP2)
81 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
82 #endif /* PWR_CR3_EWUP2 */
83 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
84 #if defined(PWR_CR3_EWUP3)
85 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
86 #endif /* PWR_CR3_EWUP3 */
87 #if defined(PWR_CR3_EWUP2)
88 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
89 #endif /* PWR_CR3_EWUP2 */
90 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
91 #define LL_PWR_SCR_CC2HF PWR_SCR_CC2HF
92 #define LL_PWR_SCR_CBLEAF PWR_SCR_CBLEAF
93 #define LL_PWR_SCR_CCRPEF PWR_SCR_CCRPEF
94 #if defined(PWR_CR3_E802A)
95 #define LL_PWR_SCR_C802AF PWR_SCR_C802AF
96 #define LL_PWR_SCR_C802WUF PWR_SCR_C802WUF
97 #endif /* PWR_CR3_E802A */
98 #define LL_PWR_SCR_CBLEWUF PWR_SCR_CBLEWUF
99 #if defined(PWR_CR5_SMPSEN)
100 #define LL_PWR_SCR_CBORHF PWR_SCR_CBORHF
101 #define LL_PWR_SCR_CSMPSFBF PWR_SCR_CSMPSFBF
102 #endif /* PWR_CR5_SMPSEN */
103 #define LL_PWR_EXTSCR_CCRPF PWR_EXTSCR_CCRPF
104 #define LL_PWR_EXTSCR_C2CSSF PWR_EXTSCR_C2CSSF
105 #define LL_PWR_EXTSCR_C1CSSF PWR_EXTSCR_C1CSSF
106 /**
107 * @}
108 */
109
110 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
111 * @brief Flags defines which can be used with LL_PWR_ReadReg function
112 * @{
113 */
114 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI
115 #if defined(PWR_CR3_EWUP5)
116 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
117 #endif /* PWR_CR3_EWUP5 */
118 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
119 #if defined(PWR_CR3_EWUP3)
120 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
121 #endif /* PWR_CR3_EWUP3 */
122 #if defined(PWR_CR3_EWUP2)
123 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
124 #endif /* PWR_CR3_EWUP2 */
125 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
126 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
127 #if defined(PWR_CR2_PVME1)
128 #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
129 #endif /* PWR_CR2_PVME1 */
130 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO
131 #if defined(PWR_CR1_VOS)
132 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF
133 #endif /* PWR_CR1_VOS */
134 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
135 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
136
137 /* BOR flags */
138 #define LL_PWR_FLAG_BORH PWR_SR1_BORHF /* BORH interrupt flag */
139
140 #if defined(PWR_CR5_SMPSEN)
141 /* SMPS flags */
142 #define LL_PWR_FLAG_SMPS PWR_SR2_SMPSF /* SMPS step down converter ready flag */
143 #define LL_PWR_FLAG_SMPSB PWR_SR2_SMPSBF /* SMPS step down converter in bypass mode flag */
144 #define LL_PWR_FLAG_SMPSFB PWR_SR1_SMPSFB /* SMPS step down converter forced in bypass mode interrupt flag */
145 #endif /* PWR_CR5_SMPSEN */
146
147 /* Radio (BLE or 802.15.4) flags */
148 #define LL_PWR_FLAG_BLEWU PWR_SR1_BLEWUF /* BLE wakeup interrupt flag */
149
150 #define LL_PWR_FLAG_BLEA PWR_SR1_BLEAF /* BLE end of activity interrupt flag */
151 #if defined(PWR_CR3_E802A)
152 #define LL_PWR_FLAG_802WU PWR_SR1_802WUF /* 802.15.4 wakeup interrupt flag */
153 #define LL_PWR_FLAG_802A PWR_SR1_802AF /* 802.15.4 end of activity interrupt flag */
154 #endif /* PWR_CR3_E802A */
155 #define LL_PWR_FLAG_CRPE PWR_SR1_CRPEF /* Critical radio phase end of activity interrupt flag */
156 #define LL_PWR_FLAG_CRP PWR_EXTSCR_CRPF /* Critical radio system phase */
157
158 /* Multicore flags */
159 #define LL_PWR_EXTSCR_C1SBF PWR_EXTSCR_C1SBF /* System standby flag for CPU1 */
160 #define LL_PWR_EXTSCR_C1STOPF PWR_EXTSCR_C1STOPF /* System stop flag for CPU1 */
161 #define LL_PWR_EXTSCR_C1DS PWR_EXTSCR_C1DS /* CPU1 deepsleep mode */
162 #define LL_PWR_EXTSCR_C2SBF PWR_EXTSCR_C2SBF /* System standby flag for CPU2 */
163 #define LL_PWR_EXTSCR_C2STOPF PWR_EXTSCR_C2STOPF /* System stop flag for CPU2 */
164 #define LL_PWR_EXTSCR_C2DS PWR_EXTSCR_C2DS /* CPU2 deepsleep mode */
165 #define LL_PWR_SR1_C2HF PWR_SR1_C2HF /* CPU2 hold interrupt flag */
166 /**
167 * @}
168 */
169
170 #if defined(PWR_CR1_VOS)
171 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
172 * @{
173 */
174 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0) /* Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz. */
175 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1) /* Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz. */
176 /**
177 * @}
178 */
179 #endif /* PWR_CR1_VOS */
180
181 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
182 * @{
183 */
184 #define LL_PWR_MODE_STOP0 (0x000000000U)
185 #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0)
186 #if defined(PWR_SUPPORT_STOP2)
187 #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_1)
188 #endif /* PWR_SUPPORT_STOP2 */
189 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0)
190 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2)
191 /**
192 * @}
193 */
194
195 /** @defgroup PWR_LL_EC_FLASH_LPRUN_POWER_DOWN_MODE Flash power-down mode during low-power run mode
196 * @{
197 */
198 #define LL_PWR_FLASH_LPRUN_MODE_IDLE (0x000000000U)
199 #define LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN (PWR_CR1_FPDR)
200 /**
201 * @}
202 */
203
204 /** @defgroup PWR_LL_EC_FLASH_SLEEP_POWER_DOWN_MODE Flash power-down mode during sleep mode
205 * @{
206 */
207 #define LL_PWR_FLASH_SLEEP_MODE_IDLE (0x000000000U)
208 #define LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN (PWR_CR1_FPDS)
209 /**
210 * @}
211 */
212
213 /** @defgroup PWR_LL_EC_PVM Peripheral voltage monitoring
214 * @{
215 */
216 #if defined(PWR_CR2_PVME1)
217 #define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */
218 #endif /* PWR_CR2_PVME1 */
219 #define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
220 /**
221 * @}
222 */
223
224 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
225 * @{
226 */
227 #define LL_PWR_PVDLEVEL_0 (0x00000000U) /* VPVD0 around 2.0 V */
228 #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_0) /* VPVD1 around 2.2 V */
229 #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_1) /* VPVD2 around 2.4 V */
230 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* VPVD3 around 2.5 V */
231 #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_2) /* VPVD4 around 2.6 V */
232 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0) /* VPVD5 around 2.8 V */
233 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1) /* VPVD6 around 2.9 V */
234 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* External input analog voltage (Compare internally to VREFINT) */
235 /**
236 * @}
237 */
238
239 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
240 * @{
241 */
242 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
243 #if defined(PWR_CR3_EWUP2)
244 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
245 #endif /* PWR_CR3_EWUP2 */
246 #if defined(PWR_CR3_EWUP3)
247 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
248 #endif /* PWR_CR3_EWUP3 */
249 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
250 #if defined(PWR_CR3_EWUP5)
251 #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
252 #endif /* PWR_CR3_EWUP5 */
253 /**
254 * @}
255 */
256
257 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
258 * @{
259 */
260 #define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U)
261 #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
262 /**
263 * @}
264 */
265
266 /** @defgroup PWR_LL_EC_GPIO GPIO
267 * @{
268 */
269 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
270 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
271 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
272 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
273 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
274 #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))
275 /**
276 * @}
277 */
278
279 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
280 * @{
281 */
282 #if defined(PWR_PUCRC_PC0)
283 /* Note: LL_PWR_GPIO_BIT_x defined from port C because all pins are available */
284 /* for PWR pull-up and pull-down. */
285 #define LL_PWR_GPIO_BIT_0 (PWR_PUCRC_PC0)
286 #define LL_PWR_GPIO_BIT_1 (PWR_PUCRC_PC1)
287 #define LL_PWR_GPIO_BIT_2 (PWR_PUCRC_PC2)
288 #define LL_PWR_GPIO_BIT_3 (PWR_PUCRC_PC3)
289 #define LL_PWR_GPIO_BIT_4 (PWR_PUCRC_PC4)
290 #define LL_PWR_GPIO_BIT_5 (PWR_PUCRC_PC5)
291 #define LL_PWR_GPIO_BIT_6 (PWR_PUCRC_PC6)
292 #define LL_PWR_GPIO_BIT_7 (PWR_PUCRC_PC7)
293 #define LL_PWR_GPIO_BIT_8 (PWR_PUCRC_PC8)
294 #define LL_PWR_GPIO_BIT_9 (PWR_PUCRC_PC9)
295 #define LL_PWR_GPIO_BIT_10 (PWR_PUCRC_PC10)
296 #define LL_PWR_GPIO_BIT_11 (PWR_PUCRC_PC11)
297 #define LL_PWR_GPIO_BIT_12 (PWR_PUCRC_PC12)
298 #define LL_PWR_GPIO_BIT_13 (PWR_PUCRC_PC13)
299 #define LL_PWR_GPIO_BIT_14 (PWR_PUCRC_PC14)
300 #define LL_PWR_GPIO_BIT_15 (PWR_PUCRC_PC15)
301 #else
302 #define LL_PWR_GPIO_BIT_0 (PWR_PUCRA_PA0)
303 #define LL_PWR_GPIO_BIT_1 (PWR_PUCRA_PA1)
304 #define LL_PWR_GPIO_BIT_2 (PWR_PUCRA_PA2)
305 #define LL_PWR_GPIO_BIT_3 (PWR_PUCRA_PA3)
306 #define LL_PWR_GPIO_BIT_4 (PWR_PUCRA_PA4)
307 #define LL_PWR_GPIO_BIT_5 (PWR_PUCRA_PA5)
308 #define LL_PWR_GPIO_BIT_6 (PWR_PUCRA_PA6)
309 #define LL_PWR_GPIO_BIT_7 (PWR_PUCRA_PA7)
310 #define LL_PWR_GPIO_BIT_8 (PWR_PUCRA_PA8)
311 #define LL_PWR_GPIO_BIT_9 (PWR_PUCRA_PA9)
312 #define LL_PWR_GPIO_BIT_10 (PWR_PUCRA_PA10)
313 #define LL_PWR_GPIO_BIT_11 (PWR_PUCRA_PA11)
314 #define LL_PWR_GPIO_BIT_12 (PWR_PUCRA_PA12)
315 #define LL_PWR_GPIO_BIT_13 (PWR_PUCRA_PA13)
316 #define LL_PWR_GPIO_BIT_14 (PWR_PUCRC_PC14)
317 #define LL_PWR_GPIO_BIT_15 (PWR_PUCRC_PC15)
318 #endif /* PWR_PUCRC_PC0 */
319 /**
320 * @}
321 */
322
323 #if defined(PWR_CR5_SMPSEN)
324 /** @defgroup PWR_LL_EC_BOR_CONFIGURATION BOR configuration
325 * @{
326 */
327 #define LL_PWR_BOR_SYSTEM_RESET (0x00000000U) /*!< BOR will generate a system reset */
328 #define LL_PWR_BOR_SMPS_FORCE_BYPASS (PWR_CR5_BORHC) /*!< BOR will for SMPS step down converter in bypass mode */
329 /**
330 * @}
331 */
332
333 /** @defgroup PWR_LL_EC_SMPS_OPERATING_MODES SMPS step down converter operating modes
334 * @{
335 */
336 /* Note: Literals values are defined from register SR2 bits SMPSF and SMPSBF */
337 /* but they are also used as register CR5 bits SMPSEN and SMPSBEN, */
338 /* as used by all SMPS operating mode functions targeting different */
339 /* registers: */
340 /* "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()" */
341 /* and "LL_PWR_SMPS_GetEffectiveMode()". */
342 #define LL_PWR_SMPS_BYPASS (PWR_SR2_SMPSBF) /*!< SMPS step down in bypass mode. */
343 #define LL_PWR_SMPS_STEP_DOWN (PWR_SR2_SMPSF) /*!< SMPS step down in step down mode if system low power mode is run, LP run or stop0. If system low power mode is stop1, stop2, standby, shutdown, then SMPS is forced in mode open to preserve energy stored in decoupling capacitor as long as possible. */
344 /**
345 * @}
346 */
347
348 /** @defgroup PWR_LL_EC_SMPS_STARTUP_CURRENT SMPS step down converter supply startup current selection
349 * @{
350 */
351 #define LL_PWR_SMPS_STARTUP_CURRENT_80MA (0x00000000U) /*!< SMPS step down converter supply startup current 80mA */
352 #define LL_PWR_SMPS_STARTUP_CURRENT_100MA ( PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 100mA */
353 #define LL_PWR_SMPS_STARTUP_CURRENT_120MA ( PWR_CR5_SMPSSC_1 ) /*!< SMPS step down converter supply startup current 120mA */
354 #define LL_PWR_SMPS_STARTUP_CURRENT_140MA ( PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 140mA */
355 #define LL_PWR_SMPS_STARTUP_CURRENT_160MA (PWR_CR5_SMPSSC_2 ) /*!< SMPS step down converter supply startup current 160mA */
356 #define LL_PWR_SMPS_STARTUP_CURRENT_180MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 180mA */
357 #define LL_PWR_SMPS_STARTUP_CURRENT_200MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 ) /*!< SMPS step down converter supply startup current 200mA */
358 #define LL_PWR_SMPS_STARTUP_CURRENT_220MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 220mA */
359 /**
360 * @}
361 */
362
363 /** @defgroup PWR_LL_EC_SMPS_OUTPUT_VOLTAGE_LEVEL SMPS step down converter output voltage scaling voltage level
364 * @{
365 */
366 /* Note: SMPS voltage is trimmed during device production to control
367 the actual voltage level variation from device to device. */
368 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20 (0x00000000U) /*!< SMPS step down converter supply output voltage 1.20V */
369 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25 ( PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.25V */
370 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30 ( PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.30V */
371 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35 ( PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.35V */
372 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40 ( PWR_CR5_SMPSVOS_2 ) /*!< SMPS step down converter supply output voltage 1.40V */
373 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.45V */
374 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.50V */
375 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.55V */
376 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60 (PWR_CR5_SMPSVOS_3 ) /*!< SMPS step down converter supply output voltage 1.60V */
377 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.65V */
378 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.70V */
379 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.75V */
380 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 ) /*!< SMPS step down converter supply output voltage 1.80V */
381 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.85V */
382 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.90V */
383 /**
384 * @}
385 */
386 #endif /* PWR_CR5_SMPSEN */
387
388 /**
389 * @}
390 */
391
392 /* Exported macro ------------------------------------------------------------*/
393 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
394 * @{
395 */
396
397 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
398 * @{
399 */
400
401 /**
402 * @brief Write a value in PWR register
403 * @param __REG__ Register to be written
404 * @param __VALUE__ Value to be written in the register
405 * @retval None
406 */
407 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
408
409 /**
410 * @brief Read a value in PWR register
411 * @param __REG__ Register to be read
412 * @retval Register value
413 */
414 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
415 /**
416 * @}
417 */
418
419 /**
420 * @}
421 */
422
423
424 /* Exported functions --------------------------------------------------------*/
425 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
426 * @{
427 */
428
429 /** @defgroup PWR_LL_EF_Configuration Configuration
430 * @{
431 */
432
433 /**
434 * @brief Switch from run main mode to run low-power mode.
435 * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
436 * @retval None
437 */
LL_PWR_EnterLowPowerRunMode(void)438 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
439 {
440 SET_BIT(PWR->CR1, PWR_CR1_LPR);
441 }
442
443 /**
444 * @brief Switch from run main mode to low-power mode.
445 * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
446 * @retval None
447 */
LL_PWR_ExitLowPowerRunMode(void)448 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
449 {
450 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
451 }
452
453 /**
454 * @brief Check if the regulator is in low-power mode
455 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
456 * @retval State of bit (1 or 0).
457 */
LL_PWR_IsEnabledLowPowerRunMode(void)458 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
459 {
460 return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL);
461 }
462
463 #if defined(PWR_CR1_VOS)
464 /**
465 * @brief Set the main internal regulator output voltage
466 * @note A delay is required for the internal regulator to be ready
467 * after the voltage scaling has been changed.
468 * Check whether regulator reached the selected voltage level
469 * can be done using function @ref LL_PWR_IsActiveFlag_VOS().
470 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
471 * @param VoltageScaling This parameter can be one of the following values:
472 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
473 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
474 * @retval None
475 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)476 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
477 {
478 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
479 }
480
481 /**
482 * @brief Get the main internal regulator output voltage
483 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
484 * @retval Returned value can be one of the following values:
485 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
486 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
487 */
LL_PWR_GetRegulVoltageScaling(void)488 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
489 {
490 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
491 }
492 #endif /* PWR_CR1_VOS */
493
494 /**
495 * @brief Enable access to the backup domain
496 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
497 * @retval None
498 */
LL_PWR_EnableBkUpAccess(void)499 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
500 {
501 SET_BIT(PWR->CR1, PWR_CR1_DBP);
502 }
503
504 /**
505 * @brief Disable access to the backup domain
506 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
507 * @retval None
508 */
LL_PWR_DisableBkUpAccess(void)509 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
510 {
511 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
512 }
513
514 /**
515 * @brief Check if the backup domain is enabled
516 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
517 * @retval State of bit (1 or 0).
518 */
LL_PWR_IsEnabledBkUpAccess(void)519 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
520 {
521 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
522 }
523
524 /**
525 * @brief Set Low-Power mode
526 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
527 * @param LowPowerMode This parameter can be one of the following values:
528 * @arg @ref LL_PWR_MODE_STOP0
529 * @arg @ref LL_PWR_MODE_STOP1
530 * @arg @ref LL_PWR_MODE_STOP2 (*)
531 * @arg @ref LL_PWR_MODE_STANDBY
532 * @arg @ref LL_PWR_MODE_SHUTDOWN
533 *
534 * (*) Not available on devices STM32WB15xx, STM32WB10xx, STM32WB1Mxx
535 * @retval None
536 */
LL_PWR_SetPowerMode(uint32_t LowPowerMode)537 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
538 {
539 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
540 }
541
542 /**
543 * @brief Get Low-Power mode
544 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
545 * @retval Returned value can be one of the following values:
546 * @arg @ref LL_PWR_MODE_STOP0
547 * @arg @ref LL_PWR_MODE_STOP1
548 * @arg @ref LL_PWR_MODE_STOP2 (*)
549 * @arg @ref LL_PWR_MODE_STANDBY
550 * @arg @ref LL_PWR_MODE_SHUTDOWN
551 *
552 * (*) Not available on devices STM32WB15xx, STM32WB10xx, STM32WB1Mxx
553 */
LL_PWR_GetPowerMode(void)554 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
555 {
556 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
557 }
558
559 /**
560 * @brief Set flash power-down mode during low-power run mode
561 * @rmtoll CR1 FPDR LL_PWR_SetFlashPowerModeLPRun
562 * @param FlashLowPowerMode This parameter can be one of the following values:
563 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
564 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
565 * @retval None
566 */
LL_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)567 __STATIC_INLINE void LL_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)
568 {
569 /* Unlock bit FPDR */
570 WRITE_REG(PWR->CR1, 0x0000C1B0UL);
571
572 /* Update bit FPDR */
573 MODIFY_REG(PWR->CR1, PWR_CR1_FPDR, FlashLowPowerMode);
574 }
575
576 /**
577 * @brief Get flash power-down mode during low-power run mode
578 * @rmtoll CR1 FPDR LL_PWR_GetFlashPowerModeLPRun
579 * @retval Returned value can be one of the following values:
580 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
581 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
582 */
LL_PWR_GetFlashPowerModeLPRun(void)583 __STATIC_INLINE uint32_t LL_PWR_GetFlashPowerModeLPRun(void)
584 {
585 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_FPDR));
586 }
587
588 /**
589 * @brief Set flash power-down mode during sleep mode
590 * @rmtoll CR1 FPDS LL_PWR_SetFlashPowerModeSleep
591 * @param FlashLowPowerMode This parameter can be one of the following values:
592 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
593 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
594 * @retval None
595 */
LL_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode)596 __STATIC_INLINE void LL_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode)
597 {
598 MODIFY_REG(PWR->CR1, PWR_CR1_FPDS, FlashLowPowerMode);
599 }
600
601 /**
602 * @brief Get flash power-down mode during sleep mode
603 * @rmtoll CR1 FPDS LL_PWR_GetFlashPowerModeSleep
604 * @retval Returned value can be one of the following values:
605 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
606 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
607 */
LL_PWR_GetFlashPowerModeSleep(void)608 __STATIC_INLINE uint32_t LL_PWR_GetFlashPowerModeSleep(void)
609 {
610 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_FPDS));
611 }
612
613 #if defined(PWR_CR2_PVME1)
614 /**
615 * @brief Enable VDDUSB supply
616 * @rmtoll CR2 USV LL_PWR_EnableVddUSB
617 * @retval None
618 */
LL_PWR_EnableVddUSB(void)619 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
620 {
621 SET_BIT(PWR->CR2, PWR_CR2_USV);
622 }
623
624 /**
625 * @brief Disable VDDUSB supply
626 * @rmtoll CR2 USV LL_PWR_DisableVddUSB
627 * @retval None
628 */
LL_PWR_DisableVddUSB(void)629 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
630 {
631 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
632 }
633
634 /**
635 * @brief Check if VDDUSB supply is enabled
636 * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
637 * @retval State of bit (1 or 0).
638 */
LL_PWR_IsEnabledVddUSB(void)639 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
640 {
641 return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL);
642 }
643 #endif
644
645 /**
646 * @brief Enable the Power Voltage Monitoring on a peripheral
647 * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
648 * CR2 PVME3 LL_PWR_EnablePVM
649 * @param PeriphVoltage This parameter can be one of the following values:
650 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
651 * @arg @ref LL_PWR_PVM_VDDA_1_62V
652 *
653 * (*) Not available on devices STM32WB50xx, STM32WB30xx, STM32WB15xx, STM32WB10xx, STM32WB1Mxx
654 * @retval None
655 */
LL_PWR_EnablePVM(uint32_t PeriphVoltage)656 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
657 {
658 SET_BIT(PWR->CR2, PeriphVoltage);
659 }
660
661 /**
662 * @brief Disable the Power Voltage Monitoring on a peripheral
663 * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
664 * CR2 PVME3 LL_PWR_DisablePVM
665 * @param PeriphVoltage This parameter can be one of the following values:
666 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
667 * @arg @ref LL_PWR_PVM_VDDA_1_62V
668 *
669 * (*) Not available on devices STM32WB50xx, STM32WB30xx, STM32WB15xx, STM32WB10xx, STM32WB1Mxx
670 * @retval None
671 */
LL_PWR_DisablePVM(uint32_t PeriphVoltage)672 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
673 {
674 CLEAR_BIT(PWR->CR2, PeriphVoltage);
675 }
676
677 /**
678 * @brief Check if Power Voltage Monitoring is enabled on a peripheral
679 * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
680 * CR2 PVME3 LL_PWR_IsEnabledPVM
681 * @param PeriphVoltage This parameter can be one of the following values:
682 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
683 * @arg @ref LL_PWR_PVM_VDDA_1_62V
684 *
685 * (*) Not available on devices STM32WB50xx, STM32WB30xx, STM32WB15xx, STM32WB10xx, STM32WB1Mxx
686 * @retval State of bit (1 or 0).
687 */
LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)688 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
689 {
690 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL);
691 }
692
693 /**
694 * @brief Configure the voltage threshold detected by the Power Voltage Detector
695 * @rmtoll CR2 PLS LL_PWR_SetPVDLevel
696 * @param PVDLevel This parameter can be one of the following values:
697 * @arg @ref LL_PWR_PVDLEVEL_0
698 * @arg @ref LL_PWR_PVDLEVEL_1
699 * @arg @ref LL_PWR_PVDLEVEL_2
700 * @arg @ref LL_PWR_PVDLEVEL_3
701 * @arg @ref LL_PWR_PVDLEVEL_4
702 * @arg @ref LL_PWR_PVDLEVEL_5
703 * @arg @ref LL_PWR_PVDLEVEL_6
704 * @arg @ref LL_PWR_PVDLEVEL_7
705 * @retval None
706 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)707 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
708 {
709 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
710 }
711
712 /**
713 * @brief Get the voltage threshold detection
714 * @rmtoll CR2 PLS LL_PWR_GetPVDLevel
715 * @retval Returned value can be one of the following values:
716 * @arg @ref LL_PWR_PVDLEVEL_0
717 * @arg @ref LL_PWR_PVDLEVEL_1
718 * @arg @ref LL_PWR_PVDLEVEL_2
719 * @arg @ref LL_PWR_PVDLEVEL_3
720 * @arg @ref LL_PWR_PVDLEVEL_4
721 * @arg @ref LL_PWR_PVDLEVEL_5
722 * @arg @ref LL_PWR_PVDLEVEL_6
723 * @arg @ref LL_PWR_PVDLEVEL_7
724 */
LL_PWR_GetPVDLevel(void)725 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
726 {
727 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
728 }
729
730 /**
731 * @brief Enable Power Voltage Detector
732 * @rmtoll CR2 PVDE LL_PWR_EnablePVD
733 * @retval None
734 */
LL_PWR_EnablePVD(void)735 __STATIC_INLINE void LL_PWR_EnablePVD(void)
736 {
737 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
738 }
739
740 /**
741 * @brief Disable Power Voltage Detector
742 * @rmtoll CR2 PVDE LL_PWR_DisablePVD
743 * @retval None
744 */
LL_PWR_DisablePVD(void)745 __STATIC_INLINE void LL_PWR_DisablePVD(void)
746 {
747 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
748 }
749
750 /**
751 * @brief Check if Power Voltage Detector is enabled
752 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
753 * @retval State of bit (1 or 0).
754 */
LL_PWR_IsEnabledPVD(void)755 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
756 {
757 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL);
758 }
759
760 /**
761 * @brief Enable Internal Wake-up line
762 * @rmtoll CR3 EIWF LL_PWR_EnableInternWU
763 * @retval None
764 */
LL_PWR_EnableInternWU(void)765 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
766 {
767 SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
768 }
769
770 /**
771 * @brief Disable Internal Wake-up line
772 * @rmtoll CR3 EIWF LL_PWR_DisableInternWU
773 * @retval None
774 */
LL_PWR_DisableInternWU(void)775 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
776 {
777 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
778 }
779
780 /**
781 * @brief Check if Internal Wake-up line is enabled
782 * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
783 * @retval State of bit (1 or 0).
784 */
LL_PWR_IsEnabledInternWU(void)785 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
786 {
787 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL);
788 }
789
790 /**
791 * @brief Enable pull-up and pull-down configuration
792 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
793 * @retval None
794 */
LL_PWR_EnablePUPDCfg(void)795 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
796 {
797 SET_BIT(PWR->CR3, PWR_CR3_APC);
798 }
799
800 /**
801 * @brief Disable pull-up and pull-down configuration
802 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
803 * @retval None
804 */
LL_PWR_DisablePUPDCfg(void)805 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
806 {
807 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
808 }
809
810 /**
811 * @brief Check if pull-up and pull-down configuration is enabled
812 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
813 * @retval State of bit (1 or 0).
814 */
LL_PWR_IsEnabledPUPDCfg(void)815 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
816 {
817 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
818 }
819
820 /**
821 * @brief Enable SRAM2a content retention in Standby mode
822 * @note On devices STM32WB15xx, STM32WB10xx, STM32WB1Mxx, retention is extended
823 * to SRAM1, SRAM2a and SRAM2b.
824 * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
825 * @retval None
826 */
LL_PWR_EnableSRAM2Retention(void)827 __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
828 {
829 SET_BIT(PWR->CR3, PWR_CR3_RRS);
830 }
831
832 /**
833 * @brief Disable SRAM2a content retention in Standby mode
834 * @note On devices STM32WB15xx, STM32WB10xx, STM32WB1Mxx, retention is extended
835 * to SRAM1, SRAM2a and SRAM2b.
836 * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
837 * @retval None
838 */
LL_PWR_DisableSRAM2Retention(void)839 __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
840 {
841 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
842 }
843
844 /**
845 * @brief Check if SRAM2 content retention in Standby mode is enabled
846 * @note On devices STM32WB15xx, STM32WB10xx, STM32WB1Mxx, retention is extended
847 * to SRAM1, SRAM2a and SRAM2b.
848 * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
849 * @retval State of bit (1 or 0).
850 */
LL_PWR_IsEnabledSRAM2Retention(void)851 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
852 {
853 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL);
854 }
855
856 /**
857 * @brief Enable the WakeUp PINx functionality
858 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
859 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
860 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
861 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
862 * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
863 * @param WakeUpPin This parameter can be one of the following values:
864 * @arg @ref LL_PWR_WAKEUP_PIN1
865 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
866 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
867 * @arg @ref LL_PWR_WAKEUP_PIN4
868 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
869 *
870 * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx, STM32WB1Mxx
871 * @retval None
872 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)873 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
874 {
875 SET_BIT(PWR->CR3, WakeUpPin);
876 }
877
878 /**
879 * @brief Disable the WakeUp PINx functionality
880 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
881 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
882 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
883 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
884 * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
885 * @param WakeUpPin This parameter can be one of the following values:
886 * @arg @ref LL_PWR_WAKEUP_PIN1
887 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
888 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
889 * @arg @ref LL_PWR_WAKEUP_PIN4
890 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
891 *
892 * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx, STM32WB1Mxx
893 * @retval None
894 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)895 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
896 {
897 CLEAR_BIT(PWR->CR3, WakeUpPin);
898 }
899
900 /**
901 * @brief Check if the WakeUp PINx functionality is enabled
902 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
903 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
904 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
905 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
906 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
907 * @param WakeUpPin This parameter can be one of the following values:
908 * @arg @ref LL_PWR_WAKEUP_PIN1
909 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
910 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
911 * @arg @ref LL_PWR_WAKEUP_PIN4
912 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
913 *
914 * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx, STM32WB1Mxx
915 * @retval State of bit (1 or 0).
916 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)917 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
918 {
919 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
920 }
921
922 /**
923 * @brief Set the resistor impedance
924 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
925 * @param Resistor This parameter can be one of the following values:
926 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
927 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
928 * @retval None
929 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)930 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
931 {
932 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
933 }
934
935 /**
936 * @brief Get the resistor impedance
937 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
938 * @retval Returned value can be one of the following values:
939 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
940 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
941 */
LL_PWR_GetBattChargResistor(void)942 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
943 {
944 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
945 }
946
947 /**
948 * @brief Enable battery charging
949 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
950 * @retval None
951 */
LL_PWR_EnableBatteryCharging(void)952 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
953 {
954 SET_BIT(PWR->CR4, PWR_CR4_VBE);
955 }
956
957 /**
958 * @brief Disable battery charging
959 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
960 * @retval None
961 */
LL_PWR_DisableBatteryCharging(void)962 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
963 {
964 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
965 }
966
967 /**
968 * @brief Check if battery charging is enabled
969 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
970 * @retval State of bit (1 or 0).
971 */
LL_PWR_IsEnabledBatteryCharging(void)972 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
973 {
974 return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL);
975 }
976
977 /**
978 * @brief Set the Wake-Up pin polarity low for the event detection
979 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
980 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
981 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
982 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
983 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
984 * @param WakeUpPin This parameter can be one of the following values:
985 * @arg @ref LL_PWR_WAKEUP_PIN1
986 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
987 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
988 * @arg @ref LL_PWR_WAKEUP_PIN4
989 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
990 *
991 * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx, STM32WB1Mxx
992 * @retval None
993 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)994 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
995 {
996 SET_BIT(PWR->CR4, WakeUpPin);
997 }
998
999 /**
1000 * @brief Set the Wake-Up pin polarity high for the event detection
1001 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
1002 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
1003 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
1004 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
1005 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
1006 * @param WakeUpPin This parameter can be one of the following values:
1007 * @arg @ref LL_PWR_WAKEUP_PIN1
1008 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
1009 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1010 * @arg @ref LL_PWR_WAKEUP_PIN4
1011 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1012 *
1013 * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx, STM32WB1Mxx
1014 * @retval None
1015 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)1016 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1017 {
1018 CLEAR_BIT(PWR->CR4, WakeUpPin);
1019 }
1020
1021 /**
1022 * @brief Get the Wake-Up pin polarity for the event detection
1023 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
1024 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
1025 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
1026 * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
1027 * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
1028 * @param WakeUpPin This parameter can be one of the following values:
1029 * @arg @ref LL_PWR_WAKEUP_PIN1
1030 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
1031 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1032 * @arg @ref LL_PWR_WAKEUP_PIN4
1033 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1034 *
1035 * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx, STM32WB1Mxx
1036 * @retval State of bit (1 or 0).
1037 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)1038 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1039 {
1040 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1041 }
1042
1043 /**
1044 * @brief Enable GPIO pull-up state in Standby and Shutdown modes
1045 * @note Some pins are not configurable for pulling in Standby and Shutdown
1046 * modes. Refer to reference manual for available pins and ports.
1047 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
1048 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
1049 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
1050 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
1051 * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
1052 * PUCRH PU0-15 LL_PWR_EnableGPIOPullUp
1053 * @param GPIO This parameter can be one of the following values:
1054 * @arg @ref LL_PWR_GPIO_A
1055 * @arg @ref LL_PWR_GPIO_B
1056 * @arg @ref LL_PWR_GPIO_C
1057 * @arg @ref LL_PWR_GPIO_D
1058 * @arg @ref LL_PWR_GPIO_E
1059 * @arg @ref LL_PWR_GPIO_H
1060 * @param GPIONumber This parameter can be one of the following values:
1061 * @arg @ref LL_PWR_GPIO_BIT_0
1062 * @arg @ref LL_PWR_GPIO_BIT_1
1063 * @arg @ref LL_PWR_GPIO_BIT_2
1064 * @arg @ref LL_PWR_GPIO_BIT_3
1065 * @arg @ref LL_PWR_GPIO_BIT_4
1066 * @arg @ref LL_PWR_GPIO_BIT_5
1067 * @arg @ref LL_PWR_GPIO_BIT_6
1068 * @arg @ref LL_PWR_GPIO_BIT_7
1069 * @arg @ref LL_PWR_GPIO_BIT_8
1070 * @arg @ref LL_PWR_GPIO_BIT_9
1071 * @arg @ref LL_PWR_GPIO_BIT_10
1072 * @arg @ref LL_PWR_GPIO_BIT_11
1073 * @arg @ref LL_PWR_GPIO_BIT_12
1074 * @arg @ref LL_PWR_GPIO_BIT_13
1075 * @arg @ref LL_PWR_GPIO_BIT_14
1076 * @arg @ref LL_PWR_GPIO_BIT_15
1077 * @retval None
1078 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1079 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1080 {
1081 SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1082 }
1083
1084 /**
1085 * @brief Disable GPIO pull-up state in Standby and Shutdown modes
1086 * @note Some pins are not configurable for pulling in Standby and Shutdown
1087 * modes. Refer to reference manual for available pins and ports.
1088 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
1089 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
1090 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
1091 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
1092 * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
1093 * PUCRH PU0-15 LL_PWR_DisableGPIOPullUp
1094 * @param GPIO This parameter can be one of the following values:
1095 * @arg @ref LL_PWR_GPIO_A
1096 * @arg @ref LL_PWR_GPIO_B
1097 * @arg @ref LL_PWR_GPIO_C
1098 * @arg @ref LL_PWR_GPIO_D
1099 * @arg @ref LL_PWR_GPIO_E
1100 * @arg @ref LL_PWR_GPIO_H
1101 * @param GPIONumber This parameter can be one of the following values:
1102 * @arg @ref LL_PWR_GPIO_BIT_0
1103 * @arg @ref LL_PWR_GPIO_BIT_1
1104 * @arg @ref LL_PWR_GPIO_BIT_2
1105 * @arg @ref LL_PWR_GPIO_BIT_3
1106 * @arg @ref LL_PWR_GPIO_BIT_4
1107 * @arg @ref LL_PWR_GPIO_BIT_5
1108 * @arg @ref LL_PWR_GPIO_BIT_6
1109 * @arg @ref LL_PWR_GPIO_BIT_7
1110 * @arg @ref LL_PWR_GPIO_BIT_8
1111 * @arg @ref LL_PWR_GPIO_BIT_9
1112 * @arg @ref LL_PWR_GPIO_BIT_10
1113 * @arg @ref LL_PWR_GPIO_BIT_11
1114 * @arg @ref LL_PWR_GPIO_BIT_12
1115 * @arg @ref LL_PWR_GPIO_BIT_13
1116 * @arg @ref LL_PWR_GPIO_BIT_14
1117 * @arg @ref LL_PWR_GPIO_BIT_15
1118 * @retval None
1119 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1120 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1121 {
1122 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1123 }
1124
1125 /**
1126 * @brief Check if GPIO pull-up state is enabled
1127 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1128 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1129 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1130 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1131 * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1132 * PUCRH PU0-15 LL_PWR_IsEnabledGPIOPullUp
1133 * @param GPIO This parameter can be one of the following values:
1134 * @arg @ref LL_PWR_GPIO_A
1135 * @arg @ref LL_PWR_GPIO_B
1136 * @arg @ref LL_PWR_GPIO_C
1137 * @arg @ref LL_PWR_GPIO_D
1138 * @arg @ref LL_PWR_GPIO_E
1139 * @arg @ref LL_PWR_GPIO_H
1140 * @param GPIONumber This parameter can be one of the following values:
1141 * @arg @ref LL_PWR_GPIO_BIT_0
1142 * @arg @ref LL_PWR_GPIO_BIT_1
1143 * @arg @ref LL_PWR_GPIO_BIT_2
1144 * @arg @ref LL_PWR_GPIO_BIT_3
1145 * @arg @ref LL_PWR_GPIO_BIT_4
1146 * @arg @ref LL_PWR_GPIO_BIT_5
1147 * @arg @ref LL_PWR_GPIO_BIT_6
1148 * @arg @ref LL_PWR_GPIO_BIT_7
1149 * @arg @ref LL_PWR_GPIO_BIT_8
1150 * @arg @ref LL_PWR_GPIO_BIT_9
1151 * @arg @ref LL_PWR_GPIO_BIT_10
1152 * @arg @ref LL_PWR_GPIO_BIT_11
1153 * @arg @ref LL_PWR_GPIO_BIT_12
1154 * @arg @ref LL_PWR_GPIO_BIT_13
1155 * @arg @ref LL_PWR_GPIO_BIT_14
1156 * @arg @ref LL_PWR_GPIO_BIT_15
1157 * @retval State of bit (1 or 0).
1158 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1159 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1160 {
1161 return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1162 }
1163
1164 /**
1165 * @brief Enable GPIO pull-down state in Standby and Shutdown modes
1166 * @note Some pins are not configurable for pulling in Standby and Shutdown
1167 * modes. Refer to reference manual for available pins and ports.
1168 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
1169 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
1170 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
1171 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
1172 * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
1173 * PDCRH PD0-15 LL_PWR_EnableGPIOPullDown
1174 * @param GPIO This parameter can be one of the following values:
1175 * @arg @ref LL_PWR_GPIO_A
1176 * @arg @ref LL_PWR_GPIO_B
1177 * @arg @ref LL_PWR_GPIO_C
1178 * @arg @ref LL_PWR_GPIO_D
1179 * @arg @ref LL_PWR_GPIO_E
1180 * @arg @ref LL_PWR_GPIO_H
1181 * @param GPIONumber This parameter can be one of the following values:
1182 * @arg @ref LL_PWR_GPIO_BIT_0
1183 * @arg @ref LL_PWR_GPIO_BIT_1
1184 * @arg @ref LL_PWR_GPIO_BIT_2
1185 * @arg @ref LL_PWR_GPIO_BIT_3
1186 * @arg @ref LL_PWR_GPIO_BIT_4
1187 * @arg @ref LL_PWR_GPIO_BIT_5
1188 * @arg @ref LL_PWR_GPIO_BIT_6
1189 * @arg @ref LL_PWR_GPIO_BIT_7
1190 * @arg @ref LL_PWR_GPIO_BIT_8
1191 * @arg @ref LL_PWR_GPIO_BIT_9
1192 * @arg @ref LL_PWR_GPIO_BIT_10
1193 * @arg @ref LL_PWR_GPIO_BIT_11
1194 * @arg @ref LL_PWR_GPIO_BIT_12
1195 * @arg @ref LL_PWR_GPIO_BIT_13
1196 * @arg @ref LL_PWR_GPIO_BIT_14
1197 * @arg @ref LL_PWR_GPIO_BIT_15
1198 * @retval None
1199 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1200 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1201 {
1202 SET_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber);
1203 }
1204
1205 /**
1206 * @brief Disable GPIO pull-down state in Standby and Shutdown modes
1207 * @note Some pins are not configurable for pulling in Standby and Shutdown
1208 * modes. Refer to reference manual for available pins and ports.
1209 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
1210 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
1211 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
1212 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
1213 * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
1214 * PDCRH PD0-15 LL_PWR_DisableGPIOPullDown
1215 * @param GPIO This parameter can be one of the following values:
1216 * @arg @ref LL_PWR_GPIO_A
1217 * @arg @ref LL_PWR_GPIO_B
1218 * @arg @ref LL_PWR_GPIO_C
1219 * @arg @ref LL_PWR_GPIO_D
1220 * @arg @ref LL_PWR_GPIO_E
1221 * @arg @ref LL_PWR_GPIO_H
1222 * @param GPIONumber This parameter can be one of the following values:
1223 * @arg @ref LL_PWR_GPIO_BIT_0
1224 * @arg @ref LL_PWR_GPIO_BIT_1
1225 * @arg @ref LL_PWR_GPIO_BIT_2
1226 * @arg @ref LL_PWR_GPIO_BIT_3
1227 * @arg @ref LL_PWR_GPIO_BIT_4
1228 * @arg @ref LL_PWR_GPIO_BIT_5
1229 * @arg @ref LL_PWR_GPIO_BIT_6
1230 * @arg @ref LL_PWR_GPIO_BIT_7
1231 * @arg @ref LL_PWR_GPIO_BIT_8
1232 * @arg @ref LL_PWR_GPIO_BIT_9
1233 * @arg @ref LL_PWR_GPIO_BIT_10
1234 * @arg @ref LL_PWR_GPIO_BIT_11
1235 * @arg @ref LL_PWR_GPIO_BIT_12
1236 * @arg @ref LL_PWR_GPIO_BIT_13
1237 * @arg @ref LL_PWR_GPIO_BIT_14
1238 * @arg @ref LL_PWR_GPIO_BIT_15
1239 * @retval None
1240 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1241 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1242 {
1243 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber);
1244 }
1245
1246 /**
1247 * @brief Check if GPIO pull-down state is enabled
1248 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1249 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1250 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1251 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1252 * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1253 * PDCRH PD0-15 LL_PWR_IsEnabledGPIOPullDown
1254 * @param GPIO This parameter can be one of the following values:
1255 * @arg @ref LL_PWR_GPIO_A
1256 * @arg @ref LL_PWR_GPIO_B
1257 * @arg @ref LL_PWR_GPIO_C
1258 * @arg @ref LL_PWR_GPIO_D
1259 * @arg @ref LL_PWR_GPIO_E
1260 * @arg @ref LL_PWR_GPIO_H
1261 * @param GPIONumber This parameter can be one of the following values:
1262 * @arg @ref LL_PWR_GPIO_BIT_0
1263 * @arg @ref LL_PWR_GPIO_BIT_1
1264 * @arg @ref LL_PWR_GPIO_BIT_2
1265 * @arg @ref LL_PWR_GPIO_BIT_3
1266 * @arg @ref LL_PWR_GPIO_BIT_4
1267 * @arg @ref LL_PWR_GPIO_BIT_5
1268 * @arg @ref LL_PWR_GPIO_BIT_6
1269 * @arg @ref LL_PWR_GPIO_BIT_7
1270 * @arg @ref LL_PWR_GPIO_BIT_8
1271 * @arg @ref LL_PWR_GPIO_BIT_9
1272 * @arg @ref LL_PWR_GPIO_BIT_10
1273 * @arg @ref LL_PWR_GPIO_BIT_11
1274 * @arg @ref LL_PWR_GPIO_BIT_12
1275 * @arg @ref LL_PWR_GPIO_BIT_13
1276 * @arg @ref LL_PWR_GPIO_BIT_14
1277 * @arg @ref LL_PWR_GPIO_BIT_15
1278 * @retval State of bit (1 or 0).
1279 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1280 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1281 {
1282 return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1283 }
1284
1285 #if defined(PWR_CR5_SMPSEN)
1286 /**
1287 * @brief Set BOR configuration
1288 * @rmtoll CR5 BORHC LL_PWR_SetBORConfig
1289 * @param BORConfiguration This parameter can be one of the following values:
1290 * @arg @ref LL_PWR_BOR_SYSTEM_RESET
1291 * @arg @ref LL_PWR_BOR_SMPS_FORCE_BYPASS
1292 */
LL_PWR_SetBORConfig(uint32_t BORConfiguration)1293 __STATIC_INLINE void LL_PWR_SetBORConfig(uint32_t BORConfiguration)
1294 {
1295 MODIFY_REG(PWR->CR5, PWR_CR5_BORHC, BORConfiguration);
1296 }
1297
1298 /**
1299 * @brief Get BOR configuration
1300 * @rmtoll CR5 BORHC LL_PWR_GetBORConfig
1301 * @retval Returned value can be one of the following values:
1302 * @arg @ref LL_PWR_BOR_SYSTEM_RESET
1303 * @arg @ref LL_PWR_BOR_SMPS_FORCE_BYPASS
1304 */
LL_PWR_GetBORConfig(void)1305 __STATIC_INLINE uint32_t LL_PWR_GetBORConfig(void)
1306 {
1307 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_BORHC));
1308 }
1309 #endif /* PWR_CR5_SMPSEN */
1310
1311 /**
1312 * @}
1313 */
1314
1315 #if defined(PWR_CR5_SMPSEN)
1316 /** @defgroup PWR_LL_EF_Configuration_SMPS Configuration of SMPS
1317 * @{
1318 */
1319
1320 /**
1321 * @brief Set SMPS operating mode
1322 * @note When SMPS step down converter SMPS mode is enabled,
1323 * it is good practice to enable the BORH to monitor the supply:
1324 * in this case, when the supply drops below the SMPS step down
1325 * converter SMPS mode operating supply level,
1326 * switching on the fly is performed automaticcaly
1327 * and interruption is generated.
1328 * Refer to function @ref LL_PWR_SetBORConfig().
1329 * @note Occurrence of SMPS step down converter forced in bypass mode
1330 * can be monitored by flag and interruption.
1331 * Refer to functions
1332 * @ref LL_PWR_IsActiveFlag_SMPSFB(), @ref LL_PWR_ClearFlag_SMPSFB(),
1333 * @ref LL_PWR_EnableIT_BORH_SMPSFB().
1334 * @rmtoll CR5 SMPSEN LL_PWR_SMPS_SetMode \n
1335 * CR5 SMPSBEN LL_PWR_SMPS_SetMode
1336 * @param OperatingMode This parameter can be one of the following values:
1337 * @arg @ref LL_PWR_SMPS_BYPASS
1338 * @arg @ref LL_PWR_SMPS_STEP_DOWN (1)
1339 *
1340 * (1) SMPS operating mode step down or open depends on system low-power mode:
1341 * - step down mode if system low power mode is run, LP run or stop0,
1342 * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
1343 * @retval None
1344 */
LL_PWR_SMPS_SetMode(uint32_t OperatingMode)1345 __STATIC_INLINE void LL_PWR_SMPS_SetMode(uint32_t OperatingMode)
1346 {
1347 /* Note: Operation on bits performed to keep compatibility of literals */
1348 /* for all SMPS operating mode functions: */
1349 /* "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()" */
1350 /* and "LL_PWR_SMPS_GetEffectiveMode()". */
1351 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSEN, (OperatingMode & PWR_SR2_SMPSF) << (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSF_Pos));
1352 }
1353
1354 /**
1355 * @brief Get SMPS operating mode
1356 * @rmtoll CR5 SMPSEN LL_PWR_SMPS_GetMode \n
1357 * CR5 SMPSBEN LL_PWR_SMPS_GetMode
1358 * @retval Returned value can be one of the following values:
1359 * @arg @ref LL_PWR_SMPS_BYPASS
1360 * @arg @ref LL_PWR_SMPS_STEP_DOWN (1)
1361 *
1362 * (1) SMPS operating mode step down or open depends on system low-power mode:
1363 * - step down mode if system low power mode is run, LP run or stop0,
1364 * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
1365 */
LL_PWR_SMPS_GetMode(void)1366 __STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void)
1367 {
1368 /* Note: Operation on bits performed to keep compatibility of literals */
1369 /* for all SMPS operating mode functions: */
1370 /* "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()" */
1371 /* and "LL_PWR_SMPS_GetEffectiveMode()". */
1372 uint32_t OperatingMode = (READ_BIT(PWR->CR5, PWR_CR5_SMPSEN) >> (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSF_Pos));
1373
1374 OperatingMode = (OperatingMode | ((~OperatingMode >> 1U) & PWR_SR2_SMPSBF));
1375
1376 return OperatingMode;
1377 }
1378
1379 /**
1380 * @brief Get SMPS effective operating mode
1381 * @note SMPS operating mode can be changed by hardware, therefore
1382 * requested operating mode can differ from effective low power mode.
1383 * - dependency on system low-power mode:
1384 * - step down mode if system low power mode is run, LP run or stop0,
1385 * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
1386 * - dependency on BOR level:
1387 * - bypass mode if supply voltage drops below BOR level
1388 * @note This functions check flags of SMPS operating modes step down
1389 * and bypass. If the SMPS is not among these 2 operating modes,
1390 * then it can be in mode off or open.
1391 * @rmtoll SR2 SMPSF LL_PWR_SMPS_GetEffectiveMode \n
1392 * SR2 SMPSBF LL_PWR_SMPS_GetEffectiveMode
1393 * @retval Returned value can be one of the following values:
1394 * @arg @ref LL_PWR_SMPS_BYPASS
1395 * @arg @ref LL_PWR_SMPS_STEP_DOWN (1)
1396 *
1397 * (1) SMPS operating mode step down or open depends on system low-power mode:
1398 * - step down mode if system low power mode is run, LP run or stop0,
1399 * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
1400 */
LL_PWR_SMPS_GetEffectiveMode(void)1401 __STATIC_INLINE uint32_t LL_PWR_SMPS_GetEffectiveMode(void)
1402 {
1403 return (uint32_t)(READ_BIT(PWR->SR2, (PWR_SR2_SMPSF | PWR_SR2_SMPSBF)));
1404 }
1405
1406 /**
1407 * @brief SMPS step down converter enable
1408 * @note This function can be used for specific usage of the SMPS,
1409 * for general usage of the SMPS the function
1410 * @ref LL_PWR_SMPS_SetMode() should be used instead.
1411 * @rmtoll CR5 SMPSEN LL_PWR_SMPS_Enable
1412 * @retval None
1413 */
LL_PWR_SMPS_Enable(void)1414 __STATIC_INLINE void LL_PWR_SMPS_Enable(void)
1415 {
1416 SET_BIT(PWR->CR5, PWR_CR5_SMPSEN);
1417 }
1418
1419 /**
1420 * @brief SMPS step down converter enable
1421 * @note This function can be used for specific usage of the SMPS,
1422 * for general usage of the SMPS the function
1423 * @ref LL_PWR_SMPS_SetMode() should be used instead.
1424 * @rmtoll CR5 SMPSEN LL_PWR_SMPS_Disable
1425 * @retval None
1426 */
LL_PWR_SMPS_Disable(void)1427 __STATIC_INLINE void LL_PWR_SMPS_Disable(void)
1428 {
1429 CLEAR_BIT(PWR->CR5, PWR_CR5_SMPSEN);
1430 }
1431
1432 /**
1433 * @brief Check if the SMPS step down converter is enabled
1434 * @rmtoll CR5 SMPSEN LL_PWR_SMPS_IsEnabled
1435 * @retval State of bit (1 or 0).
1436 */
LL_PWR_SMPS_IsEnabled(void)1437 __STATIC_INLINE uint32_t LL_PWR_SMPS_IsEnabled(void)
1438 {
1439 return ((READ_BIT(PWR->CR5, PWR_CR5_SMPSEN) == (PWR_CR5_SMPSEN)) ? 1UL : 0UL);
1440 }
1441
1442 /**
1443 * @brief Set SMPS step down converter supply startup current selection
1444 * @rmtoll CR5 SMPSSC LL_PWR_SMPS_SetStartupCurrent
1445 * @param StartupCurrent This parameter can be one of the following values:
1446 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_80MA
1447 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_100MA
1448 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_120MA
1449 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_140MA
1450 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_160MA
1451 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_180MA
1452 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_200MA
1453 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_220MA
1454 * @retval None
1455 */
LL_PWR_SMPS_SetStartupCurrent(uint32_t StartupCurrent)1456 __STATIC_INLINE void LL_PWR_SMPS_SetStartupCurrent(uint32_t StartupCurrent)
1457 {
1458 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSSC, StartupCurrent);
1459 }
1460
1461 /**
1462 * @brief Get SMPS step down converter supply startup current selection
1463 * @rmtoll CR5 SMPSSC LL_PWR_SMPS_GetStartupCurrent
1464 * @retval Returned value can be one of the following values:
1465 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_80MA
1466 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_100MA
1467 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_120MA
1468 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_140MA
1469 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_160MA
1470 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_180MA
1471 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_200MA
1472 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_220MA
1473 */
LL_PWR_SMPS_GetStartupCurrent(void)1474 __STATIC_INLINE uint32_t LL_PWR_SMPS_GetStartupCurrent(void)
1475 {
1476 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSSC));
1477 }
1478
1479 /**
1480 * @brief Set SMPS step down converter output voltage scaling
1481 * @note SMPS output voltage is calibrated in production,
1482 * calibration parameters are applied to the voltage level parameter
1483 * to reach the requested voltage value.
1484 * @rmtoll CR5 SMPSVOS LL_PWR_SMPS_SetOutputVoltageLevel
1485 * @param OutputVoltageLevel This parameter can be one of the following values:
1486 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20
1487 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25
1488 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30
1489 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35
1490 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40
1491 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45
1492 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50
1493 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55
1494 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60
1495 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65
1496 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70
1497 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75
1498 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80
1499 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85
1500 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90
1501 * @retval None
1502 */
LL_PWR_SMPS_SetOutputVoltageLevel(uint32_t OutputVoltageLevel)1503 __STATIC_INLINE void LL_PWR_SMPS_SetOutputVoltageLevel(uint32_t OutputVoltageLevel)
1504 {
1505 __IO const uint32_t OutputVoltageLevel_calibration = (((*SMPS_VOLTAGE_CAL_ADDR) & SMPS_VOLTAGE_CAL) >> SMPS_VOLTAGE_CAL_POS); /* SMPS output voltage level calibrated in production */
1506 int32_t TrimmingSteps; /* Trimming steps between theoretical output voltage and calibrated output voltage */
1507 int32_t OutputVoltageLevelTrimmed; /* SMPS output voltage level after calibration: trimming value added to required level */
1508
1509 if (OutputVoltageLevel_calibration == 0UL)
1510 {
1511 /* Device with SMPS output voltage not calibrated in production: Apply output voltage value directly */
1512
1513 /* Update register */
1514 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSVOS, OutputVoltageLevel);
1515 }
1516 else
1517 {
1518 /* Device with SMPS output voltage calibrated in production: Apply output voltage value after correction by calibration value */
1519
1520 TrimmingSteps = ((int32_t)OutputVoltageLevel_calibration - (int32_t)(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 >> PWR_CR5_SMPSVOS_Pos));
1521 OutputVoltageLevelTrimmed = ((int32_t)((uint32_t)(OutputVoltageLevel >> PWR_CR5_SMPSVOS_Pos)) + (int32_t)TrimmingSteps);
1522
1523 /* Clamp value to voltage trimming bitfield range */
1524 if (OutputVoltageLevelTrimmed < 0)
1525 {
1526 OutputVoltageLevelTrimmed = 0;
1527 }
1528 else
1529 {
1530 if (OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS)
1531 {
1532 OutputVoltageLevelTrimmed = (int32_t)PWR_CR5_SMPSVOS;
1533 }
1534 }
1535
1536 /* Update register */
1537 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSVOS, (uint32_t)OutputVoltageLevelTrimmed);
1538 }
1539 }
1540
1541 /**
1542 * @brief Get SMPS step down converter output voltage scaling
1543 * @note SMPS output voltage is calibrated in production,
1544 * calibration parameters are applied to the voltage level parameter
1545 * to return the effective voltage value.
1546 * @rmtoll CR5 SMPSVOS LL_PWR_SMPS_GetOutputVoltageLevel
1547 * @retval Returned value can be one of the following values:
1548 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20
1549 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25
1550 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30
1551 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35
1552 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40
1553 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45
1554 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50
1555 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55
1556 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60
1557 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65
1558 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70
1559 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75
1560 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80
1561 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85
1562 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90
1563 */
LL_PWR_SMPS_GetOutputVoltageLevel(void)1564 __STATIC_INLINE uint32_t LL_PWR_SMPS_GetOutputVoltageLevel(void)
1565 {
1566 __IO const uint32_t OutputVoltageLevel_calibration = (((*SMPS_VOLTAGE_CAL_ADDR) & SMPS_VOLTAGE_CAL) >> SMPS_VOLTAGE_CAL_POS); /* SMPS output voltage level calibrated in production */
1567 int32_t TrimmingSteps; /* Trimming steps between theoretical output voltage and calibrated output voltage */
1568 int32_t OutputVoltageLevelTrimmed; /* SMPS output voltage level after calibration: trimming value added to required level */
1569
1570 if (OutputVoltageLevel_calibration == 0UL)
1571 {
1572 /* Device with SMPS output voltage not calibrated in production: Return output voltage value directly */
1573
1574 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSVOS));
1575 }
1576 else
1577 {
1578 /* Device with SMPS output voltage calibrated in production: Return output voltage value after correction by calibration value */
1579
1580 TrimmingSteps = ((int32_t)OutputVoltageLevel_calibration - (int32_t)(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 >> PWR_CR5_SMPSVOS_Pos)); /* Trimming steps between theoretical output voltage and calibrated output voltage */
1581
1582 OutputVoltageLevelTrimmed = ((int32_t)((uint32_t)READ_BIT(PWR->CR5, PWR_CR5_SMPSVOS)) - TrimmingSteps);
1583
1584 /* Clamp value to voltage range */
1585 if (OutputVoltageLevelTrimmed < 0)
1586 {
1587 OutputVoltageLevelTrimmed = (int32_t)LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20;
1588 }
1589 else
1590 {
1591 if (OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS)
1592 {
1593 OutputVoltageLevelTrimmed = (int32_t)LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90;
1594 }
1595 }
1596
1597 return (uint32_t)OutputVoltageLevelTrimmed;
1598 }
1599 }
1600
1601 /**
1602 * @}
1603 */
1604 #endif /* PWR_CR5_SMPSEN */
1605
1606 /** @defgroup PWR_LL_EF_Configuration_Multicore Configuration of multicore, intended to be executed by CPU1
1607 * @{
1608 */
1609
1610 /**
1611 * @brief Boot CPU2 after reset or wakeup from stop or standby modes
1612 * @rmtoll CR4 C2BOOT LL_PWR_EnableBootC2
1613 * @retval None
1614 */
LL_PWR_EnableBootC2(void)1615 __STATIC_INLINE void LL_PWR_EnableBootC2(void)
1616 {
1617 SET_BIT(PWR->CR4, PWR_CR4_C2BOOT);
1618 }
1619
1620 /**
1621 * @brief Release bit to boot CPU2 after reset or wakeup from stop or standby
1622 * modes
1623 * @rmtoll CR4 C2BOOT LL_PWR_DisableBootC2
1624 * @retval None
1625 */
LL_PWR_DisableBootC2(void)1626 __STATIC_INLINE void LL_PWR_DisableBootC2(void)
1627 {
1628 CLEAR_BIT(PWR->CR4, PWR_CR4_C2BOOT);
1629 }
1630
1631 /**
1632 * @brief Check if bit to boot CPU2 after reset or wakeup from stop or standby
1633 * modes is set
1634 * @rmtoll CR4 C2BOOT LL_PWR_IsEnabledBootC2
1635 * @retval State of bit (1 or 0)
1636 */
LL_PWR_IsEnabledBootC2(void)1637 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBootC2(void)
1638 {
1639 return ((READ_BIT(PWR->CR4, PWR_CR4_C2BOOT) == (PWR_CR4_C2BOOT)) ? 1UL : 0UL);
1640 }
1641
1642 /**
1643 * @}
1644 */
1645
1646 /** @defgroup PWR_LL_EF_Configuration_CPU2 Configuration of CPU2, intended to be executed by CPU2
1647 * @{
1648 */
1649
1650 /**
1651 * @brief Set Low-Power mode for CPU2
1652 * @rmtoll C2CR1 LPMS LL_C2_PWR_SetPowerMode
1653 * @param LowPowerMode This parameter can be one of the following values:
1654 * @arg @ref LL_PWR_MODE_STOP0
1655 * @arg @ref LL_PWR_MODE_STOP1
1656 * @arg @ref LL_PWR_MODE_STOP2 (*)
1657 * @arg @ref LL_PWR_MODE_STANDBY
1658 * @arg @ref LL_PWR_MODE_SHUTDOWN
1659 *
1660 * (*) Not available on devices STM32WB15xx, STM32WB10xx, STM32WB1Mxx
1661 * @retval None
1662 */
LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode)1663 __STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode)
1664 {
1665 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, LowPowerMode);
1666 }
1667
1668 /**
1669 * @brief Get Low-Power mode for CPU2
1670 * @rmtoll C2CR1 LPMS LL_C2_PWR_GetPowerMode
1671 * @retval Returned value can be one of the following values:
1672 * @arg @ref LL_PWR_MODE_STOP0
1673 * @arg @ref LL_PWR_MODE_STOP1
1674 * @arg @ref LL_PWR_MODE_STOP2 (*)
1675 * @arg @ref LL_PWR_MODE_STANDBY
1676 * @arg @ref LL_PWR_MODE_SHUTDOWN
1677 *
1678 * (*) Not available on devices STM32WB15xx, STM32WB10xx, STM32WB1Mxx
1679 */
LL_C2_PWR_GetPowerMode(void)1680 __STATIC_INLINE uint32_t LL_C2_PWR_GetPowerMode(void)
1681 {
1682 return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_LPMS));
1683 }
1684
1685 /**
1686 * @brief Set flash power-down mode during low-power run mode for CPU2
1687 * @rmtoll C2CR1 FPDR LL_C2_PWR_SetFlashPowerModeLPRun
1688 * @param FlashLowPowerMode This parameter can be one of the following values:
1689 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
1690 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
1691 * @retval None
1692 */
LL_C2_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)1693 __STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)
1694 {
1695 /* Unlock bit FPDR */
1696 WRITE_REG(PWR->C2CR1, 0x0000C1B0UL);
1697
1698 /* Update bit FPDR */
1699 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDR, FlashLowPowerMode);
1700 }
1701
1702 /**
1703 * @brief Get flash power-down mode during low-power run mode for CPU2
1704 * @rmtoll C2CR1 FPDR LL_C2_PWR_GetFlashPowerModeLPRun
1705 * @retval Returned value can be one of the following values:
1706 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
1707 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
1708 */
LL_C2_PWR_GetFlashPowerModeLPRun(void)1709 __STATIC_INLINE uint32_t LL_C2_PWR_GetFlashPowerModeLPRun(void)
1710 {
1711 return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_FPDR));
1712 }
1713
1714 /**
1715 * @brief Set flash power-down mode during sleep mode for CPU2
1716 * @rmtoll C2CR1 FPDS LL_C2_PWR_SetFlashPowerModeSleep
1717 * @param FlashLowPowerMode This parameter can be one of the following values:
1718 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
1719 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
1720 * @retval None
1721 */
LL_C2_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode)1722 __STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode)
1723 {
1724 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDS, FlashLowPowerMode);
1725 }
1726
1727 /**
1728 * @brief Get flash power-down mode during sleep mode for CPU2
1729 * @rmtoll C2CR1 FPDS LL_C2_PWR_GetFlashPowerModeSleep
1730 * @retval Returned value can be one of the following values:
1731 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
1732 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
1733 */
LL_C2_PWR_GetFlashPowerModeSleep(void)1734 __STATIC_INLINE uint32_t LL_C2_PWR_GetFlashPowerModeSleep(void)
1735 {
1736 return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_FPDS));
1737 }
1738
1739
1740 /**
1741 * @brief Enable Internal Wake-up line for CPU2
1742 * @rmtoll C2CR3 EIWUL LL_C2_PWR_EnableInternWU
1743 * @retval None
1744 */
LL_C2_PWR_EnableInternWU(void)1745 __STATIC_INLINE void LL_C2_PWR_EnableInternWU(void)
1746 {
1747 SET_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL);
1748 }
1749
1750 /**
1751 * @brief Disable Internal Wake-up line for CPU2
1752 * @rmtoll C2CR3 EIWUL LL_C2_PWR_DisableInternWU
1753 * @retval None
1754 */
LL_C2_PWR_DisableInternWU(void)1755 __STATIC_INLINE void LL_C2_PWR_DisableInternWU(void)
1756 {
1757 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL);
1758 }
1759
1760 /**
1761 * @brief Check if Internal Wake-up line is enabled for CPU2
1762 * @rmtoll C2CR3 EIWUL LL_C2_PWR_IsEnabledInternWU
1763 * @retval State of bit (1 or 0).
1764 */
LL_C2_PWR_IsEnabledInternWU(void)1765 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledInternWU(void)
1766 {
1767 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL) == (PWR_C2CR3_EIWUL)) ? 1UL : 0UL);
1768 }
1769
1770 /**
1771 * @brief Enable the WakeUp PINx functionality
1772 * @rmtoll C2CR3 EWUP1 LL_C2_PWR_EnableWakeUpPin\n
1773 * C2CR3 EWUP2 LL_C2_PWR_EnableWakeUpPin\n
1774 * C2CR3 EWUP3 LL_C2_PWR_EnableWakeUpPin\n
1775 * C2CR3 EWUP4 LL_C2_PWR_EnableWakeUpPin\n
1776 * C2CR3 EWUP5 LL_C2_PWR_EnableWakeUpPin
1777 * @param WakeUpPin This parameter can be one of the following values:
1778 * @arg @ref LL_PWR_WAKEUP_PIN1
1779 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
1780 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1781 * @arg @ref LL_PWR_WAKEUP_PIN4
1782 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1783 *
1784 * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx, STM32WB1Mxx
1785 * @retval None
1786 */
LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin)1787 __STATIC_INLINE void LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
1788 {
1789 SET_BIT(PWR->C2CR3, WakeUpPin);
1790 }
1791
1792 /**
1793 * @brief Disable the WakeUp PINx functionality
1794 * @rmtoll C2CR3 EWUP1 LL_C2_PWR_DisableWakeUpPin\n
1795 * C2CR3 EWUP2 LL_C2_PWR_DisableWakeUpPin\n
1796 * C2CR3 EWUP3 LL_C2_PWR_DisableWakeUpPin\n
1797 * C2CR3 EWUP4 LL_C2_PWR_DisableWakeUpPin\n
1798 * C2CR3 EWUP5 LL_C2_PWR_DisableWakeUpPin
1799 * @param WakeUpPin This parameter can be one of the following values:
1800 * @arg @ref LL_PWR_WAKEUP_PIN1
1801 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
1802 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1803 * @arg @ref LL_PWR_WAKEUP_PIN4
1804 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1805 *
1806 * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx, STM32WB1Mxx
1807 * @retval None
1808 */
LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin)1809 __STATIC_INLINE void LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
1810 {
1811 CLEAR_BIT(PWR->C2CR3, WakeUpPin);
1812 }
1813
1814 /**
1815 * @brief Check if the WakeUp PINx functionality is enabled
1816 * @rmtoll C2CR3 EWUP1 LL_C2_PWR_IsEnabledWakeUpPin\n
1817 * C2CR3 EWUP2 LL_C2_PWR_IsEnabledWakeUpPin\n
1818 * C2CR3 EWUP3 LL_C2_PWR_IsEnabledWakeUpPin\n
1819 * C2CR3 EWUP4 LL_C2_PWR_IsEnabledWakeUpPin\n
1820 * C2CR3 EWUP5 LL_C2_PWR_IsEnabledWakeUpPin
1821 * @param WakeUpPin This parameter can be one of the following values:
1822 * @arg @ref LL_PWR_WAKEUP_PIN1
1823 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
1824 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1825 * @arg @ref LL_PWR_WAKEUP_PIN4
1826 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1827 *
1828 * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx, STM32WB1Mxx
1829 * @retval None
1830 */
LL_C2_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)1831 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
1832 {
1833 return ((READ_BIT(PWR->C2CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1834 }
1835
1836 /**
1837 * @brief Enable pull-up and pull-down configuration for CPU2
1838 * @rmtoll C2CR3 APC LL_C2_PWR_EnablePUPDCfg
1839 * @retval None
1840 */
LL_C2_PWR_EnablePUPDCfg(void)1841 __STATIC_INLINE void LL_C2_PWR_EnablePUPDCfg(void)
1842 {
1843 SET_BIT(PWR->C2CR3, PWR_C2CR3_APC);
1844 }
1845
1846 /**
1847 * @brief Disable pull-up and pull-down configuration for CPU2
1848 * @rmtoll C2CR3 APC LL_C2_PWR_DisablePUPDCfg
1849 * @retval None
1850 */
LL_C2_PWR_DisablePUPDCfg(void)1851 __STATIC_INLINE void LL_C2_PWR_DisablePUPDCfg(void)
1852 {
1853 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_APC);
1854 }
1855
1856 /**
1857 * @brief Check if pull-up and pull-down configuration is enabled for CPU2
1858 * @rmtoll C2CR3 APC LL_C2_PWR_IsEnabledPUPDCfg
1859 * @retval State of bit (1 or 0).
1860 */
LL_C2_PWR_IsEnabledPUPDCfg(void)1861 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledPUPDCfg(void)
1862 {
1863 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_APC) == (PWR_C2CR3_APC)) ? 1UL : 0UL);
1864 }
1865
1866 /**
1867 * @}
1868 */
1869
1870 /** @defgroup PWR_LL_EF_Configuration_CPU2_Radio Configuration of radio (BLE or 802.15.4) of CPU2, intended to be executed by CPU2
1871 * @{
1872 */
1873
1874 /**
1875 * @brief Wakeup BLE controller from its sleep mode
1876 * @note This bit is automatically reset when BLE controller
1877 * exit its sleep mode.
1878 * @rmtoll C2CR1 BLEEWKUP LL_C2_PWR_WakeUp_BLE
1879 * @retval None
1880 */
LL_C2_PWR_WakeUp_BLE(void)1881 __STATIC_INLINE void LL_C2_PWR_WakeUp_BLE(void)
1882 {
1883 SET_BIT(PWR->C2CR1, PWR_C2CR1_BLEEWKUP);
1884 }
1885
1886 /**
1887 * @brief Check if the BLE controller is woken-up from
1888 * low-power mode.
1889 * @rmtoll C2CR1 BLEEWKUP LL_C2_PWR_IsWokenUp_BLE
1890 * @retval State of bit (1 or 0) (value "0": BLE is not woken-up)
1891 */
LL_C2_PWR_IsWokenUp_BLE(void)1892 __STATIC_INLINE uint32_t LL_C2_PWR_IsWokenUp_BLE(void)
1893 {
1894 return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_BLEEWKUP) == (PWR_C2CR1_BLEEWKUP)) ? 1UL : 0UL);
1895 }
1896
1897 #if defined(PWR_CR3_E802A)
1898 /**
1899 * @brief Wakeup 802.15.4 controller from its sleep mode
1900 * @note This bit is automatically reset when 802.15.4 controller
1901 * exit its sleep mode.
1902 * @rmtoll C2CR1 802EWKUP LL_C2_PWR_WakeUp_802_15_4
1903 * @retval None
1904 */
LL_C2_PWR_WakeUp_802_15_4(void)1905 __STATIC_INLINE void LL_C2_PWR_WakeUp_802_15_4(void)
1906 {
1907 SET_BIT(PWR->C2CR1, PWR_C2CR1_802EWKUP);
1908 }
1909
1910 /**
1911 * @brief Check if the 802.15.4 controller is woken-up from
1912 * low-power mode.
1913 * @rmtoll C2CR1 802EWKUP LL_C2_PWR_IsWokenUp_802_15_4
1914 * @retval State of bit (1 or 0) (value "0": 802.15.4 is not woken-up)
1915 */
LL_C2_PWR_IsWokenUp_802_15_4(void)1916 __STATIC_INLINE uint32_t LL_C2_PWR_IsWokenUp_802_15_4(void)
1917 {
1918 return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_802EWKUP) == (PWR_C2CR1_802EWKUP)) ? 1UL : 0UL);
1919 }
1920 #endif /* PWR_CR3_E802A */
1921
1922 /**
1923 * @}
1924 */
1925
1926 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1927 * @{
1928 */
1929
1930 /**
1931 * @brief Get Internal Wake-up line Flag
1932 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
1933 * @retval State of bit (1 or 0).
1934 */
LL_PWR_IsActiveFlag_InternWU(void)1935 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
1936 {
1937 return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL);
1938 }
1939
1940 #if defined(PWR_CR3_EWUP5)
1941 /**
1942 * @brief Get Wake-up Flag 5
1943 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
1944 * @retval State of bit (1 or 0).
1945 */
LL_PWR_IsActiveFlag_WU5(void)1946 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1947 {
1948 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL);
1949 }
1950 #endif /* PWR_CR3_EWUP5 */
1951
1952 /**
1953 * @brief Get Wake-up Flag 4
1954 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
1955 * @retval State of bit (1 or 0).
1956 */
LL_PWR_IsActiveFlag_WU4(void)1957 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1958 {
1959 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
1960 }
1961
1962 #if defined(PWR_CR3_EWUP3)
1963 /**
1964 * @brief Get Wake-up Flag 3
1965 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
1966 * @retval State of bit (1 or 0).
1967 */
LL_PWR_IsActiveFlag_WU3(void)1968 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1969 {
1970 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
1971 }
1972 #endif /* PWR_CR3_EWUP3 */
1973
1974 #if defined(PWR_CR3_EWUP2)
1975 /**
1976 * @brief Get Wake-up Flag 2
1977 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
1978 * @retval State of bit (1 or 0).
1979 */
LL_PWR_IsActiveFlag_WU2(void)1980 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1981 {
1982 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
1983 }
1984 #endif /* PWR_CR3_EWUP2 */
1985
1986 /**
1987 * @brief Get Wake-up Flag 1
1988 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
1989 * @retval State of bit (1 or 0).
1990 */
LL_PWR_IsActiveFlag_WU1(void)1991 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1992 {
1993 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
1994 }
1995
1996 /**
1997 * @brief Clear Wake-up Flags
1998 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
1999 * @retval None
2000 */
LL_PWR_ClearFlag_WU(void)2001 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
2002 {
2003 WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
2004 }
2005
2006 #if defined(PWR_CR3_EWUP5)
2007 /**
2008 * @brief Clear Wake-up Flag 5
2009 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
2010 * @retval None
2011 */
LL_PWR_ClearFlag_WU5(void)2012 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
2013 {
2014 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
2015 }
2016 #endif /* PWR_CR3_EWUP5 */
2017
2018 /**
2019 * @brief Clear Wake-up Flag 4
2020 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
2021 * @retval None
2022 */
LL_PWR_ClearFlag_WU4(void)2023 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
2024 {
2025 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
2026 }
2027
2028 #if defined(PWR_CR3_EWUP3)
2029 /**
2030 * @brief Clear Wake-up Flag 3
2031 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
2032 * @retval None
2033 */
LL_PWR_ClearFlag_WU3(void)2034 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
2035 {
2036 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
2037 }
2038 #endif /* PWR_CR3_EWUP3 */
2039
2040 #if defined(PWR_CR3_EWUP2)
2041 /**
2042 * @brief Clear Wake-up Flag 2
2043 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
2044 * @retval None
2045 */
LL_PWR_ClearFlag_WU2(void)2046 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
2047 {
2048 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
2049 }
2050 #endif /* PWR_CR3_EWUP2 */
2051
2052 /**
2053 * @brief Clear Wake-up Flag 1
2054 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
2055 * @retval None
2056 */
LL_PWR_ClearFlag_WU1(void)2057 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
2058 {
2059 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
2060 }
2061
2062
2063 /**
2064 * @brief Indicate whether VDDA voltage is below or above PVM3 threshold
2065 * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
2066 * @retval State of bit (1 or 0).
2067 */
LL_PWR_IsActiveFlag_PVMO3(void)2068 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
2069 {
2070 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL);
2071 }
2072
2073 #if defined(PWR_CR2_PVME1)
2074 /**
2075 * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold
2076 * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
2077 * @retval State of bit (1 or 0).
2078 */
LL_PWR_IsActiveFlag_PVMO1(void)2079 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
2080 {
2081 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL);
2082 }
2083 #endif /* PWR_CR2_PVME1 */
2084
2085 /**
2086 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold
2087 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
2088 * @retval State of bit (1 or 0).
2089 */
LL_PWR_IsActiveFlag_PVDO(void)2090 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
2091 {
2092 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL);
2093 }
2094
2095 #if defined(PWR_CR1_VOS)
2096 /**
2097 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
2098 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
2099 * @retval State of bit (1 or 0).
2100 */
LL_PWR_IsActiveFlag_VOS(void)2101 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
2102 {
2103 return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL);
2104 }
2105 #endif /* PWR_CR1_VOS */
2106
2107 /**
2108 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
2109 * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
2110 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
2111 * @retval State of bit (1 or 0).
2112 */
LL_PWR_IsActiveFlag_REGLPF(void)2113 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
2114 {
2115 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL);
2116 }
2117
2118 /**
2119 * @brief Indicate whether or not the low-power regulator is ready
2120 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
2121 * @retval State of bit (1 or 0).
2122 */
LL_PWR_IsActiveFlag_REGLPS(void)2123 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
2124 {
2125 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL);
2126 }
2127
2128 /**
2129 * @brief Get BORH interrupt flag
2130 * @rmtoll SR1 BORHF LL_PWR_IsActiveFlag_BORH
2131 * @retval State of bit (1 or 0).
2132 */
LL_PWR_IsActiveFlag_BORH(void)2133 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BORH(void)
2134 {
2135 return ((READ_BIT(PWR->SR1, PWR_SR1_BORHF) == (PWR_SR1_BORHF)) ? 1UL : 0UL);
2136 }
2137
2138 /**
2139 * @brief Clear BORH interrupt flag
2140 * @rmtoll SCR CBORHF LL_PWR_ClearFlag_BORH
2141 * @retval None
2142 */
LL_PWR_ClearFlag_BORH(void)2143 __STATIC_INLINE void LL_PWR_ClearFlag_BORH(void)
2144 {
2145 WRITE_REG(PWR->SCR, PWR_SCR_CBORHF);
2146 }
2147
2148 /**
2149 * @}
2150 */
2151
2152 #if defined(PWR_CR5_SMPSEN)
2153 /** @defgroup PWR_LL_EF_FLAG_Management_SMPS FLAG management for SMPS
2154 * @{
2155 */
2156
2157 /**
2158 * @brief Get SMPS step down converter forced in bypass mode interrupt flag
2159 * @note To activate flag of SMPS step down converter forced in bypass mode
2160 * by BORH, BOR must be preliminarily configured to control SMPS
2161 * operating mode.
2162 * Refer to function @ref LL_PWR_SetBORConfig().
2163 * @rmtoll SR1 SMPSFBF LL_PWR_IsActiveFlag_SMPSFB
2164 * @retval State of bit (1 or 0).
2165 */
LL_PWR_IsActiveFlag_SMPSFB(void)2166 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSFB(void)
2167 {
2168 return ((READ_BIT(PWR->SR1, PWR_SR1_SMPSFBF) == (PWR_SR1_SMPSFBF)) ? 1UL : 0UL);
2169 }
2170
2171 /**
2172 * @brief Clear SMPS step down converter forced in bypass mode interrupt flag
2173 * @note To activate flag of SMPS step down converter forced in bypass mode
2174 * by BORH, BOR must be preliminarily configured to control SMPS
2175 * operating mode.
2176 * Refer to function @ref LL_PWR_SetBORConfig().
2177 * @rmtoll SCR CSMPSFBF LL_PWR_ClearFlag_SMPSFB
2178 * @retval None
2179 */
LL_PWR_ClearFlag_SMPSFB(void)2180 __STATIC_INLINE void LL_PWR_ClearFlag_SMPSFB(void)
2181 {
2182 WRITE_REG(PWR->SCR, PWR_SCR_CSMPSFBF);
2183 }
2184
2185 /**
2186 * @}
2187 */
2188 #endif /* PWR_CR5_SMPSEN */
2189
2190 /** @defgroup PWR_LL_EF_FLAG_Management_Radio FLAG management for radio (BLE or 802.15.4)
2191 * @{
2192 */
2193
2194 /**
2195 * @brief Get BLE wakeup interrupt flag
2196 * @rmtoll SR1 BLEWUF LL_PWR_IsActiveFlag_BLEWU
2197 * @retval State of bit (1 or 0).
2198 */
LL_PWR_IsActiveFlag_BLEWU(void)2199 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BLEWU(void)
2200 {
2201 return ((READ_BIT(PWR->SR1, PWR_SR1_BLEWUF) == (PWR_SR1_BLEWUF)) ? 1UL : 0UL);
2202 }
2203
2204 #if defined(PWR_CR3_E802A)
2205 /**
2206 * @brief Get 802.15.4 wakeup interrupt flag
2207 * @rmtoll SR1 802WUF LL_PWR_IsActiveFlag_802WU
2208 * @retval State of bit (1 or 0).
2209 */
LL_PWR_IsActiveFlag_802WU(void)2210 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802WU(void)
2211 {
2212 return ((READ_BIT(PWR->SR1, PWR_SR1_802WUF) == (PWR_SR1_802WUF)) ? 1UL : 0UL);
2213 }
2214 #endif /* PWR_CR3_E802A */
2215
2216 /**
2217 * @brief Get BLE end of activity interrupt flag
2218 * @rmtoll SR1 BLEAF LL_PWR_IsActiveFlag_BLEA
2219 * @retval State of bit (1 or 0).
2220 */
LL_PWR_IsActiveFlag_BLEA(void)2221 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BLEA(void)
2222 {
2223 return ((READ_BIT(PWR->SR1, PWR_SR1_BLEAF) == (PWR_SR1_BLEAF)) ? 1UL : 0UL);
2224 }
2225
2226 #if defined(PWR_CR3_E802A)
2227 /**
2228 * @brief Get 802.15.4 end of activity interrupt flag
2229 * @rmtoll SR1 802AF LL_PWR_IsActiveFlag_802A
2230 * @retval State of bit (1 or 0).
2231 */
LL_PWR_IsActiveFlag_802A(void)2232 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802A(void)
2233 {
2234 return ((READ_BIT(PWR->SR1, PWR_SR1_802AF) == (PWR_SR1_802AF)) ? 1UL : 0UL);
2235 }
2236 #endif /* PWR_CR3_E802A */
2237
2238 /**
2239 * @brief Get critical radio phase end of activity interrupt flag
2240 * @rmtoll SR1 CRPEF LL_PWR_IsActiveFlag_CRPE
2241 * @retval State of bit (1 or 0).
2242 */
LL_PWR_IsActiveFlag_CRPE(void)2243 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_CRPE(void)
2244 {
2245 return ((READ_BIT(PWR->SR1, PWR_SR1_CRPEF) == (PWR_SR1_CRPEF)) ? 1UL : 0UL);
2246 }
2247
2248 /**
2249 * @brief Get critical radio system phase flag
2250 * @rmtoll EXTSCR CRPF LL_PWR_IsActiveFlag_CRP
2251 * @retval State of bit (1 or 0).
2252 */
LL_PWR_IsActiveFlag_CRP(void)2253 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_CRP(void)
2254 {
2255 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_CRPF) == (PWR_EXTSCR_CRPF)) ? 1UL : 0UL);
2256 }
2257
2258 /**
2259 * @brief Clear BLE wakeup interrupt flag
2260 * @rmtoll SCR BLEWU LL_PWR_ClearFlag_BLEWU
2261 * @retval None
2262 */
LL_PWR_ClearFlag_BLEWU(void)2263 __STATIC_INLINE void LL_PWR_ClearFlag_BLEWU(void)
2264 {
2265 WRITE_REG(PWR->SCR, PWR_SCR_CBLEWUF);
2266 }
2267
2268 #if defined(PWR_CR3_E802A)
2269 /**
2270 * @brief Clear 802.15.4 wakeup interrupt flag
2271 * @rmtoll SCR 802WU LL_PWR_ClearFlag_802WU
2272 * @retval None
2273 */
LL_PWR_ClearFlag_802WU(void)2274 __STATIC_INLINE void LL_PWR_ClearFlag_802WU(void)
2275 {
2276 WRITE_REG(PWR->SCR, PWR_SCR_C802WUF);
2277 }
2278 #endif /* PWR_CR3_E802A */
2279
2280 /**
2281 * @brief Clear BLE end of activity interrupt flag
2282 * @rmtoll SCR BLEAF LL_PWR_ClearFlag_BLEA
2283 * @retval None
2284 */
LL_PWR_ClearFlag_BLEA(void)2285 __STATIC_INLINE void LL_PWR_ClearFlag_BLEA(void)
2286 {
2287 WRITE_REG(PWR->SCR, PWR_SCR_CBLEAF);
2288 }
2289
2290 #if defined(PWR_CR3_E802A)
2291 /**
2292 * @brief Clear 802.15.4 end of activity interrupt flag
2293 * @rmtoll SCR 802AF LL_PWR_ClearFlag_802A
2294 * @retval None
2295 */
LL_PWR_ClearFlag_802A(void)2296 __STATIC_INLINE void LL_PWR_ClearFlag_802A(void)
2297 {
2298 WRITE_REG(PWR->SCR, PWR_SCR_C802AF);
2299 }
2300 #endif /* PWR_CR3_E802A */
2301
2302 /**
2303 * @brief Clear critical radio phase end of activity interrupt flag
2304 * @rmtoll SCR CCRPEF LL_PWR_ClearFlag_CRPE
2305 * @retval None
2306 */
LL_PWR_ClearFlag_CRPE(void)2307 __STATIC_INLINE void LL_PWR_ClearFlag_CRPE(void)
2308 {
2309 WRITE_REG(PWR->SCR, PWR_SCR_CCRPEF);
2310 }
2311
2312 /**
2313 * @brief Clear critical radio system phase flag
2314 * @rmtoll EXTSCR CCRP LL_PWR_ClearFlag_CRP
2315 * @retval None
2316 */
LL_PWR_ClearFlag_CRP(void)2317 __STATIC_INLINE void LL_PWR_ClearFlag_CRP(void)
2318 {
2319 WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_CCRPF);
2320 }
2321
2322 /**
2323 * @}
2324 */
2325
2326 /** @defgroup PWR_LL_EF_FLAG_Management_Multicore FLAG management for multicore
2327 * @{
2328 */
2329
2330 /**
2331 * @brief Get CPU2 hold interrupt flag
2332 * @rmtoll SCR CC2HF LL_PWR_IsActiveFlag_C2H
2333 * @retval State of bit (1 or 0).
2334 */
LL_PWR_IsActiveFlag_C2H(void)2335 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2H(void)
2336 {
2337 return ((READ_BIT(PWR->SR1, PWR_SR1_C2HF) == (PWR_SR1_C2HF)) ? 1UL : 0UL);
2338 }
2339
2340 /**
2341 * @brief Get system stop flag for CPU1
2342 * @rmtoll EXTSCR C1STOPF LL_PWR_IsActiveFlag_C1STOP
2343 * @retval State of bit (1 or 0).
2344 */
LL_PWR_IsActiveFlag_C1STOP(void)2345 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1STOP(void)
2346 {
2347 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1STOPF) == (PWR_EXTSCR_C1STOPF)) ? 1UL : 0UL);
2348 }
2349
2350 /**
2351 * @brief Get system standby flag for CPU1
2352 * @rmtoll EXTSCR C1SBF LL_PWR_IsActiveFlag_C1SB
2353 * @retval State of bit (1 or 0).
2354 */
LL_PWR_IsActiveFlag_C1SB(void)2355 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1SB(void)
2356 {
2357 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1SBF) == (PWR_EXTSCR_C1SBF)) ? 1UL : 0UL);
2358 }
2359
2360 /**
2361 * @brief Get deepsleep mode for CPU1
2362 * @rmtoll EXTSCR C1DS LL_PWR_IsActiveFlag_C1DS
2363 * @retval State of bit (1 or 0).
2364 */
LL_PWR_IsActiveFlag_C1DS(void)2365 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1DS(void)
2366 {
2367 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1DS) == (PWR_EXTSCR_C1DS)) ? 1UL : 0UL);
2368 }
2369
2370 /**
2371 * @brief System stop flag for CPU2
2372 * @rmtoll EXTSCR C2STOPF LL_PWR_IsActiveFlag_C2STOP
2373 * @retval State of bit (1 or 0).
2374 */
LL_PWR_IsActiveFlag_C2STOP(void)2375 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2STOP(void)
2376 {
2377 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2STOPF) == (PWR_EXTSCR_C2STOPF)) ? 1UL : 0UL);
2378 }
2379
2380 /**
2381 * @brief System standby flag for CPU2
2382 * @rmtoll EXTSCR C2SBF LL_PWR_IsActiveFlag_C2SB
2383 * @retval State of bit (1 or 0).
2384 */
LL_PWR_IsActiveFlag_C2SB(void)2385 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2SB(void)
2386 {
2387 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2SBF) == (PWR_EXTSCR_C2SBF)) ? 1UL : 0UL);
2388 }
2389
2390 /**
2391 * @brief Get deepsleep mode for CPU2
2392 * @rmtoll EXTSCR C2DS LL_PWR_IsActiveFlag_C2DS
2393 * @retval State of bit (1 or 0).
2394 */
LL_PWR_IsActiveFlag_C2DS(void)2395 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2DS(void)
2396 {
2397 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2DS) == (PWR_EXTSCR_C2DS)) ? 1UL : 0UL);
2398 }
2399
2400 /**
2401 * @brief Clear CPU2 hold interrupt flag
2402 * @rmtoll SCR CC2HF LL_PWR_ClearFlag_C2H
2403 * @retval None
2404 */
LL_PWR_ClearFlag_C2H(void)2405 __STATIC_INLINE void LL_PWR_ClearFlag_C2H(void)
2406 {
2407 WRITE_REG(PWR->SCR, PWR_SCR_CC2HF);
2408 }
2409 /**
2410 * @brief Clear standby and stop flags for CPU1
2411 * @rmtoll EXTSCR C1CSSF LL_PWR_ClearFlag_C1STOP_C1STB
2412 * @retval None
2413 */
LL_PWR_ClearFlag_C1STOP_C1STB(void)2414 __STATIC_INLINE void LL_PWR_ClearFlag_C1STOP_C1STB(void)
2415 {
2416 WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C1CSSF);
2417 }
2418
2419 /**
2420 * @brief Clear standby and stop flags for CPU2
2421 * @rmtoll EXTSCR C2CSSF LL_PWR_ClearFlag_C2STOP_C2STB
2422 * @retval None
2423 */
LL_PWR_ClearFlag_C2STOP_C2STB(void)2424 __STATIC_INLINE void LL_PWR_ClearFlag_C2STOP_C2STB(void)
2425 {
2426 WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C2CSSF);
2427 }
2428
2429 /**
2430 * @}
2431 */
2432
2433 #if defined(PWR_CR5_SMPSEN)
2434 /** @defgroup PWR_LL_EF_IT_Management_SMPS PWR IT management for SMPS
2435 * @{
2436 */
2437
2438 /**
2439 * @brief Enable SMPS step down converter forced in bypass mode by BORH
2440 * interrupt for CPU1
2441 * @note To activate flag of SMPS step down converter forced in bypass mode
2442 * by BORH, BOR must be preliminarily configured to control SMPS
2443 * operating mode.
2444 * Refer to function @ref LL_PWR_SetBORConfig().
2445 * @rmtoll CR3 EBORHSMPSFB LL_PWR_EnableIT_BORH_SMPSFB
2446 * @retval None
2447 */
LL_PWR_EnableIT_BORH_SMPSFB(void)2448 __STATIC_INLINE void LL_PWR_EnableIT_BORH_SMPSFB(void)
2449 {
2450 SET_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB);
2451 }
2452
2453 /**
2454 * @brief Disable SMPS step down converter forced in bypass mode by BORH
2455 * interrupt for CPU1
2456 * @rmtoll CR3 EBORHSMPSFB LL_PWR_DisableIT_BORH_SMPSFB
2457 * @retval None
2458 */
LL_PWR_DisableIT_BORH_SMPSFB(void)2459 __STATIC_INLINE void LL_PWR_DisableIT_BORH_SMPSFB(void)
2460 {
2461 CLEAR_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB);
2462 }
2463
2464 /**
2465 * @brief Check if SMPS step down converter forced in bypass mode by BORH
2466 * interrupt is enabled for CPU1
2467 * @rmtoll CR3 EBORHSMPSFB LL_PWR_IsEnabledIT_BORH_SMPSFB
2468 * @retval State of bit (1 or 0).
2469 */
LL_PWR_IsEnabledIT_BORH_SMPSFB(void)2470 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_BORH_SMPSFB(void)
2471 {
2472 return ((READ_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB) == (PWR_CR3_EBORHSMPSFB)) ? 1UL : 0UL);
2473 }
2474
2475 /**
2476 * @}
2477 */
2478 #endif /* PWR_CR5_SMPSEN */
2479
2480 /** @defgroup PWR_LL_EF_IT_Management_Radio PWR IT management for radio (BLE or 802.15.4)
2481 * @{
2482 */
2483
2484 /**
2485 * @brief Enable BLE end of activity interrupt for CPU1
2486 * @rmtoll CR3 EBLEA LL_PWR_EnableIT_BLEA
2487 * @retval None
2488 */
LL_PWR_EnableIT_BLEA(void)2489 __STATIC_INLINE void LL_PWR_EnableIT_BLEA(void)
2490 {
2491 SET_BIT(PWR->CR3, PWR_CR3_EBLEA);
2492 }
2493
2494 #if defined(PWR_CR3_E802A)
2495 /**
2496 * @brief Enable 802.15.4 end of activity interrupt for CPU1
2497 * @rmtoll CR3 E802A LL_PWR_EnableIT_802A
2498 * @retval None
2499 */
LL_PWR_EnableIT_802A(void)2500 __STATIC_INLINE void LL_PWR_EnableIT_802A(void)
2501 {
2502 SET_BIT(PWR->CR3, PWR_CR3_E802A);
2503 }
2504 #endif /* PWR_CR3_E802A */
2505
2506 /**
2507 * @brief Disable BLE end of activity interrupt for CPU1
2508 * @rmtoll CR3 EBLEA LL_PWR_DisableIT_BLEA
2509 * @retval None
2510 */
LL_PWR_DisableIT_BLEA(void)2511 __STATIC_INLINE void LL_PWR_DisableIT_BLEA(void)
2512 {
2513 CLEAR_BIT(PWR->CR3, PWR_CR3_EBLEA);
2514 }
2515
2516 #if defined(PWR_CR3_E802A)
2517 /**
2518 * @brief Disable 802.15.4 end of activity interrupt for CPU1
2519 * @rmtoll CR3 E802A LL_PWR_DisableIT_802A
2520 * @retval None
2521 */
LL_PWR_DisableIT_802A(void)2522 __STATIC_INLINE void LL_PWR_DisableIT_802A(void)
2523 {
2524 CLEAR_BIT(PWR->CR3, PWR_CR3_E802A);
2525 }
2526 #endif /* PWR_CR3_E802A */
2527
2528 /**
2529 * @brief Check if BLE end of activity interrupt is enabled for CPU1
2530 * @rmtoll CR3 EBLEA LL_PWR_IsEnabledIT_BLEA
2531 * @retval State of bit (1 or 0).
2532 */
LL_PWR_IsEnabledIT_BLEA(void)2533 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_BLEA(void)
2534 {
2535 return ((READ_BIT(PWR->CR3, PWR_CR3_EBLEA) == (PWR_CR3_EBLEA)) ? 1UL : 0UL);
2536 }
2537
2538 #if defined(PWR_CR3_E802A)
2539 /**
2540 * @brief Check if 802.15.4 end of activity interrupt is enabled for CPU1
2541 * @rmtoll CR3 E802A LL_PWR_IsEnabledIT_802A
2542 * @retval State of bit (1 or 0).
2543 */
LL_PWR_IsEnabledIT_802A(void)2544 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_802A(void)
2545 {
2546 return ((READ_BIT(PWR->CR3, PWR_CR3_E802A) == (PWR_CR3_E802A)) ? 1UL : 0UL);
2547 }
2548 #endif /* PWR_CR3_E802A */
2549
2550 /**
2551 * @brief Enable critical radio phase end of activity interrupt for CPU1
2552 * @rmtoll CR3 ECRPE LL_PWR_EnableIT_802A
2553 * @retval None
2554 */
LL_PWR_EnableIT_CRPE(void)2555 __STATIC_INLINE void LL_PWR_EnableIT_CRPE(void)
2556 {
2557 SET_BIT(PWR->CR3, PWR_CR3_ECRPE);
2558 }
2559
2560 /**
2561 * @brief Disable critical radio phase end of activity interrupt for CPU1
2562 * @rmtoll CR3 ECRPE LL_PWR_DisableIT_802A
2563 * @retval None
2564 */
LL_PWR_DisableIT_CRPE(void)2565 __STATIC_INLINE void LL_PWR_DisableIT_CRPE(void)
2566 {
2567 CLEAR_BIT(PWR->CR3, PWR_CR3_ECRPE);
2568 }
2569
2570 /**
2571 * @brief Check if critical radio phase end of activity interrupt is enabled for CPU1
2572 * @rmtoll CR3 ECRPE LL_PWR_IsEnabledIT_802A
2573 * @retval State of bit (1 or 0).
2574 */
LL_PWR_IsEnabledIT_CRPE(void)2575 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_CRPE(void)
2576 {
2577 return ((READ_BIT(PWR->CR3, PWR_CR3_ECRPE) == (PWR_CR3_ECRPE)) ? 1UL : 0UL);
2578 }
2579
2580 /**
2581 * @}
2582 */
2583
2584 /** @defgroup PWR_LL_EF_IT_Management_Multicore PWR IT management for multicore
2585 * @{
2586 */
2587
2588 /**
2589 * @brief Enable CPU2 hold interrupt for CPU1
2590 * @rmtoll CR3 EC2H LL_PWR_EnableIT_HoldCPU2
2591 * @retval None
2592 */
LL_PWR_EnableIT_HoldCPU2(void)2593 __STATIC_INLINE void LL_PWR_EnableIT_HoldCPU2(void)
2594 {
2595 SET_BIT(PWR->CR3, PWR_CR3_EC2H);
2596 }
2597
2598 /**
2599 * @brief Disable 802.15.4 host wakeup interrupt for CPU2
2600 * @rmtoll CR3 EC2H LL_PWR_DisableIT_HoldCPU2
2601 * @retval None
2602 */
LL_PWR_DisableIT_HoldCPU2(void)2603 __STATIC_INLINE void LL_PWR_DisableIT_HoldCPU2(void)
2604 {
2605 CLEAR_BIT(PWR->CR3, PWR_CR3_EC2H);
2606 }
2607
2608 /**
2609 * @brief Check if BLE host wakeup interrupt is enabled for CPU2
2610 * @rmtoll CR3 EC2H LL_PWR_IsEnabledIT_HoldCPU2
2611 * @retval State of bit (1 or 0).
2612 */
LL_PWR_IsEnabledIT_HoldCPU2(void)2613 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_HoldCPU2(void)
2614 {
2615 return ((READ_BIT(PWR->CR3, PWR_CR3_EC2H) == (PWR_CR3_EC2H)) ? 1UL : 0UL);
2616 }
2617
2618 /**
2619 * @}
2620 */
2621
2622 /** @defgroup PWR_LL_EF_IT_Management_CPU2 PWR IT management of CPU2, intended to be executed by CPU2
2623 * @{
2624 */
2625
2626 /**
2627 * @brief Enable BLE host wakeup interrupt for CPU2
2628 * @rmtoll C2CR3 EBLEWUP LL_C2_PWR_EnableIT_BLEWU
2629 * @retval None
2630 */
LL_C2_PWR_EnableIT_BLEWU(void)2631 __STATIC_INLINE void LL_C2_PWR_EnableIT_BLEWU(void)
2632 {
2633 SET_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP);
2634 }
2635
2636 #if defined(PWR_CR3_E802A)
2637 /**
2638 * @brief Enable 802.15.4 host wakeup interrupt for CPU2
2639 * @rmtoll C2CR3 E802WUP LL_C2_PWR_EnableIT_802WU
2640 * @retval None
2641 */
LL_C2_PWR_EnableIT_802WU(void)2642 __STATIC_INLINE void LL_C2_PWR_EnableIT_802WU(void)
2643 {
2644 SET_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP);
2645 }
2646 #endif /* PWR_CR3_E802A */
2647
2648 /**
2649 * @brief Disable BLE host wakeup interrupt for CPU2
2650 * @rmtoll C2CR3 EBLEWUP LL_C2_PWR_DisableIT_BLEWU
2651 * @retval None
2652 */
LL_C2_PWR_DisableIT_BLEWU(void)2653 __STATIC_INLINE void LL_C2_PWR_DisableIT_BLEWU(void)
2654 {
2655 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP);
2656 }
2657
2658 #if defined(PWR_CR3_E802A)
2659 /**
2660 * @brief Disable 802.15.4 host wakeup interrupt for CPU2
2661 * @rmtoll C2CR3 E802WUP LL_C2_PWR_DisableIT_802WU
2662 * @retval None
2663 */
LL_C2_PWR_DisableIT_802WU(void)2664 __STATIC_INLINE void LL_C2_PWR_DisableIT_802WU(void)
2665 {
2666 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP);
2667 }
2668 #endif /* PWR_CR3_E802A */
2669
2670 /**
2671 * @brief Check if BLE host wakeup interrupt is enabled for CPU2
2672 * @rmtoll C2CR3 EBLEWUP LL_C2_PWR_IsEnabledIT_BLEWU
2673 * @retval State of bit (1 or 0).
2674 */
LL_C2_PWR_IsEnabledIT_BLEWU(void)2675 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledIT_BLEWU(void)
2676 {
2677 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP) == (PWR_C2CR3_EBLEWUP)) ? 1UL : 0UL);
2678 }
2679
2680 #if defined(PWR_CR3_E802A)
2681 /**
2682 * @brief Check if 802.15.4 host wakeup interrupt is enabled for CPU2
2683 * @rmtoll C2CR3 E802WUP LL_C2_PWR_IsEnabledIT_802WU
2684 * @retval State of bit (1 or 0).
2685 */
LL_C2_PWR_IsEnabledIT_802WU(void)2686 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledIT_802WU(void)
2687 {
2688 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP) == (PWR_C2CR3_E802WUP)) ? 1UL : 0UL);
2689 }
2690 #endif /* PWR_CR3_E802A */
2691
2692 /**
2693 * @}
2694 */
2695
2696 #if defined(USE_FULL_LL_DRIVER)
2697 /** @defgroup PWR_LL_EF_Init De-initialization function
2698 * @{
2699 */
2700 ErrorStatus LL_PWR_DeInit(void);
2701 /**
2702 * @}
2703 */
2704 #endif /* USE_FULL_LL_DRIVER */
2705
2706 /**
2707 * @}
2708 */
2709
2710 /**
2711 * @}
2712 */
2713
2714 #endif /* PWR */
2715
2716 /**
2717 * @}
2718 */
2719
2720 #ifdef __cplusplus
2721 }
2722 #endif
2723
2724 #endif /* STM32WBxx_LL_PWR_H */
2725
2726
