1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_lpuart.h
4 * @author MCD Application Team
5 * @brief Header file of LPUART LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBxx_LL_LPUART_H
21 #define STM32WBxx_LL_LPUART_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbxx.h"
29
30 /** @addtogroup STM32WBxx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPUART1)
35
36 /** @defgroup LPUART_LL LPUART
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
43 * @{
44 */
45 /* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
46 static const uint16_t LPUART_PRESCALER_TAB[] =
47 {
48 (uint16_t)1,
49 (uint16_t)2,
50 (uint16_t)4,
51 (uint16_t)6,
52 (uint16_t)8,
53 (uint16_t)10,
54 (uint16_t)12,
55 (uint16_t)16,
56 (uint16_t)32,
57 (uint16_t)64,
58 (uint16_t)128,
59 (uint16_t)256
60 };
61 /**
62 * @}
63 */
64
65 /* Private constants ---------------------------------------------------------*/
66 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
67 * @{
68 */
69 /* Defines used in Baud Rate related macros and corresponding register setting computation */
70 #define LPUART_LPUARTDIV_FREQ_MUL 256U
71 #define LPUART_BRR_MASK 0x000FFFFFU
72 #define LPUART_BRR_MIN_VALUE 0x00000300U
73 /**
74 * @}
75 */
76
77
78 /* Private macros ------------------------------------------------------------*/
79 #if defined(USE_FULL_LL_DRIVER)
80 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
81 * @{
82 */
83 /**
84 * @}
85 */
86 #endif /*USE_FULL_LL_DRIVER*/
87
88 /* Exported types ------------------------------------------------------------*/
89 #if defined(USE_FULL_LL_DRIVER)
90 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
91 * @{
92 */
93
94 /**
95 * @brief LL LPUART Init Structure definition
96 */
97 typedef struct
98 {
99 uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
100 This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
101
102 This feature can be modified afterwards using unitary
103 function @ref LL_LPUART_SetPrescaler().*/
104
105 uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
106
107 This feature can be modified afterwards using unitary
108 function @ref LL_LPUART_SetBaudRate().*/
109
110 uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
111 This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
112
113 This feature can be modified afterwards using unitary
114 function @ref LL_LPUART_SetDataWidth().*/
115
116 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
117 This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
118
119 This feature can be modified afterwards using unitary
120 function @ref LL_LPUART_SetStopBitsLength().*/
121
122 uint32_t Parity; /*!< Specifies the parity mode.
123 This parameter can be a value of @ref LPUART_LL_EC_PARITY.
124
125 This feature can be modified afterwards using unitary
126 function @ref LL_LPUART_SetParity().*/
127
128 uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
129 This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
130
131 This feature can be modified afterwards using unitary
132 function @ref LL_LPUART_SetTransferDirection().*/
133
134 uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
135 This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
136
137 This feature can be modified afterwards using unitary
138 function @ref LL_LPUART_SetHWFlowCtrl().*/
139
140 } LL_LPUART_InitTypeDef;
141
142 /**
143 * @}
144 */
145 #endif /* USE_FULL_LL_DRIVER */
146
147 /* Exported constants --------------------------------------------------------*/
148 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
149 * @{
150 */
151
152 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
153 * @brief Flags defines which can be used with LL_LPUART_WriteReg function
154 * @{
155 */
156 #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
157 #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
158 #define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */
159 #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
160 #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
161 #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
162 #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
163 #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
164 #define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
165 /**
166 * @}
167 */
168
169 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
170 * @brief Flags defines which can be used with LL_LPUART_ReadReg function
171 * @{
172 */
173 #define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
174 #define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
175 #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
176 #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
177 #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
178 #define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
179 #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
180 #define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
181 #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
182 #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
183 #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
184 #define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
185 #define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
186 #define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
187 #define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
188 #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
189 #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
190 #define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
191 #define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
192 #define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
193 #define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
194 /**
195 * @}
196 */
197
198 /** @defgroup LPUART_LL_EC_IT IT Defines
199 * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
200 * @{
201 */
202 #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
203 #define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
204 interrupt enable */
205 #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
206 #define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO
207 not full interrupt enable */
208 #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
209 #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
210 #define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
211 #define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
212 #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
213 #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
214 #define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
215 #define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
216 #define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
217 /**
218 * @}
219 */
220
221 /** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
222 * @{
223 */
224 #define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
225 #define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
226 #define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
227 #define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
228 #define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
229 #define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
230 /**
231 * @}
232 */
233
234 /** @defgroup LPUART_LL_EC_DIRECTION Direction
235 * @{
236 */
237 #define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
238 #define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
239 #define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
240 #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
241 /**
242 * @}
243 */
244
245 /** @defgroup LPUART_LL_EC_PARITY Parity Control
246 * @{
247 */
248 #define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
249 #define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
250 #define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
251 /**
252 * @}
253 */
254
255 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
256 * @{
257 */
258 #define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
259 #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
260 /**
261 * @}
262 */
263
264 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
265 * @{
266 */
267 #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
268 #define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
269 #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
270 /**
271 * @}
272 */
273
274 /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
275 * @{
276 */
277 #define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
278 #define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
279 #define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
280 #define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\
281 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
282 #define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
283 #define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\
284 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
285 #define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\
286 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
287 #define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\
288 USART_PRESC_PRESCALER_1 |\
289 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
290 #define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
291 #define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\
292 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
293 #define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
294 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
295 #define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
296 USART_PRESC_PRESCALER_1 |\
297 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
298 /**
299 * @}
300 */
301
302 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
303 * @{
304 */
305 #define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
306 #define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
307 /**
308 * @}
309 */
310
311 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
312 * @{
313 */
314 #define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
315 #define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
316 /**
317 * @}
318 */
319
320 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
321 * @{
322 */
323 #define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
324 #define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
325 /**
326 * @}
327 */
328
329 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
330 * @{
331 */
332 #define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
333 #define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
334 /**
335 * @}
336 */
337
338 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
339 * @{
340 */
341 #define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received
342 in positive/direct logic. (1=H, 0=L) */
343 #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
344 in negative/inverse logic. (1=L, 0=H).
345 The parity bit is also inverted. */
346 /**
347 * @}
348 */
349
350 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
351 * @{
352 */
353 #define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first,
354 following the start bit */
355 #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
356 following the start bit */
357 /**
358 * @}
359 */
360
361 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
362 * @{
363 */
364 #define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
365 #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
366 /**
367 * @}
368 */
369
370 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
371 * @{
372 */
373 #define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
374 #define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested
375 when there is space in the receive buffer */
376 #define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted
377 when the nCTS input is asserted (tied to 0)*/
378 #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
379 /**
380 * @}
381 */
382
383 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
384 * @{
385 */
386 #define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
387 #define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
388 #define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
389 /**
390 * @}
391 */
392
393 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
394 * @{
395 */
396 #define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
397 #define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
398 /**
399 * @}
400 */
401
402 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
403 * @{
404 */
405 #define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
406 #define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
407 /**
408 * @}
409 */
410
411 /**
412 * @}
413 */
414
415 /* Exported macro ------------------------------------------------------------*/
416 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
417 * @{
418 */
419
420 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
421 * @{
422 */
423
424 /**
425 * @brief Write a value in LPUART register
426 * @param __INSTANCE__ LPUART Instance
427 * @param __REG__ Register to be written
428 * @param __VALUE__ Value to be written in the register
429 * @retval None
430 */
431 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
432
433 /**
434 * @brief Read a value in LPUART register
435 * @param __INSTANCE__ LPUART Instance
436 * @param __REG__ Register to be read
437 * @retval Register value
438 */
439 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
440 /**
441 * @}
442 */
443
444 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
445 * @{
446 */
447
448 /**
449 * @brief Compute LPUARTDIV value according to Peripheral Clock and
450 * expected Baud Rate (20-bit value of LPUARTDIV is returned)
451 * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
452 * @param __PRESCALER__ This parameter can be one of the following values:
453 * @arg @ref LL_LPUART_PRESCALER_DIV1
454 * @arg @ref LL_LPUART_PRESCALER_DIV2
455 * @arg @ref LL_LPUART_PRESCALER_DIV4
456 * @arg @ref LL_LPUART_PRESCALER_DIV6
457 * @arg @ref LL_LPUART_PRESCALER_DIV8
458 * @arg @ref LL_LPUART_PRESCALER_DIV10
459 * @arg @ref LL_LPUART_PRESCALER_DIV12
460 * @arg @ref LL_LPUART_PRESCALER_DIV16
461 * @arg @ref LL_LPUART_PRESCALER_DIV32
462 * @arg @ref LL_LPUART_PRESCALER_DIV64
463 * @arg @ref LL_LPUART_PRESCALER_DIV128
464 * @arg @ref LL_LPUART_PRESCALER_DIV256
465 * @param __BAUDRATE__ Baud Rate value to achieve
466 * @retval LPUARTDIV value to be used for BRR register filling
467 */
468 #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
469 ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
470 * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
471
472 /**
473 * @}
474 */
475
476 /**
477 * @}
478 */
479
480 /* Exported functions --------------------------------------------------------*/
481 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
482 * @{
483 */
484
485 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
486 * @{
487 */
488
489 /**
490 * @brief LPUART Enable
491 * @rmtoll CR1 UE LL_LPUART_Enable
492 * @param LPUARTx LPUART Instance
493 * @retval None
494 */
LL_LPUART_Enable(USART_TypeDef * LPUARTx)495 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
496 {
497 SET_BIT(LPUARTx->CR1, USART_CR1_UE);
498 }
499
500 /**
501 * @brief LPUART Disable
502 * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
503 * and current operations are discarded. The configuration of the LPUART is kept, but all the status
504 * flags, in the LPUARTx_ISR are set to their default values.
505 * @note In order to go into low-power mode without generating errors on the line,
506 * the TE bit must be reset before and the software must wait
507 * for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
508 * The DMA requests are also reset when UE = 0 so the DMA channel must
509 * be disabled before resetting the UE bit.
510 * @rmtoll CR1 UE LL_LPUART_Disable
511 * @param LPUARTx LPUART Instance
512 * @retval None
513 */
LL_LPUART_Disable(USART_TypeDef * LPUARTx)514 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
515 {
516 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
517 }
518
519 /**
520 * @brief Indicate if LPUART is enabled
521 * @rmtoll CR1 UE LL_LPUART_IsEnabled
522 * @param LPUARTx LPUART Instance
523 * @retval State of bit (1 or 0).
524 */
LL_LPUART_IsEnabled(const USART_TypeDef * LPUARTx)525 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx)
526 {
527 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
528 }
529
530 /**
531 * @brief FIFO Mode Enable
532 * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
533 * @param LPUARTx LPUART Instance
534 * @retval None
535 */
LL_LPUART_EnableFIFO(USART_TypeDef * LPUARTx)536 __STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
537 {
538 SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
539 }
540
541 /**
542 * @brief FIFO Mode Disable
543 * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
544 * @param LPUARTx LPUART Instance
545 * @retval None
546 */
LL_LPUART_DisableFIFO(USART_TypeDef * LPUARTx)547 __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
548 {
549 CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
550 }
551
552 /**
553 * @brief Indicate if FIFO Mode is enabled
554 * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
555 * @param LPUARTx LPUART Instance
556 * @retval State of bit (1 or 0).
557 */
LL_LPUART_IsEnabledFIFO(const USART_TypeDef * LPUARTx)558 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx)
559 {
560 return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
561 }
562
563 /**
564 * @brief Configure TX FIFO Threshold
565 * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
566 * @param LPUARTx LPUART Instance
567 * @param Threshold This parameter can be one of the following values:
568 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
569 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
570 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
571 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
572 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
573 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
574 * @retval None
575 */
LL_LPUART_SetTXFIFOThreshold(USART_TypeDef * LPUARTx,uint32_t Threshold)576 __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
577 {
578 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
579 }
580
581 /**
582 * @brief Return TX FIFO Threshold Configuration
583 * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
584 * @param LPUARTx LPUART Instance
585 * @retval Returned value can be one of the following values:
586 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
587 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
588 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
589 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
590 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
591 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
592 */
LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef * LPUARTx)593 __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx)
594 {
595 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
596 }
597
598 /**
599 * @brief Configure RX FIFO Threshold
600 * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
601 * @param LPUARTx LPUART Instance
602 * @param Threshold This parameter can be one of the following values:
603 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
604 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
605 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
606 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
607 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
608 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
609 * @retval None
610 */
LL_LPUART_SetRXFIFOThreshold(USART_TypeDef * LPUARTx,uint32_t Threshold)611 __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
612 {
613 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
614 }
615
616 /**
617 * @brief Return RX FIFO Threshold Configuration
618 * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
619 * @param LPUARTx LPUART Instance
620 * @retval Returned value can be one of the following values:
621 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
622 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
623 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
624 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
625 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
626 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
627 */
LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef * LPUARTx)628 __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx)
629 {
630 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
631 }
632
633 /**
634 * @brief Configure TX and RX FIFOs Threshold
635 * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
636 * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
637 * @param LPUARTx LPUART Instance
638 * @param TXThreshold This parameter can be one of the following values:
639 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
640 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
641 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
642 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
643 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
644 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
645 * @param RXThreshold This parameter can be one of the following values:
646 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
647 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
648 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
649 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
650 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
651 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
652 * @retval None
653 */
LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef * LPUARTx,uint32_t TXThreshold,uint32_t RXThreshold)654 __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
655 {
656 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
657 (RXThreshold << USART_CR3_RXFTCFG_Pos));
658 }
659
660 /**
661 * @brief LPUART enabled in STOP Mode
662 * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
663 * LPUART clock selection is HSI or LSE in RCC.
664 * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
665 * @param LPUARTx LPUART Instance
666 * @retval None
667 */
LL_LPUART_EnableInStopMode(USART_TypeDef * LPUARTx)668 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
669 {
670 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
671 }
672
673 /**
674 * @brief LPUART disabled in STOP Mode
675 * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
676 * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
677 * @param LPUARTx LPUART Instance
678 * @retval None
679 */
LL_LPUART_DisableInStopMode(USART_TypeDef * LPUARTx)680 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
681 {
682 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
683 }
684
685 /**
686 * @brief Indicate if LPUART is enabled in STOP Mode
687 * (able to wake up MCU from Stop mode or not)
688 * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
689 * @param LPUARTx LPUART Instance
690 * @retval State of bit (1 or 0).
691 */
LL_LPUART_IsEnabledInStopMode(const USART_TypeDef * LPUARTx)692 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx)
693 {
694 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
695 }
696
697 /**
698 * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
699 * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
700 * @param LPUARTx LPUART Instance
701 * @retval None
702 */
LL_LPUART_EnableDirectionRx(USART_TypeDef * LPUARTx)703 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
704 {
705 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
706 }
707
708 /**
709 * @brief Receiver Disable
710 * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
711 * @param LPUARTx LPUART Instance
712 * @retval None
713 */
LL_LPUART_DisableDirectionRx(USART_TypeDef * LPUARTx)714 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
715 {
716 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
717 }
718
719 /**
720 * @brief Transmitter Enable
721 * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
722 * @param LPUARTx LPUART Instance
723 * @retval None
724 */
LL_LPUART_EnableDirectionTx(USART_TypeDef * LPUARTx)725 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
726 {
727 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
728 }
729
730 /**
731 * @brief Transmitter Disable
732 * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
733 * @param LPUARTx LPUART Instance
734 * @retval None
735 */
LL_LPUART_DisableDirectionTx(USART_TypeDef * LPUARTx)736 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
737 {
738 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
739 }
740
741 /**
742 * @brief Configure simultaneously enabled/disabled states
743 * of Transmitter and Receiver
744 * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
745 * CR1 TE LL_LPUART_SetTransferDirection
746 * @param LPUARTx LPUART Instance
747 * @param TransferDirection This parameter can be one of the following values:
748 * @arg @ref LL_LPUART_DIRECTION_NONE
749 * @arg @ref LL_LPUART_DIRECTION_RX
750 * @arg @ref LL_LPUART_DIRECTION_TX
751 * @arg @ref LL_LPUART_DIRECTION_TX_RX
752 * @retval None
753 */
LL_LPUART_SetTransferDirection(USART_TypeDef * LPUARTx,uint32_t TransferDirection)754 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
755 {
756 ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
757 }
758
759 /**
760 * @brief Return enabled/disabled states of Transmitter and Receiver
761 * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
762 * CR1 TE LL_LPUART_GetTransferDirection
763 * @param LPUARTx LPUART Instance
764 * @retval Returned value can be one of the following values:
765 * @arg @ref LL_LPUART_DIRECTION_NONE
766 * @arg @ref LL_LPUART_DIRECTION_RX
767 * @arg @ref LL_LPUART_DIRECTION_TX
768 * @arg @ref LL_LPUART_DIRECTION_TX_RX
769 */
LL_LPUART_GetTransferDirection(const USART_TypeDef * LPUARTx)770 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx)
771 {
772 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
773 }
774
775 /**
776 * @brief Configure Parity (enabled/disabled and parity mode if enabled)
777 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
778 * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
779 * (depending on data width) and parity is checked on the received data.
780 * @rmtoll CR1 PS LL_LPUART_SetParity\n
781 * CR1 PCE LL_LPUART_SetParity
782 * @param LPUARTx LPUART Instance
783 * @param Parity This parameter can be one of the following values:
784 * @arg @ref LL_LPUART_PARITY_NONE
785 * @arg @ref LL_LPUART_PARITY_EVEN
786 * @arg @ref LL_LPUART_PARITY_ODD
787 * @retval None
788 */
LL_LPUART_SetParity(USART_TypeDef * LPUARTx,uint32_t Parity)789 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
790 {
791 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
792 }
793
794 /**
795 * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
796 * @rmtoll CR1 PS LL_LPUART_GetParity\n
797 * CR1 PCE LL_LPUART_GetParity
798 * @param LPUARTx LPUART Instance
799 * @retval Returned value can be one of the following values:
800 * @arg @ref LL_LPUART_PARITY_NONE
801 * @arg @ref LL_LPUART_PARITY_EVEN
802 * @arg @ref LL_LPUART_PARITY_ODD
803 */
LL_LPUART_GetParity(const USART_TypeDef * LPUARTx)804 __STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx)
805 {
806 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
807 }
808
809 /**
810 * @brief Set Receiver Wake Up method from Mute mode.
811 * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
812 * @param LPUARTx LPUART Instance
813 * @param Method This parameter can be one of the following values:
814 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
815 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
816 * @retval None
817 */
LL_LPUART_SetWakeUpMethod(USART_TypeDef * LPUARTx,uint32_t Method)818 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
819 {
820 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
821 }
822
823 /**
824 * @brief Return Receiver Wake Up method from Mute mode
825 * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
826 * @param LPUARTx LPUART Instance
827 * @retval Returned value can be one of the following values:
828 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
829 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
830 */
LL_LPUART_GetWakeUpMethod(const USART_TypeDef * LPUARTx)831 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx)
832 {
833 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
834 }
835
836 /**
837 * @brief Set Word length (nb of data bits, excluding start and stop bits)
838 * @rmtoll CR1 M LL_LPUART_SetDataWidth
839 * @param LPUARTx LPUART Instance
840 * @param DataWidth This parameter can be one of the following values:
841 * @arg @ref LL_LPUART_DATAWIDTH_7B
842 * @arg @ref LL_LPUART_DATAWIDTH_8B
843 * @arg @ref LL_LPUART_DATAWIDTH_9B
844 * @retval None
845 */
LL_LPUART_SetDataWidth(USART_TypeDef * LPUARTx,uint32_t DataWidth)846 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
847 {
848 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
849 }
850
851 /**
852 * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
853 * @rmtoll CR1 M LL_LPUART_GetDataWidth
854 * @param LPUARTx LPUART Instance
855 * @retval Returned value can be one of the following values:
856 * @arg @ref LL_LPUART_DATAWIDTH_7B
857 * @arg @ref LL_LPUART_DATAWIDTH_8B
858 * @arg @ref LL_LPUART_DATAWIDTH_9B
859 */
LL_LPUART_GetDataWidth(const USART_TypeDef * LPUARTx)860 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx)
861 {
862 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
863 }
864
865 /**
866 * @brief Allow switch between Mute Mode and Active mode
867 * @rmtoll CR1 MME LL_LPUART_EnableMuteMode
868 * @param LPUARTx LPUART Instance
869 * @retval None
870 */
LL_LPUART_EnableMuteMode(USART_TypeDef * LPUARTx)871 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
872 {
873 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
874 }
875
876 /**
877 * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
878 * @rmtoll CR1 MME LL_LPUART_DisableMuteMode
879 * @param LPUARTx LPUART Instance
880 * @retval None
881 */
LL_LPUART_DisableMuteMode(USART_TypeDef * LPUARTx)882 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
883 {
884 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
885 }
886
887 /**
888 * @brief Indicate if switch between Mute Mode and Active mode is allowed
889 * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
890 * @param LPUARTx LPUART Instance
891 * @retval State of bit (1 or 0).
892 */
LL_LPUART_IsEnabledMuteMode(const USART_TypeDef * LPUARTx)893 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx)
894 {
895 return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
896 }
897
898 /**
899 * @brief Configure Clock source prescaler for baudrate generator and oversampling
900 * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
901 * @param LPUARTx LPUART Instance
902 * @param PrescalerValue This parameter can be one of the following values:
903 * @arg @ref LL_LPUART_PRESCALER_DIV1
904 * @arg @ref LL_LPUART_PRESCALER_DIV2
905 * @arg @ref LL_LPUART_PRESCALER_DIV4
906 * @arg @ref LL_LPUART_PRESCALER_DIV6
907 * @arg @ref LL_LPUART_PRESCALER_DIV8
908 * @arg @ref LL_LPUART_PRESCALER_DIV10
909 * @arg @ref LL_LPUART_PRESCALER_DIV12
910 * @arg @ref LL_LPUART_PRESCALER_DIV16
911 * @arg @ref LL_LPUART_PRESCALER_DIV32
912 * @arg @ref LL_LPUART_PRESCALER_DIV64
913 * @arg @ref LL_LPUART_PRESCALER_DIV128
914 * @arg @ref LL_LPUART_PRESCALER_DIV256
915 * @retval None
916 */
LL_LPUART_SetPrescaler(USART_TypeDef * LPUARTx,uint32_t PrescalerValue)917 __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
918 {
919 MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
920 }
921
922 /**
923 * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
924 * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
925 * @param LPUARTx LPUART Instance
926 * @retval Returned value can be one of the following values:
927 * @arg @ref LL_LPUART_PRESCALER_DIV1
928 * @arg @ref LL_LPUART_PRESCALER_DIV2
929 * @arg @ref LL_LPUART_PRESCALER_DIV4
930 * @arg @ref LL_LPUART_PRESCALER_DIV6
931 * @arg @ref LL_LPUART_PRESCALER_DIV8
932 * @arg @ref LL_LPUART_PRESCALER_DIV10
933 * @arg @ref LL_LPUART_PRESCALER_DIV12
934 * @arg @ref LL_LPUART_PRESCALER_DIV16
935 * @arg @ref LL_LPUART_PRESCALER_DIV32
936 * @arg @ref LL_LPUART_PRESCALER_DIV64
937 * @arg @ref LL_LPUART_PRESCALER_DIV128
938 * @arg @ref LL_LPUART_PRESCALER_DIV256
939 */
LL_LPUART_GetPrescaler(const USART_TypeDef * LPUARTx)940 __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx)
941 {
942 return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
943 }
944
945 /**
946 * @brief Set the length of the stop bits
947 * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
948 * @param LPUARTx LPUART Instance
949 * @param StopBits This parameter can be one of the following values:
950 * @arg @ref LL_LPUART_STOPBITS_1
951 * @arg @ref LL_LPUART_STOPBITS_2
952 * @retval None
953 */
LL_LPUART_SetStopBitsLength(USART_TypeDef * LPUARTx,uint32_t StopBits)954 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
955 {
956 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
957 }
958
959 /**
960 * @brief Retrieve the length of the stop bits
961 * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
962 * @param LPUARTx LPUART Instance
963 * @retval Returned value can be one of the following values:
964 * @arg @ref LL_LPUART_STOPBITS_1
965 * @arg @ref LL_LPUART_STOPBITS_2
966 */
LL_LPUART_GetStopBitsLength(const USART_TypeDef * LPUARTx)967 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx)
968 {
969 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
970 }
971
972 /**
973 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
974 * @note Call of this function is equivalent to following function call sequence :
975 * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
976 * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
977 * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
978 * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
979 * CR1 PCE LL_LPUART_ConfigCharacter\n
980 * CR1 M LL_LPUART_ConfigCharacter\n
981 * CR2 STOP LL_LPUART_ConfigCharacter
982 * @param LPUARTx LPUART Instance
983 * @param DataWidth This parameter can be one of the following values:
984 * @arg @ref LL_LPUART_DATAWIDTH_7B
985 * @arg @ref LL_LPUART_DATAWIDTH_8B
986 * @arg @ref LL_LPUART_DATAWIDTH_9B
987 * @param Parity This parameter can be one of the following values:
988 * @arg @ref LL_LPUART_PARITY_NONE
989 * @arg @ref LL_LPUART_PARITY_EVEN
990 * @arg @ref LL_LPUART_PARITY_ODD
991 * @param StopBits This parameter can be one of the following values:
992 * @arg @ref LL_LPUART_STOPBITS_1
993 * @arg @ref LL_LPUART_STOPBITS_2
994 * @retval None
995 */
LL_LPUART_ConfigCharacter(USART_TypeDef * LPUARTx,uint32_t DataWidth,uint32_t Parity,uint32_t StopBits)996 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
997 uint32_t StopBits)
998 {
999 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
1000 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
1001 }
1002
1003 /**
1004 * @brief Configure TX/RX pins swapping setting.
1005 * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
1006 * @param LPUARTx LPUART Instance
1007 * @param SwapConfig This parameter can be one of the following values:
1008 * @arg @ref LL_LPUART_TXRX_STANDARD
1009 * @arg @ref LL_LPUART_TXRX_SWAPPED
1010 * @retval None
1011 */
LL_LPUART_SetTXRXSwap(USART_TypeDef * LPUARTx,uint32_t SwapConfig)1012 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
1013 {
1014 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
1015 }
1016
1017 /**
1018 * @brief Retrieve TX/RX pins swapping configuration.
1019 * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
1020 * @param LPUARTx LPUART Instance
1021 * @retval Returned value can be one of the following values:
1022 * @arg @ref LL_LPUART_TXRX_STANDARD
1023 * @arg @ref LL_LPUART_TXRX_SWAPPED
1024 */
LL_LPUART_GetTXRXSwap(const USART_TypeDef * LPUARTx)1025 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx)
1026 {
1027 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
1028 }
1029
1030 /**
1031 * @brief Configure RX pin active level logic
1032 * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
1033 * @param LPUARTx LPUART Instance
1034 * @param PinInvMethod This parameter can be one of the following values:
1035 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1036 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1037 * @retval None
1038 */
LL_LPUART_SetRXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)1039 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1040 {
1041 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
1042 }
1043
1044 /**
1045 * @brief Retrieve RX pin active level logic configuration
1046 * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
1047 * @param LPUARTx LPUART Instance
1048 * @retval Returned value can be one of the following values:
1049 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1050 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1051 */
LL_LPUART_GetRXPinLevel(const USART_TypeDef * LPUARTx)1052 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx)
1053 {
1054 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
1055 }
1056
1057 /**
1058 * @brief Configure TX pin active level logic
1059 * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
1060 * @param LPUARTx LPUART Instance
1061 * @param PinInvMethod This parameter can be one of the following values:
1062 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1063 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1064 * @retval None
1065 */
LL_LPUART_SetTXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)1066 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1067 {
1068 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
1069 }
1070
1071 /**
1072 * @brief Retrieve TX pin active level logic configuration
1073 * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
1074 * @param LPUARTx LPUART Instance
1075 * @retval Returned value can be one of the following values:
1076 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1077 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1078 */
LL_LPUART_GetTXPinLevel(const USART_TypeDef * LPUARTx)1079 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx)
1080 {
1081 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
1082 }
1083
1084 /**
1085 * @brief Configure Binary data logic.
1086 *
1087 * @note Allow to define how Logical data from the data register are send/received :
1088 * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
1089 * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
1090 * @param LPUARTx LPUART Instance
1091 * @param DataLogic This parameter can be one of the following values:
1092 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1093 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1094 * @retval None
1095 */
LL_LPUART_SetBinaryDataLogic(USART_TypeDef * LPUARTx,uint32_t DataLogic)1096 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
1097 {
1098 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
1099 }
1100
1101 /**
1102 * @brief Retrieve Binary data configuration
1103 * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
1104 * @param LPUARTx LPUART Instance
1105 * @retval Returned value can be one of the following values:
1106 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1107 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1108 */
LL_LPUART_GetBinaryDataLogic(const USART_TypeDef * LPUARTx)1109 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx)
1110 {
1111 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
1112 }
1113
1114 /**
1115 * @brief Configure transfer bit order (either Less or Most Significant Bit First)
1116 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1117 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1118 * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
1119 * @param LPUARTx LPUART Instance
1120 * @param BitOrder This parameter can be one of the following values:
1121 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1122 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1123 * @retval None
1124 */
LL_LPUART_SetTransferBitOrder(USART_TypeDef * LPUARTx,uint32_t BitOrder)1125 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
1126 {
1127 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
1128 }
1129
1130 /**
1131 * @brief Return transfer bit order (either Less or Most Significant Bit First)
1132 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1133 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1134 * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
1135 * @param LPUARTx LPUART Instance
1136 * @retval Returned value can be one of the following values:
1137 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1138 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1139 */
LL_LPUART_GetTransferBitOrder(const USART_TypeDef * LPUARTx)1140 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx)
1141 {
1142 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
1143 }
1144
1145 /**
1146 * @brief Set Address of the LPUART node.
1147 * @note This is used in multiprocessor communication during Mute mode or Stop mode,
1148 * for wake up with address mark detection.
1149 * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
1150 * (b7-b4 should be set to 0)
1151 * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
1152 * (This is used in multiprocessor communication during Mute mode or Stop mode,
1153 * for wake up with 7-bit address mark detection.
1154 * The MSB of the character sent by the transmitter should be equal to 1.
1155 * It may also be used for character detection during normal reception,
1156 * Mute mode inactive (for example, end of block detection in ModBus protocol).
1157 * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
1158 * value and CMF flag is set on match)
1159 * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
1160 * CR2 ADDM7 LL_LPUART_ConfigNodeAddress
1161 * @param LPUARTx LPUART Instance
1162 * @param AddressLen This parameter can be one of the following values:
1163 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1164 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1165 * @param NodeAddress 4 or 7 bit Address of the LPUART node.
1166 * @retval None
1167 */
LL_LPUART_ConfigNodeAddress(USART_TypeDef * LPUARTx,uint32_t AddressLen,uint32_t NodeAddress)1168 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
1169 {
1170 MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
1171 (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
1172 }
1173
1174 /**
1175 * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
1176 * @note If 4-bit Address Detection is selected in ADDM7,
1177 * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
1178 * If 7-bit Address Detection is selected in ADDM7,
1179 * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
1180 * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
1181 * @param LPUARTx LPUART Instance
1182 * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
1183 */
LL_LPUART_GetNodeAddress(const USART_TypeDef * LPUARTx)1184 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx)
1185 {
1186 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
1187 }
1188
1189 /**
1190 * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
1191 * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
1192 * @param LPUARTx LPUART Instance
1193 * @retval Returned value can be one of the following values:
1194 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1195 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1196 */
LL_LPUART_GetNodeAddressLen(const USART_TypeDef * LPUARTx)1197 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx)
1198 {
1199 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
1200 }
1201
1202 /**
1203 * @brief Enable RTS HW Flow Control
1204 * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
1205 * @param LPUARTx LPUART Instance
1206 * @retval None
1207 */
LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)1208 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1209 {
1210 SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1211 }
1212
1213 /**
1214 * @brief Disable RTS HW Flow Control
1215 * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
1216 * @param LPUARTx LPUART Instance
1217 * @retval None
1218 */
LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)1219 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1220 {
1221 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1222 }
1223
1224 /**
1225 * @brief Enable CTS HW Flow Control
1226 * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
1227 * @param LPUARTx LPUART Instance
1228 * @retval None
1229 */
LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)1230 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1231 {
1232 SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1233 }
1234
1235 /**
1236 * @brief Disable CTS HW Flow Control
1237 * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
1238 * @param LPUARTx LPUART Instance
1239 * @retval None
1240 */
LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)1241 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1242 {
1243 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1244 }
1245
1246 /**
1247 * @brief Configure HW Flow Control mode (both CTS and RTS)
1248 * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
1249 * CR3 CTSE LL_LPUART_SetHWFlowCtrl
1250 * @param LPUARTx LPUART Instance
1251 * @param HardwareFlowControl This parameter can be one of the following values:
1252 * @arg @ref LL_LPUART_HWCONTROL_NONE
1253 * @arg @ref LL_LPUART_HWCONTROL_RTS
1254 * @arg @ref LL_LPUART_HWCONTROL_CTS
1255 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1256 * @retval None
1257 */
LL_LPUART_SetHWFlowCtrl(USART_TypeDef * LPUARTx,uint32_t HardwareFlowControl)1258 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
1259 {
1260 MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
1261 }
1262
1263 /**
1264 * @brief Return HW Flow Control configuration (both CTS and RTS)
1265 * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
1266 * CR3 CTSE LL_LPUART_GetHWFlowCtrl
1267 * @param LPUARTx LPUART Instance
1268 * @retval Returned value can be one of the following values:
1269 * @arg @ref LL_LPUART_HWCONTROL_NONE
1270 * @arg @ref LL_LPUART_HWCONTROL_RTS
1271 * @arg @ref LL_LPUART_HWCONTROL_CTS
1272 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1273 */
LL_LPUART_GetHWFlowCtrl(const USART_TypeDef * LPUARTx)1274 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx)
1275 {
1276 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
1277 }
1278
1279 /**
1280 * @brief Enable Overrun detection
1281 * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
1282 * @param LPUARTx LPUART Instance
1283 * @retval None
1284 */
LL_LPUART_EnableOverrunDetect(USART_TypeDef * LPUARTx)1285 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
1286 {
1287 CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1288 }
1289
1290 /**
1291 * @brief Disable Overrun detection
1292 * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
1293 * @param LPUARTx LPUART Instance
1294 * @retval None
1295 */
LL_LPUART_DisableOverrunDetect(USART_TypeDef * LPUARTx)1296 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
1297 {
1298 SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1299 }
1300
1301 /**
1302 * @brief Indicate if Overrun detection is enabled
1303 * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
1304 * @param LPUARTx LPUART Instance
1305 * @retval State of bit (1 or 0).
1306 */
LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef * LPUARTx)1307 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx)
1308 {
1309 return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
1310 }
1311
1312 /**
1313 * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1314 * @rmtoll CR3 WUS LL_LPUART_SetWKUPType
1315 * @param LPUARTx LPUART Instance
1316 * @param Type This parameter can be one of the following values:
1317 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1318 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1319 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1320 * @retval None
1321 */
LL_LPUART_SetWKUPType(USART_TypeDef * LPUARTx,uint32_t Type)1322 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
1323 {
1324 MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
1325 }
1326
1327 /**
1328 * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1329 * @rmtoll CR3 WUS LL_LPUART_GetWKUPType
1330 * @param LPUARTx LPUART Instance
1331 * @retval Returned value can be one of the following values:
1332 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1333 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1334 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1335 */
LL_LPUART_GetWKUPType(const USART_TypeDef * LPUARTx)1336 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx)
1337 {
1338 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
1339 }
1340
1341 /**
1342 * @brief Configure LPUART BRR register for achieving expected Baud Rate value.
1343 *
1344 * @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
1345 * according to used Peripheral Clock and expected Baud Rate values
1346 * @note Peripheral clock and Baud Rate values provided as function parameters should be valid
1347 * (Baud rate value != 0).
1348 * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
1349 * a care should be taken when generating high baud rates using high PeriphClk
1350 * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
1351 * @rmtoll BRR BRR LL_LPUART_SetBaudRate
1352 * @param LPUARTx LPUART Instance
1353 * @param PeriphClk Peripheral Clock
1354 * @param PrescalerValue This parameter can be one of the following values:
1355 * @arg @ref LL_LPUART_PRESCALER_DIV1
1356 * @arg @ref LL_LPUART_PRESCALER_DIV2
1357 * @arg @ref LL_LPUART_PRESCALER_DIV4
1358 * @arg @ref LL_LPUART_PRESCALER_DIV6
1359 * @arg @ref LL_LPUART_PRESCALER_DIV8
1360 * @arg @ref LL_LPUART_PRESCALER_DIV10
1361 * @arg @ref LL_LPUART_PRESCALER_DIV12
1362 * @arg @ref LL_LPUART_PRESCALER_DIV16
1363 * @arg @ref LL_LPUART_PRESCALER_DIV32
1364 * @arg @ref LL_LPUART_PRESCALER_DIV64
1365 * @arg @ref LL_LPUART_PRESCALER_DIV128
1366 * @arg @ref LL_LPUART_PRESCALER_DIV256
1367 * @param BaudRate Baud Rate
1368 * @retval None
1369 */
LL_LPUART_SetBaudRate(USART_TypeDef * LPUARTx,uint32_t PeriphClk,uint32_t PrescalerValue,uint32_t BaudRate)1370 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
1371 uint32_t BaudRate)
1372 {
1373 if (BaudRate != 0U)
1374 {
1375 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
1376 }
1377 }
1378
1379 /**
1380 * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
1381 * (full BRR content), and to used Peripheral Clock values
1382 * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
1383 * @rmtoll BRR BRR LL_LPUART_GetBaudRate
1384 * @param LPUARTx LPUART Instance
1385 * @param PeriphClk Peripheral Clock
1386 * @param PrescalerValue This parameter can be one of the following values:
1387 * @arg @ref LL_LPUART_PRESCALER_DIV1
1388 * @arg @ref LL_LPUART_PRESCALER_DIV2
1389 * @arg @ref LL_LPUART_PRESCALER_DIV4
1390 * @arg @ref LL_LPUART_PRESCALER_DIV6
1391 * @arg @ref LL_LPUART_PRESCALER_DIV8
1392 * @arg @ref LL_LPUART_PRESCALER_DIV10
1393 * @arg @ref LL_LPUART_PRESCALER_DIV12
1394 * @arg @ref LL_LPUART_PRESCALER_DIV16
1395 * @arg @ref LL_LPUART_PRESCALER_DIV32
1396 * @arg @ref LL_LPUART_PRESCALER_DIV64
1397 * @arg @ref LL_LPUART_PRESCALER_DIV128
1398 * @arg @ref LL_LPUART_PRESCALER_DIV256
1399 * @retval Baud Rate
1400 */
LL_LPUART_GetBaudRate(const USART_TypeDef * LPUARTx,uint32_t PeriphClk,uint32_t PrescalerValue)1401 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
1402 uint32_t PrescalerValue)
1403 {
1404 uint32_t lpuartdiv;
1405 uint32_t brrresult;
1406 uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
1407
1408 lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
1409
1410 if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
1411 {
1412 brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
1413 }
1414 else
1415 {
1416 brrresult = 0x0UL;
1417 }
1418
1419 return (brrresult);
1420 }
1421
1422 /**
1423 * @}
1424 */
1425
1426 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
1427 * @{
1428 */
1429
1430 /**
1431 * @brief Enable Single Wire Half-Duplex mode
1432 * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
1433 * @param LPUARTx LPUART Instance
1434 * @retval None
1435 */
LL_LPUART_EnableHalfDuplex(USART_TypeDef * LPUARTx)1436 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
1437 {
1438 SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1439 }
1440
1441 /**
1442 * @brief Disable Single Wire Half-Duplex mode
1443 * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
1444 * @param LPUARTx LPUART Instance
1445 * @retval None
1446 */
LL_LPUART_DisableHalfDuplex(USART_TypeDef * LPUARTx)1447 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
1448 {
1449 CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1450 }
1451
1452 /**
1453 * @brief Indicate if Single Wire Half-Duplex mode is enabled
1454 * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
1455 * @param LPUARTx LPUART Instance
1456 * @retval State of bit (1 or 0).
1457 */
LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef * LPUARTx)1458 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx)
1459 {
1460 return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
1461 }
1462
1463 /**
1464 * @}
1465 */
1466
1467 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
1468 * @{
1469 */
1470
1471 /**
1472 * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1473 * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
1474 * @param LPUARTx LPUART Instance
1475 * @param Time Value between Min_Data=0 and Max_Data=31
1476 * @retval None
1477 */
LL_LPUART_SetDEDeassertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1478 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1479 {
1480 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
1481 }
1482
1483 /**
1484 * @brief Return DEDT (Driver Enable De-Assertion Time)
1485 * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
1486 * @param LPUARTx LPUART Instance
1487 * @retval Time value expressed on 5 bits ([4:0] bits) : c
1488 */
LL_LPUART_GetDEDeassertionTime(const USART_TypeDef * LPUARTx)1489 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx)
1490 {
1491 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
1492 }
1493
1494 /**
1495 * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1496 * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
1497 * @param LPUARTx LPUART Instance
1498 * @param Time Value between Min_Data=0 and Max_Data=31
1499 * @retval None
1500 */
LL_LPUART_SetDEAssertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1501 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1502 {
1503 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
1504 }
1505
1506 /**
1507 * @brief Return DEAT (Driver Enable Assertion Time)
1508 * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
1509 * @param LPUARTx LPUART Instance
1510 * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
1511 */
LL_LPUART_GetDEAssertionTime(const USART_TypeDef * LPUARTx)1512 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx)
1513 {
1514 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
1515 }
1516
1517 /**
1518 * @brief Enable Driver Enable (DE) Mode
1519 * @rmtoll CR3 DEM LL_LPUART_EnableDEMode
1520 * @param LPUARTx LPUART Instance
1521 * @retval None
1522 */
LL_LPUART_EnableDEMode(USART_TypeDef * LPUARTx)1523 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
1524 {
1525 SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
1526 }
1527
1528 /**
1529 * @brief Disable Driver Enable (DE) Mode
1530 * @rmtoll CR3 DEM LL_LPUART_DisableDEMode
1531 * @param LPUARTx LPUART Instance
1532 * @retval None
1533 */
LL_LPUART_DisableDEMode(USART_TypeDef * LPUARTx)1534 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
1535 {
1536 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
1537 }
1538
1539 /**
1540 * @brief Indicate if Driver Enable (DE) Mode is enabled
1541 * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
1542 * @param LPUARTx LPUART Instance
1543 * @retval State of bit (1 or 0).
1544 */
LL_LPUART_IsEnabledDEMode(const USART_TypeDef * LPUARTx)1545 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx)
1546 {
1547 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
1548 }
1549
1550 /**
1551 * @brief Select Driver Enable Polarity
1552 * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
1553 * @param LPUARTx LPUART Instance
1554 * @param Polarity This parameter can be one of the following values:
1555 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1556 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1557 * @retval None
1558 */
LL_LPUART_SetDESignalPolarity(USART_TypeDef * LPUARTx,uint32_t Polarity)1559 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
1560 {
1561 MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
1562 }
1563
1564 /**
1565 * @brief Return Driver Enable Polarity
1566 * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
1567 * @param LPUARTx LPUART Instance
1568 * @retval Returned value can be one of the following values:
1569 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1570 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1571 */
LL_LPUART_GetDESignalPolarity(const USART_TypeDef * LPUARTx)1572 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx)
1573 {
1574 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
1575 }
1576
1577 /**
1578 * @}
1579 */
1580
1581 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
1582 * @{
1583 */
1584
1585 /**
1586 * @brief Check if the LPUART Parity Error Flag is set or not
1587 * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
1588 * @param LPUARTx LPUART Instance
1589 * @retval State of bit (1 or 0).
1590 */
LL_LPUART_IsActiveFlag_PE(const USART_TypeDef * LPUARTx)1591 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx)
1592 {
1593 return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
1594 }
1595
1596 /**
1597 * @brief Check if the LPUART Framing Error Flag is set or not
1598 * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
1599 * @param LPUARTx LPUART Instance
1600 * @retval State of bit (1 or 0).
1601 */
LL_LPUART_IsActiveFlag_FE(const USART_TypeDef * LPUARTx)1602 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx)
1603 {
1604 return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
1605 }
1606
1607 /**
1608 * @brief Check if the LPUART Noise error detected Flag is set or not
1609 * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
1610 * @param LPUARTx LPUART Instance
1611 * @retval State of bit (1 or 0).
1612 */
LL_LPUART_IsActiveFlag_NE(const USART_TypeDef * LPUARTx)1613 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx)
1614 {
1615 return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
1616 }
1617
1618 /**
1619 * @brief Check if the LPUART OverRun Error Flag is set or not
1620 * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
1621 * @param LPUARTx LPUART Instance
1622 * @retval State of bit (1 or 0).
1623 */
LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef * LPUARTx)1624 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx)
1625 {
1626 return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
1627 }
1628
1629 /**
1630 * @brief Check if the LPUART IDLE line detected Flag is set or not
1631 * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
1632 * @param LPUARTx LPUART Instance
1633 * @retval State of bit (1 or 0).
1634 */
LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef * LPUARTx)1635 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx)
1636 {
1637 return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
1638 }
1639
1640 #define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
1641
1642 /**
1643 * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
1644 * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
1645 * @param LPUARTx LPUART Instance
1646 * @retval State of bit (1 or 0).
1647 */
LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef * LPUARTx)1648 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
1649 {
1650 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
1651 }
1652
1653 /**
1654 * @brief Check if the LPUART Transmission Complete Flag is set or not
1655 * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
1656 * @param LPUARTx LPUART Instance
1657 * @retval State of bit (1 or 0).
1658 */
LL_LPUART_IsActiveFlag_TC(const USART_TypeDef * LPUARTx)1659 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
1660 {
1661 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
1662 }
1663
1664 #define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
1665
1666 /**
1667 * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
1668 * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
1669 * @param LPUARTx LPUART Instance
1670 * @retval State of bit (1 or 0).
1671 */
LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef * LPUARTx)1672 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx)
1673 {
1674 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
1675 }
1676
1677 /**
1678 * @brief Check if the LPUART CTS interrupt Flag is set or not
1679 * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
1680 * @param LPUARTx LPUART Instance
1681 * @retval State of bit (1 or 0).
1682 */
LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef * LPUARTx)1683 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx)
1684 {
1685 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
1686 }
1687
1688 /**
1689 * @brief Check if the LPUART CTS Flag is set or not
1690 * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
1691 * @param LPUARTx LPUART Instance
1692 * @retval State of bit (1 or 0).
1693 */
LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef * LPUARTx)1694 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx)
1695 {
1696 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
1697 }
1698
1699 /**
1700 * @brief Check if the LPUART Busy Flag is set or not
1701 * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
1702 * @param LPUARTx LPUART Instance
1703 * @retval State of bit (1 or 0).
1704 */
LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef * LPUARTx)1705 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx)
1706 {
1707 return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
1708 }
1709
1710 /**
1711 * @brief Check if the LPUART Character Match Flag is set or not
1712 * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
1713 * @param LPUARTx LPUART Instance
1714 * @retval State of bit (1 or 0).
1715 */
LL_LPUART_IsActiveFlag_CM(const USART_TypeDef * LPUARTx)1716 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx)
1717 {
1718 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
1719 }
1720
1721 /**
1722 * @brief Check if the LPUART Send Break Flag is set or not
1723 * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
1724 * @param LPUARTx LPUART Instance
1725 * @retval State of bit (1 or 0).
1726 */
LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef * LPUARTx)1727 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx)
1728 {
1729 return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
1730 }
1731
1732 /**
1733 * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
1734 * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
1735 * @param LPUARTx LPUART Instance
1736 * @retval State of bit (1 or 0).
1737 */
LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef * LPUARTx)1738 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx)
1739 {
1740 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
1741 }
1742
1743 /**
1744 * @brief Check if the LPUART Wake Up from stop mode Flag is set or not
1745 * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
1746 * @param LPUARTx LPUART Instance
1747 * @retval State of bit (1 or 0).
1748 */
LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef * LPUARTx)1749 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx)
1750 {
1751 return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
1752 }
1753
1754 /**
1755 * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
1756 * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
1757 * @param LPUARTx LPUART Instance
1758 * @retval State of bit (1 or 0).
1759 */
LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef * LPUARTx)1760 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx)
1761 {
1762 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
1763 }
1764
1765 /**
1766 * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
1767 * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
1768 * @param LPUARTx LPUART Instance
1769 * @retval State of bit (1 or 0).
1770 */
LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef * LPUARTx)1771 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx)
1772 {
1773 return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
1774 }
1775
1776 /**
1777 * @brief Check if the LPUART TX FIFO Empty Flag is set or not
1778 * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
1779 * @param LPUARTx LPUART Instance
1780 * @retval State of bit (1 or 0).
1781 */
LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef * LPUARTx)1782 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx)
1783 {
1784 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
1785 }
1786
1787 /**
1788 * @brief Check if the LPUART RX FIFO Full Flag is set or not
1789 * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
1790 * @param LPUARTx LPUART Instance
1791 * @retval State of bit (1 or 0).
1792 */
LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef * LPUARTx)1793 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx)
1794 {
1795 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
1796 }
1797
1798 /**
1799 * @brief Check if the LPUART TX FIFO Threshold Flag is set or not
1800 * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
1801 * @param LPUARTx LPUART Instance
1802 * @retval State of bit (1 or 0).
1803 */
LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef * LPUARTx)1804 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx)
1805 {
1806 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
1807 }
1808
1809 /**
1810 * @brief Check if the LPUART RX FIFO Threshold Flag is set or not
1811 * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
1812 * @param LPUARTx LPUART Instance
1813 * @retval State of bit (1 or 0).
1814 */
LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef * LPUARTx)1815 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx)
1816 {
1817 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
1818 }
1819
1820 /**
1821 * @brief Clear Parity Error Flag
1822 * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
1823 * @param LPUARTx LPUART Instance
1824 * @retval None
1825 */
LL_LPUART_ClearFlag_PE(USART_TypeDef * LPUARTx)1826 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
1827 {
1828 WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
1829 }
1830
1831 /**
1832 * @brief Clear Framing Error Flag
1833 * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
1834 * @param LPUARTx LPUART Instance
1835 * @retval None
1836 */
LL_LPUART_ClearFlag_FE(USART_TypeDef * LPUARTx)1837 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
1838 {
1839 WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
1840 }
1841
1842 /**
1843 * @brief Clear Noise detected Flag
1844 * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
1845 * @param LPUARTx LPUART Instance
1846 * @retval None
1847 */
LL_LPUART_ClearFlag_NE(USART_TypeDef * LPUARTx)1848 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
1849 {
1850 WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
1851 }
1852
1853 /**
1854 * @brief Clear OverRun Error Flag
1855 * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
1856 * @param LPUARTx LPUART Instance
1857 * @retval None
1858 */
LL_LPUART_ClearFlag_ORE(USART_TypeDef * LPUARTx)1859 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
1860 {
1861 WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
1862 }
1863
1864 /**
1865 * @brief Clear IDLE line detected Flag
1866 * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
1867 * @param LPUARTx LPUART Instance
1868 * @retval None
1869 */
LL_LPUART_ClearFlag_IDLE(USART_TypeDef * LPUARTx)1870 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
1871 {
1872 WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
1873 }
1874
1875 /**
1876 * @brief Clear Transmission Complete Flag
1877 * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
1878 * @param LPUARTx LPUART Instance
1879 * @retval None
1880 */
LL_LPUART_ClearFlag_TC(USART_TypeDef * LPUARTx)1881 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
1882 {
1883 WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
1884 }
1885
1886 /**
1887 * @brief Clear CTS Interrupt Flag
1888 * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
1889 * @param LPUARTx LPUART Instance
1890 * @retval None
1891 */
LL_LPUART_ClearFlag_nCTS(USART_TypeDef * LPUARTx)1892 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
1893 {
1894 WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
1895 }
1896
1897 /**
1898 * @brief Clear Character Match Flag
1899 * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
1900 * @param LPUARTx LPUART Instance
1901 * @retval None
1902 */
LL_LPUART_ClearFlag_CM(USART_TypeDef * LPUARTx)1903 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
1904 {
1905 WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
1906 }
1907
1908 /**
1909 * @brief Clear Wake Up from stop mode Flag
1910 * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
1911 * @param LPUARTx LPUART Instance
1912 * @retval None
1913 */
LL_LPUART_ClearFlag_WKUP(USART_TypeDef * LPUARTx)1914 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
1915 {
1916 WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
1917 }
1918
1919 /**
1920 * @}
1921 */
1922
1923 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
1924 * @{
1925 */
1926
1927 /**
1928 * @brief Enable IDLE Interrupt
1929 * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
1930 * @param LPUARTx LPUART Instance
1931 * @retval None
1932 */
LL_LPUART_EnableIT_IDLE(USART_TypeDef * LPUARTx)1933 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
1934 {
1935 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
1936 }
1937
1938 #define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
1939
1940 /**
1941 * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
1942 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
1943 * @param LPUARTx LPUART Instance
1944 * @retval None
1945 */
LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef * LPUARTx)1946 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
1947 {
1948 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
1949 }
1950
1951 /**
1952 * @brief Enable Transmission Complete Interrupt
1953 * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
1954 * @param LPUARTx LPUART Instance
1955 * @retval None
1956 */
LL_LPUART_EnableIT_TC(USART_TypeDef * LPUARTx)1957 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
1958 {
1959 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
1960 }
1961
1962 #define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
1963
1964 /**
1965 * @brief Enable TX Empty and TX FIFO Not Full Interrupt
1966 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
1967 * @param LPUARTx LPUART Instance
1968 * @retval None
1969 */
LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef * LPUARTx)1970 __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
1971 {
1972 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
1973 }
1974
1975 /**
1976 * @brief Enable Parity Error Interrupt
1977 * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
1978 * @param LPUARTx LPUART Instance
1979 * @retval None
1980 */
LL_LPUART_EnableIT_PE(USART_TypeDef * LPUARTx)1981 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
1982 {
1983 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
1984 }
1985
1986 /**
1987 * @brief Enable Character Match Interrupt
1988 * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
1989 * @param LPUARTx LPUART Instance
1990 * @retval None
1991 */
LL_LPUART_EnableIT_CM(USART_TypeDef * LPUARTx)1992 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
1993 {
1994 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
1995 }
1996
1997 /**
1998 * @brief Enable TX FIFO Empty Interrupt
1999 * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
2000 * @param LPUARTx LPUART Instance
2001 * @retval None
2002 */
LL_LPUART_EnableIT_TXFE(USART_TypeDef * LPUARTx)2003 __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
2004 {
2005 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2006 }
2007
2008 /**
2009 * @brief Enable RX FIFO Full Interrupt
2010 * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
2011 * @param LPUARTx LPUART Instance
2012 * @retval None
2013 */
LL_LPUART_EnableIT_RXFF(USART_TypeDef * LPUARTx)2014 __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
2015 {
2016 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2017 }
2018
2019 /**
2020 * @brief Enable Error Interrupt
2021 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2022 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2023 * - 0: Interrupt is inhibited
2024 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2025 * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
2026 * @param LPUARTx LPUART Instance
2027 * @retval None
2028 */
LL_LPUART_EnableIT_ERROR(USART_TypeDef * LPUARTx)2029 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
2030 {
2031 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
2032 }
2033
2034 /**
2035 * @brief Enable CTS Interrupt
2036 * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
2037 * @param LPUARTx LPUART Instance
2038 * @retval None
2039 */
LL_LPUART_EnableIT_CTS(USART_TypeDef * LPUARTx)2040 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
2041 {
2042 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2043 }
2044
2045 /**
2046 * @brief Enable Wake Up from Stop Mode Interrupt
2047 * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
2048 * @param LPUARTx LPUART Instance
2049 * @retval None
2050 */
LL_LPUART_EnableIT_WKUP(USART_TypeDef * LPUARTx)2051 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
2052 {
2053 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2054 }
2055
2056 /**
2057 * @brief Enable TX FIFO Threshold Interrupt
2058 * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
2059 * @param LPUARTx LPUART Instance
2060 * @retval None
2061 */
LL_LPUART_EnableIT_TXFT(USART_TypeDef * LPUARTx)2062 __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
2063 {
2064 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2065 }
2066
2067 /**
2068 * @brief Enable RX FIFO Threshold Interrupt
2069 * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
2070 * @param LPUARTx LPUART Instance
2071 * @retval None
2072 */
LL_LPUART_EnableIT_RXFT(USART_TypeDef * LPUARTx)2073 __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
2074 {
2075 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2076 }
2077
2078 /**
2079 * @brief Disable IDLE Interrupt
2080 * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
2081 * @param LPUARTx LPUART Instance
2082 * @retval None
2083 */
LL_LPUART_DisableIT_IDLE(USART_TypeDef * LPUARTx)2084 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
2085 {
2086 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
2087 }
2088
2089 #define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
2090
2091 /**
2092 * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
2093 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
2094 * @param LPUARTx LPUART Instance
2095 * @retval None
2096 */
LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef * LPUARTx)2097 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2098 {
2099 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
2100 }
2101
2102 /**
2103 * @brief Disable Transmission Complete Interrupt
2104 * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
2105 * @param LPUARTx LPUART Instance
2106 * @retval None
2107 */
LL_LPUART_DisableIT_TC(USART_TypeDef * LPUARTx)2108 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
2109 {
2110 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
2111 }
2112
2113 #define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
2114
2115 /**
2116 * @brief Disable TX Empty and TX FIFO Not Full Interrupt
2117 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
2118 * @param LPUARTx LPUART Instance
2119 * @retval None
2120 */
LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef * LPUARTx)2121 __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2122 {
2123 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
2124 }
2125
2126 /**
2127 * @brief Disable Parity Error Interrupt
2128 * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
2129 * @param LPUARTx LPUART Instance
2130 * @retval None
2131 */
LL_LPUART_DisableIT_PE(USART_TypeDef * LPUARTx)2132 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
2133 {
2134 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
2135 }
2136
2137 /**
2138 * @brief Disable Character Match Interrupt
2139 * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
2140 * @param LPUARTx LPUART Instance
2141 * @retval None
2142 */
LL_LPUART_DisableIT_CM(USART_TypeDef * LPUARTx)2143 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
2144 {
2145 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
2146 }
2147
2148 /**
2149 * @brief Disable TX FIFO Empty Interrupt
2150 * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
2151 * @param LPUARTx LPUART Instance
2152 * @retval None
2153 */
LL_LPUART_DisableIT_TXFE(USART_TypeDef * LPUARTx)2154 __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
2155 {
2156 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2157 }
2158
2159 /**
2160 * @brief Disable RX FIFO Full Interrupt
2161 * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
2162 * @param LPUARTx LPUART Instance
2163 * @retval None
2164 */
LL_LPUART_DisableIT_RXFF(USART_TypeDef * LPUARTx)2165 __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
2166 {
2167 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2168 }
2169
2170 /**
2171 * @brief Disable Error Interrupt
2172 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2173 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2174 * - 0: Interrupt is inhibited
2175 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2176 * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
2177 * @param LPUARTx LPUART Instance
2178 * @retval None
2179 */
LL_LPUART_DisableIT_ERROR(USART_TypeDef * LPUARTx)2180 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
2181 {
2182 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
2183 }
2184
2185 /**
2186 * @brief Disable CTS Interrupt
2187 * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
2188 * @param LPUARTx LPUART Instance
2189 * @retval None
2190 */
LL_LPUART_DisableIT_CTS(USART_TypeDef * LPUARTx)2191 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
2192 {
2193 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2194 }
2195
2196 /**
2197 * @brief Disable Wake Up from Stop Mode Interrupt
2198 * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
2199 * @param LPUARTx LPUART Instance
2200 * @retval None
2201 */
LL_LPUART_DisableIT_WKUP(USART_TypeDef * LPUARTx)2202 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
2203 {
2204 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2205 }
2206
2207 /**
2208 * @brief Disable TX FIFO Threshold Interrupt
2209 * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
2210 * @param LPUARTx LPUART Instance
2211 * @retval None
2212 */
LL_LPUART_DisableIT_TXFT(USART_TypeDef * LPUARTx)2213 __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
2214 {
2215 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2216 }
2217
2218 /**
2219 * @brief Disable RX FIFO Threshold Interrupt
2220 * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
2221 * @param LPUARTx LPUART Instance
2222 * @retval None
2223 */
LL_LPUART_DisableIT_RXFT(USART_TypeDef * LPUARTx)2224 __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
2225 {
2226 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2227 }
2228
2229 /**
2230 * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
2231 * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
2232 * @param LPUARTx LPUART Instance
2233 * @retval State of bit (1 or 0).
2234 */
LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef * LPUARTx)2235 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx)
2236 {
2237 return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
2238 }
2239
2240 #define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
2241
2242 /**
2243 * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
2244 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
2245 * @param LPUARTx LPUART Instance
2246 * @retval State of bit (1 or 0).
2247 */
LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef * LPUARTx)2248 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
2249 {
2250 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
2251 }
2252
2253 /**
2254 * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
2255 * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
2256 * @param LPUARTx LPUART Instance
2257 * @retval State of bit (1 or 0).
2258 */
LL_LPUART_IsEnabledIT_TC(const USART_TypeDef * LPUARTx)2259 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
2260 {
2261 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
2262 }
2263
2264 #define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
2265
2266 /**
2267 * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
2268 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
2269 * @param LPUARTx LPUART Instance
2270 * @retval State of bit (1 or 0).
2271 */
LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef * LPUARTx)2272 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx)
2273 {
2274 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
2275 }
2276
2277 /**
2278 * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
2279 * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
2280 * @param LPUARTx LPUART Instance
2281 * @retval State of bit (1 or 0).
2282 */
LL_LPUART_IsEnabledIT_PE(const USART_TypeDef * LPUARTx)2283 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx)
2284 {
2285 return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
2286 }
2287
2288 /**
2289 * @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
2290 * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
2291 * @param LPUARTx LPUART Instance
2292 * @retval State of bit (1 or 0).
2293 */
LL_LPUART_IsEnabledIT_CM(const USART_TypeDef * LPUARTx)2294 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx)
2295 {
2296 return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
2297 }
2298
2299 /**
2300 * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
2301 * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
2302 * @param LPUARTx LPUART Instance
2303 * @retval State of bit (1 or 0).
2304 */
LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef * LPUARTx)2305 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx)
2306 {
2307 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
2308 }
2309
2310 /**
2311 * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
2312 * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
2313 * @param LPUARTx LPUART Instance
2314 * @retval State of bit (1 or 0).
2315 */
LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef * LPUARTx)2316 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx)
2317 {
2318 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
2319 }
2320
2321 /**
2322 * @brief Check if the LPUART Error Interrupt is enabled or disabled.
2323 * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
2324 * @param LPUARTx LPUART Instance
2325 * @retval State of bit (1 or 0).
2326 */
LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef * LPUARTx)2327 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx)
2328 {
2329 return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
2330 }
2331
2332 /**
2333 * @brief Check if the LPUART CTS Interrupt is enabled or disabled.
2334 * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
2335 * @param LPUARTx LPUART Instance
2336 * @retval State of bit (1 or 0).
2337 */
LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef * LPUARTx)2338 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx)
2339 {
2340 return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
2341 }
2342
2343 /**
2344 * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
2345 * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
2346 * @param LPUARTx LPUART Instance
2347 * @retval State of bit (1 or 0).
2348 */
LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef * LPUARTx)2349 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx)
2350 {
2351 return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
2352 }
2353
2354 /**
2355 * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
2356 * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
2357 * @param LPUARTx LPUART Instance
2358 * @retval State of bit (1 or 0).
2359 */
LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef * LPUARTx)2360 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx)
2361 {
2362 return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
2363 }
2364
2365 /**
2366 * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
2367 * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
2368 * @param LPUARTx LPUART Instance
2369 * @retval State of bit (1 or 0).
2370 */
LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef * LPUARTx)2371 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx)
2372 {
2373 return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
2374 }
2375
2376 /**
2377 * @}
2378 */
2379
2380 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
2381 * @{
2382 */
2383
2384 /**
2385 * @brief Enable DMA Mode for reception
2386 * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
2387 * @param LPUARTx LPUART Instance
2388 * @retval None
2389 */
LL_LPUART_EnableDMAReq_RX(USART_TypeDef * LPUARTx)2390 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
2391 {
2392 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2393 }
2394
2395 /**
2396 * @brief Disable DMA Mode for reception
2397 * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
2398 * @param LPUARTx LPUART Instance
2399 * @retval None
2400 */
LL_LPUART_DisableDMAReq_RX(USART_TypeDef * LPUARTx)2401 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
2402 {
2403 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2404 }
2405
2406 /**
2407 * @brief Check if DMA Mode is enabled for reception
2408 * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
2409 * @param LPUARTx LPUART Instance
2410 * @retval State of bit (1 or 0).
2411 */
LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef * LPUARTx)2412 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx)
2413 {
2414 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
2415 }
2416
2417 /**
2418 * @brief Enable DMA Mode for transmission
2419 * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
2420 * @param LPUARTx LPUART Instance
2421 * @retval None
2422 */
LL_LPUART_EnableDMAReq_TX(USART_TypeDef * LPUARTx)2423 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
2424 {
2425 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2426 }
2427
2428 /**
2429 * @brief Disable DMA Mode for transmission
2430 * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
2431 * @param LPUARTx LPUART Instance
2432 * @retval None
2433 */
LL_LPUART_DisableDMAReq_TX(USART_TypeDef * LPUARTx)2434 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
2435 {
2436 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2437 }
2438
2439 /**
2440 * @brief Check if DMA Mode is enabled for transmission
2441 * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
2442 * @param LPUARTx LPUART Instance
2443 * @retval State of bit (1 or 0).
2444 */
LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef * LPUARTx)2445 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx)
2446 {
2447 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
2448 }
2449
2450 /**
2451 * @brief Enable DMA Disabling on Reception Error
2452 * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
2453 * @param LPUARTx LPUART Instance
2454 * @retval None
2455 */
LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2456 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2457 {
2458 SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2459 }
2460
2461 /**
2462 * @brief Disable DMA Disabling on Reception Error
2463 * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
2464 * @param LPUARTx LPUART Instance
2465 * @retval None
2466 */
LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2467 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2468 {
2469 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2470 }
2471
2472 /**
2473 * @brief Indicate if DMA Disabling on Reception Error is disabled
2474 * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
2475 * @param LPUARTx LPUART Instance
2476 * @retval State of bit (1 or 0).
2477 */
LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef * LPUARTx)2478 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx)
2479 {
2480 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
2481 }
2482
2483 /**
2484 * @brief Get the LPUART data register address used for DMA transfer
2485 * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
2486 * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
2487 * @param LPUARTx LPUART Instance
2488 * @param Direction This parameter can be one of the following values:
2489 * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
2490 * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
2491 * @retval Address of data register
2492 */
LL_LPUART_DMA_GetRegAddr(const USART_TypeDef * LPUARTx,uint32_t Direction)2493 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction)
2494 {
2495 uint32_t data_reg_addr;
2496
2497 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
2498 {
2499 /* return address of TDR register */
2500 data_reg_addr = (uint32_t) &(LPUARTx->TDR);
2501 }
2502 else
2503 {
2504 /* return address of RDR register */
2505 data_reg_addr = (uint32_t) &(LPUARTx->RDR);
2506 }
2507
2508 return data_reg_addr;
2509 }
2510
2511 /**
2512 * @}
2513 */
2514
2515 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
2516 * @{
2517 */
2518
2519 /**
2520 * @brief Read Receiver Data register (Receive Data value, 8 bits)
2521 * @rmtoll RDR RDR LL_LPUART_ReceiveData8
2522 * @param LPUARTx LPUART Instance
2523 * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
2524 */
LL_LPUART_ReceiveData8(const USART_TypeDef * LPUARTx)2525 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx)
2526 {
2527 return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
2528 }
2529
2530 /**
2531 * @brief Read Receiver Data register (Receive Data value, 9 bits)
2532 * @rmtoll RDR RDR LL_LPUART_ReceiveData9
2533 * @param LPUARTx LPUART Instance
2534 * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
2535 */
LL_LPUART_ReceiveData9(const USART_TypeDef * LPUARTx)2536 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx)
2537 {
2538 return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
2539 }
2540
2541 /**
2542 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
2543 * @rmtoll TDR TDR LL_LPUART_TransmitData8
2544 * @param LPUARTx LPUART Instance
2545 * @param Value between Min_Data=0x00 and Max_Data=0xFF
2546 * @retval None
2547 */
LL_LPUART_TransmitData8(USART_TypeDef * LPUARTx,uint8_t Value)2548 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
2549 {
2550 LPUARTx->TDR = Value;
2551 }
2552
2553 /**
2554 * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
2555 * @rmtoll TDR TDR LL_LPUART_TransmitData9
2556 * @param LPUARTx LPUART Instance
2557 * @param Value between Min_Data=0x00 and Max_Data=0x1FF
2558 * @retval None
2559 */
LL_LPUART_TransmitData9(USART_TypeDef * LPUARTx,uint16_t Value)2560 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
2561 {
2562 LPUARTx->TDR = Value & 0x1FFUL;
2563 }
2564
2565 /**
2566 * @}
2567 */
2568
2569 /** @defgroup LPUART_LL_EF_Execution Execution
2570 * @{
2571 */
2572
2573 /**
2574 * @brief Request Break sending
2575 * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
2576 * @param LPUARTx LPUART Instance
2577 * @retval None
2578 */
LL_LPUART_RequestBreakSending(USART_TypeDef * LPUARTx)2579 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
2580 {
2581 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
2582 }
2583
2584 /**
2585 * @brief Put LPUART in mute mode and set the RWU flag
2586 * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
2587 * @param LPUARTx LPUART Instance
2588 * @retval None
2589 */
LL_LPUART_RequestEnterMuteMode(USART_TypeDef * LPUARTx)2590 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
2591 {
2592 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
2593 }
2594
2595 /**
2596 * @brief Request a Receive Data and FIFO flush
2597 * @note Allows to discard the received data without reading them, and avoid an overrun
2598 * condition.
2599 * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
2600 * @param LPUARTx LPUART Instance
2601 * @retval None
2602 */
LL_LPUART_RequestRxDataFlush(USART_TypeDef * LPUARTx)2603 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
2604 {
2605 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
2606 }
2607
2608 /**
2609 * @}
2610 */
2611
2612 #if defined(USE_FULL_LL_DRIVER)
2613 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
2614 * @{
2615 */
2616 ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
2617 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct);
2618 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
2619 /**
2620 * @}
2621 */
2622 #endif /* USE_FULL_LL_DRIVER */
2623
2624 /**
2625 * @}
2626 */
2627
2628 /**
2629 * @}
2630 */
2631
2632 #endif /* LPUART1 */
2633
2634 /**
2635 * @}
2636 */
2637
2638 #ifdef __cplusplus
2639 }
2640 #endif
2641
2642 #endif /* STM32WBxx_LL_LPUART_H */
2643
2644
