1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_ipcc.h
4 * @author MCD Application Team
5 * @brief Header file of IPCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBxx_LL_IPCC_H
21 #define STM32WBxx_LL_IPCC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbxx.h"
29
30 /** @addtogroup STM32WBxx_LL_Driver
31 * @{
32 */
33
34 #if defined(IPCC)
35
36 /** @defgroup IPCC_LL IPCC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /* Exported types ------------------------------------------------------------*/
45 /* Exported constants --------------------------------------------------------*/
46 /** @defgroup IPCC_LL_Exported_Constants IPCC Exported Constants
47 * @{
48 */
49
50 /** @defgroup IPCC_LL_EC_GET_FLAG Get Flags Defines
51 * @brief Flags defines which can be used with LL_IPCC_ReadReg function
52 * @{
53 */
54 #define LL_IPCC_C1TOC2SR_CH1F IPCC_C1TOC2SR_CH1F_Msk /*!< C1 transmit to C2 receive Channel1 status flag before masking */
55 #define LL_IPCC_C1TOC2SR_CH2F IPCC_C1TOC2SR_CH2F_Msk /*!< C1 transmit to C2 receive Channel2 status flag before masking */
56 #define LL_IPCC_C1TOC2SR_CH3F IPCC_C1TOC2SR_CH3F_Msk /*!< C1 transmit to C2 receive Channel3 status flag before masking */
57 #define LL_IPCC_C1TOC2SR_CH4F IPCC_C1TOC2SR_CH4F_Msk /*!< C1 transmit to C2 receive Channel4 status flag before masking */
58 #define LL_IPCC_C1TOC2SR_CH5F IPCC_C1TOC2SR_CH5F_Msk /*!< C1 transmit to C2 receive Channel5 status flag before masking */
59 #define LL_IPCC_C1TOC2SR_CH6F IPCC_C1TOC2SR_CH6F_Msk /*!< C1 transmit to C2 receive Channel6 status flag before masking */
60 #define LL_IPCC_C2TOC1SR_CH1F IPCC_C2TOC1SR_CH1F_Msk /*!< C2 transmit to C1 receive Channel1 status flag before masking */
61 #define LL_IPCC_C2TOC1SR_CH2F IPCC_C2TOC1SR_CH2F_Msk /*!< C2 transmit to C1 receive Channel2 status flag before masking */
62 #define LL_IPCC_C2TOC1SR_CH3F IPCC_C2TOC1SR_CH3F_Msk /*!< C2 transmit to C1 receive Channel3 status flag before masking */
63 #define LL_IPCC_C2TOC1SR_CH4F IPCC_C2TOC1SR_CH4F_Msk /*!< C2 transmit to C1 receive Channel4 status flag before masking */
64 #define LL_IPCC_C2TOC1SR_CH5F IPCC_C2TOC1SR_CH5F_Msk /*!< C2 transmit to C1 receive Channel5 status flag before masking */
65 #define LL_IPCC_C2TOC1SR_CH6F IPCC_C2TOC1SR_CH6F_Msk /*!< C2 transmit to C1 receive Channel6 status flag before masking */
66
67 /**
68 * @}
69 */
70
71 /** @defgroup IPCC_LL_EC_Channel Channel
72 * @{
73 */
74 #define LL_IPCC_CHANNEL_1 (0x00000001U) /*!< IPCC Channel 1 */
75 #define LL_IPCC_CHANNEL_2 (0x00000002U) /*!< IPCC Channel 2 */
76 #define LL_IPCC_CHANNEL_3 (0x00000004U) /*!< IPCC Channel 3 */
77 #define LL_IPCC_CHANNEL_4 (0x00000008U) /*!< IPCC Channel 4 */
78 #define LL_IPCC_CHANNEL_5 (0x00000010U) /*!< IPCC Channel 5 */
79 #define LL_IPCC_CHANNEL_6 (0x00000020U) /*!< IPCC Channel 6 */
80 /**
81 * @}
82 */
83
84 /**
85 * @}
86 */
87
88 /* Exported macro ------------------------------------------------------------*/
89 /** @defgroup IPCC_LL_Exported_Macros IPCC Exported Macros
90 * @{
91 */
92
93 /** @defgroup IPCC_LL_EM_WRITE_READ Common Write and read registers Macros
94 * @{
95 */
96
97 /**
98 * @brief Write a value in IPCC register
99 * @param __INSTANCE__ IPCC Instance
100 * @param __REG__ Register to be written
101 * @param __VALUE__ Value to be written in the register
102 * @retval None
103 */
104 #define LL_IPCC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
105
106 /**
107 * @brief Read a value in IPCC register
108 * @param __INSTANCE__ IPCC Instance
109 * @param __REG__ Register to be read
110 * @retval Register value
111 */
112 #define LL_IPCC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
113 /**
114 * @}
115 */
116
117 /**
118 * @}
119 */
120
121
122 /* Exported functions --------------------------------------------------------*/
123 /** @defgroup IPCC_LL_Exported_Functions IPCC Exported Functions
124 * @{
125 */
126
127 /** @defgroup IPCC_LL_EF_IT_Management IT_Management
128 * @{
129 */
130
131 /**
132 * @brief Enable Transmit channel free interrupt for processor 1.
133 * @rmtoll C1CR TXFIE LL_C1_IPCC_EnableIT_TXF
134 * @param IPCCx IPCC Instance.
135 * @retval None
136 */
LL_C1_IPCC_EnableIT_TXF(IPCC_TypeDef * IPCCx)137 __STATIC_INLINE void LL_C1_IPCC_EnableIT_TXF(IPCC_TypeDef *IPCCx)
138 {
139 SET_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE);
140 }
141
142 /**
143 * @brief Disable Transmit channel free interrupt for processor 1.
144 * @rmtoll C1CR TXFIE LL_C1_IPCC_DisableIT_TXF
145 * @param IPCCx IPCC Instance.
146 * @retval None
147 */
LL_C1_IPCC_DisableIT_TXF(IPCC_TypeDef * IPCCx)148 __STATIC_INLINE void LL_C1_IPCC_DisableIT_TXF(IPCC_TypeDef *IPCCx)
149 {
150 CLEAR_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE);
151 }
152
153 /**
154 * @brief Check if Transmit channel free interrupt for processor 1 is enabled.
155 * @rmtoll C1CR TXFIE LL_C1_IPCC_IsEnabledIT_TXF
156 * @param IPCCx IPCC Instance.
157 * @retval State of bit (1 or 0).
158 */
LL_C1_IPCC_IsEnabledIT_TXF(IPCC_TypeDef const * const IPCCx)159 __STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledIT_TXF(IPCC_TypeDef const *const IPCCx)
160 {
161 return ((READ_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE) == (IPCC_C1CR_TXFIE)) ? 1UL : 0UL);
162 }
163
164 /**
165 * @brief Enable Receive channel occupied interrupt for processor 1.
166 * @rmtoll C1CR RXOIE LL_C1_IPCC_EnableIT_RXO
167 * @param IPCCx IPCC Instance.
168 * @retval None
169 */
LL_C1_IPCC_EnableIT_RXO(IPCC_TypeDef * IPCCx)170 __STATIC_INLINE void LL_C1_IPCC_EnableIT_RXO(IPCC_TypeDef *IPCCx)
171 {
172 SET_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE);
173 }
174
175 /**
176 * @brief Disable Receive channel occupied interrupt for processor 1.
177 * @rmtoll C1CR RXOIE LL_C1_IPCC_DisableIT_RXO
178 * @param IPCCx IPCC Instance.
179 * @retval None
180 */
LL_C1_IPCC_DisableIT_RXO(IPCC_TypeDef * IPCCx)181 __STATIC_INLINE void LL_C1_IPCC_DisableIT_RXO(IPCC_TypeDef *IPCCx)
182 {
183 CLEAR_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE);
184 }
185
186 /**
187 * @brief Check if Receive channel occupied interrupt for processor 1 is enabled.
188 * @rmtoll C1CR RXOIE LL_C1_IPCC_IsEnabledIT_RXO
189 * @param IPCCx IPCC Instance.
190 * @retval State of bit (1 or 0).
191 */
LL_C1_IPCC_IsEnabledIT_RXO(IPCC_TypeDef const * const IPCCx)192 __STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledIT_RXO(IPCC_TypeDef const *const IPCCx)
193 {
194 return ((READ_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE) == (IPCC_C1CR_RXOIE)) ? 1UL : 0UL);
195 }
196
197 /**
198 * @brief Enable Transmit channel free interrupt for processor 2.
199 * @rmtoll C2CR TXFIE LL_C2_IPCC_EnableIT_TXF
200 * @param IPCCx IPCC Instance.
201 * @retval None
202 */
LL_C2_IPCC_EnableIT_TXF(IPCC_TypeDef * IPCCx)203 __STATIC_INLINE void LL_C2_IPCC_EnableIT_TXF(IPCC_TypeDef *IPCCx)
204 {
205 SET_BIT(IPCCx->C2CR, IPCC_C2CR_TXFIE);
206 }
207
208 /**
209 * @brief Disable Transmit channel free interrupt for processor 2.
210 * @rmtoll C2CR TXFIE LL_C2_IPCC_DisableIT_TXF
211 * @param IPCCx IPCC Instance.
212 * @retval None
213 */
LL_C2_IPCC_DisableIT_TXF(IPCC_TypeDef * IPCCx)214 __STATIC_INLINE void LL_C2_IPCC_DisableIT_TXF(IPCC_TypeDef *IPCCx)
215 {
216 CLEAR_BIT(IPCCx->C2CR, IPCC_C2CR_TXFIE);
217 }
218
219 /**
220 * @brief Check if Transmit channel free interrupt for processor 2 is enabled.
221 * @rmtoll C2CR TXFIE LL_C2_IPCC_IsEnabledIT_TXF
222 * @param IPCCx IPCC Instance.
223 * @retval State of bit (1 or 0).
224 */
LL_C2_IPCC_IsEnabledIT_TXF(IPCC_TypeDef const * const IPCCx)225 __STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledIT_TXF(IPCC_TypeDef const *const IPCCx)
226 {
227 return ((READ_BIT(IPCCx->C2CR, IPCC_C2CR_TXFIE) == (IPCC_C2CR_TXFIE)) ? 1UL : 0UL);
228 }
229
230 /**
231 * @brief Enable Receive channel occupied interrupt for processor 2.
232 * @rmtoll C2CR RXOIE LL_C2_IPCC_EnableIT_RXO
233 * @param IPCCx IPCC Instance.
234 * @retval None
235 */
LL_C2_IPCC_EnableIT_RXO(IPCC_TypeDef * IPCCx)236 __STATIC_INLINE void LL_C2_IPCC_EnableIT_RXO(IPCC_TypeDef *IPCCx)
237 {
238 SET_BIT(IPCCx->C2CR, IPCC_C2CR_RXOIE);
239 }
240
241 /**
242 * @brief Disable Receive channel occupied interrupt for processor 2.
243 * @rmtoll C2CR RXOIE LL_C2_IPCC_DisableIT_RXO
244 * @param IPCCx IPCC Instance.
245 * @retval None
246 */
LL_C2_IPCC_DisableIT_RXO(IPCC_TypeDef * IPCCx)247 __STATIC_INLINE void LL_C2_IPCC_DisableIT_RXO(IPCC_TypeDef *IPCCx)
248 {
249 CLEAR_BIT(IPCCx->C2CR, IPCC_C2CR_RXOIE);
250 }
251
252 /**
253 * @brief Check if Receive channel occupied interrupt for processor 2 is enabled.
254 * @rmtoll C2CR RXOIE LL_C2_IPCC_IsEnabledIT_RXO
255 * @param IPCCx IPCC Instance.
256 * @retval State of bit (1 or 0).
257 */
LL_C2_IPCC_IsEnabledIT_RXO(IPCC_TypeDef const * const IPCCx)258 __STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledIT_RXO(IPCC_TypeDef const *const IPCCx)
259 {
260 return ((READ_BIT(IPCCx->C2CR, IPCC_C2CR_RXOIE) == (IPCC_C2CR_RXOIE)) ? 1UL : 0UL);
261 }
262
263 /**
264 * @}
265 */
266
267 /** @defgroup IPCC_LL_EF_Configuration Configuration
268 * @{
269 */
270
271 /**
272 * @brief Unmask transmit channel free interrupt for processor 1.
273 * @rmtoll C1MR CH1FM LL_C1_IPCC_EnableTransmitChannel\n
274 * C1MR CH2FM LL_C1_IPCC_EnableTransmitChannel\n
275 * C1MR CH3FM LL_C1_IPCC_EnableTransmitChannel\n
276 * C1MR CH4FM LL_C1_IPCC_EnableTransmitChannel\n
277 * C1MR CH5FM LL_C1_IPCC_EnableTransmitChannel\n
278 * C1MR CH6FM LL_C1_IPCC_EnableTransmitChannel
279 * @param IPCCx IPCC Instance.
280 * @param Channel This parameter can be a combination of the following values:
281 * @arg @ref LL_IPCC_CHANNEL_1
282 * @arg @ref LL_IPCC_CHANNEL_2
283 * @arg @ref LL_IPCC_CHANNEL_3
284 * @arg @ref LL_IPCC_CHANNEL_4
285 * @arg @ref LL_IPCC_CHANNEL_5
286 * @arg @ref LL_IPCC_CHANNEL_6
287 * @retval None
288 */
LL_C1_IPCC_EnableTransmitChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)289 __STATIC_INLINE void LL_C1_IPCC_EnableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
290 {
291 CLEAR_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos);
292 }
293
294 /**
295 * @brief Mask transmit channel free interrupt for processor 1.
296 * @rmtoll C1MR CH1FM LL_C1_IPCC_DisableTransmitChannel\n
297 * C1MR CH2FM LL_C1_IPCC_DisableTransmitChannel\n
298 * C1MR CH3FM LL_C1_IPCC_DisableTransmitChannel\n
299 * C1MR CH4FM LL_C1_IPCC_DisableTransmitChannel\n
300 * C1MR CH5FM LL_C1_IPCC_DisableTransmitChannel\n
301 * C1MR CH6FM LL_C1_IPCC_DisableTransmitChannel
302 * @param IPCCx IPCC Instance.
303 * @param Channel This parameter can be a combination of the following values:
304 * @arg @ref LL_IPCC_CHANNEL_1
305 * @arg @ref LL_IPCC_CHANNEL_2
306 * @arg @ref LL_IPCC_CHANNEL_3
307 * @arg @ref LL_IPCC_CHANNEL_4
308 * @arg @ref LL_IPCC_CHANNEL_5
309 * @arg @ref LL_IPCC_CHANNEL_6
310 * @retval None
311 */
LL_C1_IPCC_DisableTransmitChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)312 __STATIC_INLINE void LL_C1_IPCC_DisableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
313 {
314 SET_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos);
315 }
316
317 /**
318 * @brief Check if Transmit channel free interrupt for processor 1 is masked.
319 * @rmtoll C1MR CH1FM LL_C1_IPCC_IsEnabledTransmitChannel\n
320 * C1MR CH2FM LL_C1_IPCC_IsEnabledTransmitChannel\n
321 * C1MR CH3FM LL_C1_IPCC_IsEnabledTransmitChannel\n
322 * C1MR CH4FM LL_C1_IPCC_IsEnabledTransmitChannel\n
323 * C1MR CH5FM LL_C1_IPCC_IsEnabledTransmitChannel\n
324 * C1MR CH6FM LL_C1_IPCC_IsEnabledTransmitChannel
325 * @param IPCCx IPCC Instance.
326 * @param Channel This parameter can be one of the following values:
327 * @arg @ref LL_IPCC_CHANNEL_1
328 * @arg @ref LL_IPCC_CHANNEL_2
329 * @arg @ref LL_IPCC_CHANNEL_3
330 * @arg @ref LL_IPCC_CHANNEL_4
331 * @arg @ref LL_IPCC_CHANNEL_5
332 * @arg @ref LL_IPCC_CHANNEL_6
333 * @retval State of bit (1 or 0).
334 */
LL_C1_IPCC_IsEnabledTransmitChannel(IPCC_TypeDef const * const IPCCx,uint32_t Channel)335 __STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledTransmitChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
336 {
337 return ((READ_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos) != (Channel << IPCC_C1MR_CH1FM_Pos)) ? 1UL : 0UL);
338 }
339
340 /**
341 * @brief Unmask receive channel occupied interrupt for processor 1.
342 * @rmtoll C1MR CH1OM LL_C1_IPCC_EnableReceiveChannel\n
343 * C1MR CH2OM LL_C1_IPCC_EnableReceiveChannel\n
344 * C1MR CH3OM LL_C1_IPCC_EnableReceiveChannel\n
345 * C1MR CH4OM LL_C1_IPCC_EnableReceiveChannel\n
346 * C1MR CH5OM LL_C1_IPCC_EnableReceiveChannel\n
347 * C1MR CH6OM LL_C1_IPCC_EnableReceiveChannel
348 * @param IPCCx IPCC Instance.
349 * @param Channel This parameter can be a combination of the following values:
350 * @arg @ref LL_IPCC_CHANNEL_1
351 * @arg @ref LL_IPCC_CHANNEL_2
352 * @arg @ref LL_IPCC_CHANNEL_3
353 * @arg @ref LL_IPCC_CHANNEL_4
354 * @arg @ref LL_IPCC_CHANNEL_5
355 * @arg @ref LL_IPCC_CHANNEL_6
356 * @retval None
357 */
LL_C1_IPCC_EnableReceiveChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)358 __STATIC_INLINE void LL_C1_IPCC_EnableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
359 {
360 CLEAR_BIT(IPCCx->C1MR, Channel);
361 }
362
363 /**
364 * @brief Mask receive channel occupied interrupt for processor 1.
365 * @rmtoll C1MR CH1OM LL_C1_IPCC_DisableReceiveChannel\n
366 * C1MR CH2OM LL_C1_IPCC_DisableReceiveChannel\n
367 * C1MR CH3OM LL_C1_IPCC_DisableReceiveChannel\n
368 * C1MR CH4OM LL_C1_IPCC_DisableReceiveChannel\n
369 * C1MR CH5OM LL_C1_IPCC_DisableReceiveChannel\n
370 * C1MR CH6OM LL_C1_IPCC_DisableReceiveChannel
371 * @param IPCCx IPCC Instance.
372 * @param Channel This parameter can be a combination of the following values:
373 * @arg @ref LL_IPCC_CHANNEL_1
374 * @arg @ref LL_IPCC_CHANNEL_2
375 * @arg @ref LL_IPCC_CHANNEL_3
376 * @arg @ref LL_IPCC_CHANNEL_4
377 * @arg @ref LL_IPCC_CHANNEL_5
378 * @arg @ref LL_IPCC_CHANNEL_6
379 * @retval None
380 */
LL_C1_IPCC_DisableReceiveChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)381 __STATIC_INLINE void LL_C1_IPCC_DisableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
382 {
383 SET_BIT(IPCCx->C1MR, Channel);
384 }
385
386 /**
387 * @brief Check if Receive channel occupied interrupt for processor 1 is masked.
388 * @rmtoll C1MR CH1OM LL_C1_IPCC_IsEnabledReceiveChannel\n
389 * C1MR CH2OM LL_C1_IPCC_IsEnabledReceiveChannel\n
390 * C1MR CH3OM LL_C1_IPCC_IsEnabledReceiveChannel\n
391 * C1MR CH4OM LL_C1_IPCC_IsEnabledReceiveChannel\n
392 * C1MR CH5OM LL_C1_IPCC_IsEnabledReceiveChannel\n
393 * C1MR CH6OM LL_C1_IPCC_IsEnabledReceiveChannel
394 * @param IPCCx IPCC Instance.
395 * @param Channel This parameter can be one of the following values:
396 * @arg @ref LL_IPCC_CHANNEL_1
397 * @arg @ref LL_IPCC_CHANNEL_2
398 * @arg @ref LL_IPCC_CHANNEL_3
399 * @arg @ref LL_IPCC_CHANNEL_4
400 * @arg @ref LL_IPCC_CHANNEL_5
401 * @arg @ref LL_IPCC_CHANNEL_6
402 * @retval State of bit (1 or 0).
403 */
LL_C1_IPCC_IsEnabledReceiveChannel(IPCC_TypeDef const * const IPCCx,uint32_t Channel)404 __STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledReceiveChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
405 {
406 return ((READ_BIT(IPCCx->C1MR, Channel) != (Channel)) ? 1UL : 0UL);
407 }
408
409 /**
410 * @brief Unmask transmit channel free interrupt for processor 2.
411 * @rmtoll C2MR CH1FM LL_C2_IPCC_EnableTransmitChannel\n
412 * C2MR CH2FM LL_C2_IPCC_EnableTransmitChannel\n
413 * C2MR CH3FM LL_C2_IPCC_EnableTransmitChannel\n
414 * C2MR CH4FM LL_C2_IPCC_EnableTransmitChannel\n
415 * C2MR CH5FM LL_C2_IPCC_EnableTransmitChannel\n
416 * C2MR CH6FM LL_C2_IPCC_EnableTransmitChannel
417 * @param IPCCx IPCC Instance.
418 * @param Channel This parameter can be a combination of the following values:
419 * @arg @ref LL_IPCC_CHANNEL_1
420 * @arg @ref LL_IPCC_CHANNEL_2
421 * @arg @ref LL_IPCC_CHANNEL_3
422 * @arg @ref LL_IPCC_CHANNEL_4
423 * @arg @ref LL_IPCC_CHANNEL_5
424 * @arg @ref LL_IPCC_CHANNEL_6
425 * @retval None
426 */
LL_C2_IPCC_EnableTransmitChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)427 __STATIC_INLINE void LL_C2_IPCC_EnableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
428 {
429 CLEAR_BIT(IPCCx->C2MR, Channel << IPCC_C2MR_CH1FM_Pos);
430 }
431
432 /**
433 * @brief Mask transmit channel free interrupt for processor 2.
434 * @rmtoll C2MR CH1FM LL_C2_IPCC_DisableTransmitChannel\n
435 * C2MR CH2FM LL_C2_IPCC_DisableTransmitChannel\n
436 * C2MR CH3FM LL_C2_IPCC_DisableTransmitChannel\n
437 * C2MR CH4FM LL_C2_IPCC_DisableTransmitChannel\n
438 * C2MR CH5FM LL_C2_IPCC_DisableTransmitChannel\n
439 * C2MR CH6FM LL_C2_IPCC_DisableTransmitChannel
440 * @param IPCCx IPCC Instance.
441 * @param Channel This parameter can be a combination of the following values:
442 * @arg @ref LL_IPCC_CHANNEL_1
443 * @arg @ref LL_IPCC_CHANNEL_2
444 * @arg @ref LL_IPCC_CHANNEL_3
445 * @arg @ref LL_IPCC_CHANNEL_4
446 * @arg @ref LL_IPCC_CHANNEL_5
447 * @arg @ref LL_IPCC_CHANNEL_6
448 * @retval None
449 */
LL_C2_IPCC_DisableTransmitChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)450 __STATIC_INLINE void LL_C2_IPCC_DisableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
451 {
452 SET_BIT(IPCCx->C2MR, Channel << (IPCC_C2MR_CH1FM_Pos));
453 }
454
455 /**
456 * @brief Check if Transmit channel free interrupt for processor 2 is masked.
457 * @rmtoll C2MR CH1FM LL_C2_IPCC_IsEnabledTransmitChannel\n
458 * C2MR CH2FM LL_C2_IPCC_IsEnabledTransmitChannel\n
459 * C2MR CH3FM LL_C2_IPCC_IsEnabledTransmitChannel\n
460 * C2MR CH4FM LL_C2_IPCC_IsEnabledTransmitChannel\n
461 * C2MR CH5FM LL_C2_IPCC_IsEnabledTransmitChannel\n
462 * C2MR CH6FM LL_C2_IPCC_IsEnabledTransmitChannel
463 * @param IPCCx IPCC Instance.
464 * @param Channel This parameter can be one of the following values:
465 * @arg @ref LL_IPCC_CHANNEL_1
466 * @arg @ref LL_IPCC_CHANNEL_2
467 * @arg @ref LL_IPCC_CHANNEL_3
468 * @arg @ref LL_IPCC_CHANNEL_4
469 * @arg @ref LL_IPCC_CHANNEL_5
470 * @arg @ref LL_IPCC_CHANNEL_6
471 * @retval State of bit (1 or 0).
472 */
LL_C2_IPCC_IsEnabledTransmitChannel(IPCC_TypeDef const * const IPCCx,uint32_t Channel)473 __STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledTransmitChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
474 {
475 return ((READ_BIT(IPCCx->C2MR, Channel << IPCC_C2MR_CH1FM_Pos) != (Channel << IPCC_C2MR_CH1FM_Pos)) ? 1UL : 0UL);
476 }
477
478 /**
479 * @brief Unmask receive channel occupied interrupt for processor 2.
480 * @rmtoll C2MR CH1OM LL_C2_IPCC_EnableReceiveChannel\n
481 * C2MR CH2OM LL_C2_IPCC_EnableReceiveChannel\n
482 * C2MR CH3OM LL_C2_IPCC_EnableReceiveChannel\n
483 * C2MR CH4OM LL_C2_IPCC_EnableReceiveChannel\n
484 * C2MR CH5OM LL_C2_IPCC_EnableReceiveChannel\n
485 * C2MR CH6OM LL_C2_IPCC_EnableReceiveChannel
486 * @param IPCCx IPCC Instance.
487 * @param Channel This parameter can be a combination of the following values:
488 * @arg @ref LL_IPCC_CHANNEL_1
489 * @arg @ref LL_IPCC_CHANNEL_2
490 * @arg @ref LL_IPCC_CHANNEL_3
491 * @arg @ref LL_IPCC_CHANNEL_4
492 * @arg @ref LL_IPCC_CHANNEL_5
493 * @arg @ref LL_IPCC_CHANNEL_6
494 * @retval None
495 */
LL_C2_IPCC_EnableReceiveChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)496 __STATIC_INLINE void LL_C2_IPCC_EnableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
497 {
498 CLEAR_BIT(IPCCx->C2MR, Channel);
499 }
500
501 /**
502 * @brief Mask receive channel occupied interrupt for processor 1.
503 * @rmtoll C2MR CH1OM LL_C2_IPCC_DisableReceiveChannel\n
504 * C2MR CH2OM LL_C2_IPCC_DisableReceiveChannel\n
505 * C2MR CH3OM LL_C2_IPCC_DisableReceiveChannel\n
506 * C2MR CH4OM LL_C2_IPCC_DisableReceiveChannel\n
507 * C2MR CH5OM LL_C2_IPCC_DisableReceiveChannel\n
508 * C2MR CH6OM LL_C2_IPCC_DisableReceiveChannel
509 * @param IPCCx IPCC Instance.
510 * @param Channel This parameter can be a combination of the following values:
511 * @arg @ref LL_IPCC_CHANNEL_1
512 * @arg @ref LL_IPCC_CHANNEL_2
513 * @arg @ref LL_IPCC_CHANNEL_3
514 * @arg @ref LL_IPCC_CHANNEL_4
515 * @arg @ref LL_IPCC_CHANNEL_5
516 * @arg @ref LL_IPCC_CHANNEL_6
517 * @retval None
518 */
LL_C2_IPCC_DisableReceiveChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)519 __STATIC_INLINE void LL_C2_IPCC_DisableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
520 {
521 SET_BIT(IPCCx->C2MR, Channel);
522 }
523
524 /**
525 * @brief Check if Receive channel occupied interrupt for processor 2 is masked.
526 * @rmtoll C2MR CH1OM LL_C2_IPCC_IsEnabledReceiveChannel\n
527 * C2MR CH2OM LL_C2_IPCC_IsEnabledReceiveChannel\n
528 * C2MR CH3OM LL_C2_IPCC_IsEnabledReceiveChannel\n
529 * C2MR CH4OM LL_C2_IPCC_IsEnabledReceiveChannel\n
530 * C2MR CH5OM LL_C2_IPCC_IsEnabledReceiveChannel\n
531 * C2MR CH6OM LL_C2_IPCC_IsEnabledReceiveChannel
532 * @param IPCCx IPCC Instance.
533 * @param Channel This parameter can be one of the following values:
534 * @arg @ref LL_IPCC_CHANNEL_1
535 * @arg @ref LL_IPCC_CHANNEL_2
536 * @arg @ref LL_IPCC_CHANNEL_3
537 * @arg @ref LL_IPCC_CHANNEL_4
538 * @arg @ref LL_IPCC_CHANNEL_5
539 * @arg @ref LL_IPCC_CHANNEL_6
540 * @retval State of bit (1 or 0).
541 */
LL_C2_IPCC_IsEnabledReceiveChannel(IPCC_TypeDef const * const IPCCx,uint32_t Channel)542 __STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledReceiveChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
543 {
544 return ((READ_BIT(IPCCx->C2MR, Channel) != (Channel)) ? 1UL : 0UL);
545 }
546
547 /**
548 * @}
549 */
550
551 /** @defgroup IPCC_LL_EF_FLAG_Management FLAG_Management
552 * @{
553 */
554
555 /**
556 * @brief Clear IPCC receive channel status for processor 1.
557 * @note Associated with IPCC_C2TOC1SR.CHxF
558 * @rmtoll C1SCR CH1C LL_C1_IPCC_ClearFlag_CHx\n
559 * C1SCR CH2C LL_C1_IPCC_ClearFlag_CHx\n
560 * C1SCR CH3C LL_C1_IPCC_ClearFlag_CHx\n
561 * C1SCR CH4C LL_C1_IPCC_ClearFlag_CHx\n
562 * C1SCR CH5C LL_C1_IPCC_ClearFlag_CHx\n
563 * C1SCR CH6C LL_C1_IPCC_ClearFlag_CHx
564 * @param IPCCx IPCC Instance.
565 * @param Channel This parameter can be a combination of the following values:
566 * @arg @ref LL_IPCC_CHANNEL_1
567 * @arg @ref LL_IPCC_CHANNEL_2
568 * @arg @ref LL_IPCC_CHANNEL_3
569 * @arg @ref LL_IPCC_CHANNEL_4
570 * @arg @ref LL_IPCC_CHANNEL_5
571 * @arg @ref LL_IPCC_CHANNEL_6
572 * @retval None
573 */
LL_C1_IPCC_ClearFlag_CHx(IPCC_TypeDef * IPCCx,uint32_t Channel)574 __STATIC_INLINE void LL_C1_IPCC_ClearFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
575 {
576 WRITE_REG(IPCCx->C1SCR, Channel);
577 }
578
579 /**
580 * @brief Set IPCC transmit channel status for processor 1.
581 * @note Associated with IPCC_C1TOC2SR.CHxF
582 * @rmtoll C1SCR CH1S LL_C1_IPCC_SetFlag_CHx\n
583 * C1SCR CH2S LL_C1_IPCC_SetFlag_CHx\n
584 * C1SCR CH3S LL_C1_IPCC_SetFlag_CHx\n
585 * C1SCR CH4S LL_C1_IPCC_SetFlag_CHx\n
586 * C1SCR CH5S LL_C1_IPCC_SetFlag_CHx\n
587 * C1SCR CH6S LL_C1_IPCC_SetFlag_CHx
588 * @param IPCCx IPCC Instance.
589 * @param Channel This parameter can be a combination of the following values:
590 * @arg @ref LL_IPCC_CHANNEL_1
591 * @arg @ref LL_IPCC_CHANNEL_2
592 * @arg @ref LL_IPCC_CHANNEL_3
593 * @arg @ref LL_IPCC_CHANNEL_4
594 * @arg @ref LL_IPCC_CHANNEL_5
595 * @arg @ref LL_IPCC_CHANNEL_6
596 * @retval None
597 */
LL_C1_IPCC_SetFlag_CHx(IPCC_TypeDef * IPCCx,uint32_t Channel)598 __STATIC_INLINE void LL_C1_IPCC_SetFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
599 {
600 WRITE_REG(IPCCx->C1SCR, Channel << IPCC_C1SCR_CH1S_Pos);
601 }
602
603 /**
604 * @brief Get channel status for processor 1.
605 * @rmtoll C1TOC2SR CH1F LL_C1_IPCC_IsActiveFlag_CHx\n
606 * C1TOC2SR CH2F LL_C1_IPCC_IsActiveFlag_CHx\n
607 * C1TOC2SR CH3F LL_C1_IPCC_IsActiveFlag_CHx\n
608 * C1TOC2SR CH4F LL_C1_IPCC_IsActiveFlag_CHx\n
609 * C1TOC2SR CH5F LL_C1_IPCC_IsActiveFlag_CHx\n
610 * C1TOC2SR CH6F LL_C1_IPCC_IsActiveFlag_CHx
611 * @param IPCCx IPCC Instance.
612 * @param Channel This parameter can be one of the following values:
613 * @arg @ref LL_IPCC_CHANNEL_1
614 * @arg @ref LL_IPCC_CHANNEL_2
615 * @arg @ref LL_IPCC_CHANNEL_3
616 * @arg @ref LL_IPCC_CHANNEL_4
617 * @arg @ref LL_IPCC_CHANNEL_5
618 * @arg @ref LL_IPCC_CHANNEL_6
619 * @retval State of bit (1 or 0).
620 */
LL_C1_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const * const IPCCx,uint32_t Channel)621 __STATIC_INLINE uint32_t LL_C1_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
622 {
623 return ((READ_BIT(IPCCx->C1TOC2SR, Channel) == (Channel)) ? 1UL : 0UL);
624 }
625
626 /**
627 * @brief Clear IPCC receive channel status for processor 2.
628 * @note Associated with IPCC_C1TOC2SR.CHxF
629 * @rmtoll C2SCR CH1C LL_C2_IPCC_ClearFlag_CHx\n
630 * C2SCR CH2C LL_C2_IPCC_ClearFlag_CHx\n
631 * C2SCR CH3C LL_C2_IPCC_ClearFlag_CHx\n
632 * C2SCR CH4C LL_C2_IPCC_ClearFlag_CHx\n
633 * C2SCR CH5C LL_C2_IPCC_ClearFlag_CHx\n
634 * C2SCR CH6C LL_C2_IPCC_ClearFlag_CHx
635 * @param IPCCx IPCC Instance.
636 * @param Channel This parameter can be a combination of the following values:
637 * @arg @ref LL_IPCC_CHANNEL_1
638 * @arg @ref LL_IPCC_CHANNEL_2
639 * @arg @ref LL_IPCC_CHANNEL_3
640 * @arg @ref LL_IPCC_CHANNEL_4
641 * @arg @ref LL_IPCC_CHANNEL_5
642 * @arg @ref LL_IPCC_CHANNEL_6
643 * @retval None
644 */
LL_C2_IPCC_ClearFlag_CHx(IPCC_TypeDef * IPCCx,uint32_t Channel)645 __STATIC_INLINE void LL_C2_IPCC_ClearFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
646 {
647 WRITE_REG(IPCCx->C2SCR, Channel);
648 }
649
650 /**
651 * @brief Set IPCC transmit channel status for processor 2.
652 * @note Associated with IPCC_C2TOC1SR.CHxF
653 * @rmtoll C2SCR CH1S LL_C2_IPCC_SetFlag_CHx\n
654 * C2SCR CH2S LL_C2_IPCC_SetFlag_CHx\n
655 * C2SCR CH3S LL_C2_IPCC_SetFlag_CHx\n
656 * C2SCR CH4S LL_C2_IPCC_SetFlag_CHx\n
657 * C2SCR CH5S LL_C2_IPCC_SetFlag_CHx\n
658 * C2SCR CH6S LL_C2_IPCC_SetFlag_CHx
659 * @param IPCCx IPCC Instance.
660 * @param Channel This parameter can be a combination of the following values:
661 * @arg @ref LL_IPCC_CHANNEL_1
662 * @arg @ref LL_IPCC_CHANNEL_2
663 * @arg @ref LL_IPCC_CHANNEL_3
664 * @arg @ref LL_IPCC_CHANNEL_4
665 * @arg @ref LL_IPCC_CHANNEL_5
666 * @arg @ref LL_IPCC_CHANNEL_6
667 * @retval None
668 */
LL_C2_IPCC_SetFlag_CHx(IPCC_TypeDef * IPCCx,uint32_t Channel)669 __STATIC_INLINE void LL_C2_IPCC_SetFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
670 {
671 WRITE_REG(IPCCx->C2SCR, Channel << IPCC_C2SCR_CH1S_Pos);
672 }
673
674 /**
675 * @brief Get channel status for processor 2.
676 * @rmtoll C2TOC1SR CH1F LL_C2_IPCC_IsActiveFlag_CHx\n
677 * C2TOC1SR CH2F LL_C2_IPCC_IsActiveFlag_CHx\n
678 * C2TOC1SR CH3F LL_C2_IPCC_IsActiveFlag_CHx\n
679 * C2TOC1SR CH4F LL_C2_IPCC_IsActiveFlag_CHx\n
680 * C2TOC1SR CH5F LL_C2_IPCC_IsActiveFlag_CHx\n
681 * C2TOC1SR CH6F LL_C2_IPCC_IsActiveFlag_CHx
682 * @param IPCCx IPCC Instance.
683 * @param Channel This parameter can be one of the following values:
684 * @arg @ref LL_IPCC_CHANNEL_1
685 * @arg @ref LL_IPCC_CHANNEL_2
686 * @arg @ref LL_IPCC_CHANNEL_3
687 * @arg @ref LL_IPCC_CHANNEL_4
688 * @arg @ref LL_IPCC_CHANNEL_5
689 * @arg @ref LL_IPCC_CHANNEL_6
690 * @retval State of bit (1 or 0).
691 */
LL_C2_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const * const IPCCx,uint32_t Channel)692 __STATIC_INLINE uint32_t LL_C2_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
693 {
694 return ((READ_BIT(IPCCx->C2TOC1SR, Channel) == (Channel)) ? 1UL : 0UL);
695 }
696
697 /**
698 * @brief Get the number of supported channels.
699 * @param IPCCx IPCC Instance.
700 * @retval Number of supported channels.
701 */
LL_IPCC_GetChannelNumber(IPCC_TypeDef * IPCCx)702 __STATIC_INLINE uint32_t LL_IPCC_GetChannelNumber(IPCC_TypeDef *IPCCx)
703 {
704 /* Added for compatibility with other STM32 series */
705 (void)(IPCCx); /* To avoid gcc/g++ warnings */
706 return 6U;
707 }
708
709 /**
710 * @}
711 */
712
713 /**
714 * @}
715 */
716
717 /**
718 * @}
719 */
720
721 #endif /* IPCC */
722
723 /**
724 * @}
725 */
726
727 #ifdef __cplusplus
728 }
729 #endif
730
731 #endif /* STM32WBxx_LL_IPCC_H */
732
733
