1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBxx_LL_DMA_H
21 #define STM32WBxx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbxx.h"
29 #include "stm32wbxx_ll_dmamux.h"
30
31 /** @addtogroup STM32WBxx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA1) || defined (DMA2)
36
37 /** @defgroup DMA_LL DMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
46 * @{
47 */
48
49 /**
50 * @brief Helper macro to convert DMA Instance and index into DMA channel
51 * @param __DMA_INSTANCE__ DMAx
52 * @param __CHANNEL_INDEX__ 0 to 6 to map DMAx_Channel1 to DMAx_Channel7
53 * @retval Pointer to the DMA channel
54 */
55 #if defined (DMA2)
56 #define __LL_DMA_INSTANCE_TO_CHANNEL(__DMA_INSTANCE__, __CHANNEL_INDEX__) \
57 (((__DMA_INSTANCE__) == DMA1) ? (DMA1_Channel1 + (__CHANNEL_INDEX__)) : (DMA2_Channel1 + (__CHANNEL_INDEX__)))
58 #else
59 #define __LL_DMA_INSTANCE_TO_CHANNEL(__DMA_INSTANCE__, __CHANNEL_INDEX__) \
60 (DMA1_Channel1 + (__CHANNEL_INDEX__))
61 #endif /* DMA2 */
62
63 /**
64 * @brief Helper macro to convert DMA Instance and index into DMAMUX channel
65 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
66 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
67 * @param __DMA_INSTANCE__ DMAx
68 * @param __CHANNEL_INDEX__ 0 to 6 to map DMAx_Channel1 to DMAx_Channel7
69 * @retval Pointer to the DMA channel
70 */
71 #if defined (DMA2)
72 #define __LL_DMA_INSTANCE_TO_DMAMUX_CCR(__DMA_INSTANCE__, __CHANNEL_INDEX__)\
73 (((__DMA_INSTANCE__) == DMA1) ? (DMAMUX1_Channel0 + (__CHANNEL_INDEX__)) : (DMAMUX1_Channel7 + (__CHANNEL_INDEX__)))
74 #else
75 #define __LL_DMA_INSTANCE_TO_DMAMUX_CCR(__DMA_INSTANCE__, __CHANNEL_INDEX__)\
76 (DMAMUX1_Channel0 + (__CHANNEL_INDEX__))
77 #endif /* DMA2 */
78 /**
79 * @}
80 */
81
82 /* Exported types ------------------------------------------------------------*/
83 #if defined(USE_FULL_LL_DRIVER)
84 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
85 * @{
86 */
87 typedef struct
88 {
89 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
90 or as Source base address in case of memory to memory transfer direction.
91
92 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
93
94 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
95 or as Destination base address in case of memory to memory transfer direction.
96
97 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
98
99 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
100 from memory to memory or from peripheral to memory.
101 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
102
103 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
104
105 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
106 This parameter can be a value of @ref DMA_LL_EC_MODE
107 @note: The circular buffer mode cannot be used if the memory to memory
108 data transfer direction is configured on the selected Channel
109
110 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
111
112 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
113 is incremented or not.
114 This parameter can be a value of @ref DMA_LL_EC_PERIPH
115
116 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
117
118 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
119 is incremented or not.
120 This parameter can be a value of @ref DMA_LL_EC_MEMORY
121
122 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
123
124 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
125 in case of memory to memory transfer direction.
126 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
127
128 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
129
130 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
131 in case of memory to memory transfer direction.
132 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
133
134 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
135
136 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
137 The data unit is equal to the source buffer configuration set in PeripheralSize
138 or MemorySize parameters depending in the transfer direction.
139 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
140
141 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
142
143 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
144 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
145
146 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
147
148 uint32_t Priority; /*!< Specifies the channel priority level.
149 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
150
151 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
152
153 } LL_DMA_InitTypeDef;
154 /**
155 * @}
156 */
157 #endif /*USE_FULL_LL_DRIVER*/
158
159 /* Exported constants --------------------------------------------------------*/
160 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
161 * @{
162 */
163 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
164 * @brief Flags defines which can be used with LL_DMA_WriteReg function
165 * @{
166 */
167 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
168 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
169 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
170 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
171 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
172 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
173 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
174 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
175 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
176 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
177 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
178 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
179 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
180 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
181 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
182 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
183 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
184 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
185 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
186 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
187 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
188 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
189 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
190 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
191 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
192 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
193 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
194 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
195 /**
196 * @}
197 */
198
199 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
200 * @brief Flags defines which can be used with LL_DMA_ReadReg function
201 * @{
202 */
203 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
204 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
205 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
206 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
207 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
208 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
209 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
210 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
211 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
212 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
213 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
214 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
215 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
216 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
217 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
218 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
219 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
220 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
221 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
222 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
223 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
224 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
225 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
226 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
227 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
228 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
229 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
230 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
231 /**
232 * @}
233 */
234
235 /** @defgroup DMA_LL_EC_IT IT Defines
236 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
237 * @{
238 */
239 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
240 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
241 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
242 /**
243 * @}
244 */
245
246 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
247 * @{
248 */
249 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
250 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
251 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
252 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
253 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
254 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
255 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
256 #if defined(USE_FULL_LL_DRIVER)
257 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
258 #endif /* USE_FULL_LL_DRIVER */
259 /**
260 * @}
261 */
262
263 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
264 * @{
265 */
266 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
267 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
268 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
269 /**
270 * @}
271 */
272
273 /** @defgroup DMA_LL_EC_MODE Transfer mode
274 * @{
275 */
276 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
277 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
278 /**
279 * @}
280 */
281
282 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
283 * @{
284 */
285 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
286 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
287 /**
288 * @}
289 */
290
291 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
292 * @{
293 */
294 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
295 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
296 /**
297 * @}
298 */
299
300 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
301 * @{
302 */
303 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
304 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
305 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
306 /**
307 * @}
308 */
309
310 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
311 * @{
312 */
313 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
314 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
315 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
316 /**
317 * @}
318 */
319
320 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
321 * @{
322 */
323 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
324 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
325 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
326 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
327 /**
328 * @}
329 */
330
331 /**
332 * @}
333 */
334
335 /* Exported macro ------------------------------------------------------------*/
336 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
337 * @{
338 */
339
340 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
341 * @{
342 */
343 /**
344 * @brief Write a value in DMA register
345 * @param __INSTANCE__ DMA Instance
346 * @param __REG__ Register to be written
347 * @param __VALUE__ Value to be written in the register
348 * @retval None
349 */
350 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
351
352 /**
353 * @brief Read a value in DMA register
354 * @param __INSTANCE__ DMA Instance
355 * @param __REG__ Register to be read
356 * @retval Register value
357 */
358 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
359 /**
360 * @}
361 */
362
363 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
364 * @{
365 */
366 /**
367 * @brief Convert DMAx_Channely into DMAx
368 * @param __CHANNEL_INSTANCE__ DMAx_Channely
369 * @retval DMAx
370 */
371 #if defined(DMA2)
372 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
373 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
374 #else
375 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
376 #endif /* DMA2 */
377
378 /**
379 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
380 * @param __CHANNEL_INSTANCE__ DMAx_Channely
381 * @retval LL_DMA_CHANNEL_y
382 */
383 #if defined (DMA2)
384 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
385 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
386 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
387 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
388 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
389 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
390 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
391 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
397 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
398 LL_DMA_CHANNEL_7)
399 #else
400 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
401 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
402 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
403 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
406 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
407 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
408 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
409 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
410 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
411 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
412 LL_DMA_CHANNEL_7)
413 #endif /* DMA2_Channel6 && DMA2_Channel7 */
414 #else
415 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
416 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
417 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
418 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
419 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
420 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
421 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
422 LL_DMA_CHANNEL_7)
423 #endif /* DMA2 */
424
425 /**
426 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
427 * @param __DMA_INSTANCE__ DMAx
428 * @param __CHANNEL__ LL_DMA_CHANNEL_y
429 * @retval DMAx_Channely
430 */
431 #if defined (DMA2)
432 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
433 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
434 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
435 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
436 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
446 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
447 DMA2_Channel7)
448 #else
449 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
450 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
451 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
452 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
459 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
460 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
461 DMA1_Channel7)
462 #endif /* DMA2_Channel6 && DMA2_Channel7 */
463 #else
464 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
465 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
466 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
467 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
468 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
469 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
470 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
471 DMA1_Channel7)
472 #endif /* DMA2 */
473
474 /**
475 * @}
476 */
477
478 /**
479 * @}
480 */
481
482 /* Exported functions --------------------------------------------------------*/
483 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
484 * @{
485 */
486
487 /** @defgroup DMA_LL_EF_Configuration Configuration
488 * @{
489 */
490 /**
491 * @brief Enable DMA channel.
492 * @rmtoll CCR EN LL_DMA_EnableChannel
493 * @param DMAx DMAx Instance
494 * @param Channel This parameter can be one of the following values:
495 * @arg @ref LL_DMA_CHANNEL_1
496 * @arg @ref LL_DMA_CHANNEL_2
497 * @arg @ref LL_DMA_CHANNEL_3
498 * @arg @ref LL_DMA_CHANNEL_4
499 * @arg @ref LL_DMA_CHANNEL_5
500 * @arg @ref LL_DMA_CHANNEL_6
501 * @arg @ref LL_DMA_CHANNEL_7
502 * @retval None
503 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)504 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
505 {
506 SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN);
507 }
508
509 /**
510 * @brief Disable DMA channel.
511 * @rmtoll CCR EN LL_DMA_DisableChannel
512 * @param DMAx DMAx Instance
513 * @param Channel This parameter can be one of the following values:
514 * @arg @ref LL_DMA_CHANNEL_1
515 * @arg @ref LL_DMA_CHANNEL_2
516 * @arg @ref LL_DMA_CHANNEL_3
517 * @arg @ref LL_DMA_CHANNEL_4
518 * @arg @ref LL_DMA_CHANNEL_5
519 * @arg @ref LL_DMA_CHANNEL_6
520 * @arg @ref LL_DMA_CHANNEL_7
521 * @retval None
522 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)523 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
524 {
525 CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN);
526 }
527
528 /**
529 * @brief Check if DMA channel is enabled or disabled.
530 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
531 * @param DMAx DMAx Instance
532 * @param Channel This parameter can be one of the following values:
533 * @arg @ref LL_DMA_CHANNEL_1
534 * @arg @ref LL_DMA_CHANNEL_2
535 * @arg @ref LL_DMA_CHANNEL_3
536 * @arg @ref LL_DMA_CHANNEL_4
537 * @arg @ref LL_DMA_CHANNEL_5
538 * @arg @ref LL_DMA_CHANNEL_6
539 * @arg @ref LL_DMA_CHANNEL_7
540 * @retval State of bit (1 or 0).
541 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)542 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
543 {
544 return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
545 DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
546 }
547
548 /**
549 * @brief Configure all parameters link to DMA transfer.
550 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
551 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
552 * CCR CIRC LL_DMA_ConfigTransfer\n
553 * CCR PINC LL_DMA_ConfigTransfer\n
554 * CCR MINC LL_DMA_ConfigTransfer\n
555 * CCR PSIZE LL_DMA_ConfigTransfer\n
556 * CCR MSIZE LL_DMA_ConfigTransfer\n
557 * CCR PL LL_DMA_ConfigTransfer
558 * @param DMAx DMAx Instance
559 * @param Channel This parameter can be one of the following values:
560 * @arg @ref LL_DMA_CHANNEL_1
561 * @arg @ref LL_DMA_CHANNEL_2
562 * @arg @ref LL_DMA_CHANNEL_3
563 * @arg @ref LL_DMA_CHANNEL_4
564 * @arg @ref LL_DMA_CHANNEL_5
565 * @arg @ref LL_DMA_CHANNEL_6
566 * @arg @ref LL_DMA_CHANNEL_7
567 * @param Configuration This parameter must be a combination of all the following values:
568 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
569 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
570 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
571 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
572 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
573 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
574 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
575 * @retval None
576 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)577 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
578 {
579 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
580 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
581 Configuration);
582 }
583
584 /**
585 * @brief Set Data transfer direction (read from peripheral or from memory).
586 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
587 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
588 * @param DMAx DMAx Instance
589 * @param Channel This parameter can be one of the following values:
590 * @arg @ref LL_DMA_CHANNEL_1
591 * @arg @ref LL_DMA_CHANNEL_2
592 * @arg @ref LL_DMA_CHANNEL_3
593 * @arg @ref LL_DMA_CHANNEL_4
594 * @arg @ref LL_DMA_CHANNEL_5
595 * @arg @ref LL_DMA_CHANNEL_6
596 * @arg @ref LL_DMA_CHANNEL_7
597 * @param Direction This parameter can be one of the following values:
598 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
599 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
600 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
601 * @retval None
602 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)603 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
604 {
605 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
606 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
607 }
608
609 /**
610 * @brief Get Data transfer direction (read from peripheral or from memory).
611 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
612 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
613 * @param DMAx DMAx Instance
614 * @param Channel This parameter can be one of the following values:
615 * @arg @ref LL_DMA_CHANNEL_1
616 * @arg @ref LL_DMA_CHANNEL_2
617 * @arg @ref LL_DMA_CHANNEL_3
618 * @arg @ref LL_DMA_CHANNEL_4
619 * @arg @ref LL_DMA_CHANNEL_5
620 * @arg @ref LL_DMA_CHANNEL_6
621 * @arg @ref LL_DMA_CHANNEL_7
622 * @retval Returned value can be one of the following values:
623 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
624 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
625 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
626 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)627 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
628 {
629 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
630 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
631 }
632
633 /**
634 * @brief Set DMA mode circular or normal.
635 * @note The circular buffer mode cannot be used if the memory-to-memory
636 * data transfer is configured on the selected Channel.
637 * @rmtoll CCR CIRC LL_DMA_SetMode
638 * @param DMAx DMAx Instance
639 * @param Channel This parameter can be one of the following values:
640 * @arg @ref LL_DMA_CHANNEL_1
641 * @arg @ref LL_DMA_CHANNEL_2
642 * @arg @ref LL_DMA_CHANNEL_3
643 * @arg @ref LL_DMA_CHANNEL_4
644 * @arg @ref LL_DMA_CHANNEL_5
645 * @arg @ref LL_DMA_CHANNEL_6
646 * @arg @ref LL_DMA_CHANNEL_7
647 * @param Mode This parameter can be one of the following values:
648 * @arg @ref LL_DMA_MODE_NORMAL
649 * @arg @ref LL_DMA_MODE_CIRCULAR
650 * @retval None
651 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)652 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
653 {
654 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC,
655 Mode);
656 }
657
658 /**
659 * @brief Get DMA mode circular or normal.
660 * @rmtoll CCR CIRC LL_DMA_GetMode
661 * @param DMAx DMAx Instance
662 * @param Channel This parameter can be one of the following values:
663 * @arg @ref LL_DMA_CHANNEL_1
664 * @arg @ref LL_DMA_CHANNEL_2
665 * @arg @ref LL_DMA_CHANNEL_3
666 * @arg @ref LL_DMA_CHANNEL_4
667 * @arg @ref LL_DMA_CHANNEL_5
668 * @arg @ref LL_DMA_CHANNEL_6
669 * @arg @ref LL_DMA_CHANNEL_7
670 * @retval Returned value can be one of the following values:
671 * @arg @ref LL_DMA_MODE_NORMAL
672 * @arg @ref LL_DMA_MODE_CIRCULAR
673 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)674 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
675 {
676 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
677 DMA_CCR_CIRC));
678 }
679
680 /**
681 * @brief Set Peripheral increment mode.
682 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
683 * @param DMAx DMAx Instance
684 * @param Channel This parameter can be one of the following values:
685 * @arg @ref LL_DMA_CHANNEL_1
686 * @arg @ref LL_DMA_CHANNEL_2
687 * @arg @ref LL_DMA_CHANNEL_3
688 * @arg @ref LL_DMA_CHANNEL_4
689 * @arg @ref LL_DMA_CHANNEL_5
690 * @arg @ref LL_DMA_CHANNEL_6
691 * @arg @ref LL_DMA_CHANNEL_7
692 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
693 * @arg @ref LL_DMA_PERIPH_INCREMENT
694 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
695 * @retval None
696 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)697 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
698 {
699 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC,
700 PeriphOrM2MSrcIncMode);
701 }
702
703 /**
704 * @brief Get Peripheral increment mode.
705 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
706 * @param DMAx DMAx Instance
707 * @param Channel This parameter can be one of the following values:
708 * @arg @ref LL_DMA_CHANNEL_1
709 * @arg @ref LL_DMA_CHANNEL_2
710 * @arg @ref LL_DMA_CHANNEL_3
711 * @arg @ref LL_DMA_CHANNEL_4
712 * @arg @ref LL_DMA_CHANNEL_5
713 * @arg @ref LL_DMA_CHANNEL_6
714 * @arg @ref LL_DMA_CHANNEL_7
715 * @retval Returned value can be one of the following values:
716 * @arg @ref LL_DMA_PERIPH_INCREMENT
717 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
718 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)719 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
720 {
721 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
722 DMA_CCR_PINC));
723 }
724
725 /**
726 * @brief Set Memory increment mode.
727 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
728 * @param DMAx DMAx Instance
729 * @param Channel This parameter can be one of the following values:
730 * @arg @ref LL_DMA_CHANNEL_1
731 * @arg @ref LL_DMA_CHANNEL_2
732 * @arg @ref LL_DMA_CHANNEL_3
733 * @arg @ref LL_DMA_CHANNEL_4
734 * @arg @ref LL_DMA_CHANNEL_5
735 * @arg @ref LL_DMA_CHANNEL_6
736 * @arg @ref LL_DMA_CHANNEL_7
737 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
738 * @arg @ref LL_DMA_MEMORY_INCREMENT
739 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
740 * @retval None
741 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)742 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
743 {
744 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC,
745 MemoryOrM2MDstIncMode);
746 }
747
748 /**
749 * @brief Get Memory increment mode.
750 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
751 * @param DMAx DMAx Instance
752 * @param Channel This parameter can be one of the following values:
753 * @arg @ref LL_DMA_CHANNEL_1
754 * @arg @ref LL_DMA_CHANNEL_2
755 * @arg @ref LL_DMA_CHANNEL_3
756 * @arg @ref LL_DMA_CHANNEL_4
757 * @arg @ref LL_DMA_CHANNEL_5
758 * @arg @ref LL_DMA_CHANNEL_6
759 * @arg @ref LL_DMA_CHANNEL_7
760 * @retval Returned value can be one of the following values:
761 * @arg @ref LL_DMA_MEMORY_INCREMENT
762 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
763 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)764 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
765 {
766 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
767 DMA_CCR_MINC));
768 }
769
770 /**
771 * @brief Set Peripheral size.
772 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
773 * @param DMAx DMAx Instance
774 * @param Channel This parameter can be one of the following values:
775 * @arg @ref LL_DMA_CHANNEL_1
776 * @arg @ref LL_DMA_CHANNEL_2
777 * @arg @ref LL_DMA_CHANNEL_3
778 * @arg @ref LL_DMA_CHANNEL_4
779 * @arg @ref LL_DMA_CHANNEL_5
780 * @arg @ref LL_DMA_CHANNEL_6
781 * @arg @ref LL_DMA_CHANNEL_7
782 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
783 * @arg @ref LL_DMA_PDATAALIGN_BYTE
784 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
785 * @arg @ref LL_DMA_PDATAALIGN_WORD
786 * @retval None
787 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)788 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
789 {
790 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE,
791 PeriphOrM2MSrcDataSize);
792 }
793
794 /**
795 * @brief Get Peripheral size.
796 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
797 * @param DMAx DMAx Instance
798 * @param Channel This parameter can be one of the following values:
799 * @arg @ref LL_DMA_CHANNEL_1
800 * @arg @ref LL_DMA_CHANNEL_2
801 * @arg @ref LL_DMA_CHANNEL_3
802 * @arg @ref LL_DMA_CHANNEL_4
803 * @arg @ref LL_DMA_CHANNEL_5
804 * @arg @ref LL_DMA_CHANNEL_6
805 * @arg @ref LL_DMA_CHANNEL_7
806 * @retval Returned value can be one of the following values:
807 * @arg @ref LL_DMA_PDATAALIGN_BYTE
808 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
809 * @arg @ref LL_DMA_PDATAALIGN_WORD
810 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)811 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
812 {
813 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
814 DMA_CCR_PSIZE));
815 }
816
817 /**
818 * @brief Set Memory size.
819 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
820 * @param DMAx DMAx Instance
821 * @param Channel This parameter can be one of the following values:
822 * @arg @ref LL_DMA_CHANNEL_1
823 * @arg @ref LL_DMA_CHANNEL_2
824 * @arg @ref LL_DMA_CHANNEL_3
825 * @arg @ref LL_DMA_CHANNEL_4
826 * @arg @ref LL_DMA_CHANNEL_5
827 * @arg @ref LL_DMA_CHANNEL_6
828 * @arg @ref LL_DMA_CHANNEL_7
829 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
830 * @arg @ref LL_DMA_MDATAALIGN_BYTE
831 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
832 * @arg @ref LL_DMA_MDATAALIGN_WORD
833 * @retval None
834 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)835 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
836 {
837 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE,
838 MemoryOrM2MDstDataSize);
839 }
840
841 /**
842 * @brief Get Memory size.
843 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
844 * @param DMAx DMAx Instance
845 * @param Channel This parameter can be one of the following values:
846 * @arg @ref LL_DMA_CHANNEL_1
847 * @arg @ref LL_DMA_CHANNEL_2
848 * @arg @ref LL_DMA_CHANNEL_3
849 * @arg @ref LL_DMA_CHANNEL_4
850 * @arg @ref LL_DMA_CHANNEL_5
851 * @arg @ref LL_DMA_CHANNEL_6
852 * @arg @ref LL_DMA_CHANNEL_7
853 * @retval Returned value can be one of the following values:
854 * @arg @ref LL_DMA_MDATAALIGN_BYTE
855 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
856 * @arg @ref LL_DMA_MDATAALIGN_WORD
857 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)858 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
859 {
860 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
861 DMA_CCR_MSIZE));
862 }
863
864 /**
865 * @brief Set Channel priority level.
866 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
867 * @param DMAx DMAx Instance
868 * @param Channel This parameter can be one of the following values:
869 * @arg @ref LL_DMA_CHANNEL_1
870 * @arg @ref LL_DMA_CHANNEL_2
871 * @arg @ref LL_DMA_CHANNEL_3
872 * @arg @ref LL_DMA_CHANNEL_4
873 * @arg @ref LL_DMA_CHANNEL_5
874 * @arg @ref LL_DMA_CHANNEL_6
875 * @arg @ref LL_DMA_CHANNEL_7
876 * @param Priority This parameter can be one of the following values:
877 * @arg @ref LL_DMA_PRIORITY_LOW
878 * @arg @ref LL_DMA_PRIORITY_MEDIUM
879 * @arg @ref LL_DMA_PRIORITY_HIGH
880 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
881 * @retval None
882 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)883 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
884 {
885 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL,
886 Priority);
887 }
888
889 /**
890 * @brief Get Channel priority level.
891 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
892 * @param DMAx DMAx Instance
893 * @param Channel This parameter can be one of the following values:
894 * @arg @ref LL_DMA_CHANNEL_1
895 * @arg @ref LL_DMA_CHANNEL_2
896 * @arg @ref LL_DMA_CHANNEL_3
897 * @arg @ref LL_DMA_CHANNEL_4
898 * @arg @ref LL_DMA_CHANNEL_5
899 * @arg @ref LL_DMA_CHANNEL_6
900 * @arg @ref LL_DMA_CHANNEL_7
901 * @retval Returned value can be one of the following values:
902 * @arg @ref LL_DMA_PRIORITY_LOW
903 * @arg @ref LL_DMA_PRIORITY_MEDIUM
904 * @arg @ref LL_DMA_PRIORITY_HIGH
905 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
906 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)907 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
908 {
909 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
910 DMA_CCR_PL));
911 }
912
913 /**
914 * @brief Set Number of data to transfer.
915 * @note This action has no effect if
916 * channel is enabled.
917 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
918 * @param DMAx DMAx Instance
919 * @param Channel This parameter can be one of the following values:
920 * @arg @ref LL_DMA_CHANNEL_1
921 * @arg @ref LL_DMA_CHANNEL_2
922 * @arg @ref LL_DMA_CHANNEL_3
923 * @arg @ref LL_DMA_CHANNEL_4
924 * @arg @ref LL_DMA_CHANNEL_5
925 * @arg @ref LL_DMA_CHANNEL_6
926 * @arg @ref LL_DMA_CHANNEL_7
927 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
928 * @retval None
929 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)930 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
931 {
932 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR,
933 DMA_CNDTR_NDT, NbData);
934 }
935
936 /**
937 * @brief Get Number of data to transfer.
938 * @note Once the channel is enabled, the return value indicate the
939 * remaining bytes to be transmitted.
940 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
941 * @param DMAx DMAx Instance
942 * @param Channel This parameter can be one of the following values:
943 * @arg @ref LL_DMA_CHANNEL_1
944 * @arg @ref LL_DMA_CHANNEL_2
945 * @arg @ref LL_DMA_CHANNEL_3
946 * @arg @ref LL_DMA_CHANNEL_4
947 * @arg @ref LL_DMA_CHANNEL_5
948 * @arg @ref LL_DMA_CHANNEL_6
949 * @arg @ref LL_DMA_CHANNEL_7
950 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
951 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)952 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
953 {
954 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR,
955 DMA_CNDTR_NDT));
956 }
957
958 /**
959 * @brief Configure the Source and Destination addresses.
960 * @note This API must not be called when the DMA channel is enabled.
961 * @note Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
962 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
963 * CMAR MA LL_DMA_ConfigAddresses
964 * @param DMAx DMAx Instance
965 * @param Channel This parameter can be one of the following values:
966 * @arg @ref LL_DMA_CHANNEL_1
967 * @arg @ref LL_DMA_CHANNEL_2
968 * @arg @ref LL_DMA_CHANNEL_3
969 * @arg @ref LL_DMA_CHANNEL_4
970 * @arg @ref LL_DMA_CHANNEL_5
971 * @arg @ref LL_DMA_CHANNEL_6
972 * @arg @ref LL_DMA_CHANNEL_7
973 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
974 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
975 * @param Direction This parameter can be one of the following values:
976 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
977 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
978 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
979 * @retval None
980 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)981 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
982 uint32_t DstAddress, uint32_t Direction)
983 {
984 /* Direction Memory to Periph */
985 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
986 {
987 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, SrcAddress);
988 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, DstAddress);
989 }
990 /* Direction Periph to Memory and Memory to Memory */
991 else
992 {
993 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, SrcAddress);
994 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, DstAddress);
995 }
996 }
997
998 /**
999 * @brief Set the Memory address.
1000 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1001 * @note This API must not be called when the DMA channel is enabled.
1002 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
1003 * @param DMAx DMAx Instance
1004 * @param Channel This parameter can be one of the following values:
1005 * @arg @ref LL_DMA_CHANNEL_1
1006 * @arg @ref LL_DMA_CHANNEL_2
1007 * @arg @ref LL_DMA_CHANNEL_3
1008 * @arg @ref LL_DMA_CHANNEL_4
1009 * @arg @ref LL_DMA_CHANNEL_5
1010 * @arg @ref LL_DMA_CHANNEL_6
1011 * @arg @ref LL_DMA_CHANNEL_7
1012 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1013 * @retval None
1014 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1015 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1016 {
1017 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress);
1018 }
1019
1020 /**
1021 * @brief Set the Peripheral address.
1022 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1023 * @note This API must not be called when the DMA channel is enabled.
1024 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1025 * @param DMAx DMAx Instance
1026 * @param Channel This parameter can be one of the following values:
1027 * @arg @ref LL_DMA_CHANNEL_1
1028 * @arg @ref LL_DMA_CHANNEL_2
1029 * @arg @ref LL_DMA_CHANNEL_3
1030 * @arg @ref LL_DMA_CHANNEL_4
1031 * @arg @ref LL_DMA_CHANNEL_5
1032 * @arg @ref LL_DMA_CHANNEL_6
1033 * @arg @ref LL_DMA_CHANNEL_7
1034 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1035 * @retval None
1036 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)1037 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1038 {
1039 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress);
1040 }
1041
1042 /**
1043 * @brief Get Memory address.
1044 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1045 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1046 * @param DMAx DMAx Instance
1047 * @param Channel This parameter can be one of the following values:
1048 * @arg @ref LL_DMA_CHANNEL_1
1049 * @arg @ref LL_DMA_CHANNEL_2
1050 * @arg @ref LL_DMA_CHANNEL_3
1051 * @arg @ref LL_DMA_CHANNEL_4
1052 * @arg @ref LL_DMA_CHANNEL_5
1053 * @arg @ref LL_DMA_CHANNEL_6
1054 * @arg @ref LL_DMA_CHANNEL_7
1055 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1056 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)1057 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1058 {
1059 return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR));
1060 }
1061
1062 /**
1063 * @brief Get Peripheral address.
1064 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1065 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1066 * @param DMAx DMAx Instance
1067 * @param Channel This parameter can be one of the following values:
1068 * @arg @ref LL_DMA_CHANNEL_1
1069 * @arg @ref LL_DMA_CHANNEL_2
1070 * @arg @ref LL_DMA_CHANNEL_3
1071 * @arg @ref LL_DMA_CHANNEL_4
1072 * @arg @ref LL_DMA_CHANNEL_5
1073 * @arg @ref LL_DMA_CHANNEL_6
1074 * @arg @ref LL_DMA_CHANNEL_7
1075 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1076 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1077 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1078 {
1079 return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR));
1080 }
1081
1082 /**
1083 * @brief Set the Memory to Memory Source address.
1084 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1085 * @note This API must not be called when the DMA channel is enabled.
1086 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1087 * @param DMAx DMAx Instance
1088 * @param Channel This parameter can be one of the following values:
1089 * @arg @ref LL_DMA_CHANNEL_1
1090 * @arg @ref LL_DMA_CHANNEL_2
1091 * @arg @ref LL_DMA_CHANNEL_3
1092 * @arg @ref LL_DMA_CHANNEL_4
1093 * @arg @ref LL_DMA_CHANNEL_5
1094 * @arg @ref LL_DMA_CHANNEL_6
1095 * @arg @ref LL_DMA_CHANNEL_7
1096 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1097 * @retval None
1098 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1099 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1100 {
1101 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress);
1102 }
1103
1104 /**
1105 * @brief Set the Memory to Memory Destination address.
1106 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1107 * @note This API must not be called when the DMA channel is enabled.
1108 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1109 * @param DMAx DMAx Instance
1110 * @param Channel This parameter can be one of the following values:
1111 * @arg @ref LL_DMA_CHANNEL_1
1112 * @arg @ref LL_DMA_CHANNEL_2
1113 * @arg @ref LL_DMA_CHANNEL_3
1114 * @arg @ref LL_DMA_CHANNEL_4
1115 * @arg @ref LL_DMA_CHANNEL_5
1116 * @arg @ref LL_DMA_CHANNEL_6
1117 * @arg @ref LL_DMA_CHANNEL_7
1118 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1119 * @retval None
1120 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1121 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1122 {
1123 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress);
1124 }
1125
1126 /**
1127 * @brief Get the Memory to Memory Source address.
1128 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1129 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1130 * @param DMAx DMAx Instance
1131 * @param Channel This parameter can be one of the following values:
1132 * @arg @ref LL_DMA_CHANNEL_1
1133 * @arg @ref LL_DMA_CHANNEL_2
1134 * @arg @ref LL_DMA_CHANNEL_3
1135 * @arg @ref LL_DMA_CHANNEL_4
1136 * @arg @ref LL_DMA_CHANNEL_5
1137 * @arg @ref LL_DMA_CHANNEL_6
1138 * @arg @ref LL_DMA_CHANNEL_7
1139 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1140 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1141 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1142 {
1143 return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR));
1144 }
1145
1146 /**
1147 * @brief Get the Memory to Memory Destination address.
1148 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1149 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1150 * @param DMAx DMAx Instance
1151 * @param Channel This parameter can be one of the following values:
1152 * @arg @ref LL_DMA_CHANNEL_1
1153 * @arg @ref LL_DMA_CHANNEL_2
1154 * @arg @ref LL_DMA_CHANNEL_3
1155 * @arg @ref LL_DMA_CHANNEL_4
1156 * @arg @ref LL_DMA_CHANNEL_5
1157 * @arg @ref LL_DMA_CHANNEL_6
1158 * @arg @ref LL_DMA_CHANNEL_7
1159 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1160 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1161 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1162 {
1163 return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR));
1164 }
1165
1166 /**
1167 * @brief Set DMA request for DMA Channels on DMAMUX Channel x.
1168 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1169 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
1170 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
1171 * @param DMAx DMAx Instance
1172 * @param Channel This parameter can be one of the following values:
1173 * @arg @ref LL_DMA_CHANNEL_1
1174 * @arg @ref LL_DMA_CHANNEL_2
1175 * @arg @ref LL_DMA_CHANNEL_3
1176 * @arg @ref LL_DMA_CHANNEL_4
1177 * @arg @ref LL_DMA_CHANNEL_5
1178 * @arg @ref LL_DMA_CHANNEL_6
1179 * @arg @ref LL_DMA_CHANNEL_7
1180 * @param Request This parameter can be one of the following values:
1181 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1182 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1183 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1184 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1185 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1186 * @arg @ref LL_DMAMUX_REQ_ADC1
1187 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1188 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1189 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1190 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1191 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1192 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1193 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1194 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
1195 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1196 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1197 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1198 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1199 * @arg @ref LL_DMAMUX_REQ_SAI1_A
1200 * @arg @ref LL_DMAMUX_REQ_SAI1_B
1201 * @arg @ref LL_DMAMUX_REQ_QUADSPI
1202 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1203 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1204 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1205 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1206 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1207 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1208 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1209 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1210 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1211 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1212 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1213 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1214 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1215 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1216 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1217 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1218 * @arg @ref LL_DMAMUX_REQ_AES1_IN
1219 * @arg @ref LL_DMAMUX_REQ_AES1_OUT
1220 * @arg @ref LL_DMAMUX_REQ_AES2_IN
1221 * @arg @ref LL_DMAMUX_REQ_AES2_OUT
1222 * @retval None
1223 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)1224 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
1225 {
1226 MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1227 }
1228
1229 /**
1230 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1231 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1232 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
1233 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1234 * @param DMAx DMAx Instance
1235 * @param Channel This parameter can be one of the following values:
1236 * @arg @ref LL_DMA_CHANNEL_1
1237 * @arg @ref LL_DMA_CHANNEL_2
1238 * @arg @ref LL_DMA_CHANNEL_3
1239 * @arg @ref LL_DMA_CHANNEL_4
1240 * @arg @ref LL_DMA_CHANNEL_5
1241 * @arg @ref LL_DMA_CHANNEL_6
1242 * @arg @ref LL_DMA_CHANNEL_7
1243 * @retval Returned value can be one of the following values:
1244 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1245 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1246 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1247 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1248 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1249 * @arg @ref LL_DMAMUX_REQ_ADC1
1250 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1251 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1252 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1253 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1254 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1255 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1256 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1257 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
1258 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1259 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1260 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1261 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1262 * @arg @ref LL_DMAMUX_REQ_SAI1_A
1263 * @arg @ref LL_DMAMUX_REQ_SAI1_B
1264 * @arg @ref LL_DMAMUX_REQ_QUADSPI
1265 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1266 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1267 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1268 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1269 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1270 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1271 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1272 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1273 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1274 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1275 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1276 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1277 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1278 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1279 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1280 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1281 * @arg @ref LL_DMAMUX_REQ_AES1_IN
1282 * @arg @ref LL_DMAMUX_REQ_AES1_OUT
1283 * @arg @ref LL_DMAMUX_REQ_AES2_IN
1284 * @arg @ref LL_DMAMUX_REQ_AES2_OUT
1285 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)1286 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1287 {
1288 return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CCR, DMAMUX_CxCR_DMAREQ_ID));
1289 }
1290
1291 /**
1292 * @}
1293 */
1294
1295 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1296 * @{
1297 */
1298
1299 /**
1300 * @brief Get Channel 1 global interrupt flag.
1301 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1302 * @param DMAx DMAx Instance
1303 * @retval State of bit (1 or 0).
1304 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1305 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1306 {
1307 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
1308 }
1309
1310 /**
1311 * @brief Get Channel 2 global interrupt flag.
1312 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1313 * @param DMAx DMAx Instance
1314 * @retval State of bit (1 or 0).
1315 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1316 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1317 {
1318 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
1319 }
1320
1321 /**
1322 * @brief Get Channel 3 global interrupt flag.
1323 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1324 * @param DMAx DMAx Instance
1325 * @retval State of bit (1 or 0).
1326 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1327 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1328 {
1329 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
1330 }
1331
1332 /**
1333 * @brief Get Channel 4 global interrupt flag.
1334 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1335 * @param DMAx DMAx Instance
1336 * @retval State of bit (1 or 0).
1337 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1338 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1339 {
1340 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
1341 }
1342
1343 /**
1344 * @brief Get Channel 5 global interrupt flag.
1345 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1346 * @param DMAx DMAx Instance
1347 * @retval State of bit (1 or 0).
1348 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1349 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1350 {
1351 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
1352 }
1353
1354 /**
1355 * @brief Get Channel 6 global interrupt flag.
1356 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1357 * @param DMAx DMAx Instance
1358 * @retval State of bit (1 or 0).
1359 */
LL_DMA_IsActiveFlag_GI6(DMA_TypeDef * DMAx)1360 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1361 {
1362 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
1363 }
1364
1365 /**
1366 * @brief Get Channel 7 global interrupt flag.
1367 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1368 * @param DMAx DMAx Instance
1369 * @retval State of bit (1 or 0).
1370 */
LL_DMA_IsActiveFlag_GI7(DMA_TypeDef * DMAx)1371 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1372 {
1373 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
1374 }
1375
1376 /**
1377 * @brief Get Channel 1 transfer complete flag.
1378 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1379 * @param DMAx DMAx Instance
1380 * @retval State of bit (1 or 0).
1381 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1382 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1383 {
1384 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
1385 }
1386
1387 /**
1388 * @brief Get Channel 2 transfer complete flag.
1389 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1390 * @param DMAx DMAx Instance
1391 * @retval State of bit (1 or 0).
1392 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1393 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1394 {
1395 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
1396 }
1397
1398 /**
1399 * @brief Get Channel 3 transfer complete flag.
1400 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1401 * @param DMAx DMAx Instance
1402 * @retval State of bit (1 or 0).
1403 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1404 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1405 {
1406 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
1407 }
1408
1409 /**
1410 * @brief Get Channel 4 transfer complete flag.
1411 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1412 * @param DMAx DMAx Instance
1413 * @retval State of bit (1 or 0).
1414 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1415 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1416 {
1417 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
1418 }
1419
1420 /**
1421 * @brief Get Channel 5 transfer complete flag.
1422 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1423 * @param DMAx DMAx Instance
1424 * @retval State of bit (1 or 0).
1425 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1426 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1427 {
1428 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
1429 }
1430
1431 /**
1432 * @brief Get Channel 6 transfer complete flag.
1433 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1434 * @param DMAx DMAx Instance
1435 * @retval State of bit (1 or 0).
1436 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1437 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1438 {
1439 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
1440 }
1441
1442 /**
1443 * @brief Get Channel 7 transfer complete flag.
1444 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1445 * @param DMAx DMAx Instance
1446 * @retval State of bit (1 or 0).
1447 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1448 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1449 {
1450 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
1451 }
1452
1453 /**
1454 * @brief Get Channel 1 half transfer flag.
1455 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1456 * @param DMAx DMAx Instance
1457 * @retval State of bit (1 or 0).
1458 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1459 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1460 {
1461 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
1462 }
1463
1464 /**
1465 * @brief Get Channel 2 half transfer flag.
1466 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1467 * @param DMAx DMAx Instance
1468 * @retval State of bit (1 or 0).
1469 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1470 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1471 {
1472 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
1473 }
1474
1475 /**
1476 * @brief Get Channel 3 half transfer flag.
1477 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1478 * @param DMAx DMAx Instance
1479 * @retval State of bit (1 or 0).
1480 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1481 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1482 {
1483 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
1484 }
1485
1486 /**
1487 * @brief Get Channel 4 half transfer flag.
1488 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1489 * @param DMAx DMAx Instance
1490 * @retval State of bit (1 or 0).
1491 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1492 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1493 {
1494 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
1495 }
1496
1497 /**
1498 * @brief Get Channel 5 half transfer flag.
1499 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1500 * @param DMAx DMAx Instance
1501 * @retval State of bit (1 or 0).
1502 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1503 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1504 {
1505 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
1506 }
1507
1508 /**
1509 * @brief Get Channel 6 half transfer flag.
1510 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1511 * @param DMAx DMAx Instance
1512 * @retval State of bit (1 or 0).
1513 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1514 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1515 {
1516 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
1517 }
1518
1519 /**
1520 * @brief Get Channel 7 half transfer flag.
1521 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1522 * @param DMAx DMAx Instance
1523 * @retval State of bit (1 or 0).
1524 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1525 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1526 {
1527 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
1528 }
1529
1530 /**
1531 * @brief Get Channel 1 transfer error flag.
1532 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1533 * @param DMAx DMAx Instance
1534 * @retval State of bit (1 or 0).
1535 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1536 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1537 {
1538 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
1539 }
1540
1541 /**
1542 * @brief Get Channel 2 transfer error flag.
1543 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1544 * @param DMAx DMAx Instance
1545 * @retval State of bit (1 or 0).
1546 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1547 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1548 {
1549 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
1550 }
1551
1552 /**
1553 * @brief Get Channel 3 transfer error flag.
1554 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1555 * @param DMAx DMAx Instance
1556 * @retval State of bit (1 or 0).
1557 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1558 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1559 {
1560 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
1561 }
1562
1563 /**
1564 * @brief Get Channel 4 transfer error flag.
1565 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1566 * @param DMAx DMAx Instance
1567 * @retval State of bit (1 or 0).
1568 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1569 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1570 {
1571 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
1572 }
1573
1574 /**
1575 * @brief Get Channel 5 transfer error flag.
1576 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1577 * @param DMAx DMAx Instance
1578 * @retval State of bit (1 or 0).
1579 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1580 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1581 {
1582 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
1583 }
1584
1585 /**
1586 * @brief Get Channel 6 transfer error flag.
1587 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1588 * @param DMAx DMAx Instance
1589 * @retval State of bit (1 or 0).
1590 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1591 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1592 {
1593 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
1594 }
1595
1596 /**
1597 * @brief Get Channel 7 transfer error flag.
1598 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1599 * @param DMAx DMAx Instance
1600 * @retval State of bit (1 or 0).
1601 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1602 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1603 {
1604 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
1605 }
1606
1607 /**
1608 * @brief Clear Channel 1 global interrupt flag.
1609 * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
1610 Instead clear specific flags transfer complete, half transfer & transfer
1611 error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
1612 LL_DMA_ClearFlag_TE1. bug id 2.4.1 in Product Errata Sheet.
1613 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1614 * @param DMAx DMAx Instance
1615 * @retval None
1616 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1617 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1618 {
1619 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1620 }
1621
1622 /**
1623 * @brief Clear Channel 2 global interrupt flag.
1624 * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
1625 Instead clear specific flags transfer complete, half transfer & transfer
1626 error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
1627 LL_DMA_ClearFlag_TE2. bug id 2.4.1 in Product Errata Sheet.
1628 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1629 * @param DMAx DMAx Instance
1630 * @retval None
1631 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1632 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1633 {
1634 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1635 }
1636
1637 /**
1638 * @brief Clear Channel 3 global interrupt flag.
1639 * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
1640 Instead clear specific flags transfer complete, half transfer & transfer
1641 error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
1642 LL_DMA_ClearFlag_TE3. bug id 2.4.1 in Product Errata Sheet.
1643 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1644 * @param DMAx DMAx Instance
1645 * @retval None
1646 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1647 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1648 {
1649 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1650 }
1651
1652 /**
1653 * @brief Clear Channel 4 global interrupt flag.
1654 * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
1655 Instead clear specific flags transfer complete, half transfer & transfer
1656 error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
1657 LL_DMA_ClearFlag_TE4. bug id 2.4.1 in Product Errata Sheet.
1658 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1659 * @param DMAx DMAx Instance
1660 * @retval None
1661 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1662 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1663 {
1664 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1665 }
1666
1667 /**
1668 * @brief Clear Channel 5 global interrupt flag.
1669 * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
1670 Instead clear specific flags transfer complete, half transfer & transfer
1671 error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
1672 LL_DMA_ClearFlag_TE5. bug id 2.4.1 in Product Errata Sheet.
1673 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1674 * @param DMAx DMAx Instance
1675 * @retval None
1676 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)1677 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1678 {
1679 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
1680 }
1681
1682 /**
1683 * @brief Clear Channel 6 global interrupt flag.
1684 * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
1685 Instead clear specific flags transfer complete, half transfer & transfer
1686 error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
1687 LL_DMA_ClearFlag_TE6. bug id 2.4.1 in Product Errata Sheet.
1688 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
1689 * @param DMAx DMAx Instance
1690 * @retval None
1691 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)1692 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1693 {
1694 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
1695 }
1696
1697 /**
1698 * @brief Clear Channel 7 global interrupt flag.
1699 * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
1700 Instead clear specific flags transfer complete, half transfer & transfer
1701 error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
1702 LL_DMA_ClearFlag_TE7. bug id 2.4.1 in Product Errata Sheet.
1703 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
1704 * @param DMAx DMAx Instance
1705 * @retval None
1706 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)1707 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1708 {
1709 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
1710 }
1711
1712 /**
1713 * @brief Clear Channel 1 transfer complete flag.
1714 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1715 * @param DMAx DMAx Instance
1716 * @retval None
1717 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)1718 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1719 {
1720 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1721 }
1722
1723 /**
1724 * @brief Clear Channel 2 transfer complete flag.
1725 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1726 * @param DMAx DMAx Instance
1727 * @retval None
1728 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)1729 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1730 {
1731 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1732 }
1733
1734 /**
1735 * @brief Clear Channel 3 transfer complete flag.
1736 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1737 * @param DMAx DMAx Instance
1738 * @retval None
1739 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)1740 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1741 {
1742 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
1743 }
1744
1745 /**
1746 * @brief Clear Channel 4 transfer complete flag.
1747 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
1748 * @param DMAx DMAx Instance
1749 * @retval None
1750 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)1751 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1752 {
1753 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
1754 }
1755
1756 /**
1757 * @brief Clear Channel 5 transfer complete flag.
1758 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
1759 * @param DMAx DMAx Instance
1760 * @retval None
1761 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)1762 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1763 {
1764 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
1765 }
1766
1767 /**
1768 * @brief Clear Channel 6 transfer complete flag.
1769 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
1770 * @param DMAx DMAx Instance
1771 * @retval None
1772 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)1773 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
1774 {
1775 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
1776 }
1777
1778 /**
1779 * @brief Clear Channel 7 transfer complete flag.
1780 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
1781 * @param DMAx DMAx Instance
1782 * @retval None
1783 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)1784 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
1785 {
1786 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
1787 }
1788
1789 /**
1790 * @brief Clear Channel 1 half transfer flag.
1791 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
1792 * @param DMAx DMAx Instance
1793 * @retval None
1794 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)1795 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1796 {
1797 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
1798 }
1799
1800 /**
1801 * @brief Clear Channel 2 half transfer flag.
1802 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
1803 * @param DMAx DMAx Instance
1804 * @retval None
1805 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)1806 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1807 {
1808 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
1809 }
1810
1811 /**
1812 * @brief Clear Channel 3 half transfer flag.
1813 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
1814 * @param DMAx DMAx Instance
1815 * @retval None
1816 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)1817 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1818 {
1819 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
1820 }
1821
1822 /**
1823 * @brief Clear Channel 4 half transfer flag.
1824 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
1825 * @param DMAx DMAx Instance
1826 * @retval None
1827 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)1828 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
1829 {
1830 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
1831 }
1832
1833 /**
1834 * @brief Clear Channel 5 half transfer flag.
1835 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
1836 * @param DMAx DMAx Instance
1837 * @retval None
1838 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)1839 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
1840 {
1841 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
1842 }
1843
1844 /**
1845 * @brief Clear Channel 6 half transfer flag.
1846 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
1847 * @param DMAx DMAx Instance
1848 * @retval None
1849 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)1850 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
1851 {
1852 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
1853 }
1854
1855 /**
1856 * @brief Clear Channel 7 half transfer flag.
1857 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
1858 * @param DMAx DMAx Instance
1859 * @retval None
1860 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)1861 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
1862 {
1863 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
1864 }
1865
1866 /**
1867 * @brief Clear Channel 1 transfer error flag.
1868 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
1869 * @param DMAx DMAx Instance
1870 * @retval None
1871 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)1872 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1873 {
1874 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
1875 }
1876
1877 /**
1878 * @brief Clear Channel 2 transfer error flag.
1879 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
1880 * @param DMAx DMAx Instance
1881 * @retval None
1882 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)1883 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1884 {
1885 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
1886 }
1887
1888 /**
1889 * @brief Clear Channel 3 transfer error flag.
1890 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
1891 * @param DMAx DMAx Instance
1892 * @retval None
1893 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)1894 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1895 {
1896 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
1897 }
1898
1899 /**
1900 * @brief Clear Channel 4 transfer error flag.
1901 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
1902 * @param DMAx DMAx Instance
1903 * @retval None
1904 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)1905 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
1906 {
1907 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
1908 }
1909
1910 /**
1911 * @brief Clear Channel 5 transfer error flag.
1912 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
1913 * @param DMAx DMAx Instance
1914 * @retval None
1915 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)1916 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
1917 {
1918 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
1919 }
1920
1921 /**
1922 * @brief Clear Channel 6 transfer error flag.
1923 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
1924 * @param DMAx DMAx Instance
1925 * @retval None
1926 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)1927 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
1928 {
1929 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
1930 }
1931
1932 /**
1933 * @brief Clear Channel 7 transfer error flag.
1934 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
1935 * @param DMAx DMAx Instance
1936 * @retval None
1937 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)1938 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
1939 {
1940 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
1941 }
1942
1943 /**
1944 * @}
1945 */
1946
1947 /** @defgroup DMA_LL_EF_IT_Management IT_Management
1948 * @{
1949 */
1950 /**
1951 * @brief Enable Transfer complete interrupt.
1952 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
1953 * @param DMAx DMAx Instance
1954 * @param Channel This parameter can be one of the following values:
1955 * @arg @ref LL_DMA_CHANNEL_1
1956 * @arg @ref LL_DMA_CHANNEL_2
1957 * @arg @ref LL_DMA_CHANNEL_3
1958 * @arg @ref LL_DMA_CHANNEL_4
1959 * @arg @ref LL_DMA_CHANNEL_5
1960 * @arg @ref LL_DMA_CHANNEL_6
1961 * @arg @ref LL_DMA_CHANNEL_7
1962 * @retval None
1963 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1964 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1965 {
1966 SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE);
1967 }
1968
1969 /**
1970 * @brief Enable Half transfer interrupt.
1971 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
1972 * @param DMAx DMAx Instance
1973 * @param Channel This parameter can be one of the following values:
1974 * @arg @ref LL_DMA_CHANNEL_1
1975 * @arg @ref LL_DMA_CHANNEL_2
1976 * @arg @ref LL_DMA_CHANNEL_3
1977 * @arg @ref LL_DMA_CHANNEL_4
1978 * @arg @ref LL_DMA_CHANNEL_5
1979 * @arg @ref LL_DMA_CHANNEL_6
1980 * @arg @ref LL_DMA_CHANNEL_7
1981 * @retval None
1982 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1983 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1984 {
1985 SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE);
1986 }
1987
1988 /**
1989 * @brief Enable Transfer error interrupt.
1990 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
1991 * @param DMAx DMAx Instance
1992 * @param Channel This parameter can be one of the following values:
1993 * @arg @ref LL_DMA_CHANNEL_1
1994 * @arg @ref LL_DMA_CHANNEL_2
1995 * @arg @ref LL_DMA_CHANNEL_3
1996 * @arg @ref LL_DMA_CHANNEL_4
1997 * @arg @ref LL_DMA_CHANNEL_5
1998 * @arg @ref LL_DMA_CHANNEL_6
1999 * @arg @ref LL_DMA_CHANNEL_7
2000 * @retval None
2001 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2002 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2003 {
2004 SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE);
2005 }
2006
2007 /**
2008 * @brief Disable Transfer complete interrupt.
2009 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
2010 * @param DMAx DMAx Instance
2011 * @param Channel This parameter can be one of the following values:
2012 * @arg @ref LL_DMA_CHANNEL_1
2013 * @arg @ref LL_DMA_CHANNEL_2
2014 * @arg @ref LL_DMA_CHANNEL_3
2015 * @arg @ref LL_DMA_CHANNEL_4
2016 * @arg @ref LL_DMA_CHANNEL_5
2017 * @arg @ref LL_DMA_CHANNEL_6
2018 * @arg @ref LL_DMA_CHANNEL_7
2019 * @retval None
2020 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2021 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2022 {
2023 CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE);
2024 }
2025
2026 /**
2027 * @brief Disable Half transfer interrupt.
2028 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
2029 * @param DMAx DMAx Instance
2030 * @param Channel This parameter can be one of the following values:
2031 * @arg @ref LL_DMA_CHANNEL_1
2032 * @arg @ref LL_DMA_CHANNEL_2
2033 * @arg @ref LL_DMA_CHANNEL_3
2034 * @arg @ref LL_DMA_CHANNEL_4
2035 * @arg @ref LL_DMA_CHANNEL_5
2036 * @arg @ref LL_DMA_CHANNEL_6
2037 * @arg @ref LL_DMA_CHANNEL_7
2038 * @retval None
2039 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2040 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2041 {
2042 CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE);
2043 }
2044
2045 /**
2046 * @brief Disable Transfer error interrupt.
2047 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
2048 * @param DMAx DMAx Instance
2049 * @param Channel This parameter can be one of the following values:
2050 * @arg @ref LL_DMA_CHANNEL_1
2051 * @arg @ref LL_DMA_CHANNEL_2
2052 * @arg @ref LL_DMA_CHANNEL_3
2053 * @arg @ref LL_DMA_CHANNEL_4
2054 * @arg @ref LL_DMA_CHANNEL_5
2055 * @arg @ref LL_DMA_CHANNEL_6
2056 * @arg @ref LL_DMA_CHANNEL_7
2057 * @retval None
2058 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2059 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2060 {
2061 CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE);
2062 }
2063
2064 /**
2065 * @brief Check if Transfer complete Interrupt is enabled.
2066 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
2067 * @param DMAx DMAx Instance
2068 * @param Channel This parameter can be one of the following values:
2069 * @arg @ref LL_DMA_CHANNEL_1
2070 * @arg @ref LL_DMA_CHANNEL_2
2071 * @arg @ref LL_DMA_CHANNEL_3
2072 * @arg @ref LL_DMA_CHANNEL_4
2073 * @arg @ref LL_DMA_CHANNEL_5
2074 * @arg @ref LL_DMA_CHANNEL_6
2075 * @arg @ref LL_DMA_CHANNEL_7
2076 * @retval State of bit (1 or 0).
2077 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2078 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2079 {
2080 return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
2081 DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
2082 }
2083
2084 /**
2085 * @brief Check if Half transfer Interrupt is enabled.
2086 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
2087 * @param DMAx DMAx Instance
2088 * @param Channel This parameter can be one of the following values:
2089 * @arg @ref LL_DMA_CHANNEL_1
2090 * @arg @ref LL_DMA_CHANNEL_2
2091 * @arg @ref LL_DMA_CHANNEL_3
2092 * @arg @ref LL_DMA_CHANNEL_4
2093 * @arg @ref LL_DMA_CHANNEL_5
2094 * @arg @ref LL_DMA_CHANNEL_6
2095 * @arg @ref LL_DMA_CHANNEL_7
2096 * @retval State of bit (1 or 0).
2097 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2098 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2099 {
2100 return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
2101 DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
2102 }
2103
2104 /**
2105 * @brief Check if Transfer error Interrupt is enabled.
2106 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
2107 * @param DMAx DMAx Instance
2108 * @param Channel This parameter can be one of the following values:
2109 * @arg @ref LL_DMA_CHANNEL_1
2110 * @arg @ref LL_DMA_CHANNEL_2
2111 * @arg @ref LL_DMA_CHANNEL_3
2112 * @arg @ref LL_DMA_CHANNEL_4
2113 * @arg @ref LL_DMA_CHANNEL_5
2114 * @arg @ref LL_DMA_CHANNEL_6
2115 * @arg @ref LL_DMA_CHANNEL_7
2116 * @retval State of bit (1 or 0).
2117 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2118 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2119 {
2120 return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
2121 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
2122 }
2123
2124 /**
2125 * @}
2126 */
2127
2128 #if defined(USE_FULL_LL_DRIVER)
2129 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2130 * @{
2131 */
2132 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
2133 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
2134 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2135
2136 /**
2137 * @}
2138 */
2139 #endif /* USE_FULL_LL_DRIVER */
2140
2141 /**
2142 * @}
2143 */
2144
2145 /**
2146 * @}
2147 */
2148
2149 #endif /* DMA1 || DMA2 */
2150
2151 /**
2152 * @}
2153 */
2154
2155 #ifdef __cplusplus
2156 }
2157 #endif
2158
2159 #endif /* STM32WBxx_LL_DMA_H */
2160
