1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_tsc.h 4 * @author MCD Application Team 5 * @brief Header file of TSC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBxx_HAL_TSC_H 21 #define STM32WBxx_HAL_TSC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbxx_hal_def.h" 29 30 #if defined(TSC) 31 32 /** @addtogroup STM32WBxx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup TSC 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup TSC_Exported_Types TSC Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief TSC state structure definition 47 */ 48 typedef enum 49 { 50 HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */ 51 HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */ 52 HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */ 53 HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */ 54 } HAL_TSC_StateTypeDef; 55 56 /** 57 * @brief TSC group status structure definition 58 */ 59 typedef enum 60 { 61 TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */ 62 TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */ 63 } TSC_GroupStatusTypeDef; 64 65 /** 66 * @brief TSC init structure definition 67 */ 68 typedef struct 69 { 70 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length 71 This parameter can be a value of @ref TSC_CTPulseHL_Config */ 72 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length 73 This parameter can be a value of @ref TSC_CTPulseLL_Config */ 74 FunctionalState SpreadSpectrum; /*!< Spread spectrum activation 75 This parameter can be set to ENABLE or DISABLE. */ 76 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation 77 This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ 78 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler 79 This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */ 80 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler 81 This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */ 82 uint32_t MaxCountValue; /*!< Max count value 83 This parameter can be a value of @ref TSC_MaxCount_Value */ 84 uint32_t IODefaultMode; /*!< IO default mode 85 This parameter can be a value of @ref TSC_IO_Default_Mode */ 86 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity 87 This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */ 88 uint32_t AcquisitionMode; /*!< Acquisition mode 89 This parameter can be a value of @ref TSC_Acquisition_Mode */ 90 FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation 91 This parameter can be set to ENABLE or DISABLE. */ 92 uint32_t ChannelIOs; /*!< Channel IOs mask */ 93 uint32_t ShieldIOs; /*!< Shield IOs mask */ 94 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 95 } TSC_InitTypeDef; 96 97 /** 98 * @brief TSC IOs configuration structure definition 99 */ 100 typedef struct 101 { 102 uint32_t ChannelIOs; /*!< Channel IOs mask */ 103 uint32_t ShieldIOs; /*!< Shield IOs mask */ 104 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 105 } TSC_IOConfigTypeDef; 106 107 /** 108 * @brief TSC handle Structure definition 109 */ 110 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 111 typedef struct __TSC_HandleTypeDef 112 #else 113 typedef struct 114 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 115 { 116 TSC_TypeDef *Instance; /*!< Register base address */ 117 TSC_InitTypeDef Init; /*!< Initialization parameters */ 118 __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ 119 HAL_LockTypeDef Lock; /*!< Lock feature */ 120 __IO uint32_t ErrorCode; /*!< TSC Error code */ 121 122 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 123 void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */ 124 void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */ 125 126 void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */ 127 void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */ 128 129 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 130 } TSC_HandleTypeDef; 131 132 enum 133 { 134 TSC_GROUP1_IDX = 0x00UL, 135 TSC_GROUP2_IDX, 136 TSC_GROUP3_IDX, 137 TSC_GROUP4_IDX, 138 TSC_GROUP5_IDX, 139 TSC_GROUP6_IDX, 140 TSC_GROUP7_IDX, 141 TSC_NB_OF_GROUPS 142 }; 143 144 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 145 /** 146 * @brief HAL TSC Callback ID enumeration definition 147 */ 148 typedef enum 149 { 150 HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */ 151 HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */ 152 153 HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */ 154 HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */ 155 156 } HAL_TSC_CallbackIDTypeDef; 157 158 /** 159 * @brief HAL TSC Callback pointer definition 160 */ 161 typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */ 162 163 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 164 165 /** 166 * @} 167 */ 168 169 /* Exported constants --------------------------------------------------------*/ 170 /** @defgroup TSC_Exported_Constants TSC Exported Constants 171 * @{ 172 */ 173 174 /** @defgroup TSC_Error_Code_definition TSC Error Code definition 175 * @brief TSC Error Code definition 176 * @{ 177 */ 178 #define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */ 179 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 180 #define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */ 181 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 182 /** 183 * @} 184 */ 185 186 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length 187 * @{ 188 */ 189 #define TSC_CTPH_1CYCLE 0x00000000UL 190 /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ 191 #define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 192 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ 193 #define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 194 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ 195 #define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 196 /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ 197 #define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 198 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */ 199 #define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 200 /*!< Charge transfer pulse high during 6 cycles (PGCLK) */ 201 #define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 202 /*!< Charge transfer pulse high during 7 cycles (PGCLK) */ 203 #define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 204 /*!< Charge transfer pulse high during 8 cycles (PGCLK) */ 205 #define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 206 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */ 207 #define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) 208 /*!< Charge transfer pulse high during 10 cycles (PGCLK) */ 209 #define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) 210 /*!< Charge transfer pulse high during 11 cycles (PGCLK) */ 211 #define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 212 /*!< Charge transfer pulse high during 12 cycles (PGCLK) */ 213 #define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) 214 /*!< Charge transfer pulse high during 13 cycles (PGCLK) */ 215 #define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 216 /*!< Charge transfer pulse high during 14 cycles (PGCLK) */ 217 #define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 218 /*!< Charge transfer pulse high during 15 cycles (PGCLK) */ 219 #define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 220 /*!< Charge transfer pulse high during 16 cycles (PGCLK) */ 221 /** 222 * @} 223 */ 224 225 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length 226 * @{ 227 */ 228 #define TSC_CTPL_1CYCLE 0x00000000UL 229 /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ 230 #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 231 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ 232 #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 233 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ 234 #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 235 /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ 236 #define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 237 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */ 238 #define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 239 /*!< Charge transfer pulse low during 6 cycles (PGCLK) */ 240 #define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 241 /*!< Charge transfer pulse low during 7 cycles (PGCLK) */ 242 #define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 243 /*!< Charge transfer pulse low during 8 cycles (PGCLK) */ 244 #define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 245 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */ 246 #define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) 247 /*!< Charge transfer pulse low during 10 cycles (PGCLK) */ 248 #define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) 249 /*!< Charge transfer pulse low during 11 cycles (PGCLK) */ 250 #define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 251 /*!< Charge transfer pulse low during 12 cycles (PGCLK) */ 252 #define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) 253 /*!< Charge transfer pulse low during 13 cycles (PGCLK) */ 254 #define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 255 /*!< Charge transfer pulse low during 14 cycles (PGCLK) */ 256 #define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 257 /*!< Charge transfer pulse low during 15 cycles (PGCLK) */ 258 #define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 259 /*!< Charge transfer pulse low during 16 cycles (PGCLK) */ 260 /** 261 * @} 262 */ 263 264 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler 265 * @{ 266 */ 267 #define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */ 268 #define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ 269 /** 270 * @} 271 */ 272 273 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler 274 * @{ 275 */ 276 #define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */ 277 #define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ 278 #define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ 279 #define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ 280 #define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */ 281 #define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */ 282 #define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */ 283 #define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */ 284 /** 285 * @} 286 */ 287 288 /** @defgroup TSC_MaxCount_Value Max Count Value 289 * @{ 290 */ 291 #define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */ 292 #define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ 293 #define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ 294 #define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ 295 #define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */ 296 #define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */ 297 #define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */ 298 /** 299 * @} 300 */ 301 302 /** @defgroup TSC_IO_Default_Mode IO Default Mode 303 * @{ 304 */ 305 #define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */ 306 #define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ 307 /** 308 * @} 309 */ 310 311 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity 312 * @{ 313 */ 314 #define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */ 315 #define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ 316 /** 317 * @} 318 */ 319 320 /** @defgroup TSC_Acquisition_Mode Acquisition Mode 321 * @{ 322 */ 323 #define TSC_ACQ_MODE_NORMAL 0x00000000UL 324 /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ 325 #define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM 326 /*!< Synchronized acquisition mode (acquisition starts if START bit is set and 327 when the selected signal is detected on the SYNC input pin) */ 328 /** 329 * @} 330 */ 331 332 /** @defgroup TSC_interrupts_definition Interrupts definition 333 * @{ 334 */ 335 #define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */ 336 #define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */ 337 /** 338 * @} 339 */ 340 341 /** @defgroup TSC_flags_definition Flags definition 342 * @{ 343 */ 344 #define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */ 345 #define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */ 346 /** 347 * @} 348 */ 349 350 /** @defgroup TSC_Group_definition Group definition 351 * @{ 352 */ 353 #define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX) 354 #define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX) 355 #define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX) 356 #define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX) 357 #define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX) 358 #define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX) 359 #define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) 360 361 #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ 362 #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ 363 #define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ 364 #define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ 365 366 #define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ 367 #define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ 368 #define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ 369 #define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ 370 371 #define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ 372 #define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ 373 #define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ 374 #define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ 375 376 #define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */ 377 #define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */ 378 #define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */ 379 #define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */ 380 381 #define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */ 382 #define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */ 383 #define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */ 384 #define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ 385 386 #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ 387 #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ 388 #define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ 389 #define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ 390 391 #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ 392 #define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ 393 #define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ 394 #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ 395 /** 396 * @} 397 */ 398 399 /** 400 * @} 401 */ 402 403 /* Exported macros -----------------------------------------------------------*/ 404 405 /** @defgroup TSC_Exported_Macros TSC Exported Macros 406 * @{ 407 */ 408 409 /** @brief Reset TSC handle state. 410 * @param __HANDLE__ TSC handle 411 * @retval None 412 */ 413 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 414 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 415 (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ 416 (__HANDLE__)->MspInitCallback = NULL; \ 417 (__HANDLE__)->MspDeInitCallback = NULL; \ 418 } while(0) 419 #else 420 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) 421 #endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */ 422 423 /** 424 * @brief Enable the TSC peripheral. 425 * @param __HANDLE__ TSC handle 426 * @retval None 427 */ 428 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) 429 430 /** 431 * @brief Disable the TSC peripheral. 432 * @param __HANDLE__ TSC handle 433 * @retval None 434 */ 435 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE)) 436 437 /** 438 * @brief Start acquisition. 439 * @param __HANDLE__ TSC handle 440 * @retval None 441 */ 442 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) 443 444 /** 445 * @brief Stop acquisition. 446 * @param __HANDLE__ TSC handle 447 * @retval None 448 */ 449 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START)) 450 451 /** 452 * @brief Set IO default mode to output push-pull low. 453 * @param __HANDLE__ TSC handle 454 * @retval None 455 */ 456 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF)) 457 458 /** 459 * @brief Set IO default mode to input floating. 460 * @param __HANDLE__ TSC handle 461 * @retval None 462 */ 463 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) 464 465 /** 466 * @brief Set synchronization polarity to falling edge. 467 * @param __HANDLE__ TSC handle 468 * @retval None 469 */ 470 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL)) 471 472 /** 473 * @brief Set synchronization polarity to rising edge and high level. 474 * @param __HANDLE__ TSC handle 475 * @retval None 476 */ 477 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) 478 479 /** 480 * @brief Enable TSC interrupt. 481 * @param __HANDLE__ TSC handle 482 * @param __INTERRUPT__ TSC interrupt 483 * @retval None 484 */ 485 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 486 487 /** 488 * @brief Disable TSC interrupt. 489 * @param __HANDLE__ TSC handle 490 * @param __INTERRUPT__ TSC interrupt 491 * @retval None 492 */ 493 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 494 495 /** @brief Check whether the specified TSC interrupt source is enabled or not. 496 * @param __HANDLE__ TSC Handle 497 * @param __INTERRUPT__ TSC interrupt 498 * @retval SET or RESET 499 */ 500 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ 501 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\ 502 RESET) 503 504 /** 505 * @brief Check whether the specified TSC flag is set or not. 506 * @param __HANDLE__ TSC handle 507 * @param __FLAG__ TSC flag 508 * @retval SET or RESET 509 */ 510 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\ 511 & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 512 513 /** 514 * @brief Clear the TSC's pending flag. 515 * @param __HANDLE__ TSC handle 516 * @param __FLAG__ TSC flag 517 * @retval None 518 */ 519 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 520 521 /** 522 * @brief Enable schmitt trigger hysteresis on a group of IOs. 523 * @param __HANDLE__ TSC handle 524 * @param __GX_IOY_MASK__ IOs mask 525 * @retval None 526 */ 527 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) 528 529 /** 530 * @brief Disable schmitt trigger hysteresis on a group of IOs. 531 * @param __HANDLE__ TSC handle 532 * @param __GX_IOY_MASK__ IOs mask 533 * @retval None 534 */ 535 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\ 536 &= (~(__GX_IOY_MASK__))) 537 538 /** 539 * @brief Open analog switch on a group of IOs. 540 * @param __HANDLE__ TSC handle 541 * @param __GX_IOY_MASK__ IOs mask 542 * @retval None 543 */ 544 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\ 545 &= (~(__GX_IOY_MASK__))) 546 547 /** 548 * @brief Close analog switch on a group of IOs. 549 * @param __HANDLE__ TSC handle 550 * @param __GX_IOY_MASK__ IOs mask 551 * @retval None 552 */ 553 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) 554 555 /** 556 * @brief Enable a group of IOs in channel mode. 557 * @param __HANDLE__ TSC handle 558 * @param __GX_IOY_MASK__ IOs mask 559 * @retval None 560 */ 561 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) 562 563 /** 564 * @brief Disable a group of channel IOs. 565 * @param __HANDLE__ TSC handle 566 * @param __GX_IOY_MASK__ IOs mask 567 * @retval None 568 */ 569 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\ 570 &= (~(__GX_IOY_MASK__))) 571 572 /** 573 * @brief Enable a group of IOs in sampling mode. 574 * @param __HANDLE__ TSC handle 575 * @param __GX_IOY_MASK__ IOs mask 576 * @retval None 577 */ 578 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) 579 580 /** 581 * @brief Disable a group of sampling IOs. 582 * @param __HANDLE__ TSC handle 583 * @param __GX_IOY_MASK__ IOs mask 584 * @retval None 585 */ 586 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__))) 587 588 /** 589 * @brief Enable acquisition groups. 590 * @param __HANDLE__ TSC handle 591 * @param __GX_MASK__ Groups mask 592 * @retval None 593 */ 594 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) 595 596 /** 597 * @brief Disable acquisition groups. 598 * @param __HANDLE__ TSC handle 599 * @param __GX_MASK__ Groups mask 600 * @retval None 601 */ 602 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__))) 603 604 /** @brief Gets acquisition group status. 605 * @param __HANDLE__ TSC Handle 606 * @param __GX_INDEX__ Group index 607 * @retval SET or RESET 608 */ 609 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ 610 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \ 611 (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) 612 613 /** 614 * @} 615 */ 616 617 /* Private macros ------------------------------------------------------------*/ 618 619 /** @defgroup TSC_Private_Macros TSC Private Macros 620 * @{ 621 */ 622 623 #define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ 624 ((__VALUE__) == TSC_CTPH_2CYCLES) || \ 625 ((__VALUE__) == TSC_CTPH_3CYCLES) || \ 626 ((__VALUE__) == TSC_CTPH_4CYCLES) || \ 627 ((__VALUE__) == TSC_CTPH_5CYCLES) || \ 628 ((__VALUE__) == TSC_CTPH_6CYCLES) || \ 629 ((__VALUE__) == TSC_CTPH_7CYCLES) || \ 630 ((__VALUE__) == TSC_CTPH_8CYCLES) || \ 631 ((__VALUE__) == TSC_CTPH_9CYCLES) || \ 632 ((__VALUE__) == TSC_CTPH_10CYCLES) || \ 633 ((__VALUE__) == TSC_CTPH_11CYCLES) || \ 634 ((__VALUE__) == TSC_CTPH_12CYCLES) || \ 635 ((__VALUE__) == TSC_CTPH_13CYCLES) || \ 636 ((__VALUE__) == TSC_CTPH_14CYCLES) || \ 637 ((__VALUE__) == TSC_CTPH_15CYCLES) || \ 638 ((__VALUE__) == TSC_CTPH_16CYCLES)) 639 640 #define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ 641 ((__VALUE__) == TSC_CTPL_2CYCLES) || \ 642 ((__VALUE__) == TSC_CTPL_3CYCLES) || \ 643 ((__VALUE__) == TSC_CTPL_4CYCLES) || \ 644 ((__VALUE__) == TSC_CTPL_5CYCLES) || \ 645 ((__VALUE__) == TSC_CTPL_6CYCLES) || \ 646 ((__VALUE__) == TSC_CTPL_7CYCLES) || \ 647 ((__VALUE__) == TSC_CTPL_8CYCLES) || \ 648 ((__VALUE__) == TSC_CTPL_9CYCLES) || \ 649 ((__VALUE__) == TSC_CTPL_10CYCLES) || \ 650 ((__VALUE__) == TSC_CTPL_11CYCLES) || \ 651 ((__VALUE__) == TSC_CTPL_12CYCLES) || \ 652 ((__VALUE__) == TSC_CTPL_13CYCLES) || \ 653 ((__VALUE__) == TSC_CTPL_14CYCLES) || \ 654 ((__VALUE__) == TSC_CTPL_15CYCLES) || \ 655 ((__VALUE__) == TSC_CTPL_16CYCLES)) 656 657 #define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 658 || ((FunctionalState)(__VALUE__) == ENABLE)) 659 660 #define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL))) 661 662 #define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) 663 664 #define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ 665 ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ 666 ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ 667 ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ 668 ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ 669 ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ 670 ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ 671 ((__VALUE__) == TSC_PG_PRESC_DIV128)) 672 673 #define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \ 674 (((__CTPL__) == TSC_CTPL_1CYCLE) || \ 675 ((__CTPL__) > TSC_CTPL_2CYCLES))) || \ 676 (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \ 677 ((__CTPL__) > TSC_CTPL_1CYCLE)) || \ 678 (((__PGPSC__) > TSC_PG_PRESC_DIV2) && \ 679 (((__CTPL__) == TSC_CTPL_1CYCLE) || \ 680 ((__CTPL__) > TSC_CTPL_1CYCLE)))) 681 682 #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ 683 ((__VALUE__) == TSC_MCV_511) || \ 684 ((__VALUE__) == TSC_MCV_1023) || \ 685 ((__VALUE__) == TSC_MCV_2047) || \ 686 ((__VALUE__) == TSC_MCV_4095) || \ 687 ((__VALUE__) == TSC_MCV_8191) || \ 688 ((__VALUE__) == TSC_MCV_16383)) 689 690 #define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) 691 692 #define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\ 693 || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) 694 695 #define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) 696 697 #define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 698 || ((FunctionalState)(__VALUE__) == ENABLE)) 699 700 #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\ 701 || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) 702 703 #define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\ 704 (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ 705 (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ 706 (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ 707 (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ 708 (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ 709 (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ 710 (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ 711 (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ 712 (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ 713 (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ 714 (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ 715 (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ 716 (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ 717 (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ 718 (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ 719 (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ 720 (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ 721 (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ 722 (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ 723 (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ 724 (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ 725 (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ 726 (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ 727 (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ 728 (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ 729 (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ 730 (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ 731 (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4)) 732 /** 733 * @} 734 */ 735 736 /* Exported functions --------------------------------------------------------*/ 737 /** @addtogroup TSC_Exported_Functions 738 * @{ 739 */ 740 741 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions 742 * @{ 743 */ 744 /* Initialization and de-initialization functions *****************************/ 745 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc); 746 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); 747 void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); 748 void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); 749 750 /* Callbacks Register/UnRegister functions ***********************************/ 751 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 752 HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, 753 pTSC_CallbackTypeDef pCallback); 754 HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID); 755 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 756 /** 757 * @} 758 */ 759 760 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions 761 * @{ 762 */ 763 /* IO operation functions *****************************************************/ 764 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc); 765 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); 766 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); 767 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); 768 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); 769 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index); 770 uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index); 771 /** 772 * @} 773 */ 774 775 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions 776 * @{ 777 */ 778 /* Peripheral Control functions ***********************************************/ 779 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config); 780 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice); 781 /** 782 * @} 783 */ 784 785 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions 786 * @{ 787 */ 788 /* Peripheral State and Error functions ***************************************/ 789 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); 790 /** 791 * @} 792 */ 793 794 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 795 * @{ 796 */ 797 /******* TSC IRQHandler and Callbacks used in Interrupt mode */ 798 void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); 799 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); 800 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); 801 /** 802 * @} 803 */ 804 805 /** 806 * @} 807 */ 808 809 /** 810 * @} 811 */ 812 813 /** 814 * @} 815 */ 816 #endif /* TSC */ 817 818 #ifdef __cplusplus 819 } 820 #endif 821 822 #endif /* STM32WBxx_HAL_TSC_H */ 823
