1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBxx_HAL_RCC_EX_H 21 #define STM32WBxx_HAL_RCC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbxx_hal_def.h" 29 #include "stm32wbxx_ll_crs.h" 30 #include "stm32wbxx_ll_exti.h" 31 #include "stm32wbxx_ll_pwr.h" 32 33 /** @addtogroup STM32WBxx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup RCCEx 38 * @{ 39 */ 40 /* Private constants ---------------------------------------------------------*/ 41 /** @addtogroup RCC_Private_Constants 42 * @{ 43 */ 44 /* CRS IT Error Mask */ 45 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF |\ 46 RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 47 48 /* CRS Flag Error Mask */ 49 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF |\ 50 RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) 51 52 /* RNG closk selection CLK48 clock mask */ 53 #define CLK48_MASK 0x10000000U 54 55 /* Define used for IS_RCC_* macros below */ 56 #if defined(LPUART1) && defined(I2C3) && defined(SAI1) && defined(USB) && defined(RCC_SMPS_SUPPORT) 57 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | \ 58 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 59 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_RNG | \ 60 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RFWAKEUP | \ 61 RCC_PERIPHCLK_SMPS) 62 #elif defined(LPUART1) 63 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | \ 64 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_RNG | \ 65 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RFWAKEUP) 66 #else 67 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_LPTIM1 | \ 68 RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | \ 69 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RFWAKEUP) 70 #endif /* LPUART1 */ 71 72 /** 73 * @} 74 */ 75 76 /* Private macros ------------------------------------------------------------*/ 77 /** @addtogroup RCCEx_Private_Macros 78 * @{ 79 */ 80 #if defined(RCC_LSCO3_SUPPORT) 81 #define IS_RCC_LSCO(__LSCOX__) (((__LSCOX__) == RCC_LSCO1) || \ 82 ((__LSCOX__) == RCC_LSCO2) || \ 83 ((__LSCOX__) == RCC_LSCO3)) 84 #else 85 #define IS_RCC_LSCO(__LSCOX__) (((__LSCOX__) == RCC_LSCO1) || \ 86 ((__LSCOX__) == RCC_LSCO2)) 87 #endif /* RCC_LSCO3_SUPPORT */ 88 89 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 90 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 91 92 #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \ 93 (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u)) 94 95 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 96 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 97 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 98 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 99 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 100 101 #if defined(LPUART1) 102 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 103 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ 104 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 105 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 106 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) 107 #endif /* LPUART1 */ 108 109 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 110 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 111 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ 112 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 113 114 #if defined(I2C3) 115 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 116 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ 117 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ 118 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 119 #endif /* I2C3 */ 120 121 #if defined(SAI1) 122 #define IS_RCC_SAI1CLK(__SOURCE__) \ 123 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 124 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 125 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI) || \ 126 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) 127 #endif /* SAI1 */ 128 129 #define IS_RCC_LPTIM1CLK(__SOURCE__) \ 130 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 131 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 132 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ 133 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) 134 135 #define IS_RCC_LPTIM2CLK(__SOURCE__) \ 136 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ 137 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 138 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ 139 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) 140 141 #if defined(RCC_HSI48_SUPPORT) 142 #if defined(SAI1) 143 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 144 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 145 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 146 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI) || \ 147 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ 148 ((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48) || \ 149 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \ 150 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE)) 151 #else /* SAI1 */ 152 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 153 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 154 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 155 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI) || \ 156 ((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48) || \ 157 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \ 158 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE)) 159 #endif /* SAI1 */ 160 #else /* RCC_HSI48_SUPPORT */ 161 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 162 (((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 163 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI) || \ 164 ((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48) || \ 165 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \ 166 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE)) 167 #endif /* RCC_HSI48_SUPPORT */ 168 169 #if defined(USB) 170 #if defined(SAI1) 171 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 172 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 173 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ 174 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 175 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 176 #else 177 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 178 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 179 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 180 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 181 #endif /* SAI1 */ 182 #endif /* USB */ 183 184 #if defined(STM32WB55xx) || defined (STM32WB5Mxx) || defined(STM32WB35xx) 185 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 186 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 187 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ 188 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ 189 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 190 #elif defined(STM32WB15xx) || defined(STM32WB1Mxx) 191 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 192 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 193 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ 194 ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI) || \ 195 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 196 #else 197 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 198 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 199 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ 200 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 201 #endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx */ 202 203 #define IS_RCC_RFWKPCLKSOURCE(__SOURCE__) \ 204 (((__SOURCE__) == RCC_RFWKPCLKSOURCE_NONE) || \ 205 ((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSE) || \ 206 ((__SOURCE__) == RCC_RFWKPCLKSOURCE_HSE_DIV1024)) 207 208 #if defined(RCC_SMPS_SUPPORT) 209 #define IS_RCC_SMPSCLKDIV(__DIV__) \ 210 (((__DIV__) == RCC_SMPSCLKDIV_RANGE0) || \ 211 ((__DIV__) == RCC_SMPSCLKDIV_RANGE1) || \ 212 ((__DIV__) == RCC_SMPSCLKDIV_RANGE2) || \ 213 ((__DIV__) == RCC_SMPSCLKDIV_RANGE3)) 214 215 #define IS_RCC_SMPSCLKSOURCE(__SOURCE__) \ 216 (((__SOURCE__) == RCC_SMPSCLKSOURCE_HSI) || \ 217 ((__SOURCE__) == RCC_SMPSCLKSOURCE_MSI) || \ 218 ((__SOURCE__) == RCC_SMPSCLKSOURCE_HSE)) 219 #endif /* RCC_SMPS_SUPPORT */ 220 221 222 #if defined(SAI1) 223 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U)) 224 225 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32)) 226 227 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8)) 228 229 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) 230 #endif /* SAI1 */ 231 232 #define IS_RCC_TRIMOSC(__VALUE__) ((__VALUE__) == RCC_OSCILLATORTYPE_LSI2) 233 234 #if defined(CRS) 235 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 236 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 237 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 238 239 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 240 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 241 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 242 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 243 244 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 245 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 246 247 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 248 249 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 250 251 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) 252 253 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 254 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 255 #endif /* CRS */ 256 /** 257 * @} 258 */ 259 260 /* Exported types ------------------------------------------------------------*/ 261 262 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 263 * @{ 264 */ 265 266 #if defined(SAI1) 267 /** 268 * @brief PLLSAI1 Clock structure definition 269 */ 270 typedef struct 271 { 272 273 uint32_t PLLN; /*!< PLLN: specifies the multiplication factor for PLLSAI1 VCO output clock. 274 This parameter must be a number between Min_Data=6 and Max_Data=127. */ 275 276 uint32_t PLLP; /*!< PLLP: specifies the division factor for SAI clock. 277 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 278 279 uint32_t PLLQ; /*!< PLLQ: specifies the division factor for USB/RNG clock. 280 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 281 282 uint32_t PLLR; /*!< PLLR: specifies the division factor for ADC clock. 283 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 284 285 uint32_t PLLSAI1ClockOut; /*!< PLLSAI1ClockOut: specifies PLLSAI1 output clock to be enabled. 286 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ 287 } RCC_PLLSAI1InitTypeDef; 288 #endif /* SAI1 */ 289 290 /** 291 * @brief RCC extended clocks structure definition 292 */ 293 typedef struct 294 { 295 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 296 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 297 298 #if defined(SAI1) 299 RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. 300 This parameter will be used only when PLLSAI1 is selected as Clock 301 Source for SAI, USB/RNG or ADC */ 302 #endif /* SAI1 */ 303 304 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 305 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 306 307 #if defined(LPUART1) 308 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 309 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 310 #endif /* LPUART1 */ 311 312 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 313 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 314 315 #if defined(I2C3) 316 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 317 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 318 #endif /* I2C3 */ 319 320 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 321 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 322 323 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 324 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 325 326 #if defined(SAI1) 327 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 328 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 329 #endif /* SAI1 */ 330 331 #if defined(USB) 332 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG). 333 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 334 #endif /* USB */ 335 336 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB). 337 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 338 339 340 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. 341 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 342 343 uint32_t RTCClockSelection; /*!< Specifies RTC clock source (also used for LCD). 344 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 345 346 uint32_t RFWakeUpClockSelection; /*!< Specifies RF Wake-up clock source. 347 This parameter can be a value of @ref RCCEx_RFWKP_Clock_Source */ 348 349 #if defined(RCC_SMPS_SUPPORT) 350 uint32_t SmpsClockSelection; /*!< Specifies SMPS clock source. 351 This parameter can be a value of @ref RCCEx_SMPS_Clock_Source */ 352 353 uint32_t SmpsDivSelection; /*!< Specifies SMPS clock division factor. 354 This parameter can be a value of @ref RCCEx_SMPS_Clock_Divider */ 355 #endif /* RCC_SMPS_SUPPORT */ 356 357 } RCC_PeriphCLKInitTypeDef; 358 359 360 #if defined(CRS) 361 /** 362 * @brief RCC_CRS Init structure definition 363 */ 364 typedef struct 365 { 366 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 367 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 368 369 uint32_t Source; /*!< Specifies the SYNC signal source. 370 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 371 372 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 373 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 374 375 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 376 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 377 This parameter must be a number between Min_Data=0 and Max_Data=0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 378 379 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 380 This parameter must be a number between Min_Data=0 and Max_Data=0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 381 382 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 383 This parameter must be a number between Min_Data=0 and Max_Data=0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 384 385 } RCC_CRSInitTypeDef; 386 387 /** 388 * @brief RCC_CRS Synchronization structure definition 389 */ 390 typedef struct 391 { 392 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 393 This parameter must be a number between Min_Data=0 and Max_Data=0xFFFF */ 394 395 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 396 This parameter must be a number between Min_Data=0 and Max_Data=0x3F */ 397 398 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 399 value latched in the time of the last SYNC event. 400 This parameter must be a number between Min_Data=0 and Max_Data=0xFFFF */ 401 402 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 403 frequency error counter latched in the time of the last SYNC event. 404 It shows whether the actual frequency is below or above the target. 405 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 406 407 } RCC_CRSSynchroInfoTypeDef; 408 #endif /* CRS */ 409 410 /** 411 * @} 412 */ 413 414 /* Exported constants --------------------------------------------------------*/ 415 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 416 * @{ 417 */ 418 419 /** @defgroup RCC_LSCO_Index LSCO Index 420 * @{ 421 */ 422 #define RCC_LSCO1 0x00000000U /*!< LSCO1 index */ 423 #define RCC_LSCO2 0x00000001U /*!< LSCO2 index */ 424 #if defined(RCC_LSCO3_SUPPORT) 425 #define RCC_LSCO3 0x00000002U /*!< LSCO3 index */ 426 #endif /* RCC_LSCO3_SUPPORT */ 427 /** 428 * @} 429 */ 430 431 432 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 433 * @{ 434 */ 435 #define RCC_LSCOSOURCE_LSI LL_RCC_LSCO_CLKSOURCE_LSI /*!< LSI selection for low speed clock output */ 436 #define RCC_LSCOSOURCE_LSE LL_RCC_LSCO_CLKSOURCE_LSE /*!< LSE selection for low speed clock output */ 437 /** 438 * @} 439 */ 440 441 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 442 * @{ 443 */ 444 #define RCC_PERIPHCLK_USART1 0x00000001U /*!< USART1 Peripheral Clock Selection */ 445 #if defined(LPUART1) 446 #define RCC_PERIPHCLK_LPUART1 0x00000002U /*!< LPUART1 Peripheral Clock Selection */ 447 #endif /* LPUART1 */ 448 #define RCC_PERIPHCLK_I2C1 0x00000004U /*!< I2C1 Peripheral Clock Selection */ 449 #if defined(I2C3) 450 #define RCC_PERIPHCLK_I2C3 0x00000008U /*!< I2C3 Peripheral Clock Selection */ 451 #endif /* I2C3 */ 452 #define RCC_PERIPHCLK_LPTIM1 0x00000010U /*!< LPTIM1 Peripheral Clock Selection */ 453 #define RCC_PERIPHCLK_LPTIM2 0x00000020U /*!< LPTIM2 Peripheral Clock Selection */ 454 #if defined(SAI1) 455 #define RCC_PERIPHCLK_SAI1 0x00000040U /*!< SAI1 Peripheral Clock Selection */ 456 #endif /* SAI1 */ 457 #define RCC_PERIPHCLK_CLK48SEL 0x00000100U /*!< 48 MHz clock source selection */ 458 #if defined(USB) 459 #define RCC_PERIPHCLK_USB RCC_PERIPHCLK_CLK48SEL /*!< USB Peripheral Clock Selection */ 460 #endif /* USB */ 461 #define RCC_PERIPHCLK_RNG 0x00000200U /*!< RNG Peripheral Clock Selection */ 462 #define RCC_PERIPHCLK_ADC 0x00000400U /*!< ADC Peripheral Clock Selection */ 463 #define RCC_PERIPHCLK_RTC 0x00000800U /*!< RTC Peripheral Clock Selection */ 464 #define RCC_PERIPHCLK_RFWAKEUP 0x00001000U /*!< RF Wakeup Peripheral Clock Selection */ 465 #if defined(RCC_SMPS_SUPPORT) 466 #define RCC_PERIPHCLK_SMPS 0x00002000U /*!< SMPS Peripheral Clock Selection */ 467 #endif /* RCC_SMPS_SUPPORT */ 468 /** 469 * @} 470 */ 471 472 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 473 * @{ 474 */ 475 #define RCC_USART1CLKSOURCE_PCLK2 LL_RCC_USART1_CLKSOURCE_PCLK2 /*!< APB2 clock selected as USART 1 clock*/ 476 #define RCC_USART1CLKSOURCE_SYSCLK LL_RCC_USART1_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as USART 1 clock*/ 477 #define RCC_USART1CLKSOURCE_HSI LL_RCC_USART1_CLKSOURCE_HSI /*!< HSI clock selected as USART 1 clock*/ 478 #define RCC_USART1CLKSOURCE_LSE LL_RCC_USART1_CLKSOURCE_LSE /*!< LSE clock selected as USART 1 clock*/ 479 /** 480 * @} 481 */ 482 483 #if defined(LPUART1) 484 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 485 * @{ 486 */ 487 #define RCC_LPUART1CLKSOURCE_PCLK1 LL_RCC_LPUART1_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPUART 1 clock*/ 488 #define RCC_LPUART1CLKSOURCE_SYSCLK LL_RCC_LPUART1_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as LPUART 1 clock*/ 489 #define RCC_LPUART1CLKSOURCE_HSI LL_RCC_LPUART1_CLKSOURCE_HSI /*!< HSI clock selected as LPUART 1 clock*/ 490 #define RCC_LPUART1CLKSOURCE_LSE LL_RCC_LPUART1_CLKSOURCE_LSE /*!< LSE clock selected as LPUART 1 clock*/ 491 /** 492 * @} 493 */ 494 #endif /* LPUART1 */ 495 496 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 497 * @{ 498 */ 499 #define RCC_I2C1CLKSOURCE_PCLK1 LL_RCC_I2C1_CLKSOURCE_PCLK1 /*!< APB1 clock selected as I2C1 clock */ 500 #define RCC_I2C1CLKSOURCE_SYSCLK LL_RCC_I2C1_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as I2C1 clock */ 501 #define RCC_I2C1CLKSOURCE_HSI LL_RCC_I2C1_CLKSOURCE_HSI /*!< HSI clock selected as I2C1 clock */ 502 /** 503 * @} 504 */ 505 506 #if defined(I2C3) 507 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 508 * @{ 509 */ 510 #define RCC_I2C3CLKSOURCE_PCLK1 LL_RCC_I2C3_CLKSOURCE_PCLK1 /*!< APB1 clock selected as I2C3 clock */ 511 #define RCC_I2C3CLKSOURCE_SYSCLK LL_RCC_I2C3_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as I2C3 clock */ 512 #define RCC_I2C3CLKSOURCE_HSI LL_RCC_I2C3_CLKSOURCE_HSI /*!< HSI clock selected as I2C3 clock */ 513 /** 514 * @} 515 */ 516 #endif /* I2C3 */ 517 518 #if defined(SAI1) 519 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 520 * @{ 521 */ 522 #define RCC_SAI1CLKSOURCE_PLLSAI1 LL_RCC_SAI1_CLKSOURCE_PLLSAI1 /*!< PLLSAI "P" clock selected as SAI1 clock */ 523 #define RCC_SAI1CLKSOURCE_PLL LL_RCC_SAI1_CLKSOURCE_PLL /*!< PLL "P" clock selected as SAI1 clock */ 524 #define RCC_SAI1CLKSOURCE_HSI LL_RCC_SAI1_CLKSOURCE_HSI /*!< HSI clock selected as SAI1 clock */ 525 #define RCC_SAI1CLKSOURCE_PIN LL_RCC_SAI1_CLKSOURCE_PIN /*!< External PIN clock selected as SAI1 clock */ 526 /** 527 * @} 528 */ 529 #endif /* SAI1 */ 530 531 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 532 * @{ 533 */ 534 #define RCC_LPTIM1CLKSOURCE_PCLK1 LL_RCC_LPTIM1_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPTIM1 clock */ 535 #define RCC_LPTIM1CLKSOURCE_LSI LL_RCC_LPTIM1_CLKSOURCE_LSI /*!< LSI clock selected as LPTIM1 clock */ 536 #define RCC_LPTIM1CLKSOURCE_HSI LL_RCC_LPTIM1_CLKSOURCE_HSI /*!< HSI clock selected as LPTIM1 clock */ 537 #define RCC_LPTIM1CLKSOURCE_LSE LL_RCC_LPTIM1_CLKSOURCE_LSE /*!< LSE clock selected as LPTIM1 clock */ 538 /** 539 * @} 540 */ 541 542 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 543 * @{ 544 */ 545 #define RCC_LPTIM2CLKSOURCE_PCLK1 LL_RCC_LPTIM2_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPTIM2 clock */ 546 #define RCC_LPTIM2CLKSOURCE_LSI LL_RCC_LPTIM2_CLKSOURCE_LSI /*!< LSI clock selected as LPTIM2 clock */ 547 #define RCC_LPTIM2CLKSOURCE_HSI LL_RCC_LPTIM2_CLKSOURCE_HSI /*!< HSI clock selected as LPTIM2 clock */ 548 #define RCC_LPTIM2CLKSOURCE_LSE LL_RCC_LPTIM2_CLKSOURCE_LSE /*!< LSE clock selected as LPTIM2 clock */ 549 /** 550 * @} 551 */ 552 553 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source 554 * @{ 555 */ 556 #define RCC_RNGCLKSOURCE_HSI48 (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_HSI48) /*!< HSI48 clock divided by 3 selected as RNG clock */ 557 #define RCC_RNGCLKSOURCE_PLL (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_PLL) /*!< PLL "Q" clock divided by 3 selected as RNG clock */ 558 #define RCC_RNGCLKSOURCE_MSI (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_MSI) /*!< MSI clock divided by 3 selected as RNG clock */ 559 #if defined(SAI1) 560 #define RCC_RNGCLKSOURCE_PLLSAI1 (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_PLLSAI1) /*!< PLLSAI1 "Q" clock selected as RNG clock */ 561 #endif /* SAI1 */ 562 #define RCC_RNGCLKSOURCE_CLK48 LL_RCC_RNG_CLKSOURCE_CLK48 /*!< CLK48 divided by 3 selected as RNG Clock */ 563 #define RCC_RNGCLKSOURCE_LSI LL_RCC_RNG_CLKSOURCE_LSI /*!< LSI clock selected as RNG clock */ 564 #define RCC_RNGCLKSOURCE_LSE LL_RCC_RNG_CLKSOURCE_LSE /*!< LSE clock selected as RNG clock */ 565 /** 566 * @} 567 */ 568 569 #if defined(USB) 570 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source 571 * @{ 572 */ 573 #define RCC_USBCLKSOURCE_HSI48 LL_RCC_USB_CLKSOURCE_HSI48 /*!< HSI48 clock selected as USB clock */ 574 #if defined(SAI1) 575 #define RCC_USBCLKSOURCE_PLLSAI1 LL_RCC_USB_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "Q" clock selected as USB clock */ 576 #endif /* SAI1 */ 577 #define RCC_USBCLKSOURCE_PLL LL_RCC_USB_CLKSOURCE_PLL /*!< PLL "Q" clock selected as USB clock */ 578 #define RCC_USBCLKSOURCE_MSI LL_RCC_USB_CLKSOURCE_MSI /*!< MSI clock selected as USB clock */ 579 /** 580 * @} 581 */ 582 #endif /* USB */ 583 584 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source 585 * @{ 586 */ 587 588 #define RCC_ADCCLKSOURCE_NONE LL_RCC_ADC_CLKSOURCE_NONE /*!< None clock selected as ADC clock */ 589 #if defined(STM32WB55xx) || defined (STM32WB5Mxx) || defined(STM32WB35xx) 590 #define RCC_ADCCLKSOURCE_PLLSAI1 LL_RCC_ADC_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "R" clock selected as ADC clock */ 591 #elif defined (STM32WB15xx) || defined(STM32WB1Mxx) 592 #define RCC_ADCCLKSOURCE_HSI LL_RCC_ADC_CLKSOURCE_HSI /*!< HSI clock selected as ADC clock */ 593 #endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx */ 594 #define RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL /*!< PLL "P" clock selected as ADC clock */ 595 #define RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as ADC clock */ 596 597 /** 598 * @} 599 */ 600 601 /** @defgroup RCCEx_HCLK5_Clock_Source HCLK RF Clock Source 602 * @{ 603 */ 604 605 #define RCC_HCLK5SOURCE_HSI 0x00000001U /*!< HSI clock not divided selected as Radio Domain clock */ 606 #define RCC_HCLK5SOURCE_HSE 0x00000002U /*!< HSE clock divided by 2 selected as Radio Domain clock */ 607 608 /** 609 * @} 610 */ 611 612 /** @defgroup RCCEx_RFWKP_Clock_Source RF WKP Clock Source 613 * @{ 614 */ 615 616 #define RCC_RFWKPCLKSOURCE_NONE LL_RCC_RFWKP_CLKSOURCE_NONE /*!< None clock selected as RF system wakeup clock */ 617 #define RCC_RFWKPCLKSOURCE_LSE LL_RCC_RFWKP_CLKSOURCE_LSE /*!< LSE clock selected as RF system wakeup clock */ 618 #if defined(STM32WB15xx) || defined(STM32WB10xx) 619 #define RCC_RFWKPCLKSOURCE_LSI LL_RCC_RFWKP_CLKSOURCE_LSI /*!< LSI clock selected as RF system wakeup clock */ 620 #endif /* STM32WB15xx || STM32WB10xx */ 621 #define RCC_RFWKPCLKSOURCE_HSE_DIV1024 LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 /*!< HSE clock divided by 1024 selected as RF system wakeup clock */ 622 623 /** 624 * @} 625 */ 626 627 628 #if defined(RCC_SMPS_SUPPORT) 629 /** @defgroup RCCEx_SMPS_Clock_Source SMPS Clock Source 630 * @{ 631 */ 632 #define RCC_SMPSCLKSOURCE_HSI LL_RCC_SMPS_CLKSOURCE_HSI /*!< HSI selection as smps clock */ 633 #define RCC_SMPSCLKSOURCE_MSI LL_RCC_SMPS_CLKSOURCE_MSI /*!< MSI selection as smps clock */ 634 #define RCC_SMPSCLKSOURCE_HSE LL_RCC_SMPS_CLKSOURCE_HSE /*!< HSE selection as smps clock */ 635 /** 636 * @} 637 */ 638 639 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 640 * @{ 641 */ 642 #define RCC_SMPSCLKSOURCE_STATUS_HSI LL_RCC_SMPS_CLKSOURCE_STATUS_HSI /*!< HSI selection as smps clock */ 643 #define RCC_SMPSCLKSOURCE_STATUS_MSI LL_RCC_SMPS_CLKSOURCE_STATUS_MSI /*!< MSI selection as smps clock */ 644 #define RCC_SMPSCLKSOURCE_STATUS_HSE LL_RCC_SMPS_CLKSOURCE_STATUS_HSE /*!< HSE selection as smps clock */ 645 /** 646 * @} 647 */ 648 649 /** @defgroup RCCEx_SMPS_Clock_Divider SMPS Clock Division Factor 650 * @{ 651 */ 652 #define RCC_SMPSCLKDIV_RANGE0 LL_RCC_SMPS_DIV_0 /*!< PLLM division factor = 0 */ 653 #define RCC_SMPSCLKDIV_RANGE1 LL_RCC_SMPS_DIV_1 /*!< PLLM division factor = 1 */ 654 #define RCC_SMPSCLKDIV_RANGE2 LL_RCC_SMPS_DIV_2 /*!< PLLM division factor = 2 */ 655 #define RCC_SMPSCLKDIV_RANGE3 LL_RCC_SMPS_DIV_3 /*!< PLLM division factor = 3 */ 656 /** 657 * @} 658 */ 659 #endif /* RCC_SMPS_SUPPORT */ 660 661 662 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 663 * @{ 664 */ 665 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18 /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */ 666 667 /** 668 * @} 669 */ 670 671 672 #if defined(CRS) 673 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 674 * @{ 675 */ 676 #define RCC_CRS_NONE 0x00000000U /*!< CRS status none */ 677 #define RCC_CRS_TIMEOUT 0x00000001U /*!< CRS status timeout */ 678 #define RCC_CRS_SYNCOK 0x00000002U /*!< CRS status synchronization success */ 679 #define RCC_CRS_SYNCWARN 0x00000004U /*!< CRS status synchronization warning */ 680 #define RCC_CRS_SYNCERR 0x00000008U /*!< CRS status synchronization error */ 681 #define RCC_CRS_SYNCMISS 0x00000010U /*!< CRS status synchronization missed */ 682 #define RCC_CRS_TRIMOVF 0x00000020U /*!< CRS status trimming overflow or underflow */ 683 /** 684 * @} 685 */ 686 687 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 688 * @{ 689 */ 690 #define RCC_CRS_SYNC_SOURCE_GPIO LL_CRS_SYNC_SOURCE_GPIO /*!< Synchro Signal source GPIO */ 691 #define RCC_CRS_SYNC_SOURCE_LSE LL_CRS_SYNC_SOURCE_LSE /*!< Synchro Signal source LSE */ 692 #define RCC_CRS_SYNC_SOURCE_USB LL_CRS_SYNC_SOURCE_USB /*!< Synchro Signal source USB SOF (default)*/ 693 /** 694 * @} 695 */ 696 697 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 698 * @{ 699 */ 700 #define RCC_CRS_SYNC_DIV1 LL_CRS_SYNC_DIV_1 /*!< Synchro Signal not divided (default) */ 701 #define RCC_CRS_SYNC_DIV2 LL_CRS_SYNC_DIV_2 /*!< Synchro Signal divided by 2 */ 702 #define RCC_CRS_SYNC_DIV4 LL_CRS_SYNC_DIV_4 /*!< Synchro Signal divided by 4 */ 703 #define RCC_CRS_SYNC_DIV8 LL_CRS_SYNC_DIV_8 /*!< Synchro Signal divided by 8 */ 704 #define RCC_CRS_SYNC_DIV16 LL_CRS_SYNC_DIV_16 /*!< Synchro Signal divided by 16 */ 705 #define RCC_CRS_SYNC_DIV32 LL_CRS_SYNC_DIV_32 /*!< Synchro Signal divided by 32 */ 706 #define RCC_CRS_SYNC_DIV64 LL_CRS_SYNC_DIV_64 /*!< Synchro Signal divided by 64 */ 707 #define RCC_CRS_SYNC_DIV128 LL_CRS_SYNC_DIV_128 /*!< Synchro Signal divided by 128 */ 708 /** 709 * @} 710 */ 711 712 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 713 * @{ 714 */ 715 #define RCC_CRS_SYNC_POLARITY_RISING LL_CRS_SYNC_POLARITY_RISING /*!< Synchro Active on rising edge (default) */ 716 #define RCC_CRS_SYNC_POLARITY_FALLING LL_CRS_SYNC_POLARITY_FALLING /*!< Synchro Active on falling edge */ 717 /** 718 * @} 719 */ 720 721 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 722 * @{ 723 */ 724 #define RCC_CRS_RELOADVALUE_DEFAULT LL_CRS_RELOADVALUE_DEFAULT /*!< The reset value of the RELOAD field corresponds 725 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 726 /** 727 * @} 728 */ 729 730 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 731 * @{ 732 */ 733 #define RCC_CRS_ERRORLIMIT_DEFAULT LL_CRS_ERRORLIMIT_DEFAULT /*!< Default Frequency error limit */ 734 /** 735 * @} 736 */ 737 738 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 739 * @{ 740 */ 741 #define RCC_CRS_HSI48CALIBRATION_DEFAULT LL_CRS_HSI48CALIBRATION_DEFAULT /*!< The default value is 32, which corresponds to the middle of the trimming interval. 742 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value 743 corresponds to a higher output frequency */ 744 /** 745 * @} 746 */ 747 748 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 749 * @{ 750 */ 751 #define RCC_CRS_FREQERRORDIR_UP LL_CRS_FREQ_ERROR_DIR_UP /*!< Upcounting direction, the actual frequency is above the target */ 752 #define RCC_CRS_FREQERRORDIR_DOWN LL_CRS_FREQ_ERROR_DIR_DOWN /*!< Downcounting direction, the actual frequency is below the target */ 753 /** 754 * @} 755 */ 756 757 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 758 * @{ 759 */ 760 #define RCC_CRS_IT_SYNCOK LL_CRS_CR_SYNCOKIE /*!< SYNC event OK */ 761 #define RCC_CRS_IT_SYNCWARN LL_CRS_CR_SYNCWARNIE /*!< SYNC warning */ 762 #define RCC_CRS_IT_ERR LL_CRS_CR_ERRIE /*!< Error */ 763 #define RCC_CRS_IT_ESYNC LL_CRS_CR_ESYNCIE /*!< Expected SYNC */ 764 #define RCC_CRS_IT_SYNCERR LL_CRS_CR_ERRIE /*!< SYNC error */ 765 #define RCC_CRS_IT_SYNCMISS LL_CRS_CR_ERRIE /*!< SYNC missed */ 766 #define RCC_CRS_IT_TRIMOVF LL_CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 767 768 /** 769 * @} 770 */ 771 772 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 773 * @{ 774 */ 775 #define RCC_CRS_FLAG_SYNCOK LL_CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 776 #define RCC_CRS_FLAG_SYNCWARN LL_CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 777 #define RCC_CRS_FLAG_ERR LL_CRS_ISR_ERRF /*!< Error flag */ 778 #define RCC_CRS_FLAG_ESYNC LL_CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 779 #define RCC_CRS_FLAG_SYNCERR LL_CRS_ISR_SYNCERR /*!< SYNC error */ 780 #define RCC_CRS_FLAG_SYNCMISS LL_CRS_ISR_SYNCMISS /*!< SYNC missed*/ 781 #define RCC_CRS_FLAG_TRIMOVF LL_CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 782 783 /** 784 * @} 785 */ 786 #endif /* CRS */ 787 788 /** 789 * @} 790 */ 791 792 /* Exported macros -----------------------------------------------------------*/ 793 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 794 * @{ 795 */ 796 797 /*================================================================================================================*/ 798 799 #if defined(SAI1) 800 /** 801 * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. 802 * 803 * @note This function must be used only when the PLLSAI1 is disabled. 804 * @note PLLSAI1 clock source is common with the main PLL (configured through 805 * @ref __HAL_RCC_PLL_CONFIG() macro) 806 * 807 * @param __PLLN__ specifies the multiplication factor for PLLSAI1 VCO output clock. 808 * This parameter must be a number between 6 and 127. 809 * @note You have to set the PLLN parameter correctly to ensure that the VCO 810 * output frequency is between 96 and 344 MHz. 811 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLN 812 * 813 * @param __PLLP__ specifies the division factor for SAI clock. 814 * This parameter must be a number in the range (RCC_PLLP_DIV2 to RCC_PLLP_DIV32). 815 * SAI clock frequency = f(PLLSAI1) / PLLP 816 * 817 * @param __PLLQ__ specifies the division factor for USB/RNG clock. 818 * This parameter must be in the range (RCC_PLLQ_DIV2 to RCC_PLLQ_DIV8). 819 * USB/RNG clock frequency = f(PLLSAI1) / PLLQ 820 * 821 * @param __PLLR__ specifies the division factor for SAR ADC clock. 822 * This parameter must be in the range (RCC_PLLR_DIV2 to RCC_PLLR_DIV8). 823 * ADC clock frequency = f(PLLSAI1) / PLLR 824 * 825 * @retval None 826 */ 827 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLN__, __PLLP__, __PLLQ__, __PLLR__) \ 828 MODIFY_REG(RCC->PLLSAI1CFGR, \ 829 (RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLP | RCC_PLLSAI1CFGR_PLLQ | RCC_PLLSAI1CFGR_PLLR), \ 830 (((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | (__PLLP__) | (__PLLQ__) | (__PLLR__))) 831 832 /** 833 * @brief Macro to configure the PLLSAI1 clock multiplication factor N. 834 * 835 * @note This function must be used only when the PLLSAI1 is disabled. 836 * @note PLLSAI1 clock source is common with the main PLL (configured through 837 * @ref __HAL_RCC_PLL_CONFIG() macro) 838 * 839 * @param __PLLN__ specifies the multiplication factor for PLLSAI1 VCO output clock. 840 * This parameter must be a number between Min_Data=6 and Max_Data=127. 841 * @note You have to set the PLLN parameter correctly to ensure that the VCO 842 * output frequency is between 96 and 344 MHz. 843 * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLN 844 * 845 * @retval None 846 */ 847 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLN__) \ 848 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN, (__PLLN__) << RCC_PLLSAI1CFGR_PLLN_Pos) 849 850 851 /** @brief Macro to configure the PLLSAI1 clock division factor P. 852 * 853 * @note This function must be used only when the PLLSAI1 is disabled. 854 * @note PLLSAI1 clock source is common with the main PLL (configured through 855 * @ref __HAL_RCC_PLL_CONFIG() macro) 856 * 857 * @param __PLLP__ specifies the division factor for SAI clock. 858 * This parameter must be a number in range (RCC_PLLP_DIV2 to RCC_PLLP_DIV32). 859 * Use to set SAI clock frequency = f(PLLSAI1) / PLLP 860 * 861 * @retval None 862 */ 863 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLP__) \ 864 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLP, (__PLLP__)) 865 866 867 /** @brief Macro to configure the PLLSAI1 clock division factor Q. 868 * 869 * @note This function must be used only when the PLLSAI1 is disabled. 870 * @note PLLSAI1 clock source is common with the main PLL (configured through 871 * @ref __HAL_RCC_PLL_CONFIG() macro) 872 * 873 * @param __PLLQ__ specifies the division factor for USB clock. 874 * This parameter must be in the range (RCC_PLLQ_DIV2 to RCC_PLLQ_DIV8). 875 * Use to set USB clock frequency = f(PLLSAI1) / PLLQ 876 * 877 * @retval None 878 */ 879 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLQ__) \ 880 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQ, (__PLLQ__)) 881 882 /** @brief Macro to configure the PLLSAI1 clock division factor R. 883 * 884 * @note This function must be used only when the PLLSAI1 is disabled. 885 * @note PLLSAI1 clock source is common with the main PLL (configured through 886 * @ref __HAL_RCC_PLL_CONFIG() macro) 887 * 888 * @param __PLLR__ specifies the division factor for ADC clock. 889 * This parameter must be in the range (RCC_PLLR_DIV2 to RCC_PLLR_DIV8). 890 * Use to set ADC clock frequency = f(PLLSAI1) / PLLR 891 * 892 * @retval None 893 */ 894 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLR__) \ 895 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLR, (__PLLR__)) 896 897 /** 898 * @brief Macros to enable the PLLSAI1. 899 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes. 900 * @retval None 901 */ 902 #define __HAL_RCC_PLLSAI1_ENABLE() LL_RCC_PLLSAI1_Enable() 903 904 /** 905 * @brief Macros to disable the PLLSAI1. 906 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes. 907 * @retval None 908 */ 909 #define __HAL_RCC_PLLSAI1_DISABLE() LL_RCC_PLLSAI1_Disable() 910 911 /** 912 * @brief Macros to enable each clock output (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK). 913 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 914 * This is mainly used to save Power. 915 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 916 * This parameter can be one or a combination of the following values: 917 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface 918 * @arg @ref RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral 919 * @arg @ref RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz) 920 * 921 * @retval None 922 */ 923 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 924 925 /** 926 * @brief Macros to disable each clock output (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK). 927 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 928 * This is mainly used to save Power. 929 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 930 * This parameter can be one or a combination of the following values: 931 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface 932 * @arg @ref RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral 933 * @arg @ref RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz) 934 * 935 * @retval None 936 */ 937 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 938 939 /** 940 * @brief Macro to get clock output enable status (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK). 941 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 942 * This parameter can be one or a combination of the following values: 943 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface 944 * @arg @ref RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral 945 * @arg @ref RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz) 946 * @retval SET / RESET 947 */ 948 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 949 950 951 /** 952 * @brief Macro to configure the SAI1 clock source. 953 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived 954 * from the PLLSAI1, system PLL, HSI or external clock (through a dedicated pin). 955 * This parameter can be one of the following values: 956 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock 957 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock 958 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI clock 959 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 960 * 961 * @retval None 962 */ 963 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) LL_RCC_SetSAIClockSource(__SAI1_CLKSOURCE__) 964 965 966 /** @brief Macro to get the SAI1 clock source. 967 * @retval The clock source can be one of the following values: 968 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock 969 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock 970 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI clock 971 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 972 * 973 * @retval None 974 */ 975 #define __HAL_RCC_GET_SAI1_SOURCE() LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE) 976 #endif /* SAI1 */ 977 978 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 979 * 980 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 981 * This parameter can be one of the following values: 982 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 983 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 984 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 985 * @retval None 986 */ 987 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C1_CLKSOURCE__) 988 989 /** @brief Macro to get the I2C1 clock source. 990 * @retval The clock source can be one of the following values: 991 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 992 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 993 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 994 */ 995 #define __HAL_RCC_GET_I2C1_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE) 996 997 #if defined(I2C3) 998 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 999 * 1000 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 1001 * This parameter can be one of the following values: 1002 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1003 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1004 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 1005 * @retval None 1006 */ 1007 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C3_CLKSOURCE__) 1008 1009 /** @brief Macro to get the I2C3 clock source. 1010 * @retval The clock source can be one of the following values: 1011 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1012 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1013 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 1014 */ 1015 #define __HAL_RCC_GET_I2C3_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE) 1016 #endif /* I2C3 */ 1017 1018 /** @brief Macro to configure the USART1 clock (USART1CLK). 1019 * 1020 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 1021 * This parameter can be one of the following values: 1022 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1023 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1024 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1025 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1026 * @retval None 1027 */ 1028 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) LL_RCC_SetUSARTClockSource(__USART1_CLKSOURCE__) 1029 1030 /** @brief Macro to get the USART1 clock source. 1031 * @retval The clock source can be one of the following values: 1032 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1033 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1034 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1035 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1036 */ 1037 #define __HAL_RCC_GET_USART1_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE) 1038 1039 #if defined(LPUART1) 1040 /** @brief Macro to configure the LPUART clock (LPUARTCLK). 1041 * 1042 * @param __LPUART_CLKSOURCE__ specifies the LPUART clock source. 1043 * This parameter can be one of the following values: 1044 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1045 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1046 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1047 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1048 * @retval None 1049 */ 1050 #define __HAL_RCC_LPUART1_CONFIG(__LPUART_CLKSOURCE__) LL_RCC_SetLPUARTClockSource(__LPUART_CLKSOURCE__) 1051 1052 /** @brief Macro to get the LPUART clock source. 1053 * @retval The clock source can be one of the following values: 1054 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1055 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1056 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1057 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1058 */ 1059 #define __HAL_RCC_GET_LPUART1_SOURCE() LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE) 1060 #endif /* LPUART1 */ 1061 1062 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 1063 * 1064 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 1065 * This parameter can be one of the following values: 1066 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK selected as LPTIM1 clock 1067 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 1068 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock 1069 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1070 * @retval None 1071 */ 1072 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM1_CLKSOURCE__) 1073 1074 /** @brief Macro to get the LPTIM1 clock source. 1075 * @retval The clock source can be one of the following values: 1076 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK selected as LPTIM1 clock 1077 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 1078 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPTIM1 clock 1079 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1080 */ 1081 #define __HAL_RCC_GET_LPTIM1_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE) 1082 1083 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 1084 * 1085 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 1086 * This parameter can be one of the following values: 1087 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK selected as LPTIM2 clock 1088 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 1089 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock 1090 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1091 * @retval None 1092 */ 1093 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM2_CLKSOURCE__) 1094 1095 /** @brief Macro to get the LPTIM2 clock source. 1096 * @retval The clock source can be one of the following values: 1097 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK selected as LPTIM2 clock 1098 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 1099 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPTIM2 clock 1100 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1101 */ 1102 #define __HAL_RCC_GET_LPTIM2_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE) 1103 1104 1105 /** @brief Macro to configure the RNG clock. 1106 * 1107 * @note USB and RNG peripherals share the same 48MHz clock source. 1108 * 1109 * @param __RNG_CLKSOURCE__ specifies the RNG clock source. 1110 * This parameter can be one of the following values: 1111 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 clock divided by 3 selected as RNG clock 1112 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock divided by 3 selected as RNG clock 1113 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI clock divided by 3 selected as RNG clock 1114 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock selected as RNG (*) 1115 * @arg @ref RCC_RNGCLKSOURCE_CLK48 CLK48 divided by 3 selected as RNG Clock (default HSI48) 1116 * @arg @ref RCC_RNGCLKSOURCE_LSI LSI clock selected as RNG clock 1117 * @arg @ref RCC_RNGCLKSOURCE_LSE LSE clock selected as RNG clock 1118 * 1119 * (*) Value not defined in all devices. 1120 * 1121 * @retval None 1122 */ 1123 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ 1124 do { \ 1125 if (((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSI) \ 1126 || ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSE) \ 1127 || ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_CLK48)) \ 1128 { \ 1129 LL_RCC_SetRNGClockSource((__RNG_CLKSOURCE__)); \ 1130 } \ 1131 else \ 1132 { \ 1133 uint32_t tmp = (__RNG_CLKSOURCE__) &(~CLK48_MASK); \ 1134 LL_RCC_SetRNGClockSource(RCC_RNGCLKSOURCE_CLK48); \ 1135 LL_RCC_SetCLK48ClockSource(tmp); \ 1136 } \ 1137 } while(0U) 1138 1139 /** @brief Macro to get the direct RNG clock. 1140 * @note @ref HAL_RCCEx_GetRngCLKSource can also be called to get direct 1141 * of indirect (48 MHz clock source) RNG clock source. 1142 * @retval The RNG clock source can be one of the following values: 1143 * @arg @ref RCC_RNGCLKSOURCE_CLK48 CLK48 divided by 3 selected as RNG Clock 1144 * @arg @ref RCC_RNGCLKSOURCE_LSI LSI selected as RNG clock 1145 * @arg @ref RCC_RNGCLKSOURCE_LSE LSE selected as RNG clock 1146 */ 1147 #define __HAL_RCC_GET_RNG_SOURCE() LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE) 1148 1149 #if defined(USB) 1150 /** @brief Macro to configure the USB clock (USBCLK). 1151 * 1152 * @note USB and RNG peripherals share the same 48MHz clock source. 1153 * 1154 * @param __USB_CLKSOURCE__ specifies the USB clock source. 1155 * This parameter can be one of the following values: 1156 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 1157 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 1158 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 1159 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 1160 * @retval None 1161 */ 1162 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) LL_RCC_SetUSBClockSource(__USB_CLKSOURCE__) 1163 1164 /** @brief Macro to get the USB clock source. 1165 * @retval The clock source can be one of the following values: 1166 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 1167 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 1168 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 1169 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 1170 */ 1171 #define __HAL_RCC_GET_USB_SOURCE() LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE) 1172 #endif /* USB */ 1173 1174 /** @brief Macro to configure the ADC interface clock. 1175 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. 1176 * This parameter can be one of the following values: 1177 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 1178 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock (*) 1179 * @arg @ref RCC_ADCCLKSOURCE_PLL PLL Clock selected as ADC clock 1180 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 1181 * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock (*) 1182 * @note (*) Value not defined for all devices 1183 * @retval None 1184 */ 1185 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) LL_RCC_SetADCClockSource(__ADC_CLKSOURCE__) 1186 1187 /** @brief Macro to get the ADC clock source. 1188 * @retval The clock source can be one of the following values: 1189 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 1190 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock (*) 1191 * @arg @ref RCC_ADCCLKSOURCE_PLL PLL Clock selected as ADC clock 1192 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 1193 * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock (*) 1194 * @note (*) Value not defined for all devices 1195 */ 1196 #define __HAL_RCC_GET_ADC_SOURCE() LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE) 1197 1198 /** @brief Macro to configure the RFWKP interface clock. 1199 * @param __RFWKP_CLKSOURCE__ specifies the RFWKP digital interface clock source. 1200 * This parameter can be one of the following values: 1201 * @arg @ref RCC_RFWKPCLKSOURCE_NONE No clock selected as RFWKP clock 1202 * @arg @ref RCC_RFWKPCLKSOURCE_LSE LSE Clock selected as RFWKP clock 1203 * @arg @ref RCC_RFWKPCLKSOURCE_LSI LSI Clock selected as RFWKP clock (*) 1204 * @arg @ref RCC_RFWKPCLKSOURCE_HSE_DIV1024 HSE div1024 Clock selected as RFWKP clock 1205 * @note (*) Value not defined for all devices 1206 * 1207 * @retval None 1208 */ 1209 #define __HAL_RCC_RFWAKEUP_CONFIG(__RFWKP_CLKSOURCE__) LL_RCC_SetRFWKPClockSource(__RFWKP_CLKSOURCE__) 1210 1211 /** @brief Macro to get the RFWKP clock source. 1212 * This parameter can be one of the following values: 1213 * @arg @ref RCC_RFWKPCLKSOURCE_NONE No clock selected as RFWKP clock 1214 * @arg @ref RCC_RFWKPCLKSOURCE_LSE LSE Clock selected as RFWKP clock 1215 * @arg @ref RCC_RFWKPCLKSOURCE_LSI LSI Clock selected as RFWKP clock (*) 1216 * @arg @ref RCC_RFWKPCLKSOURCE_HSE_DIV1024 HSE div1024 Clock selected as RFWKP clock 1217 * @note (*) Value not defined for all devices 1218 */ 1219 #define __HAL_RCC_GET_RFWAKEUP_SOURCE() LL_RCC_GetRFWKPClockSource() 1220 1221 #if defined(RCC_SMPS_SUPPORT) 1222 /** @brief Macro to configure the SMPS clock division factor. 1223 * 1224 * @param __SMPSCLKDIV__ specifies the division factor for SMPS clock. 1225 * This parameter can be one of the following values: 1226 * @arg @ref RCC_SMPSCLKDIV_RANGE0 1st divider factor value 1227 * @arg @ref RCC_SMPSCLKDIV_RANGE1 2nd divider factor value 1228 * @arg @ref RCC_SMPSCLKDIV_RANGE2 3th divider factor value 1229 * @arg @ref RCC_SMPSCLKDIV_RANGE3 4th divider factor value 1230 * 1231 * @note divider value predefined by HW depending of SMPS clock source 1232 * 1233 * @retval None 1234 */ 1235 #define __HAL_RCC_SMPS_DIV_CONFIG(__SMPSCLKDIV__) LL_RCC_SetSMPSPrescaler(__SMPSCLKDIV__) 1236 1237 /** @brief Macro to get the SMPS clock division factor. 1238 * 1239 * This parameter can be one of the following values: 1240 * @arg @ref RCC_SMPSCLKDIV_RANGE0 1st divider factor value 1241 * @arg @ref RCC_SMPSCLKDIV_RANGE1 2nd divider factor value 1242 * @arg @ref RCC_SMPSCLKDIV_RANGE2 3th divider factor value 1243 * @arg @ref RCC_SMPSCLKDIV_RANGE3 4th divider factor value 1244 * 1245 */ 1246 #define __HAL_RCC_GET_SMPS_DIV() LL_RCC_GetSMPSPrescaler() 1247 1248 /** @brief Macro to configure the SMPS interface clock. 1249 * @param __SMPS_CLKSOURCE__ specifies the SMPS digital interface clock source. 1250 * This parameter can be one of the following values: 1251 * @arg @ref RCC_SMPSCLKSOURCE_HSI HSI clock selected as SMPS clock 1252 * @arg @ref RCC_SMPSCLKSOURCE_MSI MSI Clock selected as SMPS clock 1253 * @arg @ref RCC_SMPSCLKSOURCE_HSE HSE Clock selected as SMPS clock 1254 * @retval None 1255 */ 1256 1257 #define __HAL_RCC_SMPS_CONFIG(__SMPS_CLKSOURCE__) LL_RCC_SetSMPSClockSource(__SMPS_CLKSOURCE__) 1258 1259 /** @brief Macro to get the SMPS clock source. 1260 * This parameter can be one of the following values: 1261 * @arg @ref RCC_SMPSCLKSOURCE_HSI HSI clock selected as SMPS clock 1262 * @arg @ref RCC_SMPSCLKSOURCE_MSI MSI Clock selected as SMPS clock 1263 * @arg @ref RCC_SMPSCLKSOURCE_HSE HSE Clock selected as SMPS clock 1264 */ 1265 #define __HAL_RCC_GET_SMPS_SOURCE() LL_RCC_GetSMPSClockSelection() 1266 1267 /** @brief Macro to get the SMPS clock source. 1268 * This parameter can be one of the following values: 1269 * @arg @ref RCC_SMPSCLKSOURCE_STATUS_HSI HSI clock selected as SMPS clock 1270 * @arg @ref RCC_SMPSCLKSOURCE_STATUS_MSI MSI Clock selected as SMPS clock 1271 * @arg @ref RCC_SMPSCLKSOURCE_STATUS_HSE HSE Clock selected as SMPS clock 1272 */ 1273 #define __HAL_RCC_GET_SMPS_SOURCE_STATUS() LL_RCC_GetSMPSClockSource() 1274 #endif /* RCC_SMPS_SUPPORT */ 1275 1276 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management 1277 * @brief macros to manage the specified RCC Flags and interrupts. 1278 * @{ 1279 */ 1280 1281 1282 #if defined(SAI1) 1283 /** @brief Enable PLLSAI1RDY interrupt. 1284 * @retval None 1285 */ 1286 #define __HAL_RCC_PLLSAI1_ENABLE_IT() LL_RCC_EnableIT_PLLSAI1RDY() 1287 1288 /** @brief Disable PLLSAI1RDY interrupt. 1289 * @retval None 1290 */ 1291 #define __HAL_RCC_PLLSAI1_DISABLE_IT() LL_RCC_DisableIT_PLLSAI1RDY() 1292 1293 /** @brief Clear the PLLSAI1RDY interrupt pending bit. 1294 * @retval None 1295 */ 1296 #define __HAL_RCC_PLLSAI1_CLEAR_IT() LL_RCC_ClearFlag_PLLSAI1RDY() 1297 1298 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not. 1299 * @retval TRUE or FALSE. 1300 */ 1301 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() LL_RCC_IsActiveFlag_PLLSAI1RDY() 1302 1303 /** @brief Check whether the PLLSAI1RDY flag is set or not. 1304 * @retval TRUE or FALSE. 1305 */ 1306 #define __HAL_RCC_PLLSAI1_GET_FLAG() LL_RCC_PLLSAI1_IsReady() 1307 #endif /* SAI1 */ 1308 1309 /** 1310 * @brief Enable the RCC LSE CSS Extended Interrupt C1 Line. 1311 * @retval None 1312 */ 1313 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS) 1314 1315 /** 1316 * @brief Enable the RCC LSE CSS Extended Interrupt C2 Line. 1317 * @retval None 1318 */ 1319 #define __HAL_C2_RCC_LSECSS_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS) 1320 1321 /** 1322 * @brief Disable the RCC LSE CSS Extended Interrupt C1 Line. 1323 * @retval None 1324 */ 1325 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS) 1326 1327 /** 1328 * @brief Disable the RCC LSE CSS Extended Interrupt C2 Line. 1329 * @retval None 1330 */ 1331 #define __HAL_C2_RCC_LSECSS_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS) 1332 1333 /** 1334 * @brief Enable the RCC LSE CSS Event C1 Line. 1335 * @retval None. 1336 */ 1337 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS) 1338 1339 /** 1340 * @brief Enable the RCC LSE CSS Event C2 Line. 1341 * @retval None. 1342 */ 1343 #define __HAL_C2_RCC_LSECSS_EXTI_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS) 1344 1345 /** 1346 * @brief Disable the RCC LSE CSS Event C1 Line. 1347 * @retval None. 1348 */ 1349 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS) 1350 1351 /** 1352 * @brief Disable the RCC LSE CSS Event C2 Line. 1353 * @retval None. 1354 */ 1355 #define __HAL_C2_RCC_LSECSS_EXTI_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS) 1356 1357 /** 1358 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. 1359 * @retval None. 1360 */ 1361 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(RCC_EXTI_LINE_LSECSS) 1362 1363 /** 1364 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 1365 * @retval None. 1366 */ 1367 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(RCC_EXTI_LINE_LSECSS) 1368 1369 /** 1370 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. 1371 * @retval None. 1372 */ 1373 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(RCC_EXTI_LINE_LSECSS) 1374 1375 /** 1376 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 1377 * @retval None. 1378 */ 1379 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(RCC_EXTI_LINE_LSECSS) 1380 1381 /** 1382 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 1383 * @retval None. 1384 */ 1385 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 1386 do { \ 1387 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 1388 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 1389 } while(0) 1390 1391 /** 1392 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 1393 * @retval None. 1394 */ 1395 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 1396 do { \ 1397 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 1398 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 1399 } while(0) 1400 1401 /** 1402 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 1403 * @retval EXTI RCC LSE CSS Line Status. 1404 */ 1405 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(RCC_EXTI_LINE_LSECSS) 1406 1407 /** 1408 * @brief Clear the RCC LSE CSS EXTI flag. 1409 * @retval None. 1410 */ 1411 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(RCC_EXTI_LINE_LSECSS) 1412 1413 /** 1414 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. 1415 * @retval None. 1416 */ 1417 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(RCC_EXTI_LINE_LSECSS) 1418 1419 #if defined(CRS) 1420 /** 1421 * @brief Enable the specified CRS interrupts. 1422 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 1423 * This parameter can be any combination of the following values: 1424 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1425 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1426 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1427 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1428 * @retval None 1429 */ 1430 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 1431 1432 /** 1433 * @brief Disable the specified CRS interrupts. 1434 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 1435 * This parameter can be any combination of the following values: 1436 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1437 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1438 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1439 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1440 * @retval None 1441 */ 1442 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 1443 1444 /** @brief Check whether the CRS interrupt has occurred or not. 1445 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 1446 * This parameter can be one of the following values: 1447 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1448 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1449 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1450 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1451 * @retval The new state of __INTERRUPT__ (SET or RESET). 1452 */ 1453 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) 1454 1455 /** @brief Clear the CRS interrupt pending bits 1456 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1457 * This parameter can be any combination of the following values: 1458 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1459 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1460 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1461 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1462 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 1463 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 1464 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 1465 */ 1466 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 1467 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ 1468 { \ 1469 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 1470 } \ 1471 else \ 1472 { \ 1473 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 1474 } \ 1475 } while(0) 1476 1477 /** 1478 * @brief Check whether the specified CRS flag is set or not. 1479 * @param __FLAG__ specifies the flag to check. 1480 * This parameter can be one of the following values: 1481 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1482 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1483 * @arg @ref RCC_CRS_FLAG_ERR Error 1484 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1485 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1486 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1487 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1488 * @retval The new state of _FLAG_ (TRUE or FALSE). 1489 */ 1490 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 1491 1492 /** 1493 * @brief Clear the CRS specified FLAG. 1494 * @param __FLAG__ specifies the flag to clear. 1495 * This parameter can be one of the following values: 1496 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1497 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1498 * @arg @ref RCC_CRS_FLAG_ERR Error 1499 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1500 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1501 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1502 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1503 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 1504 * @retval None 1505 */ 1506 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 1507 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 1508 { \ 1509 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 1510 } \ 1511 else \ 1512 { \ 1513 WRITE_REG(CRS->ICR, (__FLAG__)); \ 1514 } \ 1515 } while(0) 1516 #endif /* CRS */ 1517 /** 1518 * @} 1519 */ 1520 1521 1522 #if defined(CRS) 1523 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 1524 * @{ 1525 */ 1526 /** 1527 * @brief Enable the oscillator clock for frequency error counter. 1528 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 1529 * @retval None 1530 */ 1531 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() LL_CRS_EnableFreqErrorCounter() 1532 1533 /** 1534 * @brief Disable the oscillator clock for frequency error counter. 1535 * @retval None 1536 */ 1537 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() LL_CRS_DisableFreqErrorCounter() 1538 1539 /** 1540 * @brief Enable the automatic hardware adjustment of TRIM bits. 1541 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 1542 * @retval None 1543 */ 1544 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() LL_CRS_EnableAutoTrimming() 1545 1546 /** 1547 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 1548 * @retval None 1549 */ 1550 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() LL_CRS_DisableAutoTrimming() 1551 1552 /** 1553 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 1554 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 1555 * of the synchronization source after prescaling. It is then decreased by one in order to 1556 * reach the expected synchronization on the zero value. The formula is the following: 1557 * RELOAD = (fTARGET / fSYNC) -1 1558 * @param __FTARGET__ Target frequency (value in Hz) 1559 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 1560 * @retval None 1561 */ 1562 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) __LL_CRS_CALC_CALCULATE_RELOADVALUE((__FTARGET__),(__FSYNC__)) 1563 1564 /** 1565 * @} 1566 */ 1567 #endif /* CRS */ 1568 1569 /** 1570 * @} 1571 */ 1572 1573 /* Exported functions --------------------------------------------------------*/ 1574 /** @addtogroup RCCEx_Exported_Functions 1575 * @{ 1576 */ 1577 1578 /** @addtogroup RCCEx_Exported_Functions_Group1 1579 * @{ 1580 */ 1581 1582 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1583 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1584 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 1585 uint32_t HAL_RCCEx_GetRngCLKSource(void); 1586 1587 /** 1588 * @} 1589 */ 1590 1591 /** @addtogroup RCCEx_Exported_Functions_Group2 1592 * @{ 1593 */ 1594 1595 #if defined(SAI1) 1596 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); 1597 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); 1598 #endif /* SAI1 */ 1599 1600 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 1601 1602 void HAL_RCCEx_EnableLSECSS(void); 1603 void HAL_RCCEx_DisableLSECSS(void); 1604 void HAL_RCCEx_EnableLSECSS_IT(void); 1605 void HAL_RCCEx_LSECSS_IRQHandler(void); 1606 void HAL_RCCEx_LSECSS_Callback(void); 1607 1608 void HAL_RCCEx_LSCOConfig(uint32_t RCC_LSCOx, uint32_t RCC_LSCOSource); 1609 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 1610 void HAL_RCCEx_DisableLSCO(void); 1611 1612 void HAL_RCCEx_EnableMSIPLLMode(void); 1613 void HAL_RCCEx_DisableMSIPLLMode(void); 1614 1615 HAL_StatusTypeDef HAL_RCCEx_TrimOsc(uint32_t OscillatorType); 1616 1617 /** 1618 * @} 1619 */ 1620 1621 1622 #if defined(CRS) 1623 1624 /** @addtogroup RCCEx_Exported_Functions_Group3 1625 * @{ 1626 */ 1627 1628 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 1629 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 1630 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 1631 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 1632 void HAL_RCCEx_CRS_IRQHandler(void); 1633 void HAL_RCCEx_CRS_SyncOkCallback(void); 1634 void HAL_RCCEx_CRS_SyncWarnCallback(void); 1635 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 1636 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 1637 1638 /** 1639 * @} 1640 */ 1641 1642 #endif /* CRS */ 1643 /** 1644 * @} 1645 */ 1646 1647 /** 1648 * @} 1649 */ 1650 1651 /** 1652 * @} 1653 */ 1654 1655 #ifdef __cplusplus 1656 } 1657 #endif 1658 1659 #endif /* STM32WBxx_HAL_RCC_EX_H */ 1660
