1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_qspi.h 4 * @author MCD Application Team 5 * @brief Header file of QSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBxx_HAL_QSPI_H 21 #define STM32WBxx_HAL_QSPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbxx_hal_def.h" 29 30 #if defined(QUADSPI) 31 32 /** @addtogroup STM32WBxx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup QSPI 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup QSPI_Exported_Types QSPI Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief QSPI Init structure definition 47 */ 48 typedef struct 49 { 50 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. 51 This parameter can be a number between 0 and 255 */ 52 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) 53 This parameter can be a value between 1 and 16 */ 54 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 55 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) 56 This parameter can be a value of @ref QSPI_SampleShifting */ 57 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 58 required to address the flash memory. The flash capacity can be up to 4GB 59 (addressed using 32 bits) in indirect mode, but the addressable space in 60 memory-mapped mode is limited to 256MB 61 This parameter can be a number between 0 and 31 */ 62 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 63 of clock cycles which the chip select must remain high between commands. 64 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ 65 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. 66 This parameter can be a value of @ref QSPI_ClockMode */ 67 }QSPI_InitTypeDef; 68 69 /** 70 * @brief HAL QSPI State structures definition 71 */ 72 typedef enum 73 { 74 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ 75 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ 76 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ 77 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ 78 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ 79 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ 80 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ 81 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ 82 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ 83 }HAL_QSPI_StateTypeDef; 84 85 /** 86 * @brief QSPI Handle Structure definition 87 */ 88 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 89 typedef struct __QSPI_HandleTypeDef 90 #else 91 typedef struct 92 #endif 93 { 94 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ 95 QSPI_InitTypeDef Init; /* QSPI communication parameters */ 96 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ 97 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ 98 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ 99 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ 100 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ 101 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ 102 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ 103 __IO HAL_LockTypeDef Lock; /* Locking object */ 104 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ 105 __IO uint32_t ErrorCode; /* QSPI Error code */ 106 uint32_t Timeout; /* Timeout for the QSPI memory access */ 107 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 108 void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); 109 void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 110 void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); 111 void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 112 void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 113 void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 114 void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 115 void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 116 void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); 117 void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); 118 119 void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 120 void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 121 #endif 122 }QSPI_HandleTypeDef; 123 124 /** 125 * @brief QSPI Command structure definition 126 */ 127 typedef struct 128 { 129 uint32_t Instruction; /* Specifies the Instruction to be sent 130 This parameter can be a value (8-bit) between 0x00 and 0xFF */ 131 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) 132 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 133 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) 134 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 135 uint32_t AddressSize; /* Specifies the Address Size 136 This parameter can be a value of @ref QSPI_AddressSize */ 137 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size 138 This parameter can be a value of @ref QSPI_AlternateBytesSize */ 139 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. 140 This parameter can be a number between 0 and 31 */ 141 uint32_t InstructionMode; /* Specifies the Instruction Mode 142 This parameter can be a value of @ref QSPI_InstructionMode */ 143 uint32_t AddressMode; /* Specifies the Address Mode 144 This parameter can be a value of @ref QSPI_AddressMode */ 145 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode 146 This parameter can be a value of @ref QSPI_AlternateBytesMode */ 147 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) 148 This parameter can be a value of @ref QSPI_DataMode */ 149 uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) 150 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 151 until end of memory)*/ 152 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase 153 This parameter can be a value of @ref QSPI_DdrMode */ 154 uint32_t SIOOMode; /* Specifies the send instruction only once mode 155 This parameter can be a value of @ref QSPI_SIOOMode */ 156 }QSPI_CommandTypeDef; 157 158 /** 159 * @brief QSPI Auto Polling mode configuration structure definition 160 */ 161 typedef struct 162 { 163 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 164 This parameter can be any value between 0 and 0xFFFFFFFF */ 165 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 166 This parameter can be any value between 0 and 0xFFFFFFFF */ 167 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 168 This parameter can be any value between 0 and 0xFFFF */ 169 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. 170 This parameter can be any value between 1 and 4 */ 171 uint32_t MatchMode; /* Specifies the method used for determining a match. 172 This parameter can be a value of @ref QSPI_MatchMode */ 173 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 174 This parameter can be a value of @ref QSPI_AutomaticStop */ 175 }QSPI_AutoPollingTypeDef; 176 177 /** 178 * @brief QSPI Memory Mapped mode configuration structure definition 179 */ 180 typedef struct 181 { 182 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 183 This parameter can be any value between 0 and 0xFFFF */ 184 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. 185 This parameter can be a value of @ref QSPI_TimeOutActivation */ 186 }QSPI_MemoryMappedTypeDef; 187 188 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 189 /** 190 * @brief HAL QSPI Callback ID enumeration definition 191 */ 192 typedef enum 193 { 194 HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ 195 HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ 196 HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ 197 HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ 198 HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ 199 HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ 200 HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */ 201 HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */ 202 HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ 203 HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ 204 205 HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ 206 HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ 207 }HAL_QSPI_CallbackIDTypeDef; 208 209 /** 210 * @brief HAL QSPI Callback pointer definition 211 */ 212 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); 213 #endif 214 /** 215 * @} 216 */ 217 218 /* Exported constants --------------------------------------------------------*/ 219 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants 220 * @{ 221 */ 222 223 /** @defgroup QSPI_ErrorCode QSPI Error Code 224 * @{ 225 */ 226 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ 227 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ 228 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ 229 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ 230 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ 231 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 232 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ 233 #endif 234 /** 235 * @} 236 */ 237 238 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting 239 * @{ 240 */ 241 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ 242 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ 243 /** 244 * @} 245 */ 246 247 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time 248 * @{ 249 */ 250 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ 251 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ 252 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ 253 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ 254 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ 255 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ 256 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ 257 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ 258 /** 259 * @} 260 */ 261 262 /** @defgroup QSPI_ClockMode QSPI Clock Mode 263 * @{ 264 */ 265 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ 266 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ 267 /** 268 * @} 269 */ 270 271 /** @defgroup QSPI_AddressSize QSPI Address Size 272 * @{ 273 */ 274 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ 275 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ 276 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ 277 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ 278 /** 279 * @} 280 */ 281 282 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size 283 * @{ 284 */ 285 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ 286 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ 287 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ 288 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ 289 /** 290 * @} 291 */ 292 293 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode 294 * @{ 295 */ 296 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ 297 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ 298 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ 299 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ 300 /** 301 * @} 302 */ 303 304 /** @defgroup QSPI_AddressMode QSPI Address Mode 305 * @{ 306 */ 307 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ 308 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ 309 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ 310 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ 311 /** 312 * @} 313 */ 314 315 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode 316 * @{ 317 */ 318 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ 319 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ 320 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ 321 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ 322 /** 323 * @} 324 */ 325 326 /** @defgroup QSPI_DataMode QSPI Data Mode 327 * @{ 328 */ 329 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/ 330 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ 331 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ 332 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ 333 /** 334 * @} 335 */ 336 337 /** @defgroup QSPI_DdrMode QSPI DDR Mode 338 * @{ 339 */ 340 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ 341 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ 342 /** 343 * @} 344 */ 345 346 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode 347 * @{ 348 */ 349 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ 350 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ 351 /** 352 * @} 353 */ 354 355 /** @defgroup QSPI_MatchMode QSPI Match Mode 356 * @{ 357 */ 358 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ 359 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ 360 /** 361 * @} 362 */ 363 364 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop 365 * @{ 366 */ 367 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ 368 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ 369 /** 370 * @} 371 */ 372 373 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation 374 * @{ 375 */ 376 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ 377 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ 378 /** 379 * @} 380 */ 381 382 /** @defgroup QSPI_Flags QSPI Flags 383 * @{ 384 */ 385 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ 386 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ 387 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ 388 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ 389 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ 390 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ 391 /** 392 * @} 393 */ 394 395 /** @defgroup QSPI_Interrupts QSPI Interrupts 396 * @{ 397 */ 398 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ 399 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ 400 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ 401 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ 402 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ 403 /** 404 * @} 405 */ 406 407 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition 408 * @brief QSPI Timeout definition 409 * @{ 410 */ 411 #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ 412 /** 413 * @} 414 */ 415 416 /** 417 * @} 418 */ 419 420 /* Exported macros -----------------------------------------------------------*/ 421 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros 422 * @{ 423 */ 424 /** @brief Reset QSPI handle state. 425 * @param __HANDLE__ QSPI handle. 426 * @retval None 427 */ 428 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 429 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 430 (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \ 431 (__HANDLE__)->MspInitCallback = NULL; \ 432 (__HANDLE__)->MspDeInitCallback = NULL; \ 433 } while(0) 434 #else 435 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) 436 #endif 437 438 /** @brief Enable the QSPI peripheral. 439 * @param __HANDLE__ specifies the QSPI Handle. 440 * @retval None 441 */ 442 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 443 444 /** @brief Disable the QSPI peripheral. 445 * @param __HANDLE__ specifies the QSPI Handle. 446 * @retval None 447 */ 448 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 449 450 /** @brief Enable the specified QSPI interrupt. 451 * @param __HANDLE__ specifies the QSPI Handle. 452 * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. 453 * This parameter can be one of the following values: 454 * @arg QSPI_IT_TO: QSPI Timeout interrupt 455 * @arg QSPI_IT_SM: QSPI Status match interrupt 456 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 457 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 458 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 459 * @retval None 460 */ 461 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 462 463 464 /** @brief Disable the specified QSPI interrupt. 465 * @param __HANDLE__ specifies the QSPI Handle. 466 * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. 467 * This parameter can be one of the following values: 468 * @arg QSPI_IT_TO: QSPI Timeout interrupt 469 * @arg QSPI_IT_SM: QSPI Status match interrupt 470 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 471 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 472 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 473 * @retval None 474 */ 475 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 476 477 /** @brief Check whether the specified QSPI interrupt source is enabled or not. 478 * @param __HANDLE__ specifies the QSPI Handle. 479 * @param __INTERRUPT__ specifies the QSPI interrupt source to check. 480 * This parameter can be one of the following values: 481 * @arg QSPI_IT_TO: QSPI Timeout interrupt 482 * @arg QSPI_IT_SM: QSPI Status match interrupt 483 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 484 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 485 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 486 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 487 */ 488 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 489 490 /** 491 * @brief Check whether the selected QSPI flag is set or not. 492 * @param __HANDLE__ specifies the QSPI Handle. 493 * @param __FLAG__ specifies the QSPI flag to check. 494 * This parameter can be one of the following values: 495 * @arg QSPI_FLAG_BUSY: QSPI Busy flag 496 * @arg QSPI_FLAG_TO: QSPI Timeout flag 497 * @arg QSPI_FLAG_SM: QSPI Status match flag 498 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag 499 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 500 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 501 * @retval None 502 */ 503 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) 504 505 /** @brief Clears the specified QSPI's flag status. 506 * @param __HANDLE__ specifies the QSPI Handle. 507 * @param __FLAG__ specifies the QSPI clear register flag that needs to be set 508 * This parameter can be one of the following values: 509 * @arg QSPI_FLAG_TO: QSPI Timeout flag 510 * @arg QSPI_FLAG_SM: QSPI Status match flag 511 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 512 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 513 * @retval None 514 */ 515 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 516 /** 517 * @} 518 */ 519 520 /* Exported functions --------------------------------------------------------*/ 521 /** @addtogroup QSPI_Exported_Functions 522 * @{ 523 */ 524 525 /** @addtogroup QSPI_Exported_Functions_Group1 526 * @{ 527 */ 528 /* Initialization/de-initialization functions ********************************/ 529 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); 530 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); 531 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); 532 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); 533 /** 534 * @} 535 */ 536 537 /** @addtogroup QSPI_Exported_Functions_Group2 538 * @{ 539 */ 540 /* IO operation functions *****************************************************/ 541 /* QSPI IRQ handler method */ 542 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); 543 544 /* QSPI indirect mode */ 545 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); 546 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 547 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 548 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); 549 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 550 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 551 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 552 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 553 554 /* QSPI status flag polling mode */ 555 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 556 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); 557 558 /* QSPI memory-mapped mode */ 559 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); 560 561 /* Callback functions in non-blocking modes ***********************************/ 562 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); 563 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); 564 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); 565 566 /* QSPI indirect mode */ 567 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); 568 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); 569 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); 570 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 571 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 572 573 /* QSPI status flag polling mode */ 574 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); 575 576 /* QSPI memory-mapped mode */ 577 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); 578 579 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 580 /* QSPI callback registering/unregistering */ 581 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback); 582 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId); 583 #endif 584 /** 585 * @} 586 */ 587 588 /** @addtogroup QSPI_Exported_Functions_Group3 589 * @{ 590 */ 591 /* Peripheral Control and State functions ************************************/ 592 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); 593 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); 594 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); 595 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); 596 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); 597 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); 598 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); 599 /** 600 * @} 601 */ 602 603 /** 604 * @} 605 */ 606 /* End of exported functions -------------------------------------------------*/ 607 608 /* Private macros ------------------------------------------------------------*/ 609 /** @defgroup QSPI_Private_Macros QSPI Private Macros 610 * @{ 611 */ 612 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) 613 614 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U)) 615 616 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ 617 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) 618 619 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) 620 621 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ 622 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ 623 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ 624 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ 625 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ 626 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ 627 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ 628 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) 629 630 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ 631 ((CLKMODE) == QSPI_CLOCK_MODE_3)) 632 633 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) 634 635 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ 636 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ 637 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ 638 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) 639 640 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ 641 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ 642 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ 643 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) 644 645 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) 646 647 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ 648 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ 649 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ 650 ((MODE) == QSPI_INSTRUCTION_4_LINES)) 651 652 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ 653 ((MODE) == QSPI_ADDRESS_1_LINE) || \ 654 ((MODE) == QSPI_ADDRESS_2_LINES) || \ 655 ((MODE) == QSPI_ADDRESS_4_LINES)) 656 657 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ 658 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ 659 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ 660 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) 661 662 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ 663 ((MODE) == QSPI_DATA_1_LINE) || \ 664 ((MODE) == QSPI_DATA_2_LINES) || \ 665 ((MODE) == QSPI_DATA_4_LINES)) 666 667 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ 668 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) 669 670 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ 671 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) 672 673 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 674 675 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 676 677 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ 678 ((MODE) == QSPI_MATCH_MODE_OR)) 679 680 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ 681 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 682 683 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ 684 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 685 686 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 687 /** 688 * @} 689 */ 690 /* End of private macros -----------------------------------------------------*/ 691 692 /** 693 * @} 694 */ 695 696 /** 697 * @} 698 */ 699 700 #endif /* defined(QUADSPI) */ 701 702 #ifdef __cplusplus 703 } 704 #endif 705 706 #endif /* STM32WBxx_HAL_QSPI_H */ 707
