1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_flash.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBxx_HAL_FLASH_H 21 #define STM32WBxx_HAL_FLASH_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbxx_hal_def.h" 29 30 /** @addtogroup STM32WBxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FLASH 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup FLASH_Exported_Types FLASH Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief FLASH Erase structure definition 45 */ 46 typedef struct 47 { 48 uint32_t TypeErase; /*!< Page erase. 49 This parameter can be a value of @ref FLASH_TYPE_ERASE */ 50 uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled 51 This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */ 52 uint32_t NbPages; /*!< Number of pages to be erased. 53 This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)*/ 54 } FLASH_EraseInitTypeDef; 55 56 /** 57 * @brief FLASH Option Bytes Program structure definition 58 */ 59 typedef struct 60 { 61 uint32_t OptionType; /*!< Option byte to be configured. 62 This parameter can be a combination of the values of @ref FLASH_OB_TYPE */ 63 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). 64 Only one WRP area could be programmed at the same time. 65 This parameter can be value of @ref FLASH_OB_WRP_AREA */ 66 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). 67 This parameter must be a value between 0 and (max number of pages - 1) */ 68 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). 69 This parameter must be a value between WRPStartOffset and (max number of pages - 1) */ 70 uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP). 71 This parameter can be a value of @ref FLASH_OB_READ_PROTECTION */ 72 uint32_t UserType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 73 This parameter can be a combination of @ref FLASH_OB_USER_TYPE */ 74 uint32_t UserConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). 75 This parameter can be a combination of the values of 76 @ref FLASH_OB_USER_AGC_TRIM, @ref FLASH_OB_USER_BOR_LEVEL 77 @ref FLASH_OB_USER_RESET_CONFIG(*), @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*) 78 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, 79 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 80 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 81 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nBOOT1, 82 @ref FLASH_OB_USER_SRAM2PE, @ref FLASH_OB_USER_SRAM2RST, 83 @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0 */ 84 uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). 85 This parameter must be a combination of values of @ref FLASH_OB_PCROP_ZONE 86 and @ref FLASH_OB_PCROP_RDP */ 87 uint32_t PCROP1AStartAddr; /*!< PCROP Zone A Start address (used for OPTIONBYTE_PCROP). It represents first address of start block 88 to protect. Make sure this parameter is multiple of PCROP granularity */ 89 uint32_t PCROP1AEndAddr; /*!< PCROP Zone A End address (used for OPTIONBYTE_PCROP). It represents first address of end block 90 to protect. Make sure this parameter is multiple of PCROP granularity */ 91 uint32_t PCROP1BStartAddr; /*!< PCROP Zone B Start address (used for OPTIONBYTE_PCROP). It represents first address of start block 92 to protect. Make sure this parameter is multiple of PCROP granularity */ 93 uint32_t PCROP1BEndAddr; /*!< PCROP Zone B End address (used for OPTIONBYTE_PCROP). It represents first address of end block 94 to protect. Make sure this parameter is multiple of PCROP granularity */ 95 uint32_t SecureFlashStartAddr; /*!< Secure Flash start address (used for OPTIONBYTE_SECURE_MODE). 96 This parameter must be a value between begin and end of Flash bank 97 => Contains the start address of the first 4kB page of the secure Flash area */ 98 uint32_t SecureRAM2aStartAddr; /*!< Secure Backup RAM2a start address (used for OPTIONBYTE_SECURE_MODE). 99 This parameter can be a value of @ref FLASH_SRAM2A_ADDRESS_RANGE */ 100 uint32_t SecureRAM2bStartAddr; /*!< Secure non-Backup RAM2b start address (used for OPTIONBYTE_SECURE_MODE) 101 This parameter can be a value of @ref FLASH_SRAM2B_ADDRESS_RANGE */ 102 uint32_t SecureMode; /*!< Secure mode activated or deactivated. 103 This parameter can be a value of @ref FLASH_OB_SECURITY_MODE */ 104 uint32_t C2BootRegion; /*!< CPU2 Secure Boot memory region(used for OPTIONBYTE_C2_BOOT_VECT). 105 This parameter can be a value of @ref FLASH_C2_OB_BOOT_REGION */ 106 uint32_t C2SecureBootVectAddr; /*!< CPU2 Secure Boot reset vector (used for OPTIONBYTE_C2_BOOT_VECT). 107 This parameter contains the CPU2 boot reset start address within 108 the selected memory region. Make sure this parameter is word aligned. */ 109 uint32_t IPCCdataBufAddr; /*!< IPCC mailbox data buffer base address (used for OPTIONBYTE_IPCC_BUF_ADDR). 110 This parameter contains the IPCC mailbox data buffer start address area in SRAM2. 111 Make sure this parameter is double-word aligned. */ 112 } FLASH_OBProgramInitTypeDef; 113 114 /** 115 * @brief FLASH handle Structure definition 116 */ 117 typedef struct 118 { 119 HAL_LockTypeDef Lock; /* FLASH locking object */ 120 uint32_t ErrorCode; /* FLASH error code */ 121 uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ 122 uint32_t Address; /* Internal variable to save address selected for program in IT context */ 123 uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ 124 uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ 125 } FLASH_ProcessTypeDef; 126 127 /** 128 * @} 129 */ 130 131 /* Exported constants --------------------------------------------------------*/ 132 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 133 * @{ 134 */ 135 136 /** @defgroup FLASH_KEYS FLASH Keys 137 * @{ 138 */ 139 #define FLASH_KEY1 0x45670123U /*!< Flash key1 */ 140 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 141 to unlock the FLASH registers access */ 142 143 #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ 144 #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 145 to allow option bytes operations */ 146 /** 147 * @} 148 */ 149 150 /** @defgroup FLASH_LATENCY FLASH Latency 151 * @{ 152 */ 153 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 154 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 155 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 156 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 157 /** 158 * @} 159 */ 160 161 /** @defgroup FLASH_FLAGS FLASH Flags Definition 162 * @{ 163 */ 164 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */ 165 #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */ 166 #define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */ 167 #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */ 168 #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */ 169 #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ 170 #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */ 171 #define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */ 172 #define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */ 173 #define FLASH_FLAG_OPTNV FLASH_SR_OPTNV /*!< FLASH User Option OPTVAL indication */ 174 #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */ 175 #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ 176 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ 177 #define FLASH_FLAG_CFGBSY FLASH_SR_CFGBSY /*!< FLASH Programming/erase configuration busy */ 178 #define FLASH_FLAG_PESD FLASH_SR_PESD /*!< FLASH Programming/erase operation suspended */ 179 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ 180 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ 181 182 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 183 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 184 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 185 FLASH_FLAG_OPTVERR) /*!< All SR error flags */ 186 187 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD) 188 189 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) 190 191 /** @defgroup FLASH_INTERRUPT_DEFINITION FLASH Interrupts Definition 192 * @brief FLASH Interrupt definition 193 * @{ 194 */ 195 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ 196 #define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */ 197 #define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source */ 198 #define FLASH_IT_ECCC (FLASH_ECCR_ECCCIE >> FLASH_ECCR_ECCCIE_Pos) /*!< ECC Correction Interrupt source */ 199 /** 200 * @} 201 */ 202 203 /** @defgroup FLASH_ERROR FLASH Error 204 * @{ 205 */ 206 #define HAL_FLASH_ERROR_NONE 0x00000000U 207 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR 208 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR 209 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR 210 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR 211 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR 212 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR 213 #define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR 214 #define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR 215 #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR 216 #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR 217 /** 218 * @} 219 */ 220 221 /** @defgroup FLASH_TYPE_ERASE FLASH Erase Type 222 * @{ 223 */ 224 #define FLASH_TYPEERASE_PAGES FLASH_CR_PER /*!< Pages erase only*/ 225 /** 226 * @} 227 */ 228 229 /** @defgroup FLASH_TYPE_PROGRAM FLASH Program Type 230 * @{ 231 */ 232 #define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG /*!< Program a double-word (64-bit) at a specified address.*/ 233 #define FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG /*!< Fast program a 64 row double-word (64-bit) at a specified address. 234 And another 64 row double-word (64-bit) will be programmed */ 235 /** 236 * @} 237 */ 238 239 /** @defgroup FLASH_OB_TYPE FLASH Option Bytes Type 240 * @{ 241 */ 242 #define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ 243 #define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ 244 #define OPTIONBYTE_USER 0x00000004U /*!< User option byte configuration */ 245 #define OPTIONBYTE_PCROP 0x00000008U /*!< PCROP option byte configuration */ 246 #define OPTIONBYTE_IPCC_BUF_ADDR 0x00000010U /*!< IPCC mailbox buffer address configuration */ 247 #define OPTIONBYTE_C2_BOOT_VECT 0x00000100U /*!< CPU2 Secure Boot reset vector */ 248 #define OPTIONBYTE_SECURE_MODE 0x00000200U /*!< Secure mode on activated or not */ 249 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ 250 OPTIONBYTE_PCROP | OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | \ 251 OPTIONBYTE_SECURE_MODE) /*!< All option byte configuration */ 252 /** 253 * @} 254 */ 255 256 /** @defgroup FLASH_OB_WRP_AREA FLASH WRP Area 257 * @{ 258 */ 259 #define OB_WRPAREA_BANK1_AREAA 0x00000000U /*!< Flash Area A */ 260 #define OB_WRPAREA_BANK1_AREAB 0x00000001U /*!< Flash Area B */ 261 /** 262 * @} 263 */ 264 265 /** @defgroup FLASH_OB_READ_PROTECTION FLASH Option Bytes Read Protection 266 * @{ 267 */ 268 #define OB_RDP_LEVEL_0 0x000000AAU 269 #define OB_RDP_LEVEL_1 0x000000BBU 270 #define OB_RDP_LEVEL_2 0x000000CCU /*!< Warning: When enabling read protection level 2 271 it's no more possible to go back to level 1 or 0 */ 272 /** 273 * @} 274 */ 275 276 /** @defgroup FLASH_OB_USER_TYPE FLASH Option Bytes User Type 277 * @{ 278 */ 279 #define OB_USER_BOR_LEV FLASH_OPTR_BOR_LEV /*!< BOR reset Level */ 280 #define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */ 281 #define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */ 282 #define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering the shutdown mode */ 283 #if defined(FLASH_OPTR_IRHEN) 284 #define OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN /*!< Internal reset holder enable */ 285 #endif /* FLASH_OPTR_IRHEN */ 286 #define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */ 287 #define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */ 288 #define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */ 289 #define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Window watchdog selection */ 290 #define OB_USER_nBOOT1 FLASH_OPTR_nBOOT1 /*!< Boot configuration */ 291 #define OB_USER_SRAM2PE FLASH_OPTR_SRAM2PE /*!< SRAM2 parity check enable */ 292 #define OB_USER_SRAM2RST FLASH_OPTR_SRAM2RST /*!< SRAM2 erase when system reset */ 293 #define OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0 /*!< Software BOOT0 */ 294 #define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */ 295 #if defined(FLASH_OPTR_nRST_MODE) 296 #define OB_USER_NRST_MODE FLASH_OPTR_nRST_MODE /*!< Reset pin configuration */ 297 #endif /* FLASH_OPTR_nRST_MODE */ 298 #define OB_USER_AGC_TRIM FLASH_OPTR_AGC_TRIM /*!< Automatic Gain Control Trimming */ 299 #if defined(FLASH_OPTR_IRHEN) && defined(FLASH_OPTR_nRST_MODE) 300 #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ 301 OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ 302 OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \ 303 OB_USER_SRAM2PE | OB_USER_SRAM2RST | OB_USER_nSWBOOT0 | \ 304 OB_USER_nBOOT0 | OB_USER_AGC_TRIM | OB_USER_NRST_MODE | \ 305 OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */ 306 #else 307 #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ 308 OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ 309 OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \ 310 OB_USER_SRAM2PE | OB_USER_SRAM2RST | OB_USER_nSWBOOT0 | \ 311 OB_USER_nBOOT0 | OB_USER_AGC_TRIM) /*!< all option bits */ 312 #endif /* FLASH_OPTR_IRHEN */ 313 314 /** 315 * @} 316 */ 317 318 /** @defgroup FLASH_OB_USER_AGC_TRIM FLASH Option Bytes Automatic Gain Control Trimming 319 * @{ 320 */ 321 #define OB_AGC_TRIM_0 0x00000000U /*!< Automatic Gain Control Trimming Value 0 */ 322 #define OB_AGC_TRIM_1 FLASH_OPTR_AGC_TRIM_0 /*!< Automatic Gain Control Trimming Value 1 */ 323 #define OB_AGC_TRIM_2 FLASH_OPTR_AGC_TRIM_1 /*!< Automatic Gain Control Trimming Value 2 */ 324 #define OB_AGC_TRIM_3 (FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 3 */ 325 #define OB_AGC_TRIM_4 FLASH_OPTR_AGC_TRIM_2 /*!< Automatic Gain Control Trimming Value 4 */ 326 #define OB_AGC_TRIM_5 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 5 */ 327 #define OB_AGC_TRIM_6 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1) /*!< Automatic Gain Control Trimming Value 6 */ 328 #define OB_AGC_TRIM_7 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 7 */ 329 /** 330 * @} 331 */ 332 333 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level 334 * @{ 335 */ 336 #define OB_BOR_LEVEL_0 0x00000000U /*!< Reset level threshold is around 1.7V */ 337 #define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold is around 2.0V */ 338 #define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold is around 2.2V */ 339 #define OB_BOR_LEVEL_3 (FLASH_OPTR_BOR_LEV_0 | FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.5V */ 340 #define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold is around 2.8V */ 341 /** 342 * @} 343 */ 344 345 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 346 * @{ 347 */ 348 #define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */ 349 #define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */ 350 /** 351 * @} 352 */ 353 354 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby 355 * @{ 356 */ 357 #define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */ 358 #define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */ 359 /** 360 * @} 361 */ 362 363 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown 364 * @{ 365 */ 366 #define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */ 367 #define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */ 368 /** 369 * @} 370 */ 371 372 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 373 * @{ 374 */ 375 #define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ 376 #define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */ 377 /** 378 * @} 379 */ 380 381 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop 382 * @{ 383 */ 384 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */ 385 #define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */ 386 /** 387 * @} 388 */ 389 390 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby 391 * @{ 392 */ 393 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */ 394 #define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */ 395 /** 396 * @} 397 */ 398 399 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 400 * @{ 401 */ 402 #define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ 403 #define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */ 404 /** 405 * @} 406 */ 407 408 /** @defgroup FLASH_OB_USER_SRAM2PE FLASH Option Bytes SRAM2 parity check 409 * @{ 410 */ 411 #define OB_SRAM2_PARITY_ENABLE 0x00000000U /*!< SRAM2 parity check enable */ 412 #define OB_SRAM2_PARITY_DISABLE FLASH_OPTR_SRAM2PE /*!< SRAM2 parity check disable */ 413 /** 414 * @} 415 */ 416 417 /** @defgroup FLASH_OB_USER_SRAM2RST FLASH Option Bytes SRAM2 erase when system reset 418 * @{ 419 */ 420 #define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset */ 421 #define OB_SRAM2_RST_NOT_ERASE FLASH_OPTR_SRAM2RST /*!< SRAM2 is not erased when a system reset */ 422 /** 423 * @} 424 */ 425 426 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type 427 * @{ 428 */ 429 #define OB_BOOT1_SRAM 0x00000000U /*!< Embedded SRAM is selected as boot space (if BOOT0=1) */ 430 #define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1 /*!< System memory is selected as boot space (if BOOT0=1) */ 431 /** 432 * @} 433 */ 434 435 /** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 436 * @{ 437 */ 438 #define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */ 439 #define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from PH3/BOOT0 pin */ 440 /** 441 * @} 442 */ 443 444 /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit 445 * @{ 446 */ 447 #define OB_BOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */ 448 #define OB_BOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */ 449 /** 450 * @} 451 */ 452 453 #if defined(FLASH_OPTR_nRST_MODE) 454 /** @defgroup FLASH_OB_USER_RESET_CONFIG FLASH Option Bytes User reset config bit 455 * @{ 456 */ 457 #define OB_RESET_MODE_INPUT_ONLY FLASH_OPTR_nRST_MODE_0 /*!< Reset pin is in Reset input mode only */ 458 #define OB_RESET_MODE_GPIO FLASH_OPTR_nRST_MODE_1 /*!< Reset pin is in GPIO normal mode only */ 459 #define OB_RESET_MODE_INPUT_OUTPUT (FLASH_OPTR_nRST_MODE_0 | FLASH_OPTR_nRST_MODE_1) /*!< Reset pin is in Reset input and output mode */ 460 /** 461 * @} 462 */ 463 #endif /* FLASH_OPTR_nRST_MODE */ 464 465 #if defined(FLASH_OPTR_IRHEN) 466 /** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit 467 * @{ 468 */ 469 #define OB_IRH_ENABLE 0x00000000U /*!< Internal Reset handler enable */ 470 #define OB_IRH_DISABLE FLASH_OPTR_IRHEN /*!< Internal Reset handler disable */ 471 /** 472 * @} 473 */ 474 #endif /* FLASH_OPTR_IRHEN */ 475 476 /** @defgroup FLASH_OB_PCROP_ZONE FLASH PCROP ZONE 477 * @{ 478 */ 479 #define OB_PCROP_ZONE_A 0x00000001U /*!< PCROP Zone A */ 480 #define OB_PCROP_ZONE_B 0x00000002U /*!< PCROP Zone B */ 481 /** 482 * @} 483 */ 484 485 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type 486 * @{ 487 */ 488 #define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level 489 is decreased from Level 1 to Level 0 */ 490 #define OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP /*!< PCROP area is erased when the RDP level is 491 decreased from Level 1 to Level 0 (full mass erase) */ 492 /** 493 * @} 494 */ 495 496 /** @defgroup FLASH_OB_SECURITY_MODE Option Bytes FLASH Secure mode 497 * @{ 498 */ 499 #define SYSTEM_NOT_IN_SECURE_MODE 0x00000000U /*!< Unsecure mode: Security disabled */ 500 #define SYSTEM_IN_SECURE_MODE FLASH_OPTR_ESE /*!< Secure mode : Security enabled */ 501 /** 502 * @} 503 */ 504 505 /** @defgroup FLASH_C2_OB_BOOT_REGION CPU2 Option Bytes Reset Boot Vector 506 * @{ 507 */ 508 #define OB_C2_BOOT_FROM_SRAM 0x00000000U /*!< CPU2 boot from Sram */ 509 #define OB_C2_BOOT_FROM_FLASH FLASH_SRRVR_C2OPT /*!< CPU2 boot from Flash */ 510 /** 511 * @} 512 */ 513 /** 514 * @} 515 */ 516 517 /** @defgroup FLASH_SRAM2A_ADDRESS_RANGE RAM2A address range in secure mode 518 * @{ 519 */ 520 521 #define SRAM2A_START_SECURE_ADDR_0 (SRAM2A_BASE + 0x0000U) /* When in secure mode (SRAM2A_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 522 #define SRAM2A_START_SECURE_ADDR_1 (SRAM2A_BASE + 0x0400U) /* When in secure mode (SRAM2A_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 523 #define SRAM2A_START_SECURE_ADDR_2 (SRAM2A_BASE + 0x0800U) /* When in secure mode (SRAM2A_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 524 #define SRAM2A_START_SECURE_ADDR_3 (SRAM2A_BASE + 0x0C00U) /* When in secure mode (SRAM2A_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 525 #define SRAM2A_START_SECURE_ADDR_4 (SRAM2A_BASE + 0x1000U) /* When in secure mode (SRAM2A_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 526 #define SRAM2A_START_SECURE_ADDR_5 (SRAM2A_BASE + 0x1400U) /* When in secure mode (SRAM2A_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 527 #define SRAM2A_START_SECURE_ADDR_6 (SRAM2A_BASE + 0x1800U) /* When in secure mode (SRAM2A_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 528 #define SRAM2A_START_SECURE_ADDR_7 (SRAM2A_BASE + 0x1C00U) /* When in secure mode (SRAM2A_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 529 #define SRAM2A_START_SECURE_ADDR_8 (SRAM2A_BASE + 0x2000U) /* When in secure mode (SRAM2A_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 530 #define SRAM2A_START_SECURE_ADDR_9 (SRAM2A_BASE + 0x2400U) /* When in secure mode (SRAM2A_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 531 #define SRAM2A_START_SECURE_ADDR_10 (SRAM2A_BASE + 0x2800U) /* When in secure mode (SRAM2A_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 532 #define SRAM2A_START_SECURE_ADDR_11 (SRAM2A_BASE + 0x2C00U) /* When in secure mode (SRAM2A_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 533 #define SRAM2A_START_SECURE_ADDR_12 (SRAM2A_BASE + 0x3000U) /* When in secure mode (SRAM2A_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 534 #define SRAM2A_START_SECURE_ADDR_13 (SRAM2A_BASE + 0x3400U) /* When in secure mode (SRAM2A_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 535 #define SRAM2A_START_SECURE_ADDR_14 (SRAM2A_BASE + 0x3800U) /* When in secure mode (SRAM2A_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 536 #define SRAM2A_START_SECURE_ADDR_15 (SRAM2A_BASE + 0x3C00U) /* When in secure mode (SRAM2A_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 537 #define SRAM2A_START_SECURE_ADDR_16 (SRAM2A_BASE + 0x4000U) /* When in secure mode (SRAM2A_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 538 #define SRAM2A_START_SECURE_ADDR_17 (SRAM2A_BASE + 0x4400U) /* When in secure mode (SRAM2A_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 539 #define SRAM2A_START_SECURE_ADDR_18 (SRAM2A_BASE + 0x4800U) /* When in secure mode (SRAM2A_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 540 #define SRAM2A_START_SECURE_ADDR_19 (SRAM2A_BASE + 0x4C00U) /* When in secure mode (SRAM2A_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 541 #define SRAM2A_START_SECURE_ADDR_20 (SRAM2A_BASE + 0x5000U) /* When in secure mode (SRAM2A_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 542 #define SRAM2A_START_SECURE_ADDR_21 (SRAM2A_BASE + 0x5400U) /* When in secure mode (SRAM2A_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 543 #define SRAM2A_START_SECURE_ADDR_22 (SRAM2A_BASE + 0x5800U) /* When in secure mode (SRAM2A_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 544 #define SRAM2A_START_SECURE_ADDR_23 (SRAM2A_BASE + 0x5C00U) /* When in secure mode (SRAM2A_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 545 #define SRAM2A_START_SECURE_ADDR_24 (SRAM2A_BASE + 0x6000U) /* When in secure mode (SRAM2A_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 546 #define SRAM2A_START_SECURE_ADDR_25 (SRAM2A_BASE + 0x6400U) /* When in secure mode (SRAM2A_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 547 #define SRAM2A_START_SECURE_ADDR_26 (SRAM2A_BASE + 0x6800U) /* When in secure mode (SRAM2A_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 548 #define SRAM2A_START_SECURE_ADDR_27 (SRAM2A_BASE + 0x6C00U) /* When in secure mode (SRAM2A_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 549 #define SRAM2A_START_SECURE_ADDR_28 (SRAM2A_BASE + 0x7000U) /* When in secure mode (SRAM2A_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 550 #define SRAM2A_START_SECURE_ADDR_29 (SRAM2A_BASE + 0x7400U) /* When in secure mode (SRAM2A_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 551 #define SRAM2A_START_SECURE_ADDR_30 (SRAM2A_BASE + 0x7800U) /* When in secure mode (SRAM2A_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 552 #define SRAM2A_START_SECURE_ADDR_31 (SRAM2A_BASE + 0x7C00U) /* When in secure mode (SRAM2A_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 553 #define SRAM2A_FULL_UNSECURE (SRAM2A_BASE + 0x8000U) /* The RAM2A is accessible to M0 Plus and M4 */ 554 555 /** 556 * @} 557 */ 558 559 /** @defgroup FLASH_SRAM2B_ADDRESS_RANGE RAM2B address range in secure mode 560 * @{ 561 */ 562 563 #define SRAM2B_START_SECURE_ADDR_0 (SRAM2B_BASE + 0x0000U) /* When in secure mode (SRAM2B_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 564 #define SRAM2B_START_SECURE_ADDR_1 (SRAM2B_BASE + 0x0400U) /* When in secure mode (SRAM2B_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 565 #define SRAM2B_START_SECURE_ADDR_2 (SRAM2B_BASE + 0x0800U) /* When in secure mode (SRAM2B_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 566 #define SRAM2B_START_SECURE_ADDR_3 (SRAM2B_BASE + 0x0C00U) /* When in secure mode (SRAM2B_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 567 #if !defined(STM32WB10xx) && !defined(STM32WB15xx) && !defined(STM32WB1Mxx) 568 #define SRAM2B_START_SECURE_ADDR_4 (SRAM2B_BASE + 0x1000U) /* When in secure mode (SRAM2B_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 569 #define SRAM2B_START_SECURE_ADDR_5 (SRAM2B_BASE + 0x1400U) /* When in secure mode (SRAM2B_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 570 #define SRAM2B_START_SECURE_ADDR_6 (SRAM2B_BASE + 0x1800U) /* When in secure mode (SRAM2B_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 571 #define SRAM2B_START_SECURE_ADDR_7 (SRAM2B_BASE + 0x1C00U) /* When in secure mode (SRAM2B_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 572 #define SRAM2B_START_SECURE_ADDR_8 (SRAM2B_BASE + 0x2000U) /* When in secure mode (SRAM2B_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 573 #define SRAM2B_START_SECURE_ADDR_9 (SRAM2B_BASE + 0x2400U) /* When in secure mode (SRAM2B_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 574 #define SRAM2B_START_SECURE_ADDR_10 (SRAM2B_BASE + 0x2800U) /* When in secure mode (SRAM2B_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 575 #define SRAM2B_START_SECURE_ADDR_11 (SRAM2B_BASE + 0x2C00U) /* When in secure mode (SRAM2B_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 576 #define SRAM2B_START_SECURE_ADDR_12 (SRAM2B_BASE + 0x3000U) /* When in secure mode (SRAM2B_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 577 #define SRAM2B_START_SECURE_ADDR_13 (SRAM2B_BASE + 0x3400U) /* When in secure mode (SRAM2B_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 578 #define SRAM2B_START_SECURE_ADDR_14 (SRAM2B_BASE + 0x3800U) /* When in secure mode (SRAM2B_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 579 #define SRAM2B_START_SECURE_ADDR_15 (SRAM2B_BASE + 0x3C00U) /* When in secure mode (SRAM2B_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 580 #define SRAM2B_START_SECURE_ADDR_16 (SRAM2B_BASE + 0x4000U) /* When in secure mode (SRAM2B_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 581 #define SRAM2B_START_SECURE_ADDR_17 (SRAM2B_BASE + 0x4400U) /* When in secure mode (SRAM2B_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 582 #define SRAM2B_START_SECURE_ADDR_18 (SRAM2B_BASE + 0x4800U) /* When in secure mode (SRAM2B_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 583 #define SRAM2B_START_SECURE_ADDR_19 (SRAM2B_BASE + 0x4C00U) /* When in secure mode (SRAM2B_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 584 #define SRAM2B_START_SECURE_ADDR_20 (SRAM2B_BASE + 0x5000U) /* When in secure mode (SRAM2B_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 585 #define SRAM2B_START_SECURE_ADDR_21 (SRAM2B_BASE + 0x5400U) /* When in secure mode (SRAM2B_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 586 #define SRAM2B_START_SECURE_ADDR_22 (SRAM2B_BASE + 0x5800U) /* When in secure mode (SRAM2B_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 587 #define SRAM2B_START_SECURE_ADDR_23 (SRAM2B_BASE + 0x5C00U) /* When in secure mode (SRAM2B_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 588 #define SRAM2B_START_SECURE_ADDR_24 (SRAM2B_BASE + 0x6000U) /* When in secure mode (SRAM2B_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 589 #define SRAM2B_START_SECURE_ADDR_25 (SRAM2B_BASE + 0x6400U) /* When in secure mode (SRAM2B_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 590 #define SRAM2B_START_SECURE_ADDR_26 (SRAM2B_BASE + 0x6800U) /* When in secure mode (SRAM2B_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 591 #define SRAM2B_START_SECURE_ADDR_27 (SRAM2B_BASE + 0x6C00U) /* When in secure mode (SRAM2B_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 592 #define SRAM2B_START_SECURE_ADDR_28 (SRAM2B_BASE + 0x7000U) /* When in secure mode (SRAM2B_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 593 #define SRAM2B_START_SECURE_ADDR_29 (SRAM2B_BASE + 0x7400U) /* When in secure mode (SRAM2B_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 594 #define SRAM2B_START_SECURE_ADDR_30 (SRAM2B_BASE + 0x7800U) /* When in secure mode (SRAM2B_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 595 #define SRAM2B_START_SECURE_ADDR_31 (SRAM2B_BASE + 0x7C00U) /* When in secure mode (SRAM2B_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 596 #define SRAM2B_FULL_UNSECURE (SRAM2B_BASE + 0x8000U) /* The RAM2B is accessible to M0 Plus and M4 */ 597 #else 598 #define SRAM2B_FULL_UNSECURE (SRAM2B_BASE + 0x1000U) /* The RAM2B is accessible to M0 Plus and M4 */ 599 #endif /* !(STM32WB10xx) && !(STM32WB15xx) && !(STM32WB1Mxx) */ 600 601 /** 602 * @} 603 */ 604 605 /** 606 * @} 607 */ 608 609 /* Exported macros -----------------------------------------------------------*/ 610 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros 611 * @brief macros to control FLASH features 612 * @{ 613 */ 614 615 /** 616 * @brief Set the FLASH Latency. 617 * @param __LATENCY__ FLASH Latency 618 * This parameter can be one of the following values : 619 * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state 620 * @arg @ref FLASH_LATENCY_1 FLASH One wait state 621 * @arg @ref FLASH_LATENCY_2 FLASH Two wait states 622 * @arg @ref FLASH_LATENCY_3 FLASH Three wait states 623 * @retval None 624 */ 625 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) 626 627 /** 628 * @brief Get the FLASH Latency. 629 * @retval FLASH Latency 630 * Returned value can be one of the following values : 631 * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state 632 * @arg @ref FLASH_LATENCY_1 FLASH One wait state 633 * @arg @ref FLASH_LATENCY_2 FLASH Two wait states 634 * @arg @ref FLASH_LATENCY_3 FLASH Three wait states 635 */ 636 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) 637 638 /** 639 * @brief Enable the FLASH prefetch buffer. 640 * @retval None 641 */ 642 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 643 644 /** 645 * @brief Disable the FLASH prefetch buffer. 646 * @retval None 647 */ 648 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 649 650 /** 651 * @brief Enable the FLASH instruction cache. 652 * @retval none 653 */ 654 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) 655 656 /** 657 * @brief Disable the FLASH instruction cache. 658 * @retval none 659 */ 660 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) 661 662 /** 663 * @brief Enable the FLASH data cache. 664 * @retval none 665 */ 666 #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) 667 668 /** 669 * @brief Disable the FLASH data cache. 670 * @retval none 671 */ 672 #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) 673 674 /** 675 * @brief Reset the FLASH instruction Cache. 676 * @note This function must be used only when the Instruction Cache is disabled. 677 * @retval None 678 */ 679 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 680 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 681 } while (0) 682 683 /** 684 * @brief Reset the FLASH data Cache. 685 * @note This function must be used only when the data Cache is disabled. 686 * @retval None 687 */ 688 #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 689 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 690 } while (0) 691 692 /** 693 * @} 694 */ 695 696 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros 697 * @brief macros to handle FLASH interrupts 698 * @{ 699 */ 700 701 /** 702 * @brief Enable the specified FLASH interrupt. 703 * @param __INTERRUPT__ FLASH interrupt 704 * This parameter can be any combination of the following values: 705 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 706 * @arg @ref FLASH_IT_OPERR Error Interrupt 707 * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt 708 * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt 709 * @retval none 710 */ 711 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\ 712 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 713 } while(0) 714 715 /** 716 * @brief Disable the specified FLASH interrupt. 717 * @param __INTERRUPT__ FLASH interrupt 718 * This parameter can be any combination of the following values: 719 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 720 * @arg @ref FLASH_IT_OPERR Error Interrupt 721 * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt 722 * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt 723 * @retval none 724 */ 725 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\ 726 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 727 } while(0) 728 729 /** 730 * @brief Check whether the specified FLASH flag is set or not. 731 * @param __FLAG__ specifies the FLASH flag to check. 732 * This parameter can be one of the following values: 733 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 734 * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag 735 * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag 736 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag 737 * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag 738 * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag 739 * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag 740 * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag 741 * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag 742 * @arg @ref FLASH_FLAG_OPTNV FLASH User Option OPTVAL indication 743 * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag 744 * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag 745 * @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag 746 * @arg @ref FLASH_FLAG_CFGBSY Programming/erase configuration busy 747 * @arg @ref FLASH_FLAG_PESD FLASH Programming/erase operation suspended 748 * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected 749 * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected 750 * @retval The new state of FLASH_FLAG (SET or RESET). 751 */ 752 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) ? \ 753 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 754 (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) 755 756 /** 757 * @brief Clear the FLASH's pending flags. 758 * @param __FLAG__ specifies the FLASH flags to clear. 759 * This parameter can be any combination of the following values: 760 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 761 * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag 762 * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag 763 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag 764 * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag 765 * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag 766 * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag 767 * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag 768 * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag 769 * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag 770 * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag 771 * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected 772 * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected 773 * @arg @ref FLASH_FLAG_SR_ERRORS FLASH All SR errors flags 774 * @arg @ref FLASH_FLAG_ECCR_ERRORS FLASH All ECCR errors flags 775 * @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags 776 * @retval None 777 */ 778 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS))); }\ 779 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ 780 } while(0) 781 782 /** 783 * @} 784 */ 785 786 /* Include FLASH HAL Extended module */ 787 #include "stm32wbxx_hal_flash_ex.h" 788 /* Exported variables --------------------------------------------------------*/ 789 /** @defgroup FLASH_Exported_Variables FLASH Exported Variables 790 * @{ 791 */ 792 extern FLASH_ProcessTypeDef pFlash; 793 /** 794 * @} 795 */ 796 797 /* Exported functions --------------------------------------------------------*/ 798 /** @addtogroup FLASH_Exported_Functions 799 * @{ 800 */ 801 802 /* Program operation functions ***********************************************/ 803 /** @addtogroup FLASH_Exported_Functions_Group1 804 * @{ 805 */ 806 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 807 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 808 /* FLASH IRQ handler method */ 809 void HAL_FLASH_IRQHandler(void); 810 /* Callbacks in non blocking modes */ 811 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 812 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 813 /** 814 * @} 815 */ 816 817 /* Peripheral Control functions **********************************************/ 818 /** @addtogroup FLASH_Exported_Functions_Group2 819 * @{ 820 */ 821 HAL_StatusTypeDef HAL_FLASH_Unlock(void); 822 HAL_StatusTypeDef HAL_FLASH_Lock(void); 823 /* Option bytes control */ 824 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 825 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 826 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 827 /** 828 * @} 829 */ 830 831 /* Peripheral State functions ************************************************/ 832 /** @addtogroup FLASH_Exported_Functions_Group3 833 * @{ 834 */ 835 uint32_t HAL_FLASH_GetError(void); 836 /** 837 * @} 838 */ 839 840 /** 841 * @} 842 */ 843 844 /* Private types --------------------------------------------------------*/ 845 /** @defgroup FLASH_Private_types FLASH Private Types 846 * @{ 847 */ 848 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 849 /** 850 * @} 851 */ 852 853 /* Private constants --------------------------------------------------------*/ 854 /** @defgroup FLASH_Private_Constants FLASH Private Constants 855 * @{ 856 */ 857 #define FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE - 1U) 858 859 #define FLASH_BANK_SIZE FLASH_SIZE /*!< FLASH Bank Size */ 860 #if defined(STM32WB10xx) || defined(STM32WB15xx) || defined(STM32WB1Mxx) 861 #define FLASH_PAGE_SIZE 0x00000800U /*!< FLASH Page Size, 2 KBytes */ 862 #else 863 #define FLASH_PAGE_SIZE 0x00001000U /*!< FLASH Page Size, 4 KBytes */ 864 #endif /* STM32WB10xx || STM32WB15xx || STM32WB1Mxx */ 865 #define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE) 866 #define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */ 867 868 #if defined(STM32WB10xx) || defined(STM32WB15xx) || defined(STM32WB1Mxx) 869 #define FLASH_PCROP_GRANULARITY_OFFSET 10U /*!< FLASH Code Readout Protection granularity offset */ 870 #define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 1 KBytes */ 871 #else 872 #define FLASH_PCROP_GRANULARITY_OFFSET 11U /*!< FLASH Code Readout Protection granularity offset */ 873 #define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 2 KBytes */ 874 #endif /* STM32WB10xx || STM32WB15xx || STM32WB1Mxx */ 875 876 #define FLASH_TYPENONE 0x00000000U /*!< No Programmation Procedure On Going */ 877 /** 878 * @} 879 */ 880 881 /** @defgroup SRAM_MEMORY_SIZE SRAM memory size 882 * @{ 883 */ 884 #define SRAM_SECURE_PAGE_GRANULARITY_OFFSET 10U /*!< Secure SRAM2A and SRAM2B Protection granularity offset */ 885 #define SRAM_SECURE_PAGE_GRANULARITY (1UL << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) /*!< Secure SRAM2A and SRAM2B Protection granularity, 1KBytes */ 886 /** 887 * @} 888 */ 889 890 /* Private macros ------------------------------------------------------------*/ 891 /** @defgroup FLASH_Private_Macros FLASH Private Macros 892 * @{ 893 */ 894 #define IS_FLASH_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ 895 ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) 896 897 #define IS_FLASH_FAST_PROGRAM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ 898 ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 256UL)) && (((__VALUE__) % 256UL) == 0UL)) 899 900 #define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ 901 ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) 902 903 #define IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__) (((__VALUE__) >= OTP_AREA_BASE) &&\ 904 ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) 905 906 #define IS_FLASH_PROGRAM_ADDRESS(__VALUE__) (IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) ||\ 907 IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__)) 908 909 #define IS_FLASH_PAGE(__VALUE__) ((__VALUE__) < FLASH_PAGE_NB) 910 911 #define IS_ADDR_ALIGNED_64BITS(__VALUE__) (((__VALUE__) & 0x7U) == (0x00UL)) 912 913 #define IS_FLASH_TYPEERASE(__VALUE__) ((__VALUE__) == FLASH_TYPEERASE_PAGES) 914 915 #define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ 916 ((__VALUE__) == FLASH_TYPEPROGRAM_FAST)) 917 918 #define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ 919 ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)(FLASH_PAGE_SIZE - 1U)) == (__VALUE__))) 920 #define IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2A_BASE) &&\ 921 ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) 922 #define IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2B_BASE) &&\ 923 ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) 924 #define IS_OB_SECURE_MODE(__VALUE__) (((__VALUE__) == SYSTEM_IN_SECURE_MODE) ||\ 925 ((__VALUE__) == SYSTEM_NOT_IN_SECURE_MODE)) 926 927 #define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \ 928 OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | OPTIONBYTE_SECURE_MODE))) 929 930 #define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_BANK1_AREAA) ||\ 931 ((__VALUE__) == OB_WRPAREA_BANK1_AREAB)) 932 933 #define IS_OB_RDP_LEVEL(__VALUE__) (((__VALUE__) == OB_RDP_LEVEL_0) ||\ 934 ((__VALUE__) == OB_RDP_LEVEL_1) ||\ 935 ((__VALUE__) == OB_RDP_LEVEL_2)) 936 937 #define IS_OB_USER_TYPE(__VALUE__) ((((__VALUE__) & OB_USER_ALL) != 0U) && \ 938 (((__VALUE__) & ~OB_USER_ALL) == 0U)) 939 940 #define IS_OB_USER_CONFIG(__TYPE__, __VALUE__) ((((__TYPE__) & OB_USER_BOR_LEV) == OB_USER_BOR_LEV) \ 941 ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_0) || \ 942 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_1) || \ 943 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_2) || \ 944 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_3) || \ 945 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_4)) \ 946 : ((((__TYPE__) & OB_USER_AGC_TRIM) == OB_USER_AGC_TRIM) \ 947 ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_0) || \ 948 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_1) || \ 949 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_2) || \ 950 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_3) || \ 951 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_4) || \ 952 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_5) || \ 953 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_6) || \ 954 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_7)) \ 955 : ((~(__TYPE__) & (__VALUE__)) == 0U))) 956 957 #define IS_OB_USER_AGC_TRIMMING(__VALUE__) (((__VALUE__) == OB_AGC_TRIM_0) || ((__VALUE__) == OB_AGC_TRIM_1) || \ 958 ((__VALUE__) == OB_AGC_TRIM_2) || ((__VALUE__) == OB_AGC_TRIM_3) || \ 959 ((__VALUE__) == OB_AGC_TRIM_4) || ((__VALUE__) == OB_AGC_TRIM_5) || \ 960 ((__VALUE__) == OB_AGC_TRIM_6) || ((__VALUE__) == OB_AGC_TRIM_7)) 961 962 #define IS_OB_USER_BOR_LEVEL(__VALUE__) (((__VALUE__) == OB_BOR_LEVEL_0) || ((__VALUE__) == OB_BOR_LEVEL_1) || \ 963 ((__VALUE__) == OB_BOR_LEVEL_2) || ((__VALUE__) == OB_BOR_LEVEL_3) || \ 964 ((__VALUE__) == OB_BOR_LEVEL_4)) 965 966 #define IS_OB_PCROP_CONFIG(__VALUE__) (((__VALUE__) &\ 967 ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U) 968 969 #define IS_OB_IPCC_BUF_ADDR(__VALUE__) (IS_OB_SBRSA_START_ADDR(__VALUE__) ||\ 970 IS_OB_SNBRSA_START_ADDR(__VALUE__)) 971 972 #define IS_OB_BOOT_VECTOR_ADDR(__VALUE__) ((((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1U))) || \ 973 (((__VALUE__) >= SRAM1_BASE) && ((__VALUE__) <= (SRAM1_BASE + SRAM1_SIZE - 1U))) || \ 974 (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U))) || \ 975 (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)))) 976 977 #define IS_OB_BOOT_REGION(__VALUE__) (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) ||\ 978 ((__VALUE__) == OB_C2_BOOT_FROM_SRAM)) 979 980 #define IS_OB_SECURE_CONFIG(__VALUE__) (((__VALUE__) &\ 981 ~(OB_SECURE_CONFIG_MEMORY | OB_SECURE_CONFIG_BOOT_RESET)) == 0U) 982 983 #define IS_FLASH_LATENCY(__VALUE__) (((__VALUE__) == FLASH_LATENCY_0) || \ 984 ((__VALUE__) == FLASH_LATENCY_1) || \ 985 ((__VALUE__) == FLASH_LATENCY_2) || \ 986 ((__VALUE__) == FLASH_LATENCY_3)) 987 /** 988 * @} 989 */ 990 991 /** 992 * @} 993 */ 994 995 /** 996 * @} 997 */ 998 999 #ifdef __cplusplus 1000 } 1001 #endif 1002 1003 #endif /* STM32WBxx_HAL_FLASH_H */ 1004
