1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBxx_HAL_DMA_H 21 #define STM32WBxx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbxx_hal_def.h" 29 #include "stm32wbxx_ll_dma.h" 30 31 /** @addtogroup STM32WBxx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup DMA 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief DMA Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Request; /*!< Specifies the request selected for the specified channel. 50 This parameter can be a value of @ref DMA_request */ 51 52 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 53 from memory to memory or from peripheral to memory. 54 This parameter can be a value of @ref DMA_Data_transfer_direction */ 55 56 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 57 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 58 59 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 60 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 61 62 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 63 This parameter can be a value of @ref DMA_Peripheral_data_size */ 64 65 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 66 This parameter can be a value of @ref DMA_Memory_data_size */ 67 68 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 69 This parameter can be a value of @ref DMA_mode 70 @note The circular buffer mode cannot be used if the memory-to-memory 71 data transfer is configured on the selected Channel */ 72 73 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 74 This parameter can be a value of @ref DMA_Priority_level */ 75 } DMA_InitTypeDef; 76 77 /** 78 * @brief HAL DMA State structures definition 79 */ 80 typedef enum 81 { 82 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 83 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 84 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 85 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 86 } HAL_DMA_StateTypeDef; 87 88 /** 89 * @brief HAL DMA Error Code structure definition 90 */ 91 typedef enum 92 { 93 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 94 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 95 } HAL_DMA_LevelCompleteTypeDef; 96 97 98 /** 99 * @brief HAL DMA Callback ID structure definition 100 */ 101 typedef enum 102 { 103 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 104 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 105 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 106 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 107 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 108 109 } HAL_DMA_CallbackIDTypeDef; 110 111 /** 112 * @brief DMA handle Structure definition 113 */ 114 typedef struct __DMA_HandleTypeDef 115 { 116 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 117 118 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 119 120 HAL_LockTypeDef Lock; /*!< DMA locking object */ 121 122 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 123 124 void *Parent; /*!< Parent object state */ 125 126 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 127 128 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ 129 130 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 131 132 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ 133 134 __IO uint32_t ErrorCode; /*!< DMA Error code */ 135 136 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 137 138 uint32_t ChannelIndex; /*!< DMA Channel Index */ 139 140 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 141 142 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 143 144 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 145 146 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 147 148 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 149 150 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 151 } DMA_HandleTypeDef; 152 /** 153 * @} 154 */ 155 156 /* Exported constants --------------------------------------------------------*/ 157 158 /** @defgroup DMA_Exported_Constants DMA Exported Constants 159 * @{ 160 */ 161 162 /** @defgroup DMA_Error_Code DMA Error Code 163 * @{ 164 */ 165 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 166 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 167 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 168 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 169 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 170 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 171 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 172 173 /** 174 * @} 175 */ 176 177 /** @defgroup DMA_request DMA request 178 * @{ 179 */ 180 181 #define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM /*!< memory to memory transfer */ 182 183 #define DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0 /*!< DMAMUX request generator 0 */ 184 #define DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1 /*!< DMAMUX request generator 1 */ 185 #define DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2 /*!< DMAMUX request generator 2 */ 186 #define DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3 /*!< DMAMUX request generator 3 */ 187 188 #define DMA_REQUEST_ADC1 LL_DMAMUX_REQ_ADC1 /*!< DMAMUX ADC1 request */ 189 190 #define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */ 191 #define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */ 192 #if defined(SPI2) 193 #define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */ 194 #define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX /*!< DMAMUX SPI2 TX request */ 195 #endif /* SPI2 */ 196 197 #define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */ 198 #define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */ 199 #if defined(I2C3) 200 #define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */ 201 #define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */ 202 #endif /* I2C3 */ 203 204 #define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX /*!< DMAMUX USART1 RX request */ 205 #define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX /*!< DMAMUX USART1 TX request */ 206 207 #if defined(LPUART1) 208 #define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LP_UART1_RX request */ 209 #define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LP_UART1_RX request */ 210 #endif /* LPUART1 */ 211 212 #if defined (SAI1) 213 #define DMA_REQUEST_SAI1_A LL_DMAMUX_REQ_SAI1_A /*!< DMAMUX SAI1 A request */ 214 #define DMA_REQUEST_SAI1_B LL_DMAMUX_REQ_SAI1_B /*!< DMAMUX SAI1 B request */ 215 #endif /* SAI1 */ 216 217 #if defined(QUADSPI) 218 #define DMA_REQUEST_QUADSPI LL_DMAMUX_REQ_QUADSPI /*!< DMAMUX QUADSPI request */ 219 #endif /* QUADSPI */ 220 221 #define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1 /*!< DMAMUX TIM1 CH1 request */ 222 #define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2 /*!< DMAMUX TIM1 CH2 request */ 223 #define DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3 /*!< DMAMUX TIM1 CH3 request */ 224 #define DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4 /*!< DMAMUX TIM1 CH4 request */ 225 #define DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP /*!< DMAMUX TIM1 UP request */ 226 #define DMA_REQUEST_TIM1_TRIG LL_DMAMUX_REQ_TIM1_TRIG /*!< DMAMUX TIM1 TRIG request */ 227 #define DMA_REQUEST_TIM1_COM LL_DMAMUX_REQ_TIM1_COM /*!< DMAMUX TIM1 COM request */ 228 229 #define DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1 /*!< DMAMUX TIM2 CH1 request */ 230 #define DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2 /*!< DMAMUX TIM2 CH2 request */ 231 #define DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3 /*!< DMAMUX TIM2 CH3 request */ 232 #define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */ 233 #define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */ 234 235 #define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */ 236 #define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */ 237 238 #define DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1 /*!< DMAMUX TIM17 CH1 request */ 239 #define DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP /*!< DMAMUX TIM17 UP request */ 240 241 #if defined(AES1) 242 #define DMA_REQUEST_AES1_IN LL_DMAMUX_REQ_AES1_IN /*!< DMAMUX AES1 IN request */ 243 #define DMA_REQUEST_AES1_OUT LL_DMAMUX_REQ_AES1_OUT /*!< DMAMUX AES1 OUT request */ 244 #endif /* AES1 */ 245 246 #define DMA_REQUEST_AES2_IN LL_DMAMUX_REQ_AES2_IN /*!< DMAMUX AES2 IN request */ 247 #define DMA_REQUEST_AES2_OUT LL_DMAMUX_REQ_AES2_OUT /*!< DMAMUX AES2 OUT request */ 248 /** 249 * @} 250 */ 251 252 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 253 * @{ 254 */ 255 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Peripheral to memory direction */ 256 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /*!< Memory to peripheral direction */ 257 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Memory to memory direction */ 258 /** 259 * @} 260 */ 261 262 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 263 * @{ 264 */ 265 #define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT /*!< Peripheral increment mode Enable */ 266 #define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT /*!< Peripheral increment mode Disable */ 267 /** 268 * @} 269 */ 270 271 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 272 * @{ 273 */ 274 #define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT /*!< Memory increment mode Enable */ 275 #define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT /*!< Memory increment mode Disable */ 276 /** 277 * @} 278 */ 279 280 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 281 * @{ 282 */ 283 #define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE /*!< Peripheral data alignment : Byte */ 284 #define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD /*!< Peripheral data alignment : HalfWord */ 285 #define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD /*!< Peripheral data alignment : Word */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup DMA_Memory_data_size DMA Memory data size 291 * @{ 292 */ 293 #define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE /*!< Memory data alignment : Byte */ 294 #define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD /*!< Memory data alignment : HalfWord */ 295 #define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD /*!< Memory data alignment : Word */ 296 /** 297 * @} 298 */ 299 300 /** @defgroup DMA_mode DMA mode 301 * @{ 302 */ 303 #define DMA_NORMAL LL_DMA_MODE_NORMAL /*!< Normal mode */ 304 #define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR /*!< Circular mode */ 305 /** 306 * @} 307 */ 308 309 /** @defgroup DMA_Priority_level DMA Priority level 310 * @{ 311 */ 312 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW /*!< Priority level : Low */ 313 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM /*!< Priority level : Medium */ 314 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH /*!< Priority level : High */ 315 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH /*!< Priority level : Very_High */ 316 /** 317 * @} 318 */ 319 320 321 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 322 * @{ 323 */ 324 #define DMA_IT_TC LL_DMA_CCR_TCIE /*!< Transfer complete interrupt */ 325 #define DMA_IT_HT LL_DMA_CCR_HTIE /*!< Half Transfer interrupt */ 326 #define DMA_IT_TE LL_DMA_CCR_TEIE /*!< Transfer error interrupt */ 327 /** 328 * @} 329 */ 330 331 /** @defgroup DMA_flag_definitions DMA flag definitions 332 * @{ 333 */ 334 #define DMA_FLAG_GL1 LL_DMA_ISR_GIF1 /*!< Channel 1 global flag */ 335 #define DMA_FLAG_TC1 LL_DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ 336 #define DMA_FLAG_HT1 LL_DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ 337 #define DMA_FLAG_TE1 LL_DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ 338 #define DMA_FLAG_GL2 LL_DMA_ISR_GIF2 /*!< Channel 2 global flag */ 339 #define DMA_FLAG_TC2 LL_DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ 340 #define DMA_FLAG_HT2 LL_DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ 341 #define DMA_FLAG_TE2 LL_DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ 342 #define DMA_FLAG_GL3 LL_DMA_ISR_GIF3 /*!< Channel 3 global flag */ 343 #define DMA_FLAG_TC3 LL_DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ 344 #define DMA_FLAG_HT3 LL_DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ 345 #define DMA_FLAG_TE3 LL_DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ 346 #define DMA_FLAG_GL4 LL_DMA_ISR_GIF4 /*!< Channel 4 global flag */ 347 #define DMA_FLAG_TC4 LL_DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ 348 #define DMA_FLAG_HT4 LL_DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ 349 #define DMA_FLAG_TE4 LL_DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ 350 #define DMA_FLAG_GL5 LL_DMA_ISR_GIF5 /*!< Channel 5 global flag */ 351 #define DMA_FLAG_TC5 LL_DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ 352 #define DMA_FLAG_HT5 LL_DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ 353 #define DMA_FLAG_TE5 LL_DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ 354 #define DMA_FLAG_GL6 LL_DMA_ISR_GIF6 /*!< Channel 6 global flag */ 355 #define DMA_FLAG_TC6 LL_DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ 356 #define DMA_FLAG_HT6 LL_DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ 357 #define DMA_FLAG_TE6 LL_DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ 358 #define DMA_FLAG_GL7 LL_DMA_ISR_GIF7 /*!< Channel 7 global flag */ 359 #define DMA_FLAG_TC7 LL_DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ 360 #define DMA_FLAG_HT7 LL_DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ 361 #define DMA_FLAG_TE7 LL_DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ 362 /** 363 * @} 364 */ 365 366 /** 367 * @} 368 */ 369 370 /* Exported macros -----------------------------------------------------------*/ 371 /** @defgroup DMA_Exported_Macros DMA Exported Macros 372 * @{ 373 */ 374 375 /** @brief Reset DMA handle state. 376 * @param __HANDLE__ DMA handle 377 * @retval None 378 */ 379 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 380 381 /** 382 * @brief Enable the specified DMA Channel. 383 * @param __HANDLE__ DMA handle 384 * @retval None 385 */ 386 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 387 388 /** 389 * @brief Disable the specified DMA Channel. 390 * @param __HANDLE__ DMA handle 391 * @retval None 392 */ 393 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 394 395 396 /* Interrupt & Flag management */ 397 398 /** 399 * @brief Return the current DMA Channel transfer complete flag. 400 * @param __HANDLE__ DMA handle 401 * @retval The specified transfer complete flag index. 402 */ 403 404 #if defined(DMA2) 405 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 406 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 407 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 408 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 409 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 410 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 411 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 412 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 413 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 414 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 415 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 416 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 417 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ 418 DMA_FLAG_TC7) 419 #else 420 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 421 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 422 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 423 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 424 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 425 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 426 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 427 DMA_FLAG_TC7) 428 #endif /* DMA2 */ 429 430 /** 431 * @brief Return the current DMA Channel half transfer complete flag. 432 * @param __HANDLE__ DMA handle 433 * @retval The specified half transfer complete flag index. 434 */ 435 #if defined(DMA2) 436 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 437 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 438 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 439 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 440 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 441 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 442 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 443 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 446 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 447 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 448 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ 449 DMA_FLAG_HT7) 450 #else 451 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 452 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 458 DMA_FLAG_HT7) 459 #endif /* DMA2 */ 460 461 /** 462 * @brief Return the current DMA Channel transfer error flag. 463 * @param __HANDLE__ DMA handle 464 * @retval The specified transfer error flag index. 465 */ 466 #if defined(DMA2) 467 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 468 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ 480 DMA_FLAG_TE7) 481 #else 482 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 483 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 489 DMA_FLAG_TE7) 490 #endif /* DMA2 */ 491 492 /** 493 * @brief Return the current DMA Channel Global interrupt flag. 494 * @param __HANDLE__ DMA handle 495 * @retval The specified transfer error flag index. 496 */ 497 #if defined(DMA2) 498 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 499 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ 511 DMA_ISR_GIF7) 512 #else 513 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 514 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 520 DMA_ISR_GIF7) 521 #endif /* DMA2 */ 522 523 /** 524 * @brief Get the DMA Channel pending flags. 525 * @param __HANDLE__ DMA handle 526 * @param __FLAG__ Get the specified flag. 527 * This parameter can be any combination of the following values: 528 * @arg DMA_FLAG_TCx: Transfer complete flag 529 * @arg DMA_FLAG_HTx: Half transfer complete flag 530 * @arg DMA_FLAG_TEx: Transfer error flag 531 * @arg DMA_FLAG_GLx: Global interrupt flag 532 * Where x can be from 1 to 7 to select the DMA Channel x flag. 533 * @retval The state of FLAG (SET or RESET). 534 */ 535 #if defined(DMA2) 536 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 537 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 538 #else 539 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) 540 #endif /* DMA2 */ 541 542 /** 543 * @brief Clear the DMA Channel pending flags. 544 * @param __HANDLE__ DMA handle 545 * @param __FLAG__ specifies the flag to clear. 546 * This parameter can be any combination of the following values: 547 * @arg DMA_FLAG_TCx: Transfer complete flag 548 * @arg DMA_FLAG_HTx: Half transfer complete flag 549 * @arg DMA_FLAG_TEx: Transfer error flag 550 * @arg DMA_FLAG_GLx: Global interrupt flag 551 * Where x can be from 1 to 7 to select the DMA Channel x flag. 552 * @retval None 553 */ 554 #if defined(DMA2) 555 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 556 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 557 #else 558 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) 559 #endif /* DMA2 */ 560 561 /** 562 * @brief Enable the specified DMA Channel interrupts. 563 * @param __HANDLE__ DMA handle 564 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 565 * This parameter can be any combination of the following values: 566 * @arg DMA_IT_TC: Transfer complete interrupt mask 567 * @arg DMA_IT_HT: Half transfer complete interrupt mask 568 * @arg DMA_IT_TE: Transfer error interrupt mask 569 * @retval None 570 */ 571 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 572 573 /** 574 * @brief Disable the specified DMA Channel interrupts. 575 * @param __HANDLE__ DMA handle 576 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 577 * This parameter can be any combination of the following values: 578 * @arg DMA_IT_TC: Transfer complete interrupt mask 579 * @arg DMA_IT_HT: Half transfer complete interrupt mask 580 * @arg DMA_IT_TE: Transfer error interrupt mask 581 * @retval None 582 */ 583 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 584 585 /** 586 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 587 * @param __HANDLE__ DMA handle 588 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 589 * This parameter can be one of the following values: 590 * @arg DMA_IT_TC: Transfer complete interrupt mask 591 * @arg DMA_IT_HT: Half transfer complete interrupt mask 592 * @arg DMA_IT_TE: Transfer error interrupt mask 593 * @retval The state of DMA_IT (SET or RESET). 594 */ 595 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 596 597 /** 598 * @brief Return the number of remaining data units in the current DMA Channel transfer. 599 * @param __HANDLE__ DMA handle 600 * @retval The number of remaining data units in the current DMA Channel transfer. 601 */ 602 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 603 604 /** 605 * @} 606 */ 607 608 /* Include DMA HAL Extension module */ 609 #include "stm32wbxx_hal_dma_ex.h" 610 611 /* Exported functions --------------------------------------------------------*/ 612 613 /** @addtogroup DMA_Exported_Functions 614 * @{ 615 */ 616 617 /** @addtogroup DMA_Exported_Functions_Group1 618 * @{ 619 */ 620 /* Initialization and de-initialization functions *****************************/ 621 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 622 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 623 /** 624 * @} 625 */ 626 627 /** @addtogroup DMA_Exported_Functions_Group2 628 * @{ 629 */ 630 /* IO operation functions *****************************************************/ 631 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 632 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, 633 uint32_t DataLength); 634 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 635 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 636 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, 637 uint32_t Timeout); 638 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 639 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 640 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 641 642 /** 643 * @} 644 */ 645 646 /** @addtogroup DMA_Exported_Functions_Group3 647 * @{ 648 */ 649 /* Peripheral State and Error functions ***************************************/ 650 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 651 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 652 /** 653 * @} 654 */ 655 656 /** 657 * @} 658 */ 659 660 /* Private macros ------------------------------------------------------------*/ 661 /** @defgroup DMA_Private_Macros DMA Private Macros 662 * @{ 663 */ 664 665 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 666 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 667 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 668 669 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 670 671 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 672 ((STATE) == DMA_PINC_DISABLE)) 673 674 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 675 ((STATE) == DMA_MINC_DISABLE)) 676 677 678 #define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_AES2_OUT) 679 680 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 681 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 682 ((SIZE) == DMA_PDATAALIGN_WORD)) 683 684 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 685 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 686 ((SIZE) == DMA_MDATAALIGN_WORD )) 687 688 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 689 ((MODE) == DMA_CIRCULAR)) 690 691 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 692 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 693 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 694 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 695 696 /** 697 * @} 698 */ 699 700 /* Private functions ---------------------------------------------------------*/ 701 702 /** 703 * @} 704 */ 705 706 /** 707 * @} 708 */ 709 710 #ifdef __cplusplus 711 } 712 #endif 713 714 #endif /* STM32WBxx_HAL_DMA_H */ 715
