1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBxx_HAL_ADC_EX_H 21 #define STM32WBxx_HAL_ADC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbxx_hal_def.h" 29 30 /** @addtogroup STM32WBxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 40 * @{ 41 */ 42 43 #if defined(ADC_SUPPORT_2_5_MSPS) 44 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ 45 #else 46 /** 47 * @brief ADC Injected Conversion Oversampling structure definition 48 */ 49 typedef struct 50 { 51 uint32_t Ratio; /*!< Configures the oversampling ratio. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 53 54 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 55 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 56 } ADC_InjOversamplingTypeDef; 57 58 /** 59 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 60 * @note Parameters of this structure are shared within 2 scopes: 61 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset 62 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 63 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. 64 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 65 * ADC state can be either: 66 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') 67 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. 68 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. 69 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 70 * on ADC groups regular and injected. 71 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 72 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 73 */ 74 typedef struct 75 { 76 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 77 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 78 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 79 80 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 81 This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. 82 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 83 the new channel setting (or parameter number of conversions adjusted) */ 84 85 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 86 Unit: ADC clock cycles. 87 Conversion time is the addition of sampling time and processing time 88 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 89 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 90 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 91 It overwrites the last setting. 92 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 93 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 94 Refer to device datasheet for timings values. */ 95 96 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 97 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 98 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 99 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 100 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 101 It overwrites the last setting. 102 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 103 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 104 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 105 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 106 of another parameter update on the fly) */ 107 108 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 109 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 110 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 111 112 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 113 Offset value must be a positive number. 114 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 115 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 116 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 117 without continuous mode or external trigger that could launch a conversion). */ 118 119 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. 120 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 121 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 122 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 123 configure a channel on injected group can impact the configuration of other channels previously set. */ 124 125 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence 126 (main sequence subdivided in successive parts). 127 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 128 Discontinuous mode can be enabled only if continuous mode is disabled. 129 This parameter can be set to ENABLE or DISABLE. 130 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 131 Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). 132 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 133 configure a channel on injected group can impact the configuration of other channels previously set. */ 134 135 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one 136 This parameter can be set to ENABLE or DISABLE. 137 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 138 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) 139 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 140 To maintain JAUTO always enabled, DMA must be configured in circular mode. 141 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 142 configure a channel on injected group can impact the configuration of other channels previously set. */ 143 144 FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 145 This parameter can be set to ENABLE or DISABLE. 146 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a 147 new injected context is set when queue is full, error is triggered by interruption and through function 148 'HAL_ADCEx_InjectedQueueOverflowCallback'. 149 Caution: This feature request that the sequence is fully configured before injected conversion start. 150 Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. 151 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 152 configure a channel on injected group can impact the configuration of other channels previously set. 153 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ 154 155 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 156 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 157 This parameter can be a value of @ref ADC_injected_external_trigger_source. 158 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 159 configure a channel on injected group can impact the configuration of other channels previously set. */ 160 161 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 162 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 163 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 164 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 165 configure a channel on injected group can impact the configuration of other channels previously set. */ 166 167 FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 168 This parameter can be set to ENABLE or DISABLE. 169 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 170 171 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 172 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. 173 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 174 } ADC_InjectionConfTypeDef; 175 #endif /* ADC_SUPPORT_2_5_MSPS */ 176 177 /** 178 * @} 179 */ 180 181 /* Exported constants --------------------------------------------------------*/ 182 183 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 184 * @{ 185 */ 186 187 #if defined(ADC_SUPPORT_2_5_MSPS) 188 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ 189 #else 190 /** @defgroup ADCEx_injected_external_trigger_source ADC group injected trigger source 191 * @{ 192 */ 193 /* ADC group regular trigger sources for all ADC instances */ 194 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ 195 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 196 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 197 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 198 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 199 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 200 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 201 /** 202 * @} 203 */ 204 205 /** @defgroup ADCEx_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 206 * @{ 207 */ 208 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ 209 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ 210 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ 211 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 212 /** 213 * @} 214 */ 215 #endif /* ADC_SUPPORT_2_5_MSPS */ 216 217 /** @defgroup ADCEx_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 218 * @{ 219 */ 220 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ 221 #if !defined(ADC_SUPPORT_2_5_MSPS) 222 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ 223 #endif /* !ADC_SUPPORT_2_5_MSPS */ 224 /** 225 * @} 226 */ 227 228 /** @defgroup ADCEx_HAL_EC_OFFSET_NB ADC instance - Offset number 229 * @{ 230 */ 231 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ 232 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 233 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 234 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 235 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 236 /** 237 * @} 238 */ 239 240 #if defined(ADC_SUPPORT_2_5_MSPS) 241 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ 242 #else 243 /** @defgroup ADCEx_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 244 * @{ 245 */ 246 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 247 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 248 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 249 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 250 /** 251 * @} 252 */ 253 #endif /* ADC_SUPPORT_2_5_MSPS */ 254 255 /** @defgroup ADCEx_HAL_EC_GROUPS ADC instance - Groups 256 * @{ 257 */ 258 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ 259 #if defined(ADC_SUPPORT_2_5_MSPS) 260 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ 261 #else 262 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ 263 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 264 #endif /* ADC_SUPPORT_2_5_MSPS */ 265 /** 266 * @} 267 */ 268 269 /** @defgroup ADCEx_CFGR_fields ADCx CFGR fields 270 * @{ 271 */ 272 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 273 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 274 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 275 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 276 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 277 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) 278 /** 279 * @} 280 */ 281 282 /** @defgroup ADCEx_SMPR1_fields ADCx SMPR1 fields 283 * @{ 284 */ 285 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 286 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 287 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 288 ADC_SMPR1_SMP0) 289 /** 290 * @} 291 */ 292 293 /** @defgroup ADCEx_CFGR_fields_2 ADCx CFGR sub fields 294 * @{ 295 */ 296 /* ADC_CFGR fields of parameters that can be updated when no conversion 297 (neither regular nor injected) is on-going */ 298 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) 299 /** 300 * @} 301 */ 302 303 304 /** 305 * @} 306 */ 307 308 /* Exported macros -----------------------------------------------------------*/ 309 310 /* Private macros ------------------------------------------------------------*/ 311 312 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 313 * @{ 314 */ 315 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 316 /* code of final user. */ 317 318 /** 319 * @brief Test if conversion trigger of injected group is software start 320 * or external trigger. 321 * @param __HANDLE__ ADC handle. 322 * @retval SET (software start) or RESET (external trigger). 323 */ 324 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 325 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) 326 327 /** 328 * @brief Check whether or not ADC is independent. 329 * @param __HANDLE__ ADC handle. 330 * @note When multimode feature is not available, the macro always returns SET. 331 * @retval SET (ADC is independent) or RESET (ADC is not). 332 */ 333 #define ADC_IS_INDEPENDENT(__HANDLE__) (SET) 334 335 #if defined(ADC_SUPPORT_2_5_MSPS) 336 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ 337 #else 338 /** 339 * @brief Set the selected injected Channel rank. 340 * @param __CHANNELNB__ Channel number. 341 * @param __RANKNB__ Rank number. 342 * @retval None 343 */ 344 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) 345 346 /** 347 * @brief Configure ADC injected context queue 348 * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. 349 * @retval None 350 */ 351 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) 352 353 /** 354 * @brief Configure ADC discontinuous conversion mode for injected group 355 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 356 * @retval None 357 */ 358 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) 359 #endif /* ADC_SUPPORT_2_5_MSPS */ 360 361 /** 362 * @brief Configure ADC discontinuous conversion mode for regular group 363 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 364 * @retval None 365 */ 366 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) 367 368 /** 369 * @brief Configure the number of discontinuous conversions for regular group. 370 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 371 * @retval None 372 */ 373 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) 374 375 /** 376 * @brief Configure the ADC auto delay mode. 377 * @param __AUTOWAIT__ Auto delay bit enable or disable. 378 * @retval None 379 */ 380 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) 381 382 /** 383 * @brief Configure ADC continuous conversion mode. 384 * @param __CONTINUOUS_MODE__ Continuous mode. 385 * @retval None 386 */ 387 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) 388 389 #if defined(ADC_SUPPORT_2_5_MSPS) 390 /** 391 * @brief Enable ADC overrun mode. 392 * @param _OVERRUN_MODE_ Overrun mode. 393 * @retval Overrun bit setting to be programmed into CFGR register 394 */ 395 /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ 396 /* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ 397 /* as the default case to be compliant with other STM32 devices. */ 398 #define ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \ 399 ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ 400 )? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \ 401 ) 402 403 /** 404 * @brief Enable the ADC auto off mode. 405 * @param _AUTOOFF_ Auto off bit enable or disable. 406 * @retval None 407 */ 408 #define ADC_CFGR_AUTOOFF(_AUTOOFF_) \ 409 ((_AUTOOFF_) << 15UL) 410 411 /** 412 * @brief Set ADC scan mode with differentiation of sequencer setting 413 * fixed or configurable 414 * @param _SCAN_MODE_ Scan conversion mode. 415 * @retval None 416 */ 417 /* Note: Scan mode set using this macro (instead of parameter direct set) */ 418 /* due to different modes on other STM32 devices: */ 419 /* if scan mode is disabled, sequencer is set to fully configurable */ 420 /* with setting of only rank 1 enabled afterwards. */ 421 #define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \ 422 ( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL \ 423 )? \ 424 ((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT)) \ 425 : \ 426 (ADC_CFGR1_CHSELRMOD) \ 427 ) 428 429 #endif /* ADC_SUPPORT_2_5_MSPS */ 430 /** 431 * @brief Configure the ADC DMA continuous request. 432 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 433 * @retval None 434 */ 435 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos) 436 437 438 /** 439 * @brief Shift the offset with respect to the selected ADC resolution. 440 * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. 441 * If resolution 12 bits, no shift. 442 * If resolution 10 bits, shift of 2 ranks on the left. 443 * If resolution 8 bits, shift of 4 ranks on the left. 444 * If resolution 6 bits, shift of 6 ranks on the left. 445 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 446 * @param __HANDLE__ ADC handle 447 * @param __OFFSET__ Value to be shifted 448 * @retval None 449 */ 450 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 451 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 452 453 /** 454 * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. 455 * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 456 * If resolution 12 bits, no shift. 457 * If resolution 10 bits, shift of 2 ranks on the left. 458 * If resolution 8 bits, shift of 4 ranks on the left. 459 * If resolution 6 bits, shift of 6 ranks on the left. 460 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 461 * @param __HANDLE__ ADC handle 462 * @param __THRESHOLD__ Value to be shifted 463 * @retval None 464 */ 465 #if defined(ADC_SUPPORT_2_5_MSPS) 466 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 467 ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3UL) * 2UL)) 468 #else 469 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 470 ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 471 #endif /* ADC_SUPPORT_2_5_MSPS */ 472 473 /** 474 * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. 475 * @note Thresholds have to be left-aligned on bit 7. 476 * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). 477 * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). 478 * If resolution 8 bits, no shift. 479 * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). 480 * @param __HANDLE__ ADC handle 481 * @param __THRESHOLD__ Value to be shifted 482 * @retval None 483 */ 484 #if defined(ADC_SUPPORT_2_5_MSPS) 485 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 486 ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) != (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0)) ? \ 487 ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ 488 ((__THRESHOLD__) << 2UL) \ 489 ) 490 #else 491 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 492 ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ 493 ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ 494 ((__THRESHOLD__) << 2UL) \ 495 ) 496 #endif /* ADC_SUPPORT_2_5_MSPS */ 497 498 /** 499 * @brief Clear Common Control Register. 500 * @param __HANDLE__ ADC handle. 501 * @retval None 502 */ 503 #if defined(ADC_SUPPORT_2_5_MSPS) 504 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ 505 ADC_CCR_PRESC | \ 506 ADC_CCR_VBATEN | \ 507 ADC_CCR_TSEN | \ 508 ADC_CCR_VREFEN ) 509 #else 510 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ 511 ADC_CCR_PRESC | \ 512 ADC_CCR_VBATEN | \ 513 ADC_CCR_TSEN | \ 514 ADC_CCR_VREFEN ) 515 #endif /* ADC_SUPPORT_2_5_MSPS */ 516 517 518 /** 519 * @brief Verify the ADC instance connected to the temperature sensor. 520 * @param __HANDLE__ ADC handle. 521 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 522 */ 523 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 524 525 /** 526 * @brief Verify the ADC instance connected to the battery voltage VBAT. 527 * @param __HANDLE__ ADC handle. 528 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 529 */ 530 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 531 532 /** 533 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 534 * @param __HANDLE__ ADC handle. 535 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 536 */ 537 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 538 539 #if defined(ADC_SUPPORT_2_5_MSPS) 540 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ 541 #else 542 /** 543 * @brief Verify the length of scheduled injected conversions group. 544 * @param __LENGTH__ number of programmed conversions. 545 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) 546 */ 547 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 548 #endif /* ADC_SUPPORT_2_5_MSPS */ 549 550 /** 551 * @brief Calibration factor size verification (7 bits maximum). 552 * @param __CALIBRATION_FACTOR__ Calibration factor value. 553 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 554 */ 555 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) 556 557 558 /** 559 * @brief Verify the ADC channel setting. 560 * @param __HANDLE__ ADC handle. 561 * @param __CHANNEL__ programmed ADC channel. 562 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 563 */ 564 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \ 565 (((__CHANNEL__) == ADC_CHANNEL_0) || \ 566 ((__CHANNEL__) == ADC_CHANNEL_1) || \ 567 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 568 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 569 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 570 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 571 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 572 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 573 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 574 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 575 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 576 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 577 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 578 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 579 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 580 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 581 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 582 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 583 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 584 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 585 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 586 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) 587 588 /** 589 * @brief Verify the ADC channel setting in differential mode. 590 * @param __HANDLE__ ADC handle. 591 * @param __CHANNEL__ programmed ADC channel. 592 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 593 */ 594 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 595 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 596 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 597 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 598 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 599 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 600 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 601 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 602 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 603 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 604 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 605 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 606 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 607 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 608 ((__CHANNEL__) == ADC_CHANNEL_15) ) 609 610 /** 611 * @brief Verify the ADC single-ended input or differential mode setting. 612 * @param __SING_DIFF__ programmed channel setting. 613 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 614 */ 615 #if defined(ADC_SUPPORT_2_5_MSPS) 616 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) ((__SING_DIFF__) == ADC_SINGLE_ENDED) 617 #else 618 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 619 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 620 #endif /* ADC_SUPPORT_2_5_MSPS */ 621 622 /** 623 * @brief Verify the ADC offset management setting. 624 * @param __OFFSET_NUMBER__ ADC offset management. 625 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 626 */ 627 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 628 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 629 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 630 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 631 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 632 633 #if defined(ADC_SUPPORT_2_5_MSPS) 634 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ 635 #else 636 /** 637 * @brief Verify the ADC injected channel setting. 638 * @param __CHANNEL__ programmed ADC injected channel. 639 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 640 */ 641 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 642 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 643 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 644 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 645 646 /** 647 * @brief Verify the ADC injected conversions external trigger. 648 * @param __HANDLE__ ADC handle. 649 * @param __INJTRIG__ programmed ADC injected conversions external trigger. 650 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 651 */ 652 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 653 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 654 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 655 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 656 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 657 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 658 ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) 659 660 /** 661 * @brief Verify the ADC edge trigger setting for injected group. 662 * @param __EDGE__ programmed ADC edge trigger setting. 663 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 664 */ 665 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 666 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 667 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 668 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 669 #endif /* ADC_SUPPORT_2_5_MSPS */ 670 671 /** 672 * @brief Verify the ADC analog watchdog setting. 673 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 674 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 675 */ 676 #if defined(ADC_SUPPORT_2_5_MSPS) 677 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) 678 #else 679 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 680 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 681 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 682 #endif /* ADC_SUPPORT_2_5_MSPS */ 683 684 /** 685 * @brief Verify the ADC analog watchdog mode setting. 686 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 687 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 688 */ 689 #if defined(ADC_SUPPORT_2_5_MSPS) 690 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 691 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 692 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) ) 693 #else 694 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 695 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 696 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 697 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 698 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 699 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 700 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 701 #endif /* ADC_SUPPORT_2_5_MSPS */ 702 703 #if defined(ADC_SUPPORT_2_5_MSPS) 704 #define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \ 705 ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) ) 706 #endif /* ADC_SUPPORT_2_5_MSPS */ 707 708 /** 709 * @brief Verify the ADC conversion (regular or injected or both). 710 * @param __CONVERSION__ ADC conversion group. 711 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 712 */ 713 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 714 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 715 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 716 717 /** 718 * @brief Verify the ADC event type. 719 * @param __EVENT__ ADC event. 720 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 721 */ 722 #if defined(ADC_SUPPORT_2_5_MSPS) 723 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 724 ((__EVENT__) == ADC_AWD1_EVENT) || \ 725 ((__EVENT__) == ADC_AWD2_EVENT) || \ 726 ((__EVENT__) == ADC_AWD3_EVENT) || \ 727 ((__EVENT__) == ADC_OVR_EVENT) ) 728 #else 729 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 730 ((__EVENT__) == ADC_AWD_EVENT) || \ 731 ((__EVENT__) == ADC_AWD2_EVENT) || \ 732 ((__EVENT__) == ADC_AWD3_EVENT) || \ 733 ((__EVENT__) == ADC_OVR_EVENT) || \ 734 ((__EVENT__) == ADC_JQOVF_EVENT) ) 735 #endif /* ADC_SUPPORT_2_5_MSPS */ 736 737 #if defined(ADC_SUPPORT_2_5_MSPS) 738 /* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */ 739 #else 740 /** 741 * @brief Verify the ADC oversampling ratio. 742 * @param __RATIO__ programmed ADC oversampling ratio. 743 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) 744 */ 745 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ 746 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ 747 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ 748 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ 749 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ 750 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ 751 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ 752 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) 753 #endif /* ADC_SUPPORT_2_5_MSPS */ 754 755 /** 756 * @brief Verify the ADC oversampling shift. 757 * @param __SHIFT__ programmed ADC oversampling shift. 758 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 759 */ 760 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 761 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 762 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 763 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 764 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 765 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 766 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 767 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 768 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) 769 770 /** 771 * @brief Verify the ADC oversampling triggered mode. 772 * @param __MODE__ programmed ADC oversampling triggered mode. 773 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 774 */ 775 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 776 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 777 778 #if defined(ADC_SUPPORT_2_5_MSPS) 779 #else 780 /** 781 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 782 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 783 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 784 */ 785 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 786 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 787 #endif /* ADC_SUPPORT_2_5_MSPS */ 788 789 /** 790 * @brief Verify the DFSDM mode configuration. 791 * @param __HANDLE__ ADC handle. 792 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For 793 * this reason, the input parameter is the ADC handle and not the configuration parameter 794 * directly. 795 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) 796 */ 797 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) 798 799 /** 800 * @brief Return the DFSDM configuration mode. 801 * @param __HANDLE__ ADC handle. 802 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 803 * For this reason, the input parameter is the ADC handle and not the configuration parameter 804 * directly. 805 * @retval DFSDM configuration mode 806 */ 807 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) 808 809 /** 810 * @} 811 */ 812 813 814 /* Exported functions --------------------------------------------------------*/ 815 /** @addtogroup ADCEx_Exported_Functions 816 * @{ 817 */ 818 819 /** @addtogroup ADCEx_Exported_Functions_Group1 820 * @{ 821 */ 822 /* IO operation functions *****************************************************/ 823 824 /* ADC calibration */ 825 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 826 uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 827 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, 828 uint32_t CalibrationFactor); 829 830 #if defined(ADC_SUPPORT_2_5_MSPS) 831 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ 832 #else 833 /* Blocking mode: Polling */ 834 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); 835 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); 836 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 837 838 /* Non-blocking mode: Interruption */ 839 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); 840 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); 841 #endif /* ADC_SUPPORT_2_5_MSPS */ 842 843 #if defined(ADC_SUPPORT_2_5_MSPS) 844 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ 845 #else 846 /* ADC retrieve conversion value intended to be used with polling or interruption */ 847 uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank); 848 #endif /* ADC_SUPPORT_2_5_MSPS */ 849 850 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 851 #if defined(ADC_SUPPORT_2_5_MSPS) 852 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ 853 #else 854 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); 855 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); 856 #endif /* ADC_SUPPORT_2_5_MSPS */ 857 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); 858 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); 859 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); 860 861 #if defined(ADC_SUPPORT_2_5_MSPS) 862 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ 863 #else 864 /* ADC group regular conversions stop */ 865 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); 866 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); 867 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); 868 #endif /* ADC_SUPPORT_2_5_MSPS */ 869 /** 870 * @} 871 */ 872 873 /** @addtogroup ADCEx_Exported_Functions_Group2 874 * @{ 875 */ 876 /* Peripheral Control functions ***********************************************/ 877 #if defined(ADC_SUPPORT_2_5_MSPS) 878 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ 879 #else 880 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, const ADC_InjectionConfTypeDef* sConfigInjected); 881 #endif /* ADC_SUPPORT_2_5_MSPS */ 882 #if defined(ADC_SUPPORT_2_5_MSPS) 883 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ 884 #else 885 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); 886 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); 887 #endif /* ADC_SUPPORT_2_5_MSPS */ 888 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); 889 #if defined(ADC_SUPPORT_2_5_MSPS) 890 /* Feature " ADC deep power-down" not available on ADC peripheral of this STM32WB device */ 891 #else 892 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); 893 #endif /* ADC_SUPPORT_2_5_MSPS */ 894 895 /** 896 * @} 897 */ 898 899 /** 900 * @} 901 */ 902 903 /** 904 * @} 905 */ 906 907 /** 908 * @} 909 */ 910 911 #ifdef __cplusplus 912 } 913 #endif 914 915 #endif /* STM32WBxx_HAL_ADC_EX_H */ 916
