1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBxx_HAL_ADC_H 21 #define STM32WBxx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbxx_hal_def.h" 29 30 /* Include low level driver */ 31 #include "stm32wbxx_ll_adc.h" 32 33 /** @addtogroup STM32WBxx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ADC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup ADC_Exported_Types ADC Exported Types 43 * @{ 44 */ 45 46 #if defined(ADC_SUPPORT_2_5_MSPS) 47 /* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */ 48 #else 49 /** 50 * @brief ADC group regular oversampling structure definition 51 */ 52 typedef struct 53 { 54 uint32_t Ratio; /*!< Configures the oversampling ratio. 55 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 56 57 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 58 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 59 60 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 61 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 62 63 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 64 The oversampling is either temporary stopped or reset upon an injected 65 sequence interruption. 66 If oversampling is enabled on both regular and injected groups, this parameter 67 is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" 68 (the oversampling buffer is zeroed during injection sequence). 69 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ 70 71 } ADC_OversamplingTypeDef; 72 #endif /* ADC_SUPPORT_2_5_MSPS */ 73 74 /** 75 * @brief Structure definition of ADC instance and ADC group regular. 76 * @note Parameters of this structure are shared within 2 scopes: 77 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 78 * ScanConvMode, EOCSelection, LowPowerAutoWait. 79 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, 80 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 81 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 82 * ADC state can be either: 83 * - For all parameters: ADC disabled 84 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular. 85 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. 86 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 87 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter 88 * (which fulfills the ADC state condition) on the fly). 89 */ 90 typedef struct 91 { 92 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. 93 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 94 Note: The ADC clock configuration is common to all ADC instances. 95 Note: ADC clock source and prescaler must be selected in function of system clock to not exceed ADC maximum frequency, depending on devices. 96 Example: STM32WB55xx ADC maximum frequency is 64MHz (corresponding to 4.27Msmp/s maximum) 97 Example: STM32WB50xx ADC maximum frequency is 32MHz (corresponding to 2.13Msmp/s maximum) 98 For ADC maximum frequency, refer to datasheet of the selected device. 99 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 100 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. 101 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only 102 if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 103 must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. 104 Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. 105 Note: This parameter can be modified only if all ADC instances are disabled. */ 106 107 uint32_t Resolution; /*!< Configure the ADC resolution. 108 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 109 110 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 111 Refer to reference manual for alignments formats versus resolutions. 112 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ 113 114 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 115 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 116 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 117 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 118 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). 119 Scan direction is upward: from rank 1 to rank 'n'. 120 This parameter can be a value of @ref ADC_Scan_mode */ 121 122 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. 123 This parameter can be a value of @ref ADC_EOCSelection. */ 124 125 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous 126 conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, 127 using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). 128 This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun 129 for low frequency applications. 130 This parameter can be set to ENABLE or DISABLE. 131 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). 132 Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). 133 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: 134 use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. 135 (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ 136 137 #if defined(ADC_SUPPORT_2_5_MSPS) 138 FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). 139 This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). 140 This parameter can be set to ENABLE or DISABLE. 141 Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ 142 143 #endif /* ADC_SUPPORT_2_5_MSPS */ 144 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, 145 after the first ADC conversion start trigger occurred (software start or external trigger). 146 This parameter can be set to ENABLE or DISABLE. */ 147 148 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. 149 To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 150 This parameter must be a number between Min_Data = 1 and Max_Data = 16. 151 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without 152 continuous mode or external trigger that could launch a conversion). */ 153 154 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence 155 (main sequence subdivided in successive parts). 156 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 157 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 158 This parameter can be set to ENABLE or DISABLE. */ 159 160 #if defined(ADC_SUPPORT_2_5_MSPS) 161 /* Feature "ADC group regular number of discontinuous conversions" not available on ADC peripheral of this STM32WB device */ 162 #else 163 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. 164 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 165 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 166 #endif /* ADC_SUPPORT_2_5_MSPS */ 167 168 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. 169 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 170 This parameter can be a value of @ref ADC_regular_external_trigger_source. 171 Caution: external trigger source is common to all ADC instances. */ 172 173 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. 174 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 175 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 176 177 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) 178 or in continuous mode (DMA transfer unlimited, whatever number of conversions). 179 This parameter can be set to ENABLE or DISABLE. 180 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ 181 182 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 183 This parameter applies to ADC group regular only. 184 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 185 Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 186 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 187 HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). 188 Note: Error reporting with respect to the conversion mode: 189 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 190 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. 191 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ 192 193 #if defined(ADC_SUPPORT_2_5_MSPS) 194 uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels. 195 Unit: ADC clock cycles 196 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 197 Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. 198 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME_INST_SCOPE 199 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 200 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 201 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */ 202 203 uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible. 204 Unit: ADC clock cycles 205 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 206 Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. 207 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME_INST_SCOPE 208 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 209 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 210 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */ 211 #endif /* ADC_SUPPORT_2_5_MSPS */ 212 213 #if !defined(ADC_SUPPORT_2_5_MSPS) 214 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 215 This parameter can be set to ENABLE or DISABLE. 216 Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */ 217 218 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 219 Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ 220 #endif /* !ADC_SUPPORT_2_5_MSPS */ 221 222 #if defined(ADC_SUPPORT_2_5_MSPS) 223 uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode. 224 This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ. 225 Note: ADC trigger frequency mode must be set to low frequency when 226 a duration is exceeded before ADC conversion start trigger event 227 (between ADC enable and ADC conversion start trigger event 228 or between two ADC conversion start trigger event). 229 Duration value: Refer to device datasheet, parameter "tIdle". 230 Note: When ADC trigger frequency mode is set to low frequency, 231 some rearm cycles are inserted before performing ADC conversion 232 start, inducing a delay of 2 ADC clock cycles. */ 233 #endif /* ADC_SUPPORT_2_5_MSPS */ 234 235 } ADC_InitTypeDef; 236 237 /** 238 * @brief Structure definition of ADC channel for regular group 239 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 240 * ADC state can be either: 241 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 242 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. 243 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. 244 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 245 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) 246 * on the fly). 247 */ 248 typedef struct 249 { 250 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 251 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 252 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 253 254 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 255 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS 256 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 257 the new channel setting (or parameter number of conversions adjusted) */ 258 259 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 260 Unit: ADC clock cycles 261 Conversion time is the addition of sampling time and processing time 262 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 263 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 264 Caution: This parameter applies to a channel that can be used into regular and/or injected group. 265 It overwrites the last setting. 266 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 267 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 268 Refer to device datasheet for timings values. */ 269 270 #if !defined(ADC_SUPPORT_2_5_MSPS) 271 uint32_t SingleDiff; /*!< Select single-ended or differential input. 272 In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 273 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 274 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 275 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 276 It overwrites the last setting. 277 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 278 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 279 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 280 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 281 of another parameter update on the fly) */ 282 283 uint32_t OffsetNumber; /*!< Select the offset number 284 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 285 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 286 287 uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. 288 Offset value must be a positive number. 289 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 290 0x3FF, 0xFF or 0x3F respectively. 291 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 292 without continuous mode or external trigger that could launch a conversion). */ 293 294 #endif /* !ADC_SUPPORT_2_5_MSPS */ 295 } ADC_ChannelConfTypeDef; 296 297 /** 298 * @brief Structure definition of ADC analog watchdog 299 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 300 * ADC state can be either: 301 * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. 302 */ 303 typedef struct 304 { 305 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 306 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') 307 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel). Note: Analog Watchdog 2 and 3 are not available on devices: STM32WB10xx, STM32WB15xx, , STM32WB1Mxx. 308 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 309 310 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 311 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. 312 For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. 313 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 314 315 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 316 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). 317 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). 318 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 319 320 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 321 This parameter can be set to ENABLE or DISABLE */ 322 323 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 324 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 325 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 326 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 327 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 328 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 329 impacted: the comparison of analog watchdog thresholds is done on 330 oversampling final computation (after ratio and shift application): 331 ADC data register bitfield [15:4] (12 most significant bits). */ 332 333 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 334 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 335 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 336 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 337 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 338 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 339 impacted: the comparison of analog watchdog thresholds is done on 340 oversampling final computation (after ratio and shift application): 341 ADC data register bitfield [15:4] (12 most significant bits). */ 342 } ADC_AnalogWDGConfTypeDef; 343 344 /** 345 * @brief ADC group injected contexts queue configuration 346 * @note Structure intended to be used only through structure "ADC_HandleTypeDef" 347 */ 348 typedef struct 349 { 350 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 351 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 352 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 353 354 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 355 } ADC_InjectionConfigTypeDef; 356 357 /** @defgroup ADC_States ADC States 358 * @{ 359 */ 360 361 /** 362 * @brief HAL ADC state machine: ADC states definition (bitfields) 363 * @note ADC state machine is managed by bitfields, state must be compared 364 * with bit by bit. 365 * For example: 366 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 367 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 368 */ 369 /* States of ADC global scope */ 370 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 371 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 372 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ 373 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 374 375 /* States of ADC errors */ 376 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 377 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 378 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 379 380 /* States of ADC group regular */ 381 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, 382 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 383 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 384 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 385 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ 386 387 /* States of ADC group injected */ 388 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, 389 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 390 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ 391 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ 392 393 /* States of ADC analog watchdogs */ 394 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 395 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 396 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 397 398 /* States of ADC multi-mode */ 399 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave state, controlled by another ADC master (when feature available) */ 400 401 402 /** 403 * @} 404 */ 405 406 /** 407 * @brief ADC handle Structure definition 408 */ 409 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 410 typedef struct __ADC_HandleTypeDef 411 #else 412 typedef struct 413 #endif 414 { 415 ADC_TypeDef *Instance; /*!< Register base address */ 416 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ 417 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 418 HAL_LockTypeDef Lock; /*!< ADC locking object */ 419 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 420 __IO uint32_t ErrorCode; /*!< ADC Error code */ 421 #if defined(ADC_SUPPORT_2_5_MSPS) 422 uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks setting, used in mode "fully configurable" (refer to parameter 'ScanConvMode') */ 423 #else 424 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ 425 #endif /* ADC_SUPPORT_2_5_MSPS */ 426 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 427 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 428 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 429 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 430 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 431 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ 432 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ 433 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 434 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 435 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 436 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 437 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 438 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 439 } ADC_HandleTypeDef; 440 441 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 442 /** 443 * @brief HAL ADC Callback ID enumeration definition 444 */ 445 typedef enum 446 { 447 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 448 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 449 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 450 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 451 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 452 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ 453 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 454 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 455 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 456 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 457 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 458 } HAL_ADC_CallbackIDTypeDef; 459 460 /** 461 * @brief HAL ADC Callback pointer definition 462 */ 463 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 464 465 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 466 467 /** 468 * @} 469 */ 470 471 472 /* Exported constants --------------------------------------------------------*/ 473 474 /** @defgroup ADC_Exported_Constants ADC Exported Constants 475 * @{ 476 */ 477 478 /** @defgroup ADC_Error_Code ADC Error Code 479 * @{ 480 */ 481 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 482 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 483 enable/disable, erroneous state, ...) */ 484 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 485 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 486 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ 487 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 488 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 489 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 490 /** 491 * @} 492 */ 493 494 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 495 * @{ 496 */ 497 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */ 498 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 499 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 500 501 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ 502 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ 503 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ 504 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ 505 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ 506 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ 507 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ 508 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ 509 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ 510 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ 511 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ 512 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ 513 /** 514 * @} 515 */ 516 517 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 518 * @{ 519 */ 520 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 521 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 522 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 523 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ 524 /** 525 * @} 526 */ 527 528 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 529 * @{ 530 */ 531 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 532 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ 533 /** 534 * @} 535 */ 536 537 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 538 * @{ 539 */ 540 #if defined(ADC_SUPPORT_2_5_MSPS) 541 /* Note: On STM32WB10xx, STM32WB15xx, STM32WB1Mxx devices, ADC group regular */ 542 /* sequencer both modes "fully configurable" or "not fully configurable"*/ 543 /* are available. */ 544 /* Scan mode values must be compatible with other STM32 devices having */ 545 /* a configurable sequencer. */ 546 /* Scan direction setting values are defined by taking in account */ 547 /* already defined values for other STM32 devices: */ 548 /* ADC_SCAN_DISABLE (0x00000000UL) */ 549 /* ADC_SCAN_ENABLE (0x00000001UL) */ 550 /* Sequencer fully configurable with only rank 1 enabled is considered */ 551 /* as default setting equivalent to scan enable. */ 552 /* In case of migration from another STM32 device, the user will be */ 553 /* warned of change of setting choices with assert check. */ 554 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: only the rank 1 is enabled (no scan sequence on several ranks) */ 555 #define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: sequencer length and each rank affectation to a channel are configurable. */ 556 557 #define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */ 558 #define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */ 559 560 #define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 devices */ 561 #define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 devices */ 562 563 #else 564 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ 565 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ 566 #endif /* ADC_SUPPORT_2_5_MSPS */ 567 /** 568 * @} 569 */ 570 571 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 572 * @{ 573 */ 574 /* ADC group regular trigger sources for all ADC instances */ 575 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ 576 #if defined(ADC_SUPPORT_2_5_MSPS) 577 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 578 #define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 579 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 580 #define ADC_EXTERNALTRIG_T2_CC4 (LL_ADC_REG_TRIG_EXT_TIM2_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 581 #define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 582 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ 583 #else 584 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 585 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 586 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 587 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 588 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 589 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 590 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 591 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ 592 #endif /* ADC_SUPPORT_2_5_MSPS */ 593 /** 594 * @} 595 */ 596 597 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 598 * @{ 599 */ 600 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ 601 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ 602 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ 603 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 604 /** 605 * @} 606 */ 607 608 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 609 * @{ 610 */ 611 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 612 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 613 /** 614 * @} 615 */ 616 617 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 618 * @{ 619 */ 620 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ 621 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ 622 /** 623 * @} 624 */ 625 626 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 627 * @{ 628 */ 629 #if defined(ADC_SUPPORT_2_5_MSPS) 630 #define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ 631 #define ADC_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer */ 632 633 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 634 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 635 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 636 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 637 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 638 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 639 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 640 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 641 #else 642 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 643 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 644 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 645 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 646 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 647 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 648 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 649 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 650 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 651 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 652 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 653 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 654 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 655 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 656 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 657 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 658 #endif /* ADC_SUPPORT_2_5_MSPS */ 659 /** 660 * @} 661 */ 662 663 #if defined(ADC_SUPPORT_2_5_MSPS) 664 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME ADC instance - Sampling time common to a group of channels 665 * @{ 666 */ 667 #define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of channels: sampling time nb 1 */ 668 #define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of channels: sampling time nb 2 */ 669 /** 670 * @} 671 */ 672 673 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME_INST_SCOPE Channel - Sampling time (ADC instance scope for sampling time common 1 or 2, not channel wise) 674 * @{ 675 */ 676 #define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ 677 #define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ 678 #define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ 679 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ 680 #define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ 681 #define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ 682 #define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */ 683 #define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */ 684 /** 685 * @} 686 */ 687 #else 688 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 689 * @{ 690 */ 691 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ 692 #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ 693 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ 694 #define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ 695 #define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ 696 #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ 697 #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ 698 #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ 699 /** 700 * @} 701 */ 702 #endif /* ADC_SUPPORT_2_5_MSPS */ 703 704 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 705 * @{ 706 */ 707 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 708 /* all ADC instances (refer to Reference Manual). */ 709 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 710 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 711 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 712 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 713 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 714 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 715 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 716 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 717 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 718 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 719 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 720 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 721 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 722 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 723 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 724 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 725 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 726 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 727 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 728 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ 729 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */ 730 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */ 731 /** 732 * @} 733 */ 734 735 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 736 * @{ 737 */ 738 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 739 #if defined(ADC_SUPPORT_2_5_MSPS) 740 /* Feature "ADC analog watchdog 2 and 3" not available on ADC peripheral of this STM32WB device */ 741 #else 742 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 743 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 744 #endif /* ADC_SUPPORT_2_5_MSPS */ 745 /** 746 * @} 747 */ 748 749 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode 750 * @{ 751 */ 752 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ 753 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ 754 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ 755 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ 756 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ 757 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ 758 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ 759 /** 760 * @} 761 */ 762 763 #if defined(ADC_SUPPORT_2_5_MSPS) 764 /* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */ 765 #else 766 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 767 * @{ 768 */ 769 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 770 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 771 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 772 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 773 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 774 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 775 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 776 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 777 /** 778 * @} 779 */ 780 781 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 782 * @{ 783 */ 784 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ 785 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ 786 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ 787 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ 788 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ 789 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ 790 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ 791 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ 792 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ 793 /** 794 * @} 795 */ 796 #endif /* ADC_SUPPORT_2_5_MSPS */ 797 798 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 799 * @{ 800 */ 801 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ 802 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ 803 /** 804 * @} 805 */ 806 807 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 808 * @{ 809 */ 810 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ 811 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ 812 /** 813 * @} 814 */ 815 816 #if defined(ADC_SUPPORT_2_5_MSPS) 817 /** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode 818 * @{ 819 */ 820 #define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ 821 #define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ 822 /** 823 * @} 824 */ 825 #endif /* ADC_SUPPORT_2_5_MSPS */ 826 827 828 /** @defgroup ADC_Event_type ADC Event type 829 * @{ 830 */ 831 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 832 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ 833 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ 834 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ 835 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 836 #if !defined(ADC_SUPPORT_2_5_MSPS) 837 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 838 #endif /* !ADC_SUPPORT_2_5_MSPS */ 839 /** 840 * @} 841 */ 842 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ 843 844 /** @defgroup ADC_interrupts_definition ADC interrupts definition 845 * @{ 846 */ 847 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 848 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 849 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 850 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 851 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 852 #if defined(ADC_SUPPORT_2_5_MSPS) 853 #define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC end of calibration interrupt source */ 854 #define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */ 855 #else 856 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 857 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 858 #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ 859 #endif /* ADC_SUPPORT_2_5_MSPS */ 860 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 861 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ 862 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ 863 864 #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ 865 866 /** 867 * @} 868 */ 869 870 /** @defgroup ADC_flags_definition ADC flags definition 871 * @{ 872 */ 873 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 874 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 875 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 876 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 877 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 878 #if defined(ADC_SUPPORT_2_5_MSPS) 879 #define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC end of calibration flag */ 880 #define ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC channel configuration ready flag */ 881 #else 882 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 883 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 884 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 885 #endif /* ADC_SUPPORT_2_5_MSPS */ 886 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 887 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 888 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 889 /** 890 * @} 891 */ 892 893 /** 894 * @} 895 */ 896 897 /* Private macro -------------------------------------------------------------*/ 898 899 /** @defgroup ADC_Private_Macros ADC Private Macros 900 * @{ 901 */ 902 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 903 /* code of final user. */ 904 905 /** 906 * @brief Return resolution bits in CFGR register RES[1:0] field. 907 * @param __HANDLE__ ADC handle 908 * @retval Value of bitfield RES in CFGR register. 909 */ 910 #define ADC_GET_RESOLUTION(__HANDLE__) \ 911 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 912 913 /** 914 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 915 * @param __HANDLE__ ADC handle 916 * @retval None 917 */ 918 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 919 920 /** 921 * @brief Simultaneously clear and set specific bits of the handle State. 922 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 923 * the first parameter is the ADC handle State, the second parameter is the 924 * bit field to clear, the third and last parameter is the bit field to set. 925 * @retval None 926 */ 927 #define ADC_STATE_CLR_SET MODIFY_REG 928 929 /** 930 * @brief Verify that a given value is aligned with the ADC resolution range. 931 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 932 * @param __ADC_VALUE__ value checked against the resolution. 933 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 934 */ 935 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 936 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 937 938 /** 939 * @brief Verify the length of the scheduled regular conversions group. 940 * @param __LENGTH__ number of programmed conversions. 941 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) 942 */ 943 #if defined(ADC_SUPPORT_2_5_MSPS) 944 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (8UL))) 945 #else 946 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) 947 #endif /* ADC_SUPPORT_2_5_MSPS */ 948 949 950 /** 951 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 952 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 953 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) 954 */ 955 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) 956 957 958 /** 959 * @brief Verify the ADC clock setting. 960 * @param __ADC_CLOCK__ programmed ADC clock. 961 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 962 */ 963 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 964 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 965 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 966 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 967 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 968 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 969 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 970 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 971 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 972 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 973 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 974 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 975 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 976 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 977 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 978 979 /** 980 * @brief Verify the ADC resolution setting. 981 * @param __RESOLUTION__ programmed ADC resolution. 982 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 983 */ 984 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 985 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 986 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 987 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 988 989 /** 990 * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. 991 * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. 992 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 993 */ 994 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 995 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 996 997 /** 998 * @brief Verify the ADC converted data alignment. 999 * @param __ALIGN__ programmed ADC converted data alignment. 1000 * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) 1001 */ 1002 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ 1003 ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) 1004 1005 /** 1006 * @brief Verify the ADC scan mode. 1007 * @param __SCAN_MODE__ programmed ADC scan mode. 1008 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 1009 */ 1010 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 1011 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 1012 1013 /** 1014 * @brief Verify the ADC edge trigger setting for regular group. 1015 * @param __EDGE__ programmed ADC edge trigger setting. 1016 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 1017 */ 1018 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 1019 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 1020 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 1021 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 1022 1023 /** 1024 * @brief Verify the ADC regular conversions external trigger. 1025 * @param __HANDLE__ ADC handle 1026 * @param __REGTRIG__ programmed ADC regular conversions external trigger. 1027 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 1028 */ 1029 #if defined(ADC_SUPPORT_2_5_MSPS) 1030 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1031 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC4) || \ 1032 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1033 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC4) || \ 1034 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ 1035 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 1036 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1037 #else 1038 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1039 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1040 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1041 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1042 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 1043 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1044 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1045 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1046 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1047 #endif /* ADC_SUPPORT_2_5_MSPS */ 1048 1049 /** 1050 * @brief Verify the ADC regular conversions check for converted data availability. 1051 * @param __EOC_SELECTION__ converted data availability check. 1052 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 1053 */ 1054 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 1055 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 1056 1057 /** 1058 * @brief Verify the ADC regular conversions overrun handling. 1059 * @param __OVR__ ADC regular conversions overrun handling. 1060 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 1061 */ 1062 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 1063 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 1064 1065 #if defined(ADC_SUPPORT_2_5_MSPS) 1066 #define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \ 1067 ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2) ) 1068 #endif /* ADC_SUPPORT_2_5_MSPS */ 1069 1070 /** 1071 * @brief Verify the ADC conversions sampling time. 1072 * @param __TIME__ ADC conversions sampling time. 1073 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 1074 */ 1075 #if defined(ADC_SUPPORT_2_5_MSPS) 1076 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \ 1077 ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ 1078 ((__TIME__) == ADC_SAMPLETIME_7CYCLES_5) || \ 1079 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 1080 ((__TIME__) == ADC_SAMPLETIME_19CYCLES_5) || \ 1081 ((__TIME__) == ADC_SAMPLETIME_39CYCLES_5) || \ 1082 ((__TIME__) == ADC_SAMPLETIME_79CYCLES_5) || \ 1083 ((__TIME__) == ADC_SAMPLETIME_160CYCLES_5) ) 1084 #else 1085 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 1086 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 1087 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 1088 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 1089 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 1090 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 1091 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 1092 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 1093 #endif /* ADC_SUPPORT_2_5_MSPS */ 1094 1095 #if defined(ADC_SUPPORT_2_5_MSPS) 1096 #define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \ 1097 ((RANK) == ADC_RANK_NONE) ) 1098 #endif /* ADC_SUPPORT_2_5_MSPS */ 1099 1100 /** 1101 * @brief Verify the ADC regular channel setting. 1102 * @param RANK programmed ADC regular channel. 1103 * @retval SET (RANK is valid) or RESET (RANK is invalid) 1104 */ 1105 #if defined(ADC_SUPPORT_2_5_MSPS) 1106 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \ 1107 ((RANK) == ADC_REGULAR_RANK_2 ) || \ 1108 ((RANK) == ADC_REGULAR_RANK_3 ) || \ 1109 ((RANK) == ADC_REGULAR_RANK_4 ) || \ 1110 ((RANK) == ADC_REGULAR_RANK_5 ) || \ 1111 ((RANK) == ADC_REGULAR_RANK_6 ) || \ 1112 ((RANK) == ADC_REGULAR_RANK_7 ) || \ 1113 ((RANK) == ADC_REGULAR_RANK_8 ) ) 1114 #else 1115 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \ 1116 ((RANK) == ADC_REGULAR_RANK_2 ) || \ 1117 ((RANK) == ADC_REGULAR_RANK_3 ) || \ 1118 ((RANK) == ADC_REGULAR_RANK_4 ) || \ 1119 ((RANK) == ADC_REGULAR_RANK_5 ) || \ 1120 ((RANK) == ADC_REGULAR_RANK_6 ) || \ 1121 ((RANK) == ADC_REGULAR_RANK_7 ) || \ 1122 ((RANK) == ADC_REGULAR_RANK_8 ) || \ 1123 ((RANK) == ADC_REGULAR_RANK_9 ) || \ 1124 ((RANK) == ADC_REGULAR_RANK_10) || \ 1125 ((RANK) == ADC_REGULAR_RANK_11) || \ 1126 ((RANK) == ADC_REGULAR_RANK_12) || \ 1127 ((RANK) == ADC_REGULAR_RANK_13) || \ 1128 ((RANK) == ADC_REGULAR_RANK_14) || \ 1129 ((RANK) == ADC_REGULAR_RANK_15) || \ 1130 ((RANK) == ADC_REGULAR_RANK_16) ) 1131 #endif /* ADC_SUPPORT_2_5_MSPS */ 1132 1133 /** 1134 * @} 1135 */ 1136 1137 1138 /* Private constants ---------------------------------------------------------*/ 1139 1140 /** @defgroup ADC_Private_Constants ADC Private Constants 1141 * @{ 1142 */ 1143 1144 /* Fixed timeout values for ADC conversion (including sampling time) */ 1145 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ 1146 /* Maximum conversion time is 12.5 + Maximum sampling time */ 1147 /* or 12.5 + 640.5 = 653 ADC clock cycles */ 1148 /* Minimum ADC Clock frequency is 0.14 MHz */ 1149 /* Maximum conversion time is */ 1150 /* 653 / 0.14 MHz = 4.66 ms */ 1151 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ 1152 1153 /* Delay for temperature sensor stabilization time. */ 1154 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 1155 /* Unit: us */ 1156 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 1157 1158 #if defined(ADC_SUPPORT_2_5_MSPS) 1159 #define ADC_SCAN_SEQ_FIXED_INT 0x80000000U /* Internal definition to differentiate sequencer setting fixed or configurable */ 1160 #endif /* ADC_SUPPORT_2_5_MSPS */ 1161 1162 /** 1163 * @} 1164 */ 1165 1166 /* Exported macro ------------------------------------------------------------*/ 1167 1168 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1169 * @{ 1170 */ 1171 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1172 /* final user. */ 1173 1174 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1175 * @{ 1176 */ 1177 1178 /** @brief Reset ADC handle state. 1179 * @param __HANDLE__ ADC handle 1180 * @retval None 1181 */ 1182 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1183 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1184 do{ \ 1185 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1186 (__HANDLE__)->MspInitCallback = NULL; \ 1187 (__HANDLE__)->MspDeInitCallback = NULL; \ 1188 } while(0) 1189 #else 1190 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1191 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1192 #endif 1193 1194 /** 1195 * @brief Enable ADC interrupt. 1196 * @param __HANDLE__ ADC handle 1197 * @param __INTERRUPT__ ADC Interrupt 1198 * This parameter can be one of the following values: 1199 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1200 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1201 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1202 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1203 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1204 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1205 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1206 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1207 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1208 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1209 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1210 * 1211 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx. 1212 * @retval None 1213 */ 1214 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1215 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1216 1217 /** 1218 * @brief Disable ADC interrupt. 1219 * @param __HANDLE__ ADC handle 1220 * @param __INTERRUPT__ ADC Interrupt 1221 * This parameter can be one of the following values: 1222 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1223 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1224 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1225 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1226 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1227 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1228 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1229 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1230 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1231 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1232 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1233 * 1234 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx. 1235 * @retval None 1236 */ 1237 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1238 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1239 1240 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1241 * @param __HANDLE__ ADC handle 1242 * @param __INTERRUPT__ ADC interrupt source to check 1243 * This parameter can be one of the following values: 1244 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1245 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1246 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1247 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1248 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1249 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source (1) 1250 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source (1) 1251 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source (1) 1252 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1253 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1254 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1255 * 1256 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx. 1257 * @retval State of interruption (SET or RESET) 1258 */ 1259 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1260 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1261 1262 /** 1263 * @brief Check whether the specified ADC flag is set or not. 1264 * @param __HANDLE__ ADC handle 1265 * @param __FLAG__ ADC flag 1266 * This parameter can be one of the following values: 1267 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1268 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1269 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1270 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1271 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1272 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag (1) 1273 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag (1) 1274 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag (1) 1275 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1276 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1277 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1278 * 1279 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx. 1280 * @retval State of flag (TRUE or FALSE). 1281 */ 1282 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1283 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1284 1285 /** 1286 * @brief Clear the specified ADC flag. 1287 * @param __HANDLE__ ADC handle 1288 * @param __FLAG__ ADC flag 1289 * This parameter can be one of the following values: 1290 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1291 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1292 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1293 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1294 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1295 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag (1) 1296 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag (1) 1297 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag (1) 1298 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1299 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1300 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1301 * 1302 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx. 1303 * @retval None 1304 */ 1305 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1306 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1307 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1308 1309 /** 1310 * @} 1311 */ 1312 1313 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1314 * @{ 1315 */ 1316 1317 /** 1318 * @brief Helper macro to get ADC channel number in decimal format 1319 * from literals ADC_CHANNEL_x. 1320 * @note Example: 1321 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1322 * will return decimal number "4". 1323 * @note The input can be a value from functions where a channel 1324 * number is returned, either defined with number 1325 * or with bitfield (only one bit must be set). 1326 * @param __CHANNEL__ This parameter can be one of the following values: 1327 * @arg @ref ADC_CHANNEL_0 1328 * @arg @ref ADC_CHANNEL_1 (7) 1329 * @arg @ref ADC_CHANNEL_2 (7) 1330 * @arg @ref ADC_CHANNEL_3 (7) 1331 * @arg @ref ADC_CHANNEL_4 (7) 1332 * @arg @ref ADC_CHANNEL_5 (7) 1333 * @arg @ref ADC_CHANNEL_6 1334 * @arg @ref ADC_CHANNEL_7 1335 * @arg @ref ADC_CHANNEL_8 1336 * @arg @ref ADC_CHANNEL_9 1337 * @arg @ref ADC_CHANNEL_10 1338 * @arg @ref ADC_CHANNEL_11 1339 * @arg @ref ADC_CHANNEL_12 1340 * @arg @ref ADC_CHANNEL_13 1341 * @arg @ref ADC_CHANNEL_14 1342 * @arg @ref ADC_CHANNEL_15 1343 * @arg @ref ADC_CHANNEL_16 1344 * @arg @ref ADC_CHANNEL_17 1345 * @arg @ref ADC_CHANNEL_18 1346 * @arg @ref ADC_CHANNEL_VREFINT 1347 * @arg @ref ADC_CHANNEL_TEMPSENSOR 1348 * @arg @ref ADC_CHANNEL_VBAT 1349 * 1350 * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1351 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 1352 * @retval Value between Min_Data=0 and Max_Data=18 1353 */ 1354 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1355 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1356 1357 /** 1358 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1359 * from number in decimal format. 1360 * @note Example: 1361 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1362 * will return a data equivalent to "ADC_CHANNEL_4". 1363 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1364 * @retval Returned value can be one of the following values: 1365 * @arg @ref ADC_CHANNEL_0 1366 * @arg @ref ADC_CHANNEL_1 (7) 1367 * @arg @ref ADC_CHANNEL_2 (7) 1368 * @arg @ref ADC_CHANNEL_3 (7) 1369 * @arg @ref ADC_CHANNEL_4 (7) 1370 * @arg @ref ADC_CHANNEL_5 (7) 1371 * @arg @ref ADC_CHANNEL_6 1372 * @arg @ref ADC_CHANNEL_7 1373 * @arg @ref ADC_CHANNEL_8 1374 * @arg @ref ADC_CHANNEL_9 1375 * @arg @ref ADC_CHANNEL_10 1376 * @arg @ref ADC_CHANNEL_11 1377 * @arg @ref ADC_CHANNEL_12 1378 * @arg @ref ADC_CHANNEL_13 1379 * @arg @ref ADC_CHANNEL_14 1380 * @arg @ref ADC_CHANNEL_15 1381 * @arg @ref ADC_CHANNEL_16 1382 * @arg @ref ADC_CHANNEL_17 1383 * @arg @ref ADC_CHANNEL_18 1384 * @arg @ref ADC_CHANNEL_VREFINT (1) 1385 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 1386 * @arg @ref ADC_CHANNEL_VBAT (4) 1387 * 1388 * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1389 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n 1390 * (4) For ADC channel read back from ADC register, 1391 * comparison with internal channel parameter to be done 1392 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1393 */ 1394 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1395 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1396 1397 /** 1398 * @brief Helper macro to determine whether the selected channel 1399 * corresponds to literal definitions of driver. 1400 * @note The different literal definitions of ADC channels are: 1401 * - ADC internal channel: 1402 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 1403 * - ADC external channel (channel connected to a GPIO pin): 1404 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1405 * @note The channel parameter must be a value defined from literal 1406 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1407 * ADC_CHANNEL_TEMPSENSOR, ...), 1408 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1409 * must not be a value from functions where a channel number is 1410 * returned from ADC registers, 1411 * because internal and external channels share the same channel 1412 * number in ADC registers. The differentiation is made only with 1413 * parameters definitions of driver. 1414 * @param __CHANNEL__ This parameter can be one of the following values: 1415 * @arg @ref ADC_CHANNEL_0 1416 * @arg @ref ADC_CHANNEL_1 (7) 1417 * @arg @ref ADC_CHANNEL_2 (7) 1418 * @arg @ref ADC_CHANNEL_3 (7) 1419 * @arg @ref ADC_CHANNEL_4 (7) 1420 * @arg @ref ADC_CHANNEL_5 (7) 1421 * @arg @ref ADC_CHANNEL_6 1422 * @arg @ref ADC_CHANNEL_7 1423 * @arg @ref ADC_CHANNEL_8 1424 * @arg @ref ADC_CHANNEL_9 1425 * @arg @ref ADC_CHANNEL_10 1426 * @arg @ref ADC_CHANNEL_11 1427 * @arg @ref ADC_CHANNEL_12 1428 * @arg @ref ADC_CHANNEL_13 1429 * @arg @ref ADC_CHANNEL_14 1430 * @arg @ref ADC_CHANNEL_15 1431 * @arg @ref ADC_CHANNEL_16 1432 * @arg @ref ADC_CHANNEL_17 1433 * @arg @ref ADC_CHANNEL_18 1434 * @arg @ref ADC_CHANNEL_VREFINT 1435 * @arg @ref ADC_CHANNEL_TEMPSENSOR 1436 * @arg @ref ADC_CHANNEL_VBAT 1437 * 1438 * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1439 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 1440 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 1441 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1442 */ 1443 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1444 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1445 1446 /** 1447 * @brief Helper macro to convert a channel defined from parameter 1448 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1449 * ADC_CHANNEL_TEMPSENSOR, ...), 1450 * to its equivalent parameter definition of a ADC external channel 1451 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1452 * @note The channel parameter can be, additionally to a value 1453 * defined from parameter definition of a ADC internal channel 1454 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 1455 * a value defined from parameter definition of 1456 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1457 * or a value from functions where a channel number is returned 1458 * from ADC registers. 1459 * @param __CHANNEL__ This parameter can be one of the following values: 1460 * @arg @ref ADC_CHANNEL_0 1461 * @arg @ref ADC_CHANNEL_1 (7) 1462 * @arg @ref ADC_CHANNEL_2 (7) 1463 * @arg @ref ADC_CHANNEL_3 (7) 1464 * @arg @ref ADC_CHANNEL_4 (7) 1465 * @arg @ref ADC_CHANNEL_5 (7) 1466 * @arg @ref ADC_CHANNEL_6 1467 * @arg @ref ADC_CHANNEL_7 1468 * @arg @ref ADC_CHANNEL_8 1469 * @arg @ref ADC_CHANNEL_9 1470 * @arg @ref ADC_CHANNEL_10 1471 * @arg @ref ADC_CHANNEL_11 1472 * @arg @ref ADC_CHANNEL_12 1473 * @arg @ref ADC_CHANNEL_13 1474 * @arg @ref ADC_CHANNEL_14 1475 * @arg @ref ADC_CHANNEL_15 1476 * @arg @ref ADC_CHANNEL_16 1477 * @arg @ref ADC_CHANNEL_17 1478 * @arg @ref ADC_CHANNEL_18 1479 * @arg @ref ADC_CHANNEL_VREFINT 1480 * @arg @ref ADC_CHANNEL_TEMPSENSOR 1481 * @arg @ref ADC_CHANNEL_VBAT 1482 * 1483 * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1484 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 1485 * @retval Returned value can be one of the following values: 1486 * @arg @ref ADC_CHANNEL_0 1487 * @arg @ref ADC_CHANNEL_1 1488 * @arg @ref ADC_CHANNEL_2 1489 * @arg @ref ADC_CHANNEL_3 1490 * @arg @ref ADC_CHANNEL_4 1491 * @arg @ref ADC_CHANNEL_5 1492 * @arg @ref ADC_CHANNEL_6 1493 * @arg @ref ADC_CHANNEL_7 1494 * @arg @ref ADC_CHANNEL_8 1495 * @arg @ref ADC_CHANNEL_9 1496 * @arg @ref ADC_CHANNEL_10 1497 * @arg @ref ADC_CHANNEL_11 1498 * @arg @ref ADC_CHANNEL_12 1499 * @arg @ref ADC_CHANNEL_13 1500 * @arg @ref ADC_CHANNEL_14 1501 * @arg @ref ADC_CHANNEL_15 1502 * @arg @ref ADC_CHANNEL_16 1503 * @arg @ref ADC_CHANNEL_17 1504 * @arg @ref ADC_CHANNEL_18 1505 */ 1506 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1507 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1508 1509 /** 1510 * @brief Helper macro to determine whether the internal channel 1511 * selected is available on the ADC instance selected. 1512 * @note The channel parameter must be a value defined from parameter 1513 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1514 * ADC_CHANNEL_TEMPSENSOR, ...), 1515 * must not be a value defined from parameter definition of 1516 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1517 * or a value from functions where a channel number is 1518 * returned from ADC registers, 1519 * because internal and external channels share the same channel 1520 * number in ADC registers. The differentiation is made only with 1521 * parameters definitions of driver. 1522 * @param __ADC_INSTANCE__ ADC instance 1523 * @param __CHANNEL__ This parameter can be one of the following values: 1524 * @arg @ref ADC_CHANNEL_VREFINT 1525 * @arg @ref ADC_CHANNEL_TEMPSENSOR 1526 * @arg @ref ADC_CHANNEL_VBAT 1527 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1528 * Value "1" if the internal channel selected is available on the ADC instance selected. 1529 */ 1530 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1531 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 1532 1533 /** 1534 * @brief Helper macro to select the ADC common instance 1535 * to which is belonging the selected ADC instance. 1536 * @note ADC common register instance can be used for: 1537 * - Set parameters common to several ADC instances 1538 * - Multimode (for devices with several ADC instances) 1539 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1540 * @param __ADCx__ ADC instance 1541 * @retval ADC common register instance 1542 */ 1543 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 1544 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 1545 1546 /** 1547 * @brief Helper macro to check if all ADC instances sharing the same 1548 * ADC common instance are disabled. 1549 * @note This check is required by functions with setting conditioned to 1550 * ADC state: 1551 * All ADC instances of the ADC common group must be disabled. 1552 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1553 * @note On devices with only 1 ADC common instance, parameter of this macro 1554 * is useless and can be ignored (parameter kept for compatibility 1555 * with devices featuring several ADC common instances). 1556 * @param __ADCXY_COMMON__ ADC common instance 1557 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1558 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1559 * are disabled. 1560 * Value "1" if at least one ADC instance sharing the same ADC common instance 1561 * is enabled. 1562 */ 1563 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1564 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 1565 1566 /** 1567 * @brief Helper macro to define the ADC conversion data full-scale digital 1568 * value corresponding to the selected ADC resolution. 1569 * @note ADC conversion data full-scale corresponds to voltage range 1570 * determined by analog voltage references Vref+ and Vref- 1571 * (refer to reference manual). 1572 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1573 * @arg @ref ADC_RESOLUTION_12B 1574 * @arg @ref ADC_RESOLUTION_10B 1575 * @arg @ref ADC_RESOLUTION_8B 1576 * @arg @ref ADC_RESOLUTION_6B 1577 * @retval ADC conversion data full-scale digital value 1578 */ 1579 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1580 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 1581 1582 /** 1583 * @brief Helper macro to convert the ADC conversion data from 1584 * a resolution to another resolution. 1585 * @param __DATA__ ADC conversion data to be converted 1586 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1587 * This parameter can be one of the following values: 1588 * @arg @ref ADC_RESOLUTION_12B 1589 * @arg @ref ADC_RESOLUTION_10B 1590 * @arg @ref ADC_RESOLUTION_8B 1591 * @arg @ref ADC_RESOLUTION_6B 1592 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1593 * This parameter can be one of the following values: 1594 * @arg @ref ADC_RESOLUTION_12B 1595 * @arg @ref ADC_RESOLUTION_10B 1596 * @arg @ref ADC_RESOLUTION_8B 1597 * @arg @ref ADC_RESOLUTION_6B 1598 * @retval ADC conversion data to the requested resolution 1599 */ 1600 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 1601 __ADC_RESOLUTION_CURRENT__,\ 1602 __ADC_RESOLUTION_TARGET__) \ 1603 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), \ 1604 (__ADC_RESOLUTION_CURRENT__), \ 1605 (__ADC_RESOLUTION_TARGET__)) 1606 1607 /** 1608 * @brief Helper macro to calculate the voltage (unit: mVolt) 1609 * corresponding to a ADC conversion data (unit: digital value). 1610 * @note Analog reference voltage (Vref+) must be either known from 1611 * user board environment or can be calculated using ADC measurement 1612 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1613 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1614 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1615 * (unit: digital value). 1616 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1617 * @arg @ref ADC_RESOLUTION_12B 1618 * @arg @ref ADC_RESOLUTION_10B 1619 * @arg @ref ADC_RESOLUTION_8B 1620 * @arg @ref ADC_RESOLUTION_6B 1621 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1622 */ 1623 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1624 __ADC_DATA__,\ 1625 __ADC_RESOLUTION__) \ 1626 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), \ 1627 (__ADC_DATA__), \ 1628 (__ADC_RESOLUTION__)) 1629 1630 /** 1631 * @brief Helper macro to calculate analog reference voltage (Vref+) 1632 * (unit: mVolt) from ADC conversion data of internal voltage 1633 * reference VrefInt. 1634 * @note Computation is using VrefInt calibration value 1635 * stored in system memory for each device during production. 1636 * @note This voltage depends on user board environment: voltage level 1637 * connected to pin Vref+. 1638 * On devices with small package, the pin Vref+ is not present 1639 * and internally bonded to pin Vdda. 1640 * @note On this STM32 series, calibration data of internal voltage reference 1641 * VrefInt corresponds to a resolution of 12 bits, 1642 * this is the recommended ADC resolution to convert voltage of 1643 * internal voltage reference VrefInt. 1644 * Otherwise, this macro performs the processing to scale 1645 * ADC conversion data to 12 bits. 1646 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 1647 * of internal voltage reference VrefInt (unit: digital value). 1648 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1649 * @arg @ref ADC_RESOLUTION_12B 1650 * @arg @ref ADC_RESOLUTION_10B 1651 * @arg @ref ADC_RESOLUTION_8B 1652 * @arg @ref ADC_RESOLUTION_6B 1653 * @retval Analog reference voltage (unit: mV) 1654 */ 1655 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 1656 __ADC_RESOLUTION__) \ 1657 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), \ 1658 (__ADC_RESOLUTION__)) 1659 1660 /** 1661 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1662 * from ADC conversion data of internal temperature sensor. 1663 * @note Computation is using temperature sensor calibration values 1664 * stored in system memory for each device during production. 1665 * @note Calculation formula: 1666 * Temperature = ((TS_ADC_DATA - TS_CAL1) 1667 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 1668 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 1669 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1670 * Avg_Slope = (TS_CAL2 - TS_CAL1) 1671 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 1672 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 1673 * TEMP_DEGC_CAL1 (calibrated in factory) 1674 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 1675 * TEMP_DEGC_CAL2 (calibrated in factory) 1676 * Caution: Calculation relevancy under reserve that calibration 1677 * parameters are correct (address and data). 1678 * To calculate temperature using temperature sensor 1679 * datasheet typical values (generic values less, therefore 1680 * less accurate than calibrated values), 1681 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 1682 * @note As calculation input, the analog reference voltage (Vref+) must be 1683 * defined as it impacts the ADC LSB equivalent voltage. 1684 * @note Analog reference voltage (Vref+) must be either known from 1685 * user board environment or can be calculated using ADC measurement 1686 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1687 * @note On this STM32 series, calibration data of temperature sensor 1688 * corresponds to a resolution of 12 bits, 1689 * this is the recommended ADC resolution to convert voltage of 1690 * temperature sensor. 1691 * Otherwise, this macro performs the processing to scale 1692 * ADC conversion data to 12 bits. 1693 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1694 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 1695 * temperature sensor (unit: digital value). 1696 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 1697 * sensor voltage has been measured. 1698 * This parameter can be one of the following values: 1699 * @arg @ref ADC_RESOLUTION_12B 1700 * @arg @ref ADC_RESOLUTION_10B 1701 * @arg @ref ADC_RESOLUTION_8B 1702 * @arg @ref ADC_RESOLUTION_6B 1703 * @retval Temperature (unit: degree Celsius) 1704 */ 1705 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 1706 __TEMPSENSOR_ADC_DATA__,\ 1707 __ADC_RESOLUTION__) \ 1708 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \ 1709 (__TEMPSENSOR_ADC_DATA__), \ 1710 (__ADC_RESOLUTION__)) 1711 1712 /** 1713 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1714 * from ADC conversion data of internal temperature sensor. 1715 * @note Computation is using temperature sensor typical values 1716 * (refer to device datasheet). 1717 * @note Calculation formula: 1718 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 1719 * / Avg_Slope + CALx_TEMP 1720 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1721 * (unit: digital value) 1722 * Avg_Slope = temperature sensor slope 1723 * (unit: uV/Degree Celsius) 1724 * TS_TYP_CALx_VOLT = temperature sensor digital value at 1725 * temperature CALx_TEMP (unit: mV) 1726 * Caution: Calculation relevancy under reserve the temperature sensor 1727 * of the current device has characteristics in line with 1728 * datasheet typical values. 1729 * If temperature sensor calibration values are available on 1730 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 1731 * temperature calculation will be more accurate using 1732 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 1733 * @note As calculation input, the analog reference voltage (Vref+) must be 1734 * defined as it impacts the ADC LSB equivalent voltage. 1735 * @note Analog reference voltage (Vref+) must be either known from 1736 * user board environment or can be calculated using ADC measurement 1737 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1738 * @note ADC measurement data must correspond to a resolution of 12bits 1739 * (full scale digital value 4095). If not the case, the data must be 1740 * preliminarily rescaled to an equivalent resolution of 12 bits. 1741 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). 1742 * On STM32WB, refer to device datasheet parameter "Avg_Slope". 1743 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). 1744 * On STM32WB, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). 1745 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) 1746 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 1747 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 1748 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 1749 * This parameter can be one of the following values: 1750 * @arg @ref ADC_RESOLUTION_12B 1751 * @arg @ref ADC_RESOLUTION_10B 1752 * @arg @ref ADC_RESOLUTION_8B 1753 * @arg @ref ADC_RESOLUTION_6B 1754 * @retval Temperature (unit: degree Celsius) 1755 */ 1756 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 1757 __TEMPSENSOR_TYP_CALX_V__,\ 1758 __TEMPSENSOR_CALX_TEMP__,\ 1759 __VREFANALOG_VOLTAGE__,\ 1760 __TEMPSENSOR_ADC_DATA__,\ 1761 __ADC_RESOLUTION__) \ 1762 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__), \ 1763 (__TEMPSENSOR_TYP_CALX_V__), \ 1764 (__TEMPSENSOR_CALX_TEMP__), \ 1765 (__VREFANALOG_VOLTAGE__), \ 1766 (__TEMPSENSOR_ADC_DATA__), \ 1767 (__ADC_RESOLUTION__)) 1768 1769 /** 1770 * @} 1771 */ 1772 1773 /** 1774 * @} 1775 */ 1776 1777 /* Include ADC HAL Extended module */ 1778 #include "stm32wbxx_hal_adc_ex.h" 1779 1780 /* Exported functions --------------------------------------------------------*/ 1781 /** @addtogroup ADC_Exported_Functions 1782 * @{ 1783 */ 1784 1785 /** @addtogroup ADC_Exported_Functions_Group1 1786 * @brief Initialization and Configuration functions 1787 * @{ 1788 */ 1789 /* Initialization and de-initialization functions ****************************/ 1790 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 1791 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1792 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 1793 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 1794 1795 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1796 /* Callbacks Register/UnRegister functions ***********************************/ 1797 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, 1798 pADC_CallbackTypeDef pCallback); 1799 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1800 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1801 /** 1802 * @} 1803 */ 1804 1805 /** @addtogroup ADC_Exported_Functions_Group2 1806 * @brief IO operation functions 1807 * @{ 1808 */ 1809 /* IO operation functions *****************************************************/ 1810 1811 /* Blocking mode: Polling */ 1812 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 1813 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 1814 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1815 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 1816 1817 /* Non-blocking mode: Interruption */ 1818 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 1819 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 1820 1821 /* Non-blocking mode: DMA */ 1822 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1823 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 1824 1825 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1826 uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); 1827 1828 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1829 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 1830 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 1831 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 1832 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 1833 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1834 /** 1835 * @} 1836 */ 1837 1838 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 1839 * @brief Peripheral Control functions 1840 * @{ 1841 */ 1842 /* Peripheral Control functions ***********************************************/ 1843 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *sConfig); 1844 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); 1845 1846 /** 1847 * @} 1848 */ 1849 1850 /* Peripheral State functions *************************************************/ 1851 /** @addtogroup ADC_Exported_Functions_Group4 1852 * @{ 1853 */ 1854 uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); 1855 uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); 1856 1857 /** 1858 * @} 1859 */ 1860 1861 /** 1862 * @} 1863 */ 1864 1865 /* Private functions -----------------------------------------------------------*/ 1866 /** @addtogroup ADC_Private_Functions ADC Private Functions 1867 * @{ 1868 */ 1869 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); 1870 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 1871 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 1872 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 1873 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 1874 void ADC_DMAError(DMA_HandleTypeDef *hdma); 1875 1876 /** 1877 * @} 1878 */ 1879 1880 /** 1881 * @} 1882 */ 1883 1884 /** 1885 * @} 1886 */ 1887 1888 #ifdef __cplusplus 1889 } 1890 #endif 1891 1892 #endif /* STM32WBxx_HAL_ADC_H */ 1893
