1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2019 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32WBxx_HAL_H 22 #define STM32WBxx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32wbxx_hal_conf.h" 30 #include "stm32wbxx_ll_system.h" 31 32 /** @addtogroup STM32WBxx_HAL_Driver 33 * @{ 34 */ 35 36 /** @defgroup HAL HAL 37 * @{ 38 */ 39 40 /** @defgroup HAL_TICK_FREQ Tick Frequency 41 * @{ 42 */ 43 typedef enum 44 { 45 HAL_TICK_FREQ_10HZ = 100U, 46 HAL_TICK_FREQ_100HZ = 10U, 47 HAL_TICK_FREQ_1KHZ = 1U, 48 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 49 } HAL_TickFreqTypeDef; 50 51 /** 52 * @} 53 */ 54 55 /* Exported constants --------------------------------------------------------*/ 56 /** @defgroup HAL_Exported_Constants HAL Exported Constants 57 * @{ 58 */ 59 60 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 61 * @{ 62 */ 63 64 /** @defgroup SYSCFG_BootMode BOOT Mode 65 * @{ 66 */ 67 #define SYSCFG_BOOT_MAINFLASH LL_SYSCFG_REMAP_FLASH /*!< Main Flash memory mapped at 0x00000000 */ 68 #define SYSCFG_BOOT_SYSTEMFLASH LL_SYSCFG_REMAP_SYSTEMFLASH /*!< System Flash memory mapped at 0x00000000 */ 69 #define SYSCFG_BOOT_SRAM LL_SYSCFG_REMAP_SRAM /*!< SRAM1 mapped at 0x00000000 */ 70 #if defined(LL_SYSCFG_REMAP_QUADSPI) 71 #define SYSCFG_BOOT_QUADSPI LL_SYSCFG_REMAP_QUADSPI /*!< QUADSPI memory mapped at 0x00000000 */ 72 #endif /* LL_SYSCFG_REMAP_QUADSPI */ 73 /** 74 * @} 75 */ 76 77 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 78 * @{ 79 */ 80 #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 81 #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 82 #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 83 #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 84 #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 85 #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 86 87 /** 88 * @} 89 */ 90 91 /** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31) 92 * @{ 93 */ 94 #define SYSCFG_SRAM2WRP_PAGE0 LL_SYSCFG_SRAM2WRP_PAGE0 /*!< SRAM2A Write protection page 0 */ 95 #define SYSCFG_SRAM2WRP_PAGE1 LL_SYSCFG_SRAM2WRP_PAGE1 /*!< SRAM2A Write protection page 1 */ 96 #define SYSCFG_SRAM2WRP_PAGE2 LL_SYSCFG_SRAM2WRP_PAGE2 /*!< SRAM2A Write protection page 2 */ 97 #define SYSCFG_SRAM2WRP_PAGE3 LL_SYSCFG_SRAM2WRP_PAGE3 /*!< SRAM2A Write protection page 3 */ 98 #define SYSCFG_SRAM2WRP_PAGE4 LL_SYSCFG_SRAM2WRP_PAGE4 /*!< SRAM2A Write protection page 4 */ 99 #define SYSCFG_SRAM2WRP_PAGE5 LL_SYSCFG_SRAM2WRP_PAGE5 /*!< SRAM2A Write protection page 5 */ 100 #define SYSCFG_SRAM2WRP_PAGE6 LL_SYSCFG_SRAM2WRP_PAGE6 /*!< SRAM2A Write protection page 6 */ 101 #define SYSCFG_SRAM2WRP_PAGE7 LL_SYSCFG_SRAM2WRP_PAGE7 /*!< SRAM2A Write protection page 7 */ 102 #define SYSCFG_SRAM2WRP_PAGE8 LL_SYSCFG_SRAM2WRP_PAGE8 /*!< SRAM2A Write protection page 8 */ 103 #define SYSCFG_SRAM2WRP_PAGE9 LL_SYSCFG_SRAM2WRP_PAGE9 /*!< SRAM2A Write protection page 9 */ 104 #define SYSCFG_SRAM2WRP_PAGE10 LL_SYSCFG_SRAM2WRP_PAGE10 /*!< SRAM2A Write protection page 10 */ 105 #define SYSCFG_SRAM2WRP_PAGE11 LL_SYSCFG_SRAM2WRP_PAGE11 /*!< SRAM2A Write protection page 11 */ 106 #define SYSCFG_SRAM2WRP_PAGE12 LL_SYSCFG_SRAM2WRP_PAGE12 /*!< SRAM2A Write protection page 12 */ 107 #define SYSCFG_SRAM2WRP_PAGE13 LL_SYSCFG_SRAM2WRP_PAGE13 /*!< SRAM2A Write protection page 13 */ 108 #define SYSCFG_SRAM2WRP_PAGE14 LL_SYSCFG_SRAM2WRP_PAGE14 /*!< SRAM2A Write protection page 14 */ 109 #define SYSCFG_SRAM2WRP_PAGE15 LL_SYSCFG_SRAM2WRP_PAGE15 /*!< SRAM2A Write protection page 15 */ 110 #define SYSCFG_SRAM2WRP_PAGE16 LL_SYSCFG_SRAM2WRP_PAGE16 /*!< SRAM2A Write protection page 16 */ 111 #define SYSCFG_SRAM2WRP_PAGE17 LL_SYSCFG_SRAM2WRP_PAGE17 /*!< SRAM2A Write protection page 17 */ 112 #define SYSCFG_SRAM2WRP_PAGE18 LL_SYSCFG_SRAM2WRP_PAGE18 /*!< SRAM2A Write protection page 18 */ 113 #define SYSCFG_SRAM2WRP_PAGE19 LL_SYSCFG_SRAM2WRP_PAGE19 /*!< SRAM2A Write protection page 19 */ 114 #define SYSCFG_SRAM2WRP_PAGE20 LL_SYSCFG_SRAM2WRP_PAGE20 /*!< SRAM2A Write protection page 20 */ 115 #define SYSCFG_SRAM2WRP_PAGE21 LL_SYSCFG_SRAM2WRP_PAGE21 /*!< SRAM2A Write protection page 21 */ 116 #define SYSCFG_SRAM2WRP_PAGE22 LL_SYSCFG_SRAM2WRP_PAGE22 /*!< SRAM2A Write protection page 22 */ 117 #define SYSCFG_SRAM2WRP_PAGE23 LL_SYSCFG_SRAM2WRP_PAGE23 /*!< SRAM2A Write protection page 23 */ 118 #define SYSCFG_SRAM2WRP_PAGE24 LL_SYSCFG_SRAM2WRP_PAGE24 /*!< SRAM2A Write protection page 24 */ 119 #define SYSCFG_SRAM2WRP_PAGE25 LL_SYSCFG_SRAM2WRP_PAGE25 /*!< SRAM2A Write protection page 25 */ 120 #define SYSCFG_SRAM2WRP_PAGE26 LL_SYSCFG_SRAM2WRP_PAGE26 /*!< SRAM2A Write protection page 26 */ 121 #define SYSCFG_SRAM2WRP_PAGE27 LL_SYSCFG_SRAM2WRP_PAGE27 /*!< SRAM2A Write protection page 27 */ 122 #define SYSCFG_SRAM2WRP_PAGE28 LL_SYSCFG_SRAM2WRP_PAGE28 /*!< SRAM2A Write protection page 28 */ 123 #define SYSCFG_SRAM2WRP_PAGE29 LL_SYSCFG_SRAM2WRP_PAGE29 /*!< SRAM2A Write protection page 29 */ 124 #define SYSCFG_SRAM2WRP_PAGE30 LL_SYSCFG_SRAM2WRP_PAGE30 /*!< SRAM2A Write protection page 30 */ 125 #define SYSCFG_SRAM2WRP_PAGE31 LL_SYSCFG_SRAM2WRP_PAGE31 /*!< SRAM2A Write protection page 31 */ 126 127 /** 128 * @} 129 */ 130 131 /** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63) 132 * @{ 133 */ 134 #define SYSCFG_SRAM2WRP_PAGE32 LL_SYSCFG_SRAM2WRP_PAGE32 /*!< SRAM2B Write protection page 32 */ 135 #define SYSCFG_SRAM2WRP_PAGE33 LL_SYSCFG_SRAM2WRP_PAGE33 /*!< SRAM2B Write protection page 33 */ 136 #define SYSCFG_SRAM2WRP_PAGE34 LL_SYSCFG_SRAM2WRP_PAGE34 /*!< SRAM2B Write protection page 34 */ 137 #define SYSCFG_SRAM2WRP_PAGE35 LL_SYSCFG_SRAM2WRP_PAGE35 /*!< SRAM2B Write protection page 35 */ 138 #if defined(LL_SYSCFG_SRAM2WRP_PAGE36) 139 #define SYSCFG_SRAM2WRP_PAGE36 LL_SYSCFG_SRAM2WRP_PAGE36 /*!< SRAM2B Write protection page 36 */ 140 #define SYSCFG_SRAM2WRP_PAGE37 LL_SYSCFG_SRAM2WRP_PAGE37 /*!< SRAM2B Write protection page 37 */ 141 #define SYSCFG_SRAM2WRP_PAGE38 LL_SYSCFG_SRAM2WRP_PAGE38 /*!< SRAM2B Write protection page 38 */ 142 #define SYSCFG_SRAM2WRP_PAGE39 LL_SYSCFG_SRAM2WRP_PAGE39 /*!< SRAM2B Write protection page 39 */ 143 #define SYSCFG_SRAM2WRP_PAGE40 LL_SYSCFG_SRAM2WRP_PAGE40 /*!< SRAM2B Write protection page 40 */ 144 #define SYSCFG_SRAM2WRP_PAGE41 LL_SYSCFG_SRAM2WRP_PAGE41 /*!< SRAM2B Write protection page 41 */ 145 #define SYSCFG_SRAM2WRP_PAGE42 LL_SYSCFG_SRAM2WRP_PAGE42 /*!< SRAM2B Write protection page 42 */ 146 #define SYSCFG_SRAM2WRP_PAGE43 LL_SYSCFG_SRAM2WRP_PAGE43 /*!< SRAM2B Write protection page 43 */ 147 #define SYSCFG_SRAM2WRP_PAGE44 LL_SYSCFG_SRAM2WRP_PAGE44 /*!< SRAM2B Write protection page 44 */ 148 #define SYSCFG_SRAM2WRP_PAGE45 LL_SYSCFG_SRAM2WRP_PAGE45 /*!< SRAM2B Write protection page 45 */ 149 #define SYSCFG_SRAM2WRP_PAGE46 LL_SYSCFG_SRAM2WRP_PAGE46 /*!< SRAM2B Write protection page 46 */ 150 #define SYSCFG_SRAM2WRP_PAGE47 LL_SYSCFG_SRAM2WRP_PAGE47 /*!< SRAM2B Write protection page 47 */ 151 #define SYSCFG_SRAM2WRP_PAGE48 LL_SYSCFG_SRAM2WRP_PAGE48 /*!< SRAM2B Write protection page 48 */ 152 #define SYSCFG_SRAM2WRP_PAGE49 LL_SYSCFG_SRAM2WRP_PAGE49 /*!< SRAM2B Write protection page 49 */ 153 #define SYSCFG_SRAM2WRP_PAGE50 LL_SYSCFG_SRAM2WRP_PAGE50 /*!< SRAM2B Write protection page 50 */ 154 #define SYSCFG_SRAM2WRP_PAGE51 LL_SYSCFG_SRAM2WRP_PAGE51 /*!< SRAM2B Write protection page 51 */ 155 #define SYSCFG_SRAM2WRP_PAGE52 LL_SYSCFG_SRAM2WRP_PAGE52 /*!< SRAM2B Write protection page 52 */ 156 #define SYSCFG_SRAM2WRP_PAGE53 LL_SYSCFG_SRAM2WRP_PAGE53 /*!< SRAM2B Write protection page 53 */ 157 #define SYSCFG_SRAM2WRP_PAGE54 LL_SYSCFG_SRAM2WRP_PAGE54 /*!< SRAM2B Write protection page 54 */ 158 #define SYSCFG_SRAM2WRP_PAGE55 LL_SYSCFG_SRAM2WRP_PAGE55 /*!< SRAM2B Write protection page 55 */ 159 #define SYSCFG_SRAM2WRP_PAGE56 LL_SYSCFG_SRAM2WRP_PAGE56 /*!< SRAM2B Write protection page 56 */ 160 #define SYSCFG_SRAM2WRP_PAGE57 LL_SYSCFG_SRAM2WRP_PAGE57 /*!< SRAM2B Write protection page 57 */ 161 #define SYSCFG_SRAM2WRP_PAGE58 LL_SYSCFG_SRAM2WRP_PAGE58 /*!< SRAM2B Write protection page 58 */ 162 #define SYSCFG_SRAM2WRP_PAGE59 LL_SYSCFG_SRAM2WRP_PAGE59 /*!< SRAM2B Write protection page 59 */ 163 #define SYSCFG_SRAM2WRP_PAGE60 LL_SYSCFG_SRAM2WRP_PAGE60 /*!< SRAM2B Write protection page 60 */ 164 #define SYSCFG_SRAM2WRP_PAGE61 LL_SYSCFG_SRAM2WRP_PAGE61 /*!< SRAM2B Write protection page 61 */ 165 #define SYSCFG_SRAM2WRP_PAGE62 LL_SYSCFG_SRAM2WRP_PAGE62 /*!< SRAM2B Write protection page 62 */ 166 #define SYSCFG_SRAM2WRP_PAGE63 LL_SYSCFG_SRAM2WRP_PAGE63 /*!< SRAM2B Write protection page 63 */ 167 #endif /* LL_SYSCFG_SRAM2WRP_PAGE36 */ 168 169 /** 170 * @} 171 */ 172 173 #if defined(VREFBUF) 174 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 175 * @{ 176 */ 177 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 LL_VREFBUF_VOLTAGE_SCALE0 /*!< Voltage reference scale 0 (VREF_OUT1) */ 178 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 LL_VREFBUF_VOLTAGE_SCALE1 /*!< Voltage reference scale 1 (VREF_OUT2) */ 179 180 /** 181 * @} 182 */ 183 184 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 185 * @{ 186 */ 187 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 188 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 189 190 /** 191 * @} 192 */ 193 #endif /* VREFBUF */ 194 195 /** @defgroup SYSCFG_SRAM_flags_definition SRAM Flags 196 * @{ 197 */ 198 199 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ 200 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ 201 202 /** 203 * @} 204 */ 205 206 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 207 * @{ 208 */ 209 210 /** @brief Fast-mode Plus driving capability on a specific GPIO 211 */ 212 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 213 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 214 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 215 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 216 217 /** 218 * @} 219 */ 220 221 /** @defgroup Secure_IP_Write_Access Secure IP Write Access 222 * @{ 223 */ 224 #if defined(LL_SYSCFG_SECURE_ACCESS_AES1) 225 #define HAL_SYSCFG_SECURE_ACCESS_AES1 LL_SYSCFG_SECURE_ACCESS_AES1 /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */ 226 #endif /* LL_SYSCFG_SECURE_ACCESS_AES1 */ 227 #define HAL_SYSCFG_SECURE_ACCESS_AES2 LL_SYSCFG_SECURE_ACCESS_AES2 /*!< Enabling the security access of Advanced Encryption Standard 2 */ 228 #define HAL_SYSCFG_SECURE_ACCESS_PKA LL_SYSCFG_SECURE_ACCESS_PKA /*!< Enabling the security access of Public Key Accelerator */ 229 #define HAL_SYSCFG_SECURE_ACCESS_RNG LL_SYSCFG_SECURE_ACCESS_RNG /*!< Enabling the security access of Random Number Generator */ 230 /** 231 * @} 232 */ 233 234 /** 235 * @} 236 */ 237 238 /** 239 * @} 240 */ 241 242 /* Exported macros -----------------------------------------------------------*/ 243 /** @defgroup HAL_Exported_Macros HAL Exported Macros 244 * @{ 245 */ 246 247 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 248 * @{ 249 */ 250 251 /** @brief Freeze and Unfreeze Peripherals in Debug mode 252 */ 253 254 /** @defgroup DBGMCU_APBx_GRPx_STOP_IP DBGMCU CPU1 APBx GRPx STOP IP 255 * @{ 256 */ 257 #if defined(LL_DBGMCU_APB1_GRP1_TIM2_STOP) 258 #define __HAL_DBGMCU_FREEZE_TIM2() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP) 259 #define __HAL_DBGMCU_UNFREEZE_TIM2() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP) 260 #endif /* LL_DBGMCU_APB1_GRP1_TIM2_STOP */ 261 262 #if defined(LL_DBGMCU_APB1_GRP1_RTC_STOP) 263 #define __HAL_DBGMCU_FREEZE_RTC() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP) 264 #define __HAL_DBGMCU_UNFREEZE_RTC() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP) 265 #endif /* LL_DBGMCU_APB1_GRP1_RTC_STOP */ 266 267 #if defined(LL_DBGMCU_APB1_GRP1_WWDG_STOP) 268 #define __HAL_DBGMCU_FREEZE_WWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP) 269 #define __HAL_DBGMCU_UNFREEZE_WWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP) 270 #endif /* LL_DBGMCU_APB1_GRP1_WWDG_STOP */ 271 272 #if defined(LL_DBGMCU_APB1_GRP1_IWDG_STOP) 273 #define __HAL_DBGMCU_FREEZE_IWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP) 274 #define __HAL_DBGMCU_UNFREEZE_IWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP) 275 #endif /* LL_DBGMCU_APB1_GRP1_IWDG_STOP */ 276 277 #if defined(LL_DBGMCU_APB1_GRP1_I2C1_STOP) 278 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP) 279 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP) 280 #endif /* LL_DBGMCU_APB1_GRP1_I2C1_STOP */ 281 282 #if defined(LL_DBGMCU_APB1_GRP1_I2C3_STOP) 283 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP) 284 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP) 285 #endif /* LL_DBGMCU_APB1_GRP1_I2C3_STOP */ 286 287 #if defined(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP) 288 #define __HAL_DBGMCU_FREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP) 289 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP) 290 #endif /* LL_DBGMCU_APB1_GRP1_LPTIM1_STOP */ 291 292 #if defined(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP) 293 #define __HAL_DBGMCU_FREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP) 294 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP) 295 #endif /* LL_DBGMCU_APB1_GRP2_LPTIM2_STOP */ 296 297 #if defined(LL_DBGMCU_APB2_GRP1_TIM1_STOP) 298 #define __HAL_DBGMCU_FREEZE_TIM1() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP) 299 #define __HAL_DBGMCU_UNFREEZE_TIM1() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP) 300 #endif /* LL_DBGMCU_APB2_GRP1_TIM1_STOP */ 301 302 #if defined(LL_DBGMCU_APB2_GRP1_TIM16_STOP) 303 #define __HAL_DBGMCU_FREEZE_TIM16() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP) 304 #define __HAL_DBGMCU_UNFREEZE_TIM16() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP) 305 #endif /* LL_DBGMCU_APB2_GRP1_TIM16_STOP */ 306 307 #if defined(LL_DBGMCU_APB2_GRP1_TIM17_STOP) 308 #define __HAL_DBGMCU_FREEZE_TIM17() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP) 309 #define __HAL_DBGMCU_UNFREEZE_TIM17() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP) 310 #endif /* LL_DBGMCU_APB2_GRP1_TIM17_STOP */ 311 312 /** 313 * @} 314 */ 315 316 /** @defgroup DBGMCU_C2_APBx_GRPx_STOP_IP DBGMCU CPU2 APBx GRPx STOP IP 317 * @{ 318 */ 319 #if defined(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP) 320 #define __HAL_C2_DBGMCU_FREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP) 321 #define __HAL_C2_DBGMCU_UNFREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP) 322 #endif /* LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP */ 323 324 #if defined(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP) 325 #define __HAL_C2_DBGMCU_FREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP) 326 #define __HAL_C2_DBGMCU_UNFREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP) 327 #endif /* LL_C2_DBGMCU_APB1_GRP1_RTC_STOP */ 328 329 #if defined(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP) 330 #define __HAL_C2_DBGMCU_FREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP) 331 #define __HAL_C2_DBGMCU_UNFREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP) 332 #endif /* LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP */ 333 334 #if defined(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP) 335 #define __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP) 336 #define __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP) 337 #endif /* LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP */ 338 339 #if defined(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP) 340 #define __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP) 341 #define __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP) 342 #endif /* LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP */ 343 344 #if defined(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP) 345 #define __HAL_C2_DBGMCU_FREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP) 346 #define __HAL_C2_DBGMCU_UNFREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP) 347 #endif /* LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP */ 348 349 #if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP) 350 #define __HAL_C2_DBGMCU_FREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP) 351 #define __HAL_C2_DBGMCU_UNFREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP) 352 #endif /* LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP */ 353 354 #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP) 355 #define __HAL_C2_DBGMCU_FREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP) 356 #define __HAL_C2_DBGMCU_UNFREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP) 357 #endif /* LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP */ 358 359 #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP) 360 #define __HAL_C2_DBGMCU_FREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP) 361 #define __HAL_C2_DBGMCU_UNFREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP) 362 #endif /* LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP */ 363 364 #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP) 365 #define __HAL_C2_DBGMCU_FREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP) 366 #define __HAL_C2_DBGMCU_UNFREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP) 367 #endif /* LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP */ 368 369 /** 370 * @} 371 */ 372 373 /** 374 * @} 375 */ 376 377 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 378 * @{ 379 */ 380 381 /** @brief Main Flash memory mapped at 0x00000000 382 */ 383 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH) 384 385 /** @brief System Flash memory mapped at 0x00000000 386 */ 387 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SYSTEMFLASH) 388 389 /** @brief Embedded SRAM mapped at 0x00000000 390 */ 391 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM) 392 393 #if defined(LL_SYSCFG_REMAP_QUADSPI) 394 /** @brief QUADSPI mapped at 0x00000000. 395 */ 396 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_QUADSPI) 397 #endif /* LL_SYSCFG_REMAP_QUADSPI */ 398 399 /** 400 * @brief Return the boot mode as configured by user. 401 * @retval The boot mode as configured by user. The returned value can be one 402 * of the following values: 403 * @arg @ref SYSCFG_BOOT_MAINFLASH 404 * @arg @ref SYSCFG_BOOT_SYSTEMFLASH 405 * @arg @ref SYSCFG_BOOT_SRAM 406 #if defined(LL_SYSCFG_REMAP_QUADSPI) 407 * @arg @ref SYSCFG_BOOT_QUADSPI 408 #endif 409 */ 410 #define __HAL_SYSCFG_GET_BOOT_MODE() LL_SYSCFG_GetRemapMemory() 411 412 /** @brief SRAM2 page 0 to 31 write protection enable macro 413 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP 414 * @note Write protection can only be disabled by a system reset 415 */ 416 /* Legacy define */ 417 #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE 418 #define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__) \ 419 do { \ 420 assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__))); \ 421 LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__); \ 422 } while(0) 423 424 /** @brief SRAM2 page 32 to 63 write protection enable macro 425 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63 426 * @note Write protection can only be disabled by a system reset 427 */ 428 #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) \ 429 do { \ 430 assert_param(IS_SYSCFG_SRAM2WRP2_PAGE((__SRAM2WRP__))); \ 431 LL_SYSCFG_EnableSRAM2PageWRP_32_63(__SRAM2WRP__); \ 432 } while(0) 433 434 /** @brief SRAM2 page write protection unlock prior to erase 435 * @note Writing a wrong key reactivates the write protection 436 */ 437 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() LL_SYSCFG_UnlockSRAM2WRP() 438 439 /** @brief SRAM2 erase 440 * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase 441 */ 442 #define __HAL_SYSCFG_SRAM2_ERASE() LL_SYSCFG_EnableSRAM2Erase() 443 444 /** @brief Floating Point Unit interrupt enable/disable macros 445 * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts 446 */ 447 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) \ 448 do { \ 449 assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__))); \ 450 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__)); \ 451 } while(0) 452 453 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) \ 454 do { \ 455 assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__))); \ 456 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__)); \ 457 } while(0) 458 459 /** @brief SYSCFG Break ECC lock. 460 * Enable and lock the connection of Flash ECC error connection to TIM1/16/17 Break input. 461 * @note The selected configuration is locked and can be unlocked only by system reset. 462 */ 463 #define __HAL_SYSCFG_BREAK_ECC_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_ECC) 464 465 /** @brief SYSCFG Break Cortex-M4 Lockup lock. 466 * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/16/17 Break input. 467 * @note The selected configuration is locked and can be unlocked only by system reset. 468 */ 469 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP) 470 471 /** @brief SYSCFG Break PVD lock. 472 * Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0] 473 * in the PWR_CR2 register. 474 * @note The selected configuration is locked and can be unlocked only by system reset. 475 */ 476 #define __HAL_SYSCFG_BREAK_PVD_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD) 477 478 /** @brief SYSCFG Break SRAM2 parity lock. 479 * Enable and lock the SRAM2 parity error signal connection to TIM1/16/17 Break input. 480 * @note The selected configuration is locked and can be unlocked by system reset. 481 */ 482 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_SRAM2_PARITY) 483 484 /** @brief Check SYSCFG flag is set or not. 485 * @param __FLAG__ specifies the flag to check. 486 * This parameter can be one of the following values: 487 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 488 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing 489 * @retval The new state of __FLAG__ (TRUE or FALSE). 490 */ 491 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & \ 492 (__FLAG__))!= 0U) ? 1U : 0U) 493 494 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 495 */ 496 #define __HAL_SYSCFG_CLEAR_FLAG() LL_SYSCFG_ClearFlag_SP() 497 498 /** @brief Fast mode Plus driving capability enable/disable macros 499 * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO 500 */ 501 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \ 502 do { \ 503 assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ 504 LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__); \ 505 } while(0) 506 507 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \ 508 do { \ 509 assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ 510 LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__); \ 511 } while(0) 512 513 /** 514 * @} 515 */ 516 517 /** 518 * @} 519 */ 520 521 /* Private macros ------------------------------------------------------------*/ 522 /** @defgroup HAL_Private_Macros HAL Private Macros 523 * @{ 524 */ 525 526 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 527 * @{ 528 */ 529 530 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 531 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 532 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 533 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 534 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 535 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) 536 537 #if defined(STM32WB15xx) || defined(STM32WB10xx) 538 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU)) 539 #define IS_SYSCFG_SRAM2WRP2_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x0000000FU)) 540 #else 541 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU)) 542 #define IS_SYSCFG_SRAM2WRP2_PAGE(__PAGE__) IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) 543 #endif /* STM32WB15xx || STM32WB10xx */ 544 545 #if defined(VREFBUF) 546 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 547 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) 548 549 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 550 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 551 552 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 553 #endif /* VREFBUF */ 554 555 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 556 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 557 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 558 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 559 560 #if defined(LL_SYSCFG_SECURE_ACCESS_AES1) 561 #define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES1) == HAL_SYSCFG_SECURE_ACCESS_AES1) || \ 562 (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \ 563 (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \ 564 (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG)) 565 #else 566 #define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \ 567 (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \ 568 (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG)) 569 #endif /* LL_SYSCFG_SECURE_ACCESS_AES1 */ 570 571 /** 572 * @} 573 */ 574 575 /** 576 * @} 577 */ 578 579 /** @defgroup HAL_Private_Macros HAL Private Macros 580 * @{ 581 */ 582 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 583 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 584 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 585 /** 586 * @} 587 */ 588 589 590 /* Exported functions --------------------------------------------------------*/ 591 592 /** @defgroup HAL_Exported_Functions HAL Exported Functions 593 * @{ 594 */ 595 596 /** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions 597 * @{ 598 */ 599 600 /* Initialization and Configuration functions ******************************/ 601 HAL_StatusTypeDef HAL_Init(void); 602 HAL_StatusTypeDef HAL_DeInit(void); 603 void HAL_MspInit(void); 604 void HAL_MspDeInit(void); 605 606 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 607 608 /** 609 * @} 610 */ 611 612 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions 613 * @{ 614 */ 615 616 /* Peripheral Control functions ************************************************/ 617 void HAL_IncTick(void); 618 void HAL_Delay(uint32_t Delay); 619 uint32_t HAL_GetTick(void); 620 uint32_t HAL_GetTickPrio(void); 621 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 622 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 623 void HAL_SuspendTick(void); 624 void HAL_ResumeTick(void); 625 uint32_t HAL_GetHalVersion(void); 626 uint32_t HAL_GetREVID(void); 627 uint32_t HAL_GetDEVID(void); 628 uint32_t HAL_GetUIDw0(void); 629 uint32_t HAL_GetUIDw1(void); 630 uint32_t HAL_GetUIDw2(void); 631 632 /** 633 * @} 634 */ 635 636 /** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions 637 * @{ 638 */ 639 640 /* DBGMCU Peripheral Control functions *****************************************/ 641 void HAL_DBGMCU_EnableDBGSleepMode(void); 642 void HAL_DBGMCU_DisableDBGSleepMode(void); 643 void HAL_DBGMCU_EnableDBGStopMode(void); 644 void HAL_DBGMCU_DisableDBGStopMode(void); 645 void HAL_DBGMCU_EnableDBGStandbyMode(void); 646 void HAL_DBGMCU_DisableDBGStandbyMode(void); 647 /** 648 * @} 649 */ 650 651 /* Exported variables ---------------------------------------------------------*/ 652 /** @addtogroup HAL_Exported_Variables 653 * @{ 654 */ 655 extern __IO uint32_t uwTick; 656 extern uint32_t uwTickPrio; 657 extern HAL_TickFreqTypeDef uwTickFreq; 658 /** 659 * @} 660 */ 661 662 /** @addtogroup HAL_Exported_Functions_Group4 HAL System Configuration functions 663 * @{ 664 */ 665 666 /* SYSCFG Control functions ****************************************************/ 667 void HAL_SYSCFG_SRAM2Erase(void); 668 void HAL_SYSCFG_DisableSRAMFetch(void); 669 uint32_t HAL_SYSCFG_IsEnabledSRAMFetch(void); 670 671 #if defined(VREFBUF) 672 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 673 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 674 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 675 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 676 void HAL_SYSCFG_DisableVREFBUF(void); 677 #endif /* VREFBUF */ 678 679 void HAL_SYSCFG_EnableIOBooster(void); 680 void HAL_SYSCFG_DisableIOBooster(void); 681 #if defined(SYSCFG_CFGR1_ANASWVDD) 682 void HAL_SYSCFG_EnableIOVdd(void); 683 void HAL_SYSCFG_DisableIOVdd(void); 684 #endif /* SYSCFG_CFGR1_ANASWVDD */ 685 686 void HAL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess); 687 void HAL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess); 688 uint32_t HAL_SYSCFG_IsEnabledSecurityAccess(uint32_t SecurityAccess); 689 690 /** 691 * @} 692 */ 693 694 /** 695 * @} 696 */ 697 698 /** 699 * @} 700 */ 701 702 /** 703 * @} 704 */ 705 706 #ifdef __cplusplus 707 } 708 #endif 709 710 #endif /* STM32WBxx_HAL_H */ 711
