1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### LL DMA driver acronyms #####
20 ==============================================================================
21 [..] Acronyms table :
22 =========================================
23 || Acronym || ||
24 =========================================
25 || SRC || Source ||
26 || DEST || Destination ||
27 || ADDR || Address ||
28 || ADDRS || Addresses ||
29 || INC || Increment / Incremented ||
30 || DEC || Decrement / Decremented ||
31 || BLK || Block ||
32 || RPT || Repeat / Repeated ||
33 || TRIG || Trigger ||
34 =========================================
35 @endverbatim
36 ******************************************************************************
37 */
38
39 #if defined (USE_FULL_LL_DRIVER)
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32wbaxx_ll_dma.h"
43 #include "stm32wbaxx_ll_bus.h"
44 #ifdef USE_FULL_ASSERT
45 #include "stm32_assert.h"
46 #else
47 #define assert_param(expr) ((void)0U)
48 #endif /* USE_FULL_ASSERT */
49
50 /** @addtogroup STM32WBAxx_LL_Driver
51 * @{
52 */
53
54 #if defined (GPDMA1)
55
56 /** @addtogroup DMA_LL
57 * @{
58 */
59
60 /* Private types -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62 /* Private constants ---------------------------------------------------------*/
63 /* Private macros ------------------------------------------------------------*/
64
65 /** @addtogroup DMA_LL_Private_Macros
66 * @{
67 */
68 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \
69 (((Channel) == LL_DMA_CHANNEL_0) || \
70 ((Channel) == LL_DMA_CHANNEL_1) || \
71 ((Channel) == LL_DMA_CHANNEL_2) || \
72 ((Channel) == LL_DMA_CHANNEL_3) || \
73 ((Channel) == LL_DMA_CHANNEL_4) || \
74 ((Channel) == LL_DMA_CHANNEL_5) || \
75 ((Channel) == LL_DMA_CHANNEL_6) || \
76 ((Channel) == LL_DMA_CHANNEL_7) || \
77 ((Channel) == LL_DMA_CHANNEL_ALL)))
78
79 #define IS_LL_GPDMA_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \
80 (((Channel) == LL_DMA_CHANNEL_0) || \
81 ((Channel) == LL_DMA_CHANNEL_1) || \
82 ((Channel) == LL_DMA_CHANNEL_2) || \
83 ((Channel) == LL_DMA_CHANNEL_3) || \
84 ((Channel) == LL_DMA_CHANNEL_4) || \
85 ((Channel) == LL_DMA_CHANNEL_5) || \
86 ((Channel) == LL_DMA_CHANNEL_6) || \
87 ((Channel) == LL_DMA_CHANNEL_7)))
88
89 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY) || \
90 ((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
91 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH))
92
93 #define IS_LL_DMA_DATA_ALIGNMENT(__VALUE__) (((__VALUE__) == LL_DMA_DATA_ALIGN_ZEROPADD) || \
94 ((__VALUE__) == LL_DMA_DATA_ALIGN_SIGNEXTPADD) || \
95 ((__VALUE__) == LL_DMA_DATA_PACK_UNPACK))
96
97 #define IS_LL_DMA_BURST_LENGTH(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= 64U))
98
99 #define IS_LL_DMA_SRC_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_SRC_DATAWIDTH_BYTE) || \
100 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_HALFWORD) || \
101 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_WORD))
102
103 #define IS_LL_DMA_DEST_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_DEST_DATAWIDTH_BYTE) || \
104 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_HALFWORD) || \
105 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_WORD))
106
107 #define IS_LL_DMA_SRC_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_FIXED) || \
108 ((__VALUE__) == LL_DMA_SRC_INCREMENT))
109
110 #define IS_LL_DMA_DEST_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_FIXED) || \
111 ((__VALUE__) == LL_DMA_DEST_INCREMENT))
112
113 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_LOW_PRIORITY_LOW_WEIGHT) || \
114 ((__VALUE__) == LL_DMA_LOW_PRIORITY_MID_WEIGHT) || \
115 ((__VALUE__) == LL_DMA_LOW_PRIORITY_HIGH_WEIGHT) || \
116 ((__VALUE__) == LL_DMA_HIGH_PRIORITY))
117
118 #define IS_LL_DMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0xFFFFU)
119
120 #define IS_LL_DMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x0EFFU)
121
122 #define IS_LL_DMA_TRIGGER_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TRIGM_BLK_TRANSFER) || \
123 ((__VALUE__) == LL_DMA_TRIGM_RPT_BLK_TRANSFER) || \
124 ((__VALUE__) == LL_DMA_TRIGM_LLI_LINK_TRANSFER) || \
125 ((__VALUE__) == LL_DMA_TRIGM_SINGLBURST_TRANSFER ))
126
127 #define IS_LL_DMA_TRIGGER_POLARITY(__VALUE__) (((__VALUE__) == LL_DMA_TRIG_POLARITY_MASKED) || \
128 ((__VALUE__) == LL_DMA_TRIG_POLARITY_RISING) || \
129 ((__VALUE__) == LL_DMA_TRIG_POLARITY_FALLING))
130
131 #define IS_LL_DMA_BLKHW_REQUEST(__VALUE__) (((__VALUE__) == LL_DMA_HWREQUEST_SINGLEBURST) || \
132 ((__VALUE__) == LL_DMA_HWREQUEST_BLK))
133
134 #if defined (TIM3)
135 #define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_TIM3_TRGO)
136 #else
137 #define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_ADC4_AWD1)
138 #endif /* defined (TIM3) */
139
140 #if defined (LPTIM2)
141 #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM2_UE)
142 #else
143 #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM1_UE)
144 #endif /* defined (LPTIM2) */
145
146 #define IS_LL_DMA_TRANSFER_EVENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TCEM_BLK_TRANSFER) || \
147 ((__VALUE__) == LL_DMA_TCEM_RPT_BLK_TRANSFER) || \
148 ((__VALUE__) == LL_DMA_TCEM_EACH_LLITEM_TRANSFER) || \
149 ((__VALUE__) == LL_DMA_TCEM_LAST_LLITEM_TRANSFER))
150
151 #define IS_LL_DMA_DEST_HALFWORD_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_HALFWORD_PRESERVE) || \
152 ((__VALUE__) == LL_DMA_DEST_HALFWORD_EXCHANGE))
153
154 #define IS_LL_DMA_DEST_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_BYTE_PRESERVE) || \
155 ((__VALUE__) == LL_DMA_DEST_BYTE_EXCHANGE))
156
157 #define IS_LL_DMA_SRC_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_BYTE_PRESERVE) || \
158 ((__VALUE__) == LL_DMA_SRC_BYTE_EXCHANGE))
159
160 #define IS_LL_DMA_LINK_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT0) || \
161 ((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT1))
162
163 #define IS_LL_DMA_SRC_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT0) || \
164 ((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT1))
165
166 #define IS_LL_DMA_DEST_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT0) || \
167 ((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT1))
168
169 #define IS_LL_DMA_LINK_STEP_MODE(__VALUE__) (((__VALUE__) == LL_DMA_LSM_FULL_EXECUTION) || \
170 ((__VALUE__) == LL_DMA_LSM_1LINK_EXECUTION))
171
172 #define IS_LL_DMA_BURST_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_SRC_ADDR_INCREMENT) || \
173 ((__VALUE__) == LL_DMA_BURST_SRC_ADDR_DECREMENT))
174
175 #define IS_LL_DMA_BURST_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_DEST_ADDR_INCREMENT) || \
176 ((__VALUE__) == LL_DMA_BURST_DEST_ADDR_DECREMENT))
177
178 #define IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
179
180 #define IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_INCREMENT) || \
181 ((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_DECREMENT))
182
183 #define IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_INCREMENT) || \
184 ((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_DECREMENT))
185
186 #define IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0xFFFFU)
187
188 #define IS_LL_DMA_LINK_BASEADDR(__VALUE__) (((__VALUE__) & 0xFFFFU) == 0U)
189
190 #define IS_LL_DMA_LINK_ADDR_OFFSET(__VALUE__) (((__VALUE__) & 0x03U) == 0U)
191
192 #define IS_LL_DMA_LINK_UPDATE_REGISTERS(__VALUE__) ((((__VALUE__) & 0x01FE0000U) == 0U) && ((__VALUE__) != 0U))
193
194 #define IS_LL_DMA_LINK_NODETYPE(__VALUE__) ((__VALUE__) == LL_DMA_GPDMA_LINEAR_NODE)
195
196 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
197 #define IS_LL_DMA_CHANNEL_SRC_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_SRC_NSEC) || \
198 ((__VALUE__) == LL_DMA_CHANNEL_SRC_SEC))
199
200 #define IS_LL_DMA_CHANNEL_DEST_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_DEST_NSEC) || \
201 ((__VALUE__) == LL_DMA_CHANNEL_DEST_SEC))
202
203 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
204 /**
205 * @}
206 */
207
208 /* Private function prototypes -----------------------------------------------*/
209 /* Exported functions --------------------------------------------------------*/
210
211 /** @addtogroup DMA_LL_Exported_Functions
212 * @{
213 */
214
215 /** @addtogroup DMA_LL_EF_Init
216 * @{
217 */
218
219 /**
220 * @brief De-initialize the DMA registers to their default reset values.
221 * @note This API is used for all available DMA channels.
222 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
223 * helper macros :
224 * @arg @ref LL_DMA_GET_INSTANCE
225 * @arg @ref LL_DMA_GET_CHANNEL
226 * @param DMAx DMAx Instance
227 * @param Channel This parameter can be one of the following values:
228 * @arg @ref LL_DMA_CHANNEL_0
229 * @arg @ref LL_DMA_CHANNEL_1
230 * @arg @ref LL_DMA_CHANNEL_2
231 * @arg @ref LL_DMA_CHANNEL_3
232 * @arg @ref LL_DMA_CHANNEL_4
233 * @arg @ref LL_DMA_CHANNEL_5
234 * @arg @ref LL_DMA_CHANNEL_6
235 * @arg @ref LL_DMA_CHANNEL_7
236 * @retval An ErrorStatus enumeration value:
237 * - SUCCESS : DMA registers are de-initialized.
238 * - ERROR : DMA registers are not de-initialized.
239 */
LL_DMA_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)240 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
241 {
242 DMA_Channel_TypeDef *tmp;
243 ErrorStatus status = SUCCESS;
244
245 /* Check the DMA Instance DMAx and Channel parameters */
246 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
247
248 if (Channel == LL_DMA_CHANNEL_ALL)
249 {
250 /* Force reset of DMA clock */
251 LL_AHB2_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
252
253 /* Release reset of DMA clock */
254 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
255 }
256 else
257 {
258 /* Get the DMA Channel Instance */
259 tmp = (DMA_Channel_TypeDef *)(LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
260
261 /* Suspend DMA channel */
262 LL_DMA_SuspendChannel(DMAx, Channel);
263
264 /* Disable the selected Channel */
265 LL_DMA_ResetChannel(DMAx, Channel);
266
267 /* Reset DMAx_Channely control register */
268 LL_DMA_WriteReg(tmp, CLBAR, 0U);
269
270 /* Reset DMAx_Channely control register */
271 LL_DMA_WriteReg(tmp, CCR, 0U);
272
273 /* Reset DMAx_Channely Configuration register */
274 LL_DMA_WriteReg(tmp, CTR1, 0U);
275
276 /* Reset DMAx_Channely transfer register 2 */
277 LL_DMA_WriteReg(tmp, CTR2, 0U);
278
279 /* Reset DMAx_Channely block number of data register */
280 LL_DMA_WriteReg(tmp, CBR1, 0U);
281
282 /* Reset DMAx_Channely source address register */
283 LL_DMA_WriteReg(tmp, CSAR, 0U);
284
285 /* Reset DMAx_Channely destination address register */
286 LL_DMA_WriteReg(tmp, CDAR, 0U);
287
288
289 /* Reset DMAx_Channely Linked list address register */
290 LL_DMA_WriteReg(tmp, CLLR, 0U);
291
292 /* Reset DMAx_Channely pending flags */
293 LL_DMA_WriteReg(tmp, CFCR, 0x00003F00U);
294 #if defined (DMA_PRIVCFGR_PRIV0)
295 /* Reset DMAx_Channely attribute */
296 LL_DMA_DisableChannelPrivilege(DMAx, Channel);
297 #endif /* defined (DMA_PRIVCFGR_PRIV0) */
298 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
299 LL_DMA_DisableChannelSecure(DMAx, Channel);
300 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
301 }
302
303 return (uint32_t)status;
304 }
305
306 /**
307 * @brief Initialize the DMA registers according to the specified parameters
308 * in DMA_InitStruct.
309 * @note This API is used for all available DMA channels.
310 * @note A software request transfer can be done once programming the direction
311 * field in memory to memory value.
312 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
313 * helper macros :
314 * @arg @ref LL_DMA_GET_INSTANCE
315 * @arg @ref LL_DMA_GET_CHANNEL
316 * @param DMAx DMAx Instance
317 * @param Channel This parameter can be one of the following values:
318 * @arg @ref LL_DMA_CHANNEL_0
319 * @arg @ref LL_DMA_CHANNEL_1
320 * @arg @ref LL_DMA_CHANNEL_2
321 * @arg @ref LL_DMA_CHANNEL_3
322 * @arg @ref LL_DMA_CHANNEL_4
323 * @arg @ref LL_DMA_CHANNEL_5
324 * @arg @ref LL_DMA_CHANNEL_6
325 * @arg @ref LL_DMA_CHANNEL_7
326 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
327 * @retval An ErrorStatus enumeration value:
328 * - SUCCESS : DMA registers are initialized.
329 * - ERROR : Not applicable.
330 */
LL_DMA_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitTypeDef * DMA_InitStruct)331 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
332 {
333 /* Check the DMA Instance DMAx and Channel parameters*/
334 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
335
336 /* Check the DMA parameters from DMA_InitStruct */
337 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
338
339 /* Check direction */
340 if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
341 {
342 assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitStruct->Request));
343 }
344
345 assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitStruct->DataAlignment));
346 assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitStruct->SrcDataWidth));
347 assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitStruct->DestDataWidth));
348 assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitStruct->SrcIncMode));
349 assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitStruct->DestIncMode));
350 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
351 assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitStruct->BlkDataLength));
352 assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitStruct->TriggerPolarity));
353 assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitStruct->BlkHWRequest));
354 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitStruct->TransferEventMode));
355 assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitStruct->LinkStepMode));
356 assert_param(IS_LL_DMA_LINK_BASEADDR(DMA_InitStruct->LinkedListBaseAddr));
357 assert_param(IS_LL_DMA_LINK_ADDR_OFFSET(DMA_InitStruct->LinkedListAddrOffset));
358
359 /* Check DMA instance */
360 if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
361 {
362 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->SrcBurstLength));
363 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->DestBurstLength));
364 assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitStruct->DestHWordExchange));
365 assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitStruct->DestByteExchange));
366 assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitStruct->SrcByteExchange));
367 assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitStruct->LinkAllocatedPort));
368 assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitStruct->SrcAllocatedPort));
369 assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitStruct->DestAllocatedPort));
370 }
371
372 /* Check trigger polarity */
373 if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
374 {
375 assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitStruct->TriggerMode));
376 assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitStruct->TriggerSelection));
377 }
378
379
380 /*-------------------------- DMAx CLBAR Configuration ------------------------
381 * Configure the Transfer linked list address with parameter :
382 * - LinkedListBaseAdd: DMA_CLBAR_LBA[31:16] bits
383 */
384 LL_DMA_SetLinkedListBaseAddr(DMAx, Channel, DMA_InitStruct->LinkedListBaseAddr);
385
386 /*-------------------------- DMAx CCR Configuration --------------------------
387 * Configure the control parameter :
388 * - LinkAllocatedPort: DMA_CCR_LAP bit
389 * - LinkStepMode: DMA_CCR_LSM bit
390 * - Priority: DMA_CCR_PRIO [23:22] bits
391 */
392 LL_DMA_ConfigControl(DMAx, Channel, DMA_InitStruct->Priority | \
393 DMA_InitStruct->LinkAllocatedPort | \
394 DMA_InitStruct->LinkStepMode);
395
396 /*-------------------------- DMAx CTR1 Configuration -------------------------
397 * Configure the Data transfer parameter :
398 * - DestAllocatedPort: DMA_CTR1_DAP bit
399 * - DestHWordExchange: DMA_CTR1_DHX bit
400 * - DestByteExchange: DMA_CTR1_DBX bit
401 * - DestIncMode: DMA_CTR1_DINC bit
402 * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
403 * - SrcAllocatedPort: DMA_CTR1_SAP bit
404 * - SrcByteExchange: DMA_CTR1_SBX bit
405 * - DataAlignment: DMA_CTR1_PAM [12:11] bits
406 * - SrcIncMode: DMA_CTR1_SINC bit
407 * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
408 * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
409 * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
410 */
411 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->DestAllocatedPort | \
412 DMA_InitStruct->DestHWordExchange | \
413 DMA_InitStruct->DestByteExchange | \
414 DMA_InitStruct->DestIncMode | \
415 DMA_InitStruct->DestDataWidth | \
416 DMA_InitStruct->SrcAllocatedPort | \
417 DMA_InitStruct->SrcByteExchange | \
418 DMA_InitStruct->DataAlignment | \
419 DMA_InitStruct->SrcIncMode | \
420 DMA_InitStruct->SrcDataWidth);
421 /* Check DMA instance */
422 if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
423 {
424 LL_DMA_ConfigBurstLength(DMAx, Channel, DMA_InitStruct->SrcBurstLength,
425 DMA_InitStruct->DestBurstLength);
426 }
427
428 /*-------------------------- DMAx CTR2 Configuration -------------------------
429 * Configure the channel transfer parameter :
430 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
431 * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
432 * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
433 * - BlkHWRequest: DMA_CTR2_BREQ bit
434 * - Direction: DMA_CTR2_DREQ bit
435 * - Direction: DMA_CTR2_SWREQ bit
436 * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
437 * - Request: DMA_CTR2_REQSEL [6:0] bits
438 */
439 LL_DMA_ConfigChannelTransfer(DMAx, Channel, DMA_InitStruct->TransferEventMode | \
440 DMA_InitStruct->TriggerPolarity | \
441 DMA_InitStruct->BlkHWRequest | \
442 DMA_InitStruct->Direction);
443
444 /* Check direction */
445 if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
446 {
447 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->Request);
448 }
449
450 /* Check trigger polarity */
451 if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
452 {
453 LL_DMA_SetHWTrigger(DMAx, Channel, DMA_InitStruct->TriggerSelection);
454 LL_DMA_SetTriggerMode(DMAx, Channel, DMA_InitStruct->TriggerMode);
455 }
456
457 /*-------------------------- DMAx CBR1 Configuration -------------------------
458 * Configure the Transfer Block counters and update mode with parameter :
459 * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
460 */
461 LL_DMA_SetBlkDataLength(DMAx, Channel, DMA_InitStruct->BlkDataLength);
462
463 /*-------------------------- DMAx CSAR and CDAR Configuration ----------------
464 * Configure the Transfer source address with parameter :
465 * - SrcAddress: DMA_CSAR_SA[31:0] bits
466 * - DestAddress: DMA_CDAR_DA[31:0] bits
467 */
468 LL_DMA_ConfigAddresses(DMAx, Channel, DMA_InitStruct->SrcAddress, DMA_InitStruct->DestAddress);
469
470 /*-------------------------- DMAx CLLR Configuration -------------------------
471 * Configure the Transfer linked list address with parameter :
472 * - DestAddrOffset: DMA_CLLR_LA[15:2] bits
473 */
474 LL_DMA_SetLinkedListAddrOffset(DMAx, Channel, DMA_InitStruct->LinkedListAddrOffset);
475
476 return (uint32_t)SUCCESS;
477 }
478
479 /**
480 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
481 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
482 * @retval None.
483 */
LL_DMA_StructInit(LL_DMA_InitTypeDef * DMA_InitStruct)484 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
485 {
486 /* Set DMA_InitStruct fields to default values */
487 DMA_InitStruct->SrcAddress = 0x00000000U;
488 DMA_InitStruct->DestAddress = 0x00000000U;
489 DMA_InitStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
490 DMA_InitStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
491 DMA_InitStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
492 DMA_InitStruct->SrcBurstLength = 1U;
493 DMA_InitStruct->DestBurstLength = 1U;
494 DMA_InitStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
495 DMA_InitStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
496 DMA_InitStruct->SrcIncMode = LL_DMA_SRC_FIXED;
497 DMA_InitStruct->DestIncMode = LL_DMA_DEST_FIXED;
498 DMA_InitStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
499 DMA_InitStruct->BlkDataLength = 0x00000000U;
500 DMA_InitStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
501 DMA_InitStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
502 DMA_InitStruct->TriggerSelection = 0x00000000U;
503 DMA_InitStruct->Request = 0x00000000U;
504 DMA_InitStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
505 DMA_InitStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
506 DMA_InitStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
507 DMA_InitStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
508 DMA_InitStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
509 DMA_InitStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
510 DMA_InitStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
511 DMA_InitStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
512 DMA_InitStruct->LinkedListBaseAddr = 0x00000000U;
513 DMA_InitStruct->LinkedListAddrOffset = 0x00000000U;
514 }
515
516 /**
517 * @brief Set each @ref LL_DMA_InitLinkedListTypeDef field to default value.
518 * @param DMA_InitLinkedListStruct Pointer to
519 * a @ref LL_DMA_InitLinkedListTypeDef structure.
520 * @retval None.
521 */
LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef * DMA_InitLinkedListStruct)522 void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
523 {
524 /* Set LL_DMA_InitLinkedListTypeDef fields to default values */
525 DMA_InitLinkedListStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
526 DMA_InitLinkedListStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
527 DMA_InitLinkedListStruct->TransferEventMode = LL_DMA_TCEM_LAST_LLITEM_TRANSFER;
528 DMA_InitLinkedListStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
529 }
530
531 /**
532 * @brief De-initialize the DMA linked list.
533 * @note This API is used for all available DMA channels.
534 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
535 * helper macros :
536 * @arg @ref LL_DMA_GET_INSTANCE
537 * @arg @ref LL_DMA_GET_CHANNEL
538 * @param DMAx DMAx Instance
539 * @param Channel This parameter can be one of the following values:
540 * @arg @ref LL_DMA_CHANNEL_0
541 * @arg @ref LL_DMA_CHANNEL_1
542 * @arg @ref LL_DMA_CHANNEL_2
543 * @arg @ref LL_DMA_CHANNEL_3
544 * @arg @ref LL_DMA_CHANNEL_4
545 * @arg @ref LL_DMA_CHANNEL_5
546 * @arg @ref LL_DMA_CHANNEL_6
547 * @arg @ref LL_DMA_CHANNEL_7
548 * @retval An ErrorStatus enumeration value:
549 * - SUCCESS : DMA registers are de-initialized.
550 * - ERROR : DMA registers are not de-initialized.
551 */
LL_DMA_List_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)552 uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
553 {
554 return LL_DMA_DeInit(DMAx, Channel);
555 }
556
557 /**
558 * @brief Initialize the DMA linked list according to the specified parameters
559 * in LL_DMA_InitLinkedListTypeDef.
560 * @note This API is used for all available DMA channels.
561 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
562 * helper macros :
563 * @arg @ref LL_DMA_GET_INSTANCE
564 * @arg @ref LL_DMA_GET_CHANNEL
565 * @param DMAx DMAx Instance
566 * @param Channel This parameter can be one of the following values:
567 * @arg @ref LL_DMA_CHANNEL_0
568 * @arg @ref LL_DMA_CHANNEL_1
569 * @arg @ref LL_DMA_CHANNEL_2
570 * @arg @ref LL_DMA_CHANNEL_3
571 * @arg @ref LL_DMA_CHANNEL_4
572 * @arg @ref LL_DMA_CHANNEL_5
573 * @arg @ref LL_DMA_CHANNEL_6
574 * @arg @ref LL_DMA_CHANNEL_7
575 * @param DMA_InitLinkedListStruct pointer to
576 * a @ref LL_DMA_InitLinkedListTypeDef structure.
577 * @retval An ErrorStatus enumeration value:
578 * - SUCCESS : DMA registers are initialized.
579 * - ERROR : Not applicable.
580 */
LL_DMA_List_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitLinkedListTypeDef * DMA_InitLinkedListStruct)581 uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
582 {
583 /* Check the DMA Instance DMAx and Channel parameters*/
584 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
585
586 /* Check the DMA parameters from DMA_InitLinkedListStruct */
587 assert_param(IS_LL_DMA_PRIORITY(DMA_InitLinkedListStruct->Priority));
588 assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitLinkedListStruct->LinkStepMode));
589 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitLinkedListStruct->TransferEventMode));
590 /* Check DMA instance */
591 if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
592 {
593 assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitLinkedListStruct->LinkAllocatedPort));
594 }
595
596 /*-------------------------- DMAx CCR Configuration --------------------------
597 * Configure the control parameter :
598 * - LinkAllocatedPort: DMA_CCR_LAP bit
599 * LinkAllocatedPort field is supported only by GPDMA channels.
600 * - LinkStepMode: DMA_CCR_LSM bit
601 * - Priority: DMA_CCR_PRIO [23:22] bits
602 */
603 LL_DMA_ConfigControl(DMAx, Channel, DMA_InitLinkedListStruct->Priority | \
604 DMA_InitLinkedListStruct->LinkAllocatedPort | \
605 DMA_InitLinkedListStruct->LinkStepMode);
606
607 /*-------------------------- DMAx CTR2 Configuration -------------------------
608 * Configure the channel transfer parameter :
609 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
610 */
611 LL_DMA_SetTransferEventMode(DMAx, Channel, DMA_InitLinkedListStruct->TransferEventMode);
612
613 return (uint32_t)SUCCESS;
614 }
615
616 /**
617 * @brief Set each @ref LL_DMA_InitNodeTypeDef field to default value.
618 * @param DMA_InitNodeStruct Pointer to a @ref LL_DMA_InitNodeTypeDef
619 * structure.
620 * @retval None.
621 */
LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef * DMA_InitNodeStruct)622 void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct)
623 {
624 /* Set DMA_InitNodeStruct fields to default values */
625 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
626 DMA_InitNodeStruct->DestSecure = LL_DMA_CHANNEL_DEST_NSEC;
627 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
628 DMA_InitNodeStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
629 DMA_InitNodeStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
630 DMA_InitNodeStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
631 DMA_InitNodeStruct->DestBurstLength = 1U;
632 DMA_InitNodeStruct->DestIncMode = LL_DMA_DEST_FIXED;
633 DMA_InitNodeStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
634 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
635 DMA_InitNodeStruct->SrcSecure = LL_DMA_CHANNEL_SRC_NSEC;
636 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
637 DMA_InitNodeStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
638 DMA_InitNodeStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
639 DMA_InitNodeStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
640 DMA_InitNodeStruct->SrcBurstLength = 1U;
641 DMA_InitNodeStruct->SrcIncMode = LL_DMA_SRC_FIXED;
642 DMA_InitNodeStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
643 DMA_InitNodeStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
644 DMA_InitNodeStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
645 DMA_InitNodeStruct->TriggerSelection = 0x00000000U;
646 DMA_InitNodeStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
647 DMA_InitNodeStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
648 DMA_InitNodeStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
649 DMA_InitNodeStruct->Request = 0x00000000U;
650 DMA_InitNodeStruct->BlkDataLength = 0x00000000U;
651 DMA_InitNodeStruct->SrcAddress = 0x00000000U;
652 DMA_InitNodeStruct->DestAddress = 0x00000000U;
653 DMA_InitNodeStruct->UpdateRegisters = (LL_DMA_UPDATE_CTR1 | LL_DMA_UPDATE_CTR2 | \
654 LL_DMA_UPDATE_CBR1 | LL_DMA_UPDATE_CSAR | \
655 LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CLLR);
656 DMA_InitNodeStruct->NodeType = LL_DMA_GPDMA_LINEAR_NODE;
657 }
658
659 /**
660 * @brief Initializes DMA linked list node according to the specified
661 * parameters in the DMA_InitNodeStruct.
662 * @param DMA_InitNodeStruct Pointer to a LL_DMA_InitNodeTypeDef structure
663 * that contains linked list node
664 * registers configurations.
665 * @param pNode Pointer to linked list node to fill according to
666 * LL_DMA_LinkNodeTypeDef parameters.
667 * @retval None
668 */
LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef * DMA_InitNodeStruct,LL_DMA_LinkNodeTypeDef * pNode)669 uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode)
670 {
671 uint32_t reg_counter = 0U;
672
673 /* Check the DMA Node type */
674 assert_param(IS_LL_DMA_LINK_NODETYPE(DMA_InitNodeStruct->NodeType));
675
676 /* Check the DMA parameters from DMA_InitNodeStruct */
677 assert_param(IS_LL_DMA_DIRECTION(DMA_InitNodeStruct->Direction));
678
679 /* Check direction */
680 if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
681 {
682 assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitNodeStruct->Request));
683 }
684
685 assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitNodeStruct->DataAlignment));
686 assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitNodeStruct->SrcDataWidth));
687 assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitNodeStruct->DestDataWidth));
688 assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitNodeStruct->SrcIncMode));
689 assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitNodeStruct->DestIncMode));
690 assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitNodeStruct->BlkDataLength));
691 assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitNodeStruct->TriggerPolarity));
692 assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitNodeStruct->BlkHWRequest));
693 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitNodeStruct->TransferEventMode));
694 assert_param(IS_LL_DMA_LINK_UPDATE_REGISTERS(DMA_InitNodeStruct->UpdateRegisters));
695
696 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
697 assert_param(IS_LL_DMA_CHANNEL_SRC_SEC(DMA_InitNodeStruct->SrcSecure));
698 assert_param(IS_LL_DMA_CHANNEL_DEST_SEC(DMA_InitNodeStruct->DestSecure));
699 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
700
701 /* Check trigger polarity */
702 if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
703 {
704 assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode));
705 assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection));
706 }
707
708 /* Check node type */
709 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_LINEAR_NODE)
710 {
711 assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitNodeStruct->DestHWordExchange));
712 assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitNodeStruct->DestByteExchange));
713 assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitNodeStruct->SrcByteExchange));
714 assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitNodeStruct->SrcAllocatedPort));
715 assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitNodeStruct->DestAllocatedPort));
716 }
717
718
719 /* Check if CTR1 register update is enabled */
720 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR1) == LL_DMA_UPDATE_CTR1)
721 {
722 /*-------------------------- DMAx CTR1 Configuration -----------------------
723 * Configure the Data transfer parameter :
724 * - DestAllocatedPort: DMA_CTR1_DAP bit
725 * - DestHWordExchange: DMA_CTR1_DHX bit
726 * - DestByteExchange: DMA_CTR1_DBX bit
727 * - DestIncMode: DMA_CTR1_DINC bit
728 * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
729 * - SrcAllocatedPort: DMA_CTR1_SAP bit
730 * - SrcByteExchange: DMA_CTR1_SBX bit
731 * - DataAlignment: DMA_CTR1_PAM [12:11] bits
732 * - SrcIncMode: DMA_CTR1_SINC bit
733 * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
734 * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
735 * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
736 */
737
738 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->DestIncMode | \
739 DMA_InitNodeStruct->DestDataWidth | \
740 DMA_InitNodeStruct->DataAlignment | \
741 DMA_InitNodeStruct->SrcIncMode | \
742 DMA_InitNodeStruct->SrcDataWidth);
743
744 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
745 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestSecure | \
746 DMA_InitNodeStruct->SrcSecure);
747 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
748
749 /* Update CTR1 register fields */
750 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestAllocatedPort | \
751 DMA_InitNodeStruct->DestHWordExchange | \
752 DMA_InitNodeStruct->DestByteExchange | \
753 ((DMA_InitNodeStruct->DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) | \
754 DMA_InitNodeStruct->SrcAllocatedPort | \
755 DMA_InitNodeStruct->SrcByteExchange | \
756 ((DMA_InitNodeStruct->SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos));
757
758 /* Increment counter for the next register */
759 reg_counter++;
760 }
761
762
763 /* Check if CTR2 register update is enabled */
764 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR2) == LL_DMA_UPDATE_CTR2)
765 {
766 /*-------------------------- DMAx CTR2 Configuration -----------------------
767 * Configure the channel transfer parameter :
768 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
769 * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
770 * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
771 * - BlkHWRequest: DMA_CTR2_BREQ bit
772 * - Direction: DMA_CTR2_DREQ bit
773 * - Direction: DMA_CTR2_SWREQ bit
774 * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
775 * - Request: DMA_CTR2_REQSEL [6:0] bits
776 */
777 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->TransferEventMode | \
778 DMA_InitNodeStruct->TriggerPolarity | \
779 DMA_InitNodeStruct->BlkHWRequest | \
780 DMA_InitNodeStruct->Direction);
781
782 /* Check direction */
783 if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
784 {
785 pNode->LinkRegisters[reg_counter] |= DMA_InitNodeStruct->Request & DMA_CTR2_REQSEL;
786 }
787
788 /* Check trigger polarity */
789 if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
790 {
791 pNode->LinkRegisters[reg_counter] |= (((DMA_InitNodeStruct->TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & \
792 DMA_CTR2_TRIGSEL) | DMA_InitNodeStruct->TriggerMode);
793 }
794
795
796 /* Increment counter for the next register */
797 reg_counter++;
798 }
799 /* Check if CBR1 register update is enabled */
800 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR1) == LL_DMA_UPDATE_CBR1)
801 {
802 /*-------------------------- DMAx CBR1 Configuration -----------------------
803 * Configure the Transfer Block counters and update mode with parameter :
804 * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
805 */
806 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->BlkDataLength;
807
808 /* Increment counter for the next register */
809 reg_counter++;
810 }
811 /* Check if CSAR register update is enabled */
812 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CSAR) == LL_DMA_UPDATE_CSAR)
813 {
814 /*-------------------------- DMAx CSAR Configuration -----------------------
815 * Configure the Transfer Block counters and update mode with parameter :
816 * - SrcAddress: DMA_CSAR_SA[31:0] bits
817 */
818 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->SrcAddress;
819
820 /* Increment counter for the next register */
821 reg_counter++;
822 }
823
824
825 /* Check if CDAR register update is enabled */
826 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CDAR) == LL_DMA_UPDATE_CDAR)
827 {
828 /*-------------------------- DMAx CDAR Configuration -----------------------
829 * Configure the Transfer Block counters and update mode with parameter :
830 * - DestAddress: DMA_CDAR_DA[31:0] bits
831 */
832 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->DestAddress;
833
834 /* Increment counter for the next register */
835 reg_counter++;
836 }
837
838
839
840 /* Check if CLLR register update is enabled */
841 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CLLR) == LL_DMA_UPDATE_CLLR)
842 {
843 /*-------------------------- DMAx CLLR Configuration -----------------------
844 * Configure the Transfer Block counters and update mode with parameter :
845 * - UpdateRegisters DMA_CLLR_UT1 bit
846 * - UpdateRegisters DMA_CLLR_UT2 bit
847 * - UpdateRegisters DMA_CLLR_UB1 bit
848 * - UpdateRegisters DMA_CLLR_USA bit
849 * - UpdateRegisters DMA_CLLR_UDA bit
850 * - UpdateRegisters DMA_CLLR_ULL bit
851 */
852 pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CLLR_UT2 | \
853 DMA_CLLR_UB1 | DMA_CLLR_USA | \
854 DMA_CLLR_UDA | DMA_CLLR_ULL)));
855
856 }
857
858 return (uint32_t)SUCCESS;
859 }
860
861 /**
862 * @brief Connect Linked list Nodes.
863 * @param pPrevLinkNode Pointer to previous linked list node to be connected to new Linked list node.
864 * @param PrevNodeCLLRIdx Offset of Previous Node CLLR register.
865 * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
866 * @param pNewLinkNode Pointer to new Linked list.
867 * @param NewNodeCLLRIdx Offset of New Node CLLR register.
868 * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
869 * @retval None
870 */
LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef * pPrevLinkNode,uint32_t PrevNodeCLLRIdx,LL_DMA_LinkNodeTypeDef * pNewLinkNode,uint32_t NewNodeCLLRIdx)871 void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
872 LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx)
873 {
874 pPrevLinkNode->LinkRegisters[PrevNodeCLLRIdx] = (((uint32_t)pNewLinkNode & DMA_CLLR_LA) | \
875 (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \
876 DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \
877 DMA_CLLR_ULL)));
878 }
879
880 /**
881 * @brief Disconnect the next linked list node.
882 * @param pLinkNode Pointer to linked list node to be disconnected from the next one.
883 * @param LinkNodeCLLRIdx Offset of Link Node CLLR register.
884 * @retval None.
885 */
LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef * pLinkNode,uint32_t LinkNodeCLLRIdx)886 void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx)
887 {
888 pLinkNode->LinkRegisters[LinkNodeCLLRIdx] = 0;
889 }
890
891 /**
892 * @}
893 */
894
895 /**
896 * @}
897 */
898
899 /**
900 * @}
901 */
902
903 #endif /* defined (GPDMA1) */
904
905 /**
906 * @}
907 */
908
909 #endif /* defined (USE_FULL_LL_DRIVER) */
910
911
