1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32wbaxx_ll_adc.h"
22 #include "stm32wbaxx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC4)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from asynchronous clock with prescaler 512, */
61 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
62 /* CPU clock frequency max 100MHz, HSI frequency 16MHz: ratio 7. */
63 /* Unit: CPU cycles. */
64 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 7UL)
65 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
66 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
67
68 /**
69 * @}
70 */
71
72 /* Private macros ------------------------------------------------------------*/
73
74 /** @addtogroup ADC_LL_Private_Macros
75 * @{
76 */
77
78 /* Check of parameters for configuration of ADC hierarchical scope: */
79 /* common to several ADC instances. */
80 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
81 (((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
82 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
83 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
84 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
85 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
86 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
87 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
93 )
94
95 #define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__) \
96 (((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH) \
97 || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW) \
98 )
99
100 /* Check of parameters for configuration of ADC hierarchical scope: */
101 /* ADC instance. */
102 #define IS_LL_ADC_CLOCK(__CLOCK__) \
103 (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
104 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
105 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
106 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
107 )
108
109 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
110 (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
111 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
112 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
113 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
114 )
115
116 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
117 (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
118 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
119 )
120
121 /* Check of parameters for configuration of ADC hierarchical scope: */
122 /* ADC group regular */
123 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
124 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
125 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
126 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
127 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
128 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) \
129 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE15) \
130 )
131
132 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
133 (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
134 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
135 )
136
137 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
138 (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
139 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
140 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
141 )
142
143 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
144 (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
145 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
146 )
147
148 #define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
149 (((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
150 || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
151 )
152
153 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
154 (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
155 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
156 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
157 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
158 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
159 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
160 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
161 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
162 )
163
164 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
165 (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
166 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
167 )
168
169 /**
170 * @}
171 */
172
173
174 /* Private function prototypes -----------------------------------------------*/
175
176 /* Exported functions --------------------------------------------------------*/
177 /** @addtogroup ADC_LL_Exported_Functions
178 * @{
179 */
180
181 /** @addtogroup ADC_LL_EF_Init
182 * @{
183 */
184
185 /**
186 * @brief De-initialize registers of all ADC instances belonging to
187 * the same ADC common instance to their default reset values.
188 * @note This function is performing a hard reset, using high level
189 * clock source RCC ADC reset.
190 * @param ADCxy_COMMON ADC common instance
191 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
192 * @retval An ErrorStatus enumeration value:
193 * - SUCCESS: ADC common registers are de-initialized
194 * - ERROR: not applicable
195 */
LL_ADC_CommonDeInit(const ADC_Common_TypeDef * ADCxy_COMMON)196 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON)
197 {
198 /* Check the parameters */
199 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
200
201 /* Prevent unused argument(s) compilation warning if no assert_param check */
202 (void)(ADCxy_COMMON);
203
204 /* Force reset of ADC clock (core clock) */
205 SET_BIT(RCC->AHB4RSTR, RCC_AHB4ENR_ADC4EN);
206
207 /* Release reset of ADC clock (core clock) */
208 CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4ENR_ADC4EN);
209
210 return SUCCESS;
211 }
212
213 /**
214 * @brief Initialize some features of ADC common parameters
215 * (all ADC instances belonging to the same ADC common instance)
216 * and multimode (for devices with several ADC instances available).
217 * @note The setting of ADC common parameters is conditioned to
218 * ADC instances state:
219 * All ADC instances belonging to the same ADC common instance
220 * must be disabled.
221 * @param ADCxy_COMMON ADC common instance
222 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
223 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
224 * @retval An ErrorStatus enumeration value:
225 * - SUCCESS: ADC common registers are initialized
226 * - ERROR: ADC common registers are not initialized
227 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,const LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)228 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
229 {
230 ErrorStatus status = SUCCESS;
231
232 /* Check the parameters */
233 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
234 assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
235
236 /* Note: Hardware constraint (refer to description of functions */
237 /* "LL_ADC_SetCommonXXX()": */
238 /* On this STM32 series, setting of these features is conditioned to */
239 /* ADC state: */
240 /* All ADC instances of the ADC common group must be disabled. */
241 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
242 {
243 /* Configuration of ADC hierarchical scope: */
244 /* - common to several ADC */
245 /* (all ADC instances belonging to the same ADC common instance) */
246 /* - Set ADC clock (conversion clock) */
247 LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
248 }
249 else
250 {
251 /* Initialization error: One or several ADC instances belonging to */
252 /* the same ADC common instance are not disabled. */
253 status = ERROR;
254 }
255
256 return status;
257 }
258
259 /**
260 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
261 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
262 * whose fields will be set to default values.
263 * @retval None
264 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)265 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
266 {
267 /* Set pADC_CommonInitStruct fields to default values */
268 /* Set fields of ADC common */
269 /* (all ADC instances belonging to the same ADC common instance) */
270 pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
271
272 }
273
274 /**
275 * @brief De-initialize registers of the selected ADC instance
276 * to their default reset values.
277 * @note To reset all ADC instances quickly (perform a hard reset),
278 * use function @ref LL_ADC_CommonDeInit().
279 * @note If this functions returns error status, it means that ADC instance
280 * is in an unknown state.
281 * In this case, perform a hard reset using high level
282 * clock source RCC ADC reset.
283 * Refer to function @ref LL_ADC_CommonDeInit().
284 * @param ADCx ADC instance
285 * @retval An ErrorStatus enumeration value:
286 * - SUCCESS: ADC registers are de-initialized
287 * - ERROR: ADC registers are not de-initialized
288 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)289 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
290 {
291 ErrorStatus status = SUCCESS;
292
293 __IO uint32_t timeout_cpu_cycles = 0UL;
294
295 /* Check the parameters */
296 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
297
298 /* Disable ADC instance if not already disabled. */
299 if (LL_ADC_IsEnabled(ADCx) == 1UL)
300 {
301 /* Stop potential ADC conversion on going on ADC group regular. */
302 LL_ADC_REG_StopConversion(ADCx);
303
304 /* Wait for ADC conversions are effectively stopped */
305 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
306 while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
307 {
308 timeout_cpu_cycles--;
309 if (timeout_cpu_cycles == 0UL)
310 {
311 /* Time-out error */
312 status = ERROR;
313 break;
314 }
315 }
316
317 /* Disable the ADC instance */
318 LL_ADC_Disable(ADCx);
319
320 /* Wait for ADC instance is effectively disabled */
321 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
322 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
323 {
324 timeout_cpu_cycles--;
325 if (timeout_cpu_cycles == 0UL)
326 {
327 /* Time-out error */
328 status = ERROR;
329 break;
330 }
331 }
332 }
333
334 /* Check whether ADC state is compliant with expected state */
335 if (READ_BIT(ADCx->CR,
336 (ADC_CR_ADSTP | ADC_CR_ADSTART
337 | ADC_CR_ADDIS | ADC_CR_ADEN)
338 )
339 == 0UL)
340 {
341 /* ========== Reset ADC registers ========== */
342 /* Reset register IER */
343 CLEAR_BIT(ADCx->IER,
344 (LL_ADC_IT_ADRDY
345 | LL_ADC_IT_EOC
346 | LL_ADC_IT_EOS
347 | LL_ADC_IT_OVR
348 | LL_ADC_IT_EOSMP
349 | LL_ADC_IT_AWD1
350 | LL_ADC_IT_AWD2
351 | LL_ADC_IT_AWD3
352 | LL_ADC_IT_EOCAL
353 )
354 );
355
356 /* Reset register ISR */
357 SET_BIT(ADCx->ISR,
358 (LL_ADC_FLAG_ADRDY
359 | LL_ADC_FLAG_EOC
360 | LL_ADC_FLAG_EOS
361 | LL_ADC_FLAG_OVR
362 | LL_ADC_FLAG_EOSMP
363 | LL_ADC_FLAG_AWD1
364 | LL_ADC_FLAG_AWD2
365 | LL_ADC_FLAG_AWD3
366 | LL_ADC_FLAG_EOCAL
367 )
368 );
369
370 /* Reset register CR */
371 /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
372 /* "read-set": no direct reset applicable. */
373 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
374
375 /* Reset register CFGR1 */
376 CLEAR_BIT(ADCx->CFGR1,
377 (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
378 | ADC_CFGR1_CHSELRMOD | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
379 | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
380 | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN)
381 );
382
383 /* Reset register CFGR2 */
384 CLEAR_BIT(ADCx->CFGR2,
385 (ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR
386 | ADC_CFGR2_OVSE)
387 );
388
389 /* Reset register SMPR */
390 CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
391
392 /* Reset register AWD1TR */
393 MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_LT1 | ADC_AWD1TR_HT1, ADC_AWD1TR_HT1);
394
395 /* Reset register AWD2TR */
396 MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_LT2 | ADC_AWD2TR_HT2, ADC_AWD2TR_HT2);
397
398 /* Reset register AWD3TR */
399 MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_LT3 | ADC_AWD3TR_HT3, ADC_AWD3TR_HT3);
400
401 /* Reset register CHSELR */
402 CLEAR_BIT(ADCx->CHSELR,
403 (ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
404 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
405 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
406 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0)
407 );
408
409 /* Reset register DR */
410 /* bits in access mode read only, no direct reset applicable */
411
412 /* Reset register CALFACT */
413 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
414
415 }
416 else
417 {
418 /* ADC instance is in an unknown state */
419 /* Need to performing a hard reset of ADC instance, using high level */
420 /* clock source RCC ADC reset. */
421 /* Caution: On this STM32 series, if several ADC instances are available */
422 /* on the selected device, RCC ADC reset will reset */
423 /* all ADC instances belonging to the common ADC instance. */
424 status = ERROR;
425 }
426
427 return status;
428 }
429
430 /**
431 * @brief Initialize some features of ADC instance.
432 * @note These parameters have an impact on ADC scope: ADC instance.
433 * Refer to corresponding unitary functions into
434 * @ref ADC_LL_EF_Configuration_ADC_Instance .
435 * @note The setting of these parameters by function @ref LL_ADC_Init()
436 * is conditioned to ADC state:
437 * ADC instance must be disabled.
438 * This condition is applied to all ADC features, for efficiency
439 * and compatibility over all STM32 series. However, the different
440 * features can be set under different ADC state conditions
441 * (setting possible with ADC enabled without conversion on going,
442 * ADC enabled with conversion on going, ...)
443 * Each feature can be updated afterwards with a unitary function
444 * and potentially with ADC in a different state than disabled,
445 * refer to description of each function for setting
446 * conditioned to ADC state.
447 * @note After using this function, some other features must be configured
448 * using LL unitary functions.
449 * The minimum configuration remaining to be done is:
450 * - Set ADC group regular sequencer:
451 * Depending on the sequencer mode (refer to
452 * function @ref LL_ADC_REG_SetSequencerConfigurable() ):
453 * - map channel on the selected sequencer rank.
454 * Refer to function @ref LL_ADC_REG_SetSequencerRanks();
455 * - map channel on rank corresponding to channel number.
456 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
457 * - Set ADC channel sampling time
458 * Refer to function LL_ADC_SetSamplingTimeCommonChannels();
459 * Refer to function LL_ADC_SetChannelSamplingTime();
460 * @param ADCx ADC instance
461 * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
462 * @retval An ErrorStatus enumeration value:
463 * - SUCCESS: ADC registers are initialized
464 * - ERROR: ADC registers are not initialized
465 */
LL_ADC_Init(ADC_TypeDef * ADCx,const LL_ADC_InitTypeDef * pADC_InitStruct)466 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct)
467 {
468 ErrorStatus status = SUCCESS;
469
470 /* Check the parameters */
471 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
472
473 assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
474 assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
475
476 /* Note: Hardware constraint (refer to description of this function): */
477 /* ADC instance must be disabled. */
478 if (LL_ADC_IsEnabled(ADCx) == 0UL)
479 {
480 /* Configuration of ADC hierarchical scope: */
481 /* - ADC instance */
482 /* - Set ADC data resolution */
483 /* - Set ADC conversion data alignment */
484 /* - Set ADC low power mode */
485 MODIFY_REG(ADCx->CFGR1,
486 ADC_CFGR1_RES
487 | ADC_CFGR1_ALIGN
488 ,
489 pADC_InitStruct->Resolution
490 | pADC_InitStruct->DataAlignment
491 );
492 }
493 else
494 {
495 /* Initialization error: ADC instance is not disabled. */
496 status = ERROR;
497 }
498
499 return status;
500 }
501
502 /**
503 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
504 * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
505 * whose fields will be set to default values.
506 * @retval None
507 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * pADC_InitStruct)508 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
509 {
510 /* Set pADC_InitStruct fields to default values */
511 /* Set fields of ADC instance */
512 pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
513 pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
514
515 }
516
517 /**
518 * @brief Initialize some features of ADC group regular.
519 * @note These parameters have an impact on ADC scope: ADC group regular.
520 * Refer to corresponding unitary functions into
521 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
522 * (functions with prefix "REG").
523 * @note The setting of these parameters by function @ref LL_ADC_Init()
524 * is conditioned to ADC state:
525 * ADC instance must be disabled.
526 * This condition is applied to all ADC features, for efficiency
527 * and compatibility over all STM32 series. However, the different
528 * features can be set under different ADC state conditions
529 * (setting possible with ADC enabled without conversion on going,
530 * ADC enabled with conversion on going, ...)
531 * Each feature can be updated afterwards with a unitary function
532 * and potentially with ADC in a different state than disabled,
533 * refer to description of each function for setting
534 * conditioned to ADC state.
535 * @note Before using this function, ADC group regular sequencer
536 * must be configured: refer to function
537 * @ref LL_ADC_REG_SetSequencerConfigurable().
538 * @note After using this function, other features must be configured
539 * using LL unitary functions.
540 * The minimum configuration remaining to be done is:
541 * - Set ADC group regular sequencer:
542 * Depending on the sequencer mode (refer to
543 * function @ref LL_ADC_REG_SetSequencerConfigurable() ):
544 * - map channel on the selected sequencer rank.
545 * Refer to function @ref LL_ADC_REG_SetSequencerRanks();
546 * - map channel on rank corresponding to channel number.
547 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
548 * - Set ADC channel sampling time
549 * Refer to function LL_ADC_SetSamplingTimeCommonChannels();
550 * Refer to function LL_ADC_SetChannelSamplingTime();
551 * @param ADCx ADC instance
552 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
553 * @retval An ErrorStatus enumeration value:
554 * - SUCCESS: ADC registers are initialized
555 * - ERROR: ADC registers are not initialized
556 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,const LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)557 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
558 {
559 ErrorStatus status = SUCCESS;
560
561 /* Check the parameters */
562 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
563 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
564 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
565 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
566 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
567
568 if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
569 {
570 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
571 }
572
573 if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
574 || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
575 )
576 {
577 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
578
579 /* ADC group regular continuous mode and discontinuous mode */
580 /* can not be enabled simultenaeously */
581 assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
582 || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
583 }
584
585 /* Note: Hardware constraint (refer to description of this function): */
586 /* ADC instance must be disabled. */
587 if (LL_ADC_IsEnabled(ADCx) == 0UL)
588 {
589 /* Configuration of ADC hierarchical scope: */
590 /* - ADC group regular */
591 /* - Set ADC group regular trigger source */
592 /* - Set ADC group regular sequencer length */
593 /* - Set ADC group regular sequencer discontinuous mode */
594 /* - Set ADC group regular continuous mode */
595 /* - Set ADC group regular conversion data transfer: no transfer or */
596 /* transfer by DMA, and DMA requests mode */
597 /* - Set ADC group regular overrun behavior */
598 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
599 /* setting of trigger source to SW start. */
600 if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
601 || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
602 )
603 {
604 /* Case of sequencer mode fixed
605 or sequencer length >= 2 ranks with sequencer mode fully configurable:
606 discontinuous mode configured */
607 MODIFY_REG(ADCx->CFGR1,
608 ADC_CFGR1_EXTSEL
609 | ADC_CFGR1_EXTEN
610 | ADC_CFGR1_DISCEN
611 | ADC_CFGR1_CONT
612 | ADC_CFGR1_DMAEN
613 | ADC_CFGR1_DMACFG
614 | ADC_CFGR1_OVRMOD
615 ,
616 pADC_RegInitStruct->TriggerSource
617 | pADC_RegInitStruct->SequencerDiscont
618 | pADC_RegInitStruct->ContinuousMode
619 | pADC_RegInitStruct->DMATransfer
620 | pADC_RegInitStruct->Overrun
621 );
622 }
623 else
624 {
625 /* Case of sequencer mode fully configurable
626 and sequencer length 1 rank (sequencer disabled):
627 discontinuous mode discarded (fixed to disable) */
628 MODIFY_REG(ADCx->CFGR1,
629 ADC_CFGR1_EXTSEL
630 | ADC_CFGR1_EXTEN
631 | ADC_CFGR1_DISCEN
632 | ADC_CFGR1_CONT
633 | ADC_CFGR1_DMAEN
634 | ADC_CFGR1_DMACFG
635 | ADC_CFGR1_OVRMOD
636 ,
637 pADC_RegInitStruct->TriggerSource
638 | LL_ADC_REG_SEQ_DISCONT_DISABLE
639 | pADC_RegInitStruct->ContinuousMode
640 | pADC_RegInitStruct->DMATransfer
641 | pADC_RegInitStruct->Overrun
642 );
643 }
644
645 /* Set ADC group regular sequencer length */
646 if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
647 {
648 LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength);
649 }
650 }
651 else
652 {
653 /* Initialization error: ADC instance is not disabled. */
654 status = ERROR;
655 }
656 return status;
657 }
658
659 /**
660 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
661 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
662 * whose fields will be set to default values.
663 * @retval None
664 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)665 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
666 {
667 /* Set pADC_RegInitStruct fields to default values */
668 /* Set fields of ADC group regular */
669 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
670 /* setting of trigger source to SW start. */
671 pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
672 pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
673 pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
674 pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
675 pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
676 pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
677 }
678
679 /**
680 * @}
681 */
682
683 /**
684 * @}
685 */
686
687 /**
688 * @}
689 */
690
691 #endif /* ADC4 */
692
693 /**
694 * @}
695 */
696
697 #endif /* USE_FULL_LL_DRIVER */
698
