1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @brief Extended PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller extension peripheral :
8 * + Power Supply Control Functions
9 * + Low Power Control Functions
10 * + Voltage Monitoring Functions
11 * + Memories Retention Functions
12 * + I/O Pull-Up Pull-Down Configuration Functions
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2022 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### How to use this driver #####
27 ==============================================================================
28 [..]
29 (#) Call HAL_PWREx_ControlVoltageScaling() and HAL_PWREx_GetVoltageRange() to
30 set / get the voltage scaling range.
31 (+) Voltage scaling can be one of the following values :
32 (++) voltage output scale 1 :
33 => Used when system clock frequency is up to 100 MHz
34 (++) voltage output scale 2 :
35 => Used when system clock frequency is up to 16 MHz
36
37 (#) Call HAL_PWREx_EnableUltraLowPowerMode() and
38 HAL_PWREx_DisableUltraLowPowerMode() to enable / disable the BOR ultra
39 low power mode.
40
41 (#) Call HAL_PWREx_EnableSRAM1ContentStandbyRetention() and
42 HAL_PWREx_DisableSRAM1ContentStandbyRetention() to
43 enable / disable the SRAM1 content retention in Standby low
44 power mode.
45
46 (#) Call HAL_PWREx_EnableSRAM2ContentStandbyRetention() and
47 HAL_PWREx_DisableSRAM2ContentStandbyRetention() to
48 enable / disable the SRAM2 content retention in Standby low
49 power mode.
50
51 (#) Call HAL_PWREx_EnableRAMsContentStopRetention() and
52 HAL_PWREx_DisableRAMsContentStopRetention() to
53 enable / disable the RAMs content retention in Stop mode (Stop 0/1).
54 (+) Retained RAM can be one of the following RAMs :
55 (++) SRAM1
56 (++) SRAM2
57 (++) ICACHE
58
59 (#) Call HAL_PWREx_EnableFlashFastWakeUp() and
60 HAL_PWREx_DisableFlashFastWakeUp() to enable / disable the flash memory
61 fast wakeup from Stop mode (Stop 0/1).
62
63 (#) Call HAL_PWREx_EnableStandbyIORetention() and HAL_PWREx_DisableStandbyIORetention()
64 to enable / disable the IO state retention while in Standby mode.
65
66 (#) Call HAL_PWREx_GetStandbyIORetentionStatus() to retrieve for a given port for which
67 IO the state was retained while in Standby mode.
68
69 (#) Call HAL_PWREx_DisableStandbyRetainedIOState() to disable the IO state retained in
70 Standby mode.
71
72 (#) Call HAL_PWREx_ConfigSupply to Configure the system Power Supply.
73
74 (#) Call HAL_PWREx_GetRADIOOperatingMode to get the 2.4 GHz RADIO operating mode.
75
76 (#) Call HAL_PWREx_GetRADIOPHYOperatingModeto get the 2.4 GHz RADIO PHY operating mode.
77
78 (#) Call HAL_PWREx_GetRADIOEncryptionOperatingMode to get the radio encryption mode.
79
80 (#) Call HAL_PWREx_GetRFVDDHPA to get the 2.4 GHz RADIO control.
81
82 (#) Call HAL_PWREx_SetREGVDDHPAInputSupply and HAL_PWREx_GetREGVDDHPAInputSupply
83 set / get the regulator VDDHPA input supply selection.
84
85 (#) Call HAL_PWREx_EnableREGVDDHPABypass and HAL_PWREx_DisableREGVDDHPABypass
86 to enable / disable regulator REG_VDDHPA bypass
87
88 @endverbatim
89 ******************************************************************************
90 */
91
92 /* Includes ------------------------------------------------------------------*/
93 #include "stm32wbaxx_hal.h"
94
95 /** @addtogroup STM32WBAxx_HAL_Driver
96 * @{
97 */
98
99 /** @defgroup PWREx PWREx
100 * @brief PWR Extended HAL module driver
101 * @{
102 */
103
104 #if defined (HAL_PWR_MODULE_ENABLED)
105
106 /* Private typedef -----------------------------------------------------------*/
107 /* Private define ------------------------------------------------------------*/
108
109 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
110 * @{
111 */
112 #if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx)
113 #define PWR_PORTA_AVAILABLE_PINS (0x0FFFFU)
114 #define PWR_PORTB_AVAILABLE_PINS (0x0FFFFU)
115 #define PWR_PORTC_AVAILABLE_PINS (0x0E000U)
116 #define PWR_PORTH_AVAILABLE_PINS (0x00008U)
117 #elif defined (STM32WBA50xx)
118 #define PWR_PORTA_AVAILABLE_PINS (0x0F1E3U)
119 #define PWR_PORTB_AVAILABLE_PINS (0x09318U)
120 #define PWR_PORTC_AVAILABLE_PINS (0x0C000U)
121 #define PWR_PORTH_AVAILABLE_PINS (0x00008U)
122 #endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */
123 /*!< Time out value of flags setting */
124 #define PWR_VOSF_SETTING_DELAY_VALUE (0x32U) /*!< Time out value for VOSF flag setting */
125 #define PWR_MODE_CHANGE_DELAY_VALUE (0x32U) /*!< Time out for step down converter operating mode */
126
127 /**
128 * @}
129 */
130
131 /* Private macro -------------------------------------------------------------*/
132 /* Private variables ---------------------------------------------------------*/
133 /* Private function prototypes -----------------------------------------------*/
134 /* Exported functions --------------------------------------------------------*/
135
136 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
137 * @{
138 */
139
140 /** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
141 * @brief Power supply control functions
142 *
143 @verbatim
144 ===============================================================================
145 ##### Power supply control functions #####
146 ===============================================================================
147 [..]
148 This section provides functions allowing to control power supply.
149
150 [..]
151 (+) The STM32WBA series devices embed two regulators : one LDO (linear
152 voltage regulator) and one SMPS (step down converter) in parallel to
153 provide the VCORE supply for digital peripherals, SRAM1, SRAM2 and
154 embedded Flash memory.
155
156 (+) The SMPS allows the power consumption to be reduced but some
157 peripherals can be perturbed by the noise generated by the SMPS,
158 requiring the application to switch to LDO when running this
159 peripheral in order to reach the best performances.
160
161 (+) The LDO and the SMPS regulators have two modes: Main regulator mode
162 (used when performance is needed), and Low-power regulator mode. LDO
163 or SMPS can be used in all voltage scaling ranges, and in all Stop
164 and Standby with retention modes.
165
166 (+) After reset, the regulator is the LDO, in Range 2. Switching to SMPS
167 provides lower consumption in particular at high VDD voltage. It is
168 possible to switch from LDO to SMPS, or from SMPS to LDO on the fly in
169 any range, by configuring the REGSEL bit. It is recommended to switch
170 first to SMPS before changing the voltage range.
171
172 (+) When exiting from Stop or Standby retention modes, the regulator is the
173 same than when entering these low-power modes.
174
175 (+) When exiting from Standby modes, the LDO regulator is always used. When Standby
176 has been entered from the SMPS regulator, after exiting standby with the LDO,
177 the regulator is subsequently switched to SMPS regulator.
178
179 (+) When exiting from Stop 0 modes the voltage range is the same as on entering Stop 0
180 mode. When exiting from Stop 1 and Standby modes the voltage range 2 is used.
181
182 (+) When the 2.4 GHz RADIO is active the regulator and range can not be changed. Any
183 requested regulator or range change while the 2.4 GHz RADIO is active is suspended
184 and will only take effect after the 2.4 GHz RADIO has entered Sleep or Deepsleep mode.
185
186 (+) Both regulators can provide four different voltages (voltage scaling)
187 and can operate in Stop modes.
188 Voltage scaling ranges can be one of the following values :
189 (++) voltage output scale 1 :
190 => Used when system clock frequency is up to 100 MHz
191 (++) voltage output scale 2 :
192 => Used when system clock frequency is up to 16 MHz
193
194 @endverbatim
195 * @{
196 */
197
198 /**
199 * @brief Configure the main internal regulator output voltage to achieve
200 * a tradeoff between performance and power consumption.
201 * @param VoltageScaling : Specifies the regulator output voltage scale.
202 * This parameter can be one of the following values :
203 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output range 1.
204 * Used when system clock frequency is up to 100 MHz.
205 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output range 2.
206 * Used when system clock frequency is up to 16 MHz.
207 * @note Before moving to voltage scaling 2, it is mandatory to ensure that
208 * the system frequency is equal or below 16 MHz.
209 * @note When the 2.4 GHz RADIO is active, the range cannot be changed.
210 * Any requested range change while the 2.4 GHz RADIO is active is suspended and will
211 * only take effect after the 2.4 GHz RADIO has entered Sleep or Deepsleep mode.
212 * @note In range 2, the 2.4 GHz RADIO shall not transmit nor receive.
213 * @retval HAL Status.
214 */
HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)215 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
216 {
217 uint32_t timeout;
218
219 /* Check the parameter */
220 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
221
222 /* Get the current voltage scale applied */
223 uint32_t vos_old = READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS);
224
225 /* No change, nothing to do */
226 if (vos_old == VoltageScaling)
227 {
228 return HAL_OK;
229 }
230
231 /* Set voltage scaling level */
232 MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, VoltageScaling);
233
234
235 /* Wait until VOSRDY is set */
236 timeout = ((PWR_VOSF_SETTING_DELAY_VALUE * SystemCoreClock) / 1000000U) + 1U;
237 while (HAL_IS_BIT_CLR(PWR->VOSR, PWR_VOSR_VOSRDY) && (timeout != 0U))
238 {
239 timeout--;
240 }
241
242 /* Check time out */
243 if (timeout == 0U)
244 {
245 return HAL_TIMEOUT;
246 }
247
248 /* Wait until ACTVOSRDY is set */
249 timeout = ((PWR_VOSF_SETTING_DELAY_VALUE * SystemCoreClock) / 1000000U) + 1U;
250 while ((HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)) && (timeout != 0U))
251 {
252 timeout--;
253 }
254
255 /* Check time out */
256 if (timeout == 0U)
257 {
258 return HAL_TIMEOUT;
259 }
260
261 return HAL_OK;
262 }
263
264 /**
265 * @brief Return voltage scaling range.
266 * @retval Applied voltage scaling value.
267 */
HAL_PWREx_GetVoltageRange(void)268 uint32_t HAL_PWREx_GetVoltageRange(void)
269 {
270 return (PWR->SVMSR & PWR_SVMSR_ACTVOS);
271 }
272
273 #if defined(PWR_CR3_REGSEL)
274 /**
275 * @brief Configure the system Power Supply.
276 * @param SupplySource : Specifies the Power Supply source.
277 * This parameter can be one of the following values :
278 * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power Domains.
279 * @arg PWR_SMPS_SUPPLY : The SMPS regulator supplies the Vcore Power Domains.
280 * @retval HAL status.
281 */
HAL_PWREx_ConfigSupply(uint32_t SupplySource)282 HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource)
283 {
284 uint32_t timeout;
285
286 /* Check the parameter */
287 assert_param(IS_PWR_SUPPLY(SupplySource));
288
289 /* Set maximum time out */
290 timeout = ((PWR_MODE_CHANGE_DELAY_VALUE * SystemCoreClock) / 1000000U) + 1U;
291
292 /* Configure the LDO as system regulator supply */
293 if (SupplySource == PWR_LDO_SUPPLY)
294 {
295 /* Set the power supply configuration */
296 CLEAR_BIT(PWR->CR3, PWR_CR3_REGSEL);
297
298 /* Wait until system switch on new regulator */
299 while (HAL_IS_BIT_SET(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U))
300 {
301 timeout--;
302 }
303 }
304 /* Configure the SMPS as system regulator supply */
305 else
306 {
307 /* Set the power supply configuration */
308 SET_BIT(PWR->CR3, PWR_CR3_REGSEL);
309
310 /* Wait until system switch on new regulator */
311 while (HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U))
312 {
313 timeout--;
314 }
315 }
316
317 /* Check time out */
318 if (timeout == 0U)
319 {
320 return HAL_TIMEOUT;
321 }
322
323 return HAL_OK;
324 }
325
326 /**
327 * @brief Get the power supply configuration.
328 * @retval The supply configured.
329 */
HAL_PWREx_GetSupplyConfig(void)330 uint32_t HAL_PWREx_GetSupplyConfig(void)
331 {
332 return (PWR->SVMSR & PWR_SVMSR_REGS);
333 }
334 #endif /* defined(PWR_CR3_REGSEL) */
335
336 #if defined(PWR_CR2_FPWM)
337 /**
338 * @brief Enable SMPS PWM mode
339 * @note FPWM bit is used to reduce the SMPS switching harmonics in range 1.
340 * @note Setting FPWM bit has no effect in range 2
341 * @retval None.
342 */
HAL_PWREx_EnableSMPSPWM(void)343 void HAL_PWREx_EnableSMPSPWM(void)
344 {
345 SET_BIT(PWR->CR2, PWR_CR2_FPWM);
346 }
347
348 /**
349 * @brief Disable SMPS PWM mode
350 * @retval None.
351 */
HAL_PWREx_DisableSMPSPWM(void)352 void HAL_PWREx_DisableSMPSPWM(void)
353 {
354 CLEAR_BIT(PWR->CR2, PWR_CR2_FPWM);
355 }
356 #endif /* defined(PWR_CR2_FPWM) */
357 /**
358 * @brief Enable fast soft start for the current regulator.
359 * @retval None.
360 */
HAL_PWREx_EnableFastSoftStart(void)361 void HAL_PWREx_EnableFastSoftStart(void)
362 {
363 SET_BIT(PWR->CR3, PWR_CR3_FSTEN);
364 }
365
366 /**
367 * @brief Disable fast soft start for the current regulator.
368 * @retval None.
369 */
HAL_PWREx_DisableFastSoftStart(void)370 void HAL_PWREx_DisableFastSoftStart(void)
371 {
372 CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN);
373 }
374
375 /**
376 * @}
377 */
378
379
380 /** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions
381 * @brief Low power control functions
382 */
383
384 /**
385 * @brief Enable BOR and PVD ultra-low power mode.
386 * @note BOR and PVD operations can be in discontinuous (ultra-low power) mode in
387 * Stop 1 and Standby modes.
388 * @note This bit must be set to reach the lowest power consumption in the low-power modes.
389 * @note This bit shall not be set together with autonomous peripherals using HSI16
390 * as kernel clock.
391 * @retval None.
392 */
HAL_PWREx_EnableUltraLowPowerMode(void)393 void HAL_PWREx_EnableUltraLowPowerMode(void)
394 {
395 SET_BIT(PWR->CR1, PWR_CR1_ULPMEN);
396 }
397
398 /**
399 * @brief Disable BOR and PVD ultra-low power mode.
400 * @retval None.
401 */
HAL_PWREx_DisableUltraLowPowerMode(void)402 void HAL_PWREx_DisableUltraLowPowerMode(void)
403 {
404 CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN);
405 }
406
407
408 /**
409 * @}
410 */
411
412
413
414 /** @defgroup PWREx_Exported_Functions_Group4 Memories Retention Functions
415 * @brief Memories retention functions
416 *
417 @verbatim
418 ===============================================================================
419 ##### Memories Retention Functions #####
420 ===============================================================================
421 [..]
422 Several STM32WBA devices RAMs are configurable to retain or lose RAMs content
423 during Stop mode (Stop 0/1).
424 (+) Retained content RAMs in Stop modes are :
425 (++) SRAM1
426 (++) SRAM2
427 (++) ICACHE
428
429 [..]
430 Several STM32WBA devices RAMs are configurable to retain or lose RAMs content
431 in Standby mode.
432 (+) Retained content RAMs in Standby mode are :
433 (++) SRAM1
434 (++) SRAM2
435
436 @endverbatim
437 * @{
438 */
439
440 #if defined(PWR_CR1_R1RSB1)
441 /**
442 * @brief Enable SRAM1 content retention in Standby mode.
443 * @note When R1RSB1 bit is set, SRAM1 is powered by the low-power regulator in
444 * Standby mode and its content is kept.
445 * @param SRAM1Pages : Specifies the SRAM1 area
446 * This parameter can be one of the following values :
447 * @arg PWR_SRAM1_FULL_STANDBY_RETENTION : full SRAM1 retention.
448 * @retval None.
449 */
HAL_PWREx_EnableSRAM1ContentStandbyRetention(uint32_t SRAM1Pages)450 void HAL_PWREx_EnableSRAM1ContentStandbyRetention(uint32_t SRAM1Pages)
451 {
452 /* Check the parameters */
453 assert_param(IS_PWR_SRAM1_STANDBY_RETENTION(SRAM1Pages));
454
455 /* Set RRSx bit(s) */
456 MODIFY_REG(PWR->CR1, PWR_SRAM1_FULL_STANDBY_RETENTION, SRAM1Pages);
457 }
458
459 /**
460 * @brief Disable SRAM1 content retention in Standby mode.
461 * @note When R1RSB1 bit is reset, SRAM1 is powered off in Standby
462 * mode and its content is lost.
463 * @retval None.
464 */
HAL_PWREx_DisableSRAM1ContentStandbyRetention(void)465 void HAL_PWREx_DisableSRAM1ContentStandbyRetention(void)
466 {
467 /* Clear R1RSB1 bit */
468 CLEAR_BIT(PWR->CR1, PWR_SRAM1_FULL_STANDBY_RETENTION);
469 }
470 #endif /* defined(PWR_CR1_R1RSB1) */
471
472 /**
473 * @brief Enable SRAM2 content retention in Standby mode.
474 * @note When R2RSB1 bit is set, SRAM2 is powered by the low-power regulator in
475 * Standby mode and its content is kept.
476 * @param SRAM2Pages : Specifies the SRAM2 area
477 * This parameter can be one of the following values :
478 * @arg PWR_SRAM2_FULL_STANDBY_RETENTION : full SRAM2 retention.
479 * @retval None.
480 */
HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)481 void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)
482 {
483 /* Check the parameters */
484 assert_param(IS_PWR_SRAM2_STANDBY_RETENTION(SRAM2Pages));
485
486 /* Set RRSx bit(s) */
487 MODIFY_REG(PWR->CR1, PWR_SRAM2_FULL_STANDBY_RETENTION, SRAM2Pages);
488 }
489
490 /**
491 * @brief Disable SRAM2 content retention in Standby mode.
492 * @note When R2RSB1 bit is reset, SRAM2 is powered off in Standby
493 * mode and its content is lost.
494 * @retval None.
495 */
HAL_PWREx_DisableSRAM2ContentStandbyRetention(void)496 void HAL_PWREx_DisableSRAM2ContentStandbyRetention(void)
497 {
498 /* Clear R2RSB1 bit */
499 CLEAR_BIT(PWR->CR1, PWR_SRAM2_FULL_STANDBY_RETENTION);
500 }
501
502 /**
503 * @brief Enable 2.4GHz RADIO SRAMs and Sleep clock retention in Standby mode.
504 * @note When RADIORSB bit is set, the 2.4 GHz RADIO SRAMs (TXRX and Sequence) content
505 * is retained in Standby mode and the 2.4 GHz RADIO sleep timer counter remains
506 * operational.
507 * @param RadioSRAM : Specifies the Radio SRAM area
508 * This parameter can be one of the following values :
509 * @arg PWR_RADIOSRAM_FULL_STANDBY_RETENTION: full Radio SRAM and sleep counter retention.
510 * @retval None.
511 */
HAL_PWREx_EnableRadioSRAMClockStandbyRetention(uint32_t RadioSRAM)512 void HAL_PWREx_EnableRadioSRAMClockStandbyRetention(uint32_t RadioSRAM)
513 {
514 /* Check the parameters */
515 assert_param(IS_PWR_RADIOSRAM_STANDBY_RETENTION(RadioSRAM));
516
517 /* Set Radio RAM retention bit(s) */
518 MODIFY_REG(PWR->CR1, PWR_RADIOSRAM_FULL_STANDBY_RETENTION, RadioSRAM);
519 }
520
521 /**
522 * @brief Disable 2.4GHz RADIO SRAMs and Sleep clock retention in Standby mode.
523 * @note When RADIORSB bit is reset, the 2.4 GHz RADIO SRAMs and the sleep timer counter
524 * are not retained in Standby mode.
525 * @retval None.
526 */
HAL_PWREx_DisableRadioSRAMClockStandbyRetention(void)527 void HAL_PWREx_DisableRadioSRAMClockStandbyRetention(void)
528 {
529 /* Clear RADIORSB bit */
530 CLEAR_BIT(PWR->CR1, PWR_RADIOSRAM_FULL_STANDBY_RETENTION);
531 }
532
533 /**
534 * @brief Enable RAMs content retention in Stop mode (Stop 0, 1).
535 * @note When enabling content retention for a given ram, memory is kept powered
536 * on in Stop mode. (Consumption is not optimized)
537 * @note On Silicon Cut 1.0, it is mandatory to disable the ICACHE before going into
538 * stop modes otherwise an hard fault may occur when waking up from stop modes.
539 * @param RAMSelection: Specifies RAMs content to be retained in Stop mode.
540 * This parameter can be one or a combination of the values
541 * @ref PWREx_RAM_Contents_Stop_Retention.
542 * @arg PWR_SRAM1_FULL_STOP_RETENTION : full SRAM1 retention when available.
543 * @arg PWR_SRAM2_FULL_STOP_RETENTION : full SRAM2 retention.
544 * @arg PWR_ICACHE_FULL_STOP_RETENTION : full I-CACHE RAM retention.
545 * @retval None.
546 */
HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection)547 void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection)
548 {
549 /* Check the parameters */
550 assert_param(IS_PWR_RAM_STOP_RETENTION(RAMSelection));
551
552 /* Enable RAM retention in Stop mode */
553 CLEAR_BIT(PWR->CR2, RAMSelection);
554 }
555
556 /**
557 * @brief Disable RAMs content retention in Stop mode (Stop 0, 1).
558 * @note When disabling content retention for a given RAM, memory is
559 * powered down in Stop mode. (Consumption is optimized)
560 * @param RAMSelection: Specifies RAMs content to be lost in Stop mode.
561 * This parameter can be one or a combination of
562 * @ref PWREx_RAM_Contents_Stop_Retention.
563 * @arg PWR_SRAM1_FULL_STOP_RETENTION : full SRAM1 retention when available.
564 * @arg PWR_SRAM2_FULL_STOP_RETENTION : full SRAM2 retention.
565 * @arg PWR_ICACHE_FULL_STOP_RETENTION : full I-CACHE RAM retention.
566 * @retval None.
567 */
HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection)568 void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection)
569 {
570 /* Check the parameters */
571 assert_param(IS_PWR_RAM_STOP_RETENTION(RAMSelection));
572
573 /* Disable RAM retention in Stop mode */
574 MODIFY_REG(PWR->CR2, PWR_ALL_RAM_STOP_RETENTION_MASK, RAMSelection);
575 }
576
577 /**
578 * @brief Enable the flash memory fast wakeup from Stop 0 and Stop 1 modes.
579 * @note This feature is used to obtain the best trade-off between low-power
580 * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.
581 * When this feature is enabled, the Flash memory remains in normal
582 * mode in Stop 0 and Stop 1 modes, which offers a faster startup time
583 * with higher consumption.
584 * @retval None.
585 */
HAL_PWREx_EnableFlashFastWakeUp(void)586 void HAL_PWREx_EnableFlashFastWakeUp(void)
587 {
588 SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
589 }
590
591 /**
592 * @brief Disable the Flash Power Down in Stop mode.
593 * @note This feature is used to obtain the best trade-off between low-power
594 * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.
595 * When this feature is disabled, the Flash memory enters low-power
596 * mode in Stop 0 and Stop 1 modes, which causes a slower startup time
597 * with lower consumption.
598 * @retval None.
599 */
HAL_PWREx_DisableFlashFastWakeUp(void)600 void HAL_PWREx_DisableFlashFastWakeUp(void)
601 {
602 CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
603 }
604 /**
605 * @}
606 */
607
608 /** @defgroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions
609 * @brief I/O pull-up / pull-down configuration functions
610 *
611 @verbatim
612 ===============================================================================
613 ##### IOs configuration functions #####
614 ===============================================================================
615 [..]
616 In Standby mode, the GPIOs are by default in floating state. If Standby GPIO
617 retention is enabled in the PWR_IORETENRx register, the GPIO will retain the pull
618 or output level. When entering Standby mode, GPIOs that are enabled for Standby mode
619 retention keep their pull or level during and after exiting from Standby mode until
620 the PWR_IORETRx bit is cleared by software.
621
622 [..]
623 When entering Standby mode the PWR_IORETRx bit will be set by hardware for the GPIOs with
624 Standby retention enabled in. Once PWR_IORETRx is cleared by software, the GPIO configuration
625 will switch to the one defined as below:
626 (+) when GPIO is not selecting an alternate function, GPIO configuration is applied,
627 (+) when GPIO is selecting an alternate function, the selected peripheral alternate function
628 control will be applied.
629 The GPIO Standby retention enable information in PWR_IORETENRx is lost and has to be reconfigured
630 for sub-sequent entering into Standby mode.
631
632 @endverbatim
633 * @{
634 */
635
636 /**
637 * @brief Enable GPIO state retention in Standby mode.
638 * @note Set the relevant Pxy bits of PWR_IORETENRx register to configure the I/O
639 * state retention in Standby mode.
640 * @note The configuration is kept when exiting the Standby mode.
641 * @param GPIO_Port : Specify the IO port.
642 * This parameter can be a value of
643 * @ref PWREx_GPIO_Port.
644 * @param GPIO_Pin : Specify the I/O pins numbers.
645 * This parameter can be a value of
646 * @ref PWREx_GPIO_Pin_Mask.
647 * @retval HAL Status.
648 */
HAL_PWREx_EnableStandbyIORetention(uint32_t GPIO_Port,uint32_t GPIO_Pin)649 HAL_StatusTypeDef HAL_PWREx_EnableStandbyIORetention(uint32_t GPIO_Port, uint32_t GPIO_Pin)
650 {
651 HAL_StatusTypeDef ret = HAL_OK;
652
653 /* Check the parameters */
654 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
655 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
656
657 /* Check GPIO port */
658 switch (GPIO_Port)
659 {
660 case PWR_GPIO_A: /* Enables the Standby GPIO retention feature for PAy */
661 if (((GPIO_Pin & PWR_PORTA_AVAILABLE_PINS) == 0U) || \
662 ((GPIO_Pin & (~PWR_PORTA_AVAILABLE_PINS)) != 0U))
663 {
664 ret = HAL_ERROR;
665 }
666 else
667 {
668 SET_BIT(PWR->IORETENRA, GPIO_Pin);
669 }
670 break;
671
672 case PWR_GPIO_B: /* Enables the Standby GPIO retention feature for PBy */
673 if (((GPIO_Pin & PWR_PORTB_AVAILABLE_PINS) == 0U) || \
674 ((GPIO_Pin & (~PWR_PORTB_AVAILABLE_PINS)) != 0U))
675 {
676 ret = HAL_ERROR;
677 }
678 else
679 {
680 SET_BIT(PWR->IORETENRB, GPIO_Pin);
681 }
682 break;
683
684 case PWR_GPIO_C: /* Enables the Standby GPIO retention feature for PCy */
685 if (((GPIO_Pin & PWR_PORTC_AVAILABLE_PINS) == 0U) || \
686 ((GPIO_Pin & (~PWR_PORTC_AVAILABLE_PINS)) != 0U))
687 {
688 ret = HAL_ERROR;
689 }
690 else
691 {
692 SET_BIT(PWR->IORETENRC, GPIO_Pin);
693 }
694 break;
695
696 case PWR_GPIO_H: /* Enables the Standby GPIO retention feature for PHy */
697 if (((GPIO_Pin & PWR_PORTH_AVAILABLE_PINS) == 0U) || \
698 ((GPIO_Pin & (~PWR_PORTH_AVAILABLE_PINS)) != 0U))
699 {
700 ret = HAL_ERROR;
701 }
702 else
703 {
704 SET_BIT(PWR->IORETENRH, GPIO_Pin);
705 }
706 break;
707
708 default:
709 ret = HAL_ERROR;
710 break;
711 }
712
713 return ret;
714 }
715
716 /**
717 * @brief Disable GPIO state retention in Standby mode.
718 * @note Clear the relevant Pxy bits of PWR_IORETENRx register to disable
719 * the I/O state retention in Standby mode.
720 * @note The configuration is kept when exiting the Standby mode.
721 * @param GPIO_Port : Specify the IO port.
722 * This parameter can be a value of
723 * @ref PWREx_GPIO_Port.
724 * @param GPIO_Pin : Specify the I/O pins numbers.
725 * This parameter can be a value of
726 * @ref PWREx_GPIO_Pin_Mask.
727 * @retval HAL Status.
728 */
HAL_PWREx_DisableStandbyIORetention(uint32_t GPIO_Port,uint32_t GPIO_Pin)729 HAL_StatusTypeDef HAL_PWREx_DisableStandbyIORetention(uint32_t GPIO_Port, uint32_t GPIO_Pin)
730 {
731 HAL_StatusTypeDef ret = HAL_OK;
732
733 /* Check the parameters */
734 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
735 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
736
737 /* Check GPIO port */
738 switch (GPIO_Port)
739 {
740 case PWR_GPIO_A: /* Disables the Standby GPIO retention feature for PAy */
741 if (((GPIO_Pin & PWR_PORTA_AVAILABLE_PINS) == 0U) || \
742 ((GPIO_Pin & (~PWR_PORTA_AVAILABLE_PINS)) != 0U))
743 {
744 ret = HAL_ERROR;
745 }
746 else
747 {
748 CLEAR_BIT(PWR->IORETENRA, GPIO_Pin);
749 }
750 break;
751
752 case PWR_GPIO_B: /* Disables the Standby GPIO retention feature for PBy */
753 if (((GPIO_Pin & PWR_PORTB_AVAILABLE_PINS) == 0U) || \
754 ((GPIO_Pin & (~PWR_PORTB_AVAILABLE_PINS)) != 0U))
755 {
756 ret = HAL_ERROR;
757 }
758 else
759 {
760 CLEAR_BIT(PWR->IORETENRB, GPIO_Pin);
761 }
762 break;
763
764 case PWR_GPIO_C: /* Disables the Standby GPIO retention feature for PCy */
765 if (((GPIO_Pin & PWR_PORTC_AVAILABLE_PINS) == 0U) || \
766 ((GPIO_Pin & (~PWR_PORTC_AVAILABLE_PINS)) != 0U))
767 {
768 ret = HAL_ERROR;
769 }
770 else
771 {
772 CLEAR_BIT(PWR->IORETENRC, GPIO_Pin);
773 }
774 break;
775
776 case PWR_GPIO_H: /* Disables the Standby GPIO retention feature for PHy */
777 if (((GPIO_Pin & PWR_PORTH_AVAILABLE_PINS) == 0U) || \
778 ((GPIO_Pin & (~PWR_PORTH_AVAILABLE_PINS)) != 0U))
779 {
780 ret = HAL_ERROR;
781 }
782 else
783 {
784 CLEAR_BIT(PWR->IORETENRH, GPIO_Pin);
785 }
786 break;
787
788 default:
789 ret = HAL_ERROR;
790 break;
791 }
792
793 return ret;
794 }
795
796 /**
797 * @brief Return for a given port for which IO the state was retained in Standby mode.
798 * @param GPIO_Port : Specify the IO port.
799 * This parameter can be a value of
800 * @ref PWREx_GPIO_Port.
801 * @note The API returns the whole set of IOs for a given GPIO. A '1' at GPIO_Pin
802 * position indicates that this IO state (pull or level) was retained when
803 * the device entered Standby mode.
804 * @retval HAL Status.
805 */
HAL_PWREx_GetStandbyIORetentionStatus(uint32_t GPIO_Port)806 uint32_t HAL_PWREx_GetStandbyIORetentionStatus(uint32_t GPIO_Port)
807 {
808 /* Check the parameters */
809 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
810
811 /* Check GPIO port Standby IO retention status */
812 switch (GPIO_Port)
813 {
814 case PWR_GPIO_A: /* Get port A standby GPIO retention status */
815 return READ_REG(PWR->IORETRA);
816 break;
817
818 case PWR_GPIO_B: /* Get port B standby GPIO retention status */
819 return READ_REG(PWR->IORETRB);
820 break;
821
822 case PWR_GPIO_C: /* Get port C standby GPIO retention status */
823 return READ_REG(PWR->IORETRC);
824 break;
825
826 case PWR_GPIO_H: /* Get port H standby GPIO retention status */
827 return READ_REG(PWR->IORETRH);
828 break;
829
830 default:
831 return 0U;
832 break;
833 }
834 }
835
836 /**
837 * @brief Disable the GPIO state retained in Standby mode
838 * @param GPIO_Port : Specify the IO port.
839 * This parameter can be a value of
840 * @ref PWREx_GPIO_Port.
841 * @param GPIO_Pin : Specify the I/O pins numbers.
842 * This parameter can be a value of
843 * @ref PWREx_GPIO_Pin_Mask.
844 * @note This API can be used to disable after Standby mode the IO state that
845 * was configured to be retained by HAL_PWREx_EnableStandbyIORetention().
846 * @retval HAL Status.
847 */
HAL_PWREx_DisableStandbyRetainedIOState(uint32_t GPIO_Port,uint32_t GPIO_Pin)848 HAL_StatusTypeDef HAL_PWREx_DisableStandbyRetainedIOState(uint32_t GPIO_Port, uint32_t GPIO_Pin)
849 {
850 HAL_StatusTypeDef ret = HAL_OK;
851
852 /* Check the parameters */
853 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
854 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
855
856 /* Check GPIO port */
857 switch (GPIO_Port)
858 {
859 case PWR_GPIO_A: /* Disable the IO state (pull or level) retained for PAy in Standby mode */
860 if (((GPIO_Pin & PWR_PORTA_AVAILABLE_PINS) == 0U) || \
861 ((GPIO_Pin & (~PWR_PORTA_AVAILABLE_PINS)) != 0U))
862 {
863 ret = HAL_ERROR;
864 }
865 else
866 {
867 CLEAR_BIT(PWR->IORETRA, GPIO_Pin);
868 }
869 break;
870
871 case PWR_GPIO_B: /* Disable the IO state (pull or level) retained for PBy in Standby mode */
872 if (((GPIO_Pin & PWR_PORTB_AVAILABLE_PINS) == 0U) || \
873 ((GPIO_Pin & (~PWR_PORTB_AVAILABLE_PINS)) != 0U))
874 {
875 ret = HAL_ERROR;
876 }
877 else
878 {
879 CLEAR_BIT(PWR->IORETRB, GPIO_Pin);
880 }
881 break;
882
883 case PWR_GPIO_C: /* Disable the IO state (pull or level) retained for PCy in Standby mode */
884 if (((GPIO_Pin & PWR_PORTC_AVAILABLE_PINS) == 0U) || \
885 ((GPIO_Pin & (~PWR_PORTC_AVAILABLE_PINS)) != 0U))
886 {
887 ret = HAL_ERROR;
888 }
889 else
890 {
891 CLEAR_BIT(PWR->IORETRC, GPIO_Pin);
892 }
893 break;
894
895 case PWR_GPIO_H: /* Disable the IO state (pull or level) retained for PHy in Standby mode */
896 if (((GPIO_Pin & PWR_PORTH_AVAILABLE_PINS) == 0U) || \
897 ((GPIO_Pin & (~PWR_PORTH_AVAILABLE_PINS)) != 0U))
898 {
899 ret = HAL_ERROR;
900 }
901 else
902 {
903 CLEAR_BIT(PWR->IORETRH, GPIO_Pin);
904 }
905 break;
906
907 default:
908 ret = HAL_ERROR;
909 break;
910 }
911
912 return ret;
913 }
914
915 /**
916 * @}
917 */
918
919 /** @defgroup PWREx_Exported_Functions_Group6 I/O RADIO Configuration and Status Reading Functions
920 * @brief RADIO power amplifier setting and RADIO status reading functions
921 *
922 @verbatim
923 ===============================================================================
924 ##### RADIO configuration and status reading functions #####
925 ===============================================================================
926 @endverbatim
927 * @{
928 */
929
930 /**
931 * @brief Get the 2.4 GHz RADIO operating mode.
932 * @note The output can be any value from
933 * @ref PWREx_RADIO_Mode.
934 * @arg PWR_RADIO_DEEPSLEEP_MODE : 2.4 GHz RADIO deep sleep mode.
935 * @arg PWR_RADIO_SLEEP_MODE : 2.4 GHz RADIO sleep mode.
936 * @arg PWR_RADIO_ACTIVE_MODE : 2.4 GHz RADIO active mode.
937 * @retval The operating mode
938 */
HAL_PWREx_GetRADIOOperatingMode(void)939 uint32_t HAL_PWREx_GetRADIOOperatingMode(void)
940 {
941 uint32_t temp = READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_MODE);
942
943 if ((temp & PWR_RADIOSCR_MODE_1) == PWR_RADIOSCR_MODE_1)
944 {
945 temp = PWR_RADIO_ACTIVE_MODE;
946
947 }
948 return temp;
949 }
950
951 /**
952 * @brief Get the 2.4 GHz RADIO PHY operating mode.
953 * @note The output can be any value from
954 * @ref PWREx_RADIO_PHY_Mode.
955 * @arg PWR_RADIO_PHY_SLEEP_MODE : 2.4 GHz RADIO PHY sleep mode.
956 * @arg PWR_RADIO_PHY_STANDBY_MODE : 2.4 GHz RADIO PHY standby mode.
957 * @retval The PHY operating mode
958 */
HAL_PWREx_GetRADIOPHYOperatingMode(void)959 uint32_t HAL_PWREx_GetRADIOPHYOperatingMode(void)
960 {
961 return READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_PHYMODE);
962 }
963
964 /**
965 * @brief Get the 2.4 GHz RADIO encryption operating mode.
966 * @note The output can be any value from
967 * @arg PWR_RADIO_ENCMODE_ENABLED : 2.4 GHz RADIO encryption function enabled.
968 * @arg PWR_RADIO_ENCMODE_DISABLED : 2.4 GHz RADIO encryption function disabled.
969 * @retval The Radio encryption operating mode
970 */
HAL_PWREx_GetRADIOEncryptionOperatingMode(void)971 uint32_t HAL_PWREx_GetRADIOEncryptionOperatingMode(void)
972 {
973 return READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_ENCMODE);
974 }
975
976 /**
977 * @brief Get the 2.4 GHz RADIO control.
978 * @note The output can be any value from
979 * Bits [3:0] output power table format
980 * Bit [4] rf_event.
981 * @retval The PHY operating mode
982 */
HAL_PWREx_GetRFVDDHPA(void)983 uint32_t HAL_PWREx_GetRFVDDHPA(void)
984 {
985 return READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_RFVDDHPA);
986 }
987
988 #if defined(PWR_RADIOSCR_REGPASEL)
989 /**
990 * @brief Set the regulator REG_VDDHPA input supply selection.
991 * @param SupplySelection : Specifies the regulator REG_VDDHPA input supply.
992 * This parameter can be one of the following values :
993 * @arg PWR_RADIO_REG_VDDRFPA : VDDRFPA pin selected as regulator REG_VDDHPA input supply.
994 * @arg PWR_RADIO_REG_VDDHPA_VD11 : Regulator REG_VDDHPA input supply selection between VDDRFPA
995 * and VDD11 dependent on requested regulated output voltage.
996 * @retval HAL Status.
997 */
HAL_PWREx_SetREGVDDHPAInputSupply(uint32_t SupplySelection)998 HAL_StatusTypeDef HAL_PWREx_SetREGVDDHPAInputSupply(uint32_t SupplySelection)
999 {
1000 /* Check the parameters */
1001 assert_param(IS_PWR_REGPASEL_SUPPLYSELECTION(SupplySelection));
1002
1003 MODIFY_REG(PWR->RADIOSCR, PWR_RADIOSCR_REGPASEL, SupplySelection);
1004
1005 return HAL_OK;
1006 }
1007
1008 /**
1009 * @brief Get the regulator REG_VDDHPA input supply selection.
1010 * @note The output can be one of the following values :
1011 * @arg PWR_RADIO_REG_VDDRFPA : VDDRFPA pin selected as regulator REG_VDDHPA input supply.
1012 * @arg PWR_RADIO_REG_VDDHPA_VD11 : Regulator REG_VDDHPA input supply selection between VDDRFPA
1013 * and VDD11 dependent on requested regulated output voltage.
1014 * @retval The regulator REG_VDDHPA input supply selection.
1015 */
HAL_PWREx_GetREGVDDHPAInputSupply(void)1016 uint32_t HAL_PWREx_GetREGVDDHPAInputSupply(void)
1017 {
1018 return READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPASEL);
1019 }
1020 #endif /* defined(PWR_RADIOSCR_REGPASEL) */
1021
1022 #if defined(PWR_RADIOSCR_REGPABYPEN)
1023 /**
1024 * @brief Enable regulator REG_VDDHPA bypass
1025 * @note Make 2.4 GHz RADIO PA 1.2 V supplied directly from internal VDD11. (only available when
1026 * REGPASEL = 0)
1027 * @note This API shall only be called when the VDDHPA regulator is not used
1028 * @retval None.
1029 */
HAL_PWREx_EnableREGVDDHPABypass(void)1030 void HAL_PWREx_EnableREGVDDHPABypass(void)
1031 {
1032 SET_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN);
1033 }
1034
1035 /**
1036 * @brief Disable regulator REG_VDDHPA bypass
1037 * @retval None.
1038 */
HAL_PWREx_DisableREGVDDHPABypass(void)1039 void HAL_PWREx_DisableREGVDDHPABypass(void)
1040 {
1041 CLEAR_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN);
1042 }
1043 #endif /* defined(PWR_RADIOSCR_REGPABYPEN) */
1044
1045 /**
1046 * @}
1047 */
1048
1049 #endif /* defined (HAL_PWR_MODULE_ENABLED) */
1050
1051 /**
1052 * @}
1053 */
1054
1055 /**
1056 * @}
1057 */
1058
1059 /**
1060 * @}
1061 */
1062
1063
