1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_hal_lptim.c
4 * @author MCD Application Team
5 * @brief LPTIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Low Power Timer (LPTIM) peripheral:
8 * + Initialization and de-initialization functions.
9 * + Start/Stop operation functions in polling mode.
10 * + Start/Stop operation functions in interrupt mode.
11 * + Reading operation functions.
12 * + Peripheral State functions.
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2022 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### How to use this driver #####
28 ==============================================================================
29 [..]
30 The LPTIM HAL driver can be used as follows:
31
32 (#)Initialize the LPTIM low level resources by implementing the
33 HAL_LPTIM_MspInit():
34 (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
35 (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
36 (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
37 (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
38 (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
39
40 (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
41 configures mainly:
42 (++) The instance: LPTIM1 or LPTIM2.
43 (++) Clock: the counter clock.
44 (+++) Source : it can be either the ULPTIM input (IN1) or one of
45 the internal clock; (APB, LSE, LSI or HSI).
46 (+++) Prescaler: select the clock divider.
47 (++) UltraLowPowerClock : To be used only if the ULPTIM is selected
48 as counter clock source.
49 (+++) Polarity: polarity of the active edge for the counter unit
50 if the ULPTIM input is selected.
51 (+++) SampleTime: clock sampling time to configure the clock glitch
52 filter.
53 (++) Trigger: How the counter start.
54 (+++) Source: trigger can be software or one of the hardware triggers.
55 (+++) ActiveEdge : only for hardware trigger.
56 (+++) SampleTime : trigger sampling time to configure the trigger
57 glitch filter.
58 (++) OutputPolarity : 2 opposite polarities are possible.
59 (++) UpdateMode: specifies whether the update of the autoreload and
60 the compare values is done immediately or after the end of current
61 period.
62 (++) Input1Source: Source selected for input1 (GPIO or comparator output).
63 (++) Input2Source: Source selected for input2 (GPIO or comparator output).
64 Input2 is used only for encoder feature so is used only for LPTIM1 instance.
65
66 (#)Six modes are available:
67
68 (++) PWM Mode: To generate a PWM signal with specified period and pulse,
69 call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
70 mode.
71
72 (++) One Pulse Mode: To generate pulse with specified width in response
73 to a stimulus, call HAL_LPTIM_OnePulse_Start() or
74 HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
75
76 (++) Set once Mode: In this mode, the output changes the level (from
77 low level to high level if the output polarity is configured high, else
78 the opposite) when a compare match occurs. To start this mode, call
79 HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
80 interruption mode.
81
82 (++) Encoder Mode: To use the encoder interface call
83 HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
84 interruption mode. Only available for LPTIM1 instance.
85
86 (++) Time out Mode: an active edge on one selected trigger input rests
87 the counter. The first trigger event will start the timer, any
88 successive trigger event will reset the counter and the timer will
89 restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
90 HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
91
92 (++) Counter Mode: counter can be used to count external events on
93 the LPTIM Input1 or it can be used to count internal clock cycles.
94 To start this mode, call HAL_LPTIM_Counter_Start() or
95 HAL_LPTIM_Counter_Start_IT() for interruption mode.
96
97
98 (#) User can stop any process by calling the corresponding API:
99 HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
100 already started in interruption mode.
101
102 (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
103
104 *** Callback registration ***
105 =============================================
106 [..]
107 The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
108 allows the user to configure dynamically the driver callbacks.
109 [..]
110 Use Function HAL_LPTIM_RegisterCallback() to register a callback.
111 HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
112 the Callback ID and a pointer to the user callback function.
113 [..]
114 Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
115 default weak function.
116 HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
117 and the Callback ID.
118 [..]
119 These functions allow to register/unregister following callbacks:
120
121 (+) MspInitCallback : LPTIM Base Msp Init Callback.
122 (+) MspDeInitCallback : LPTIM Base Msp DeInit Callback.
123 (+) CompareMatchCallback : Compare match Callback.
124 (+) AutoReloadMatchCallback : Auto-reload match Callback.
125 (+) TriggerCallback : External trigger event detection Callback.
126 (+) CompareWriteCallback : Compare register write complete Callback.
127 (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
128 (+) DirectionUpCallback : Up-counting direction change Callback.
129 (+) DirectionDownCallback : Down-counting direction change Callback.
130 (+) UpdateEventCallback : Update event detection Callback.
131 (+) RepCounterWriteCallback : Repetition counter register write complete Callback.
132
133 [..]
134 By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
135 all interrupt callbacks are set to the corresponding weak functions:
136 examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().
137
138 [..]
139 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
140 functionalities in the Init/DeInit only when these callbacks are null
141 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
142 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
143
144 [..]
145 Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
146 Exception done MspInit/MspDeInit that can be registered/unregistered
147 in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
148 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
149 In that case first register the MspInit/MspDeInit user callbacks
150 using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
151
152 [..]
153 When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
154 not defined, the callback registration feature is not available and all callbacks
155 are set to the corresponding weak functions.
156
157 @endverbatim
158 ******************************************************************************
159 */
160
161 /* Includes ------------------------------------------------------------------*/
162 #include "stm32wbaxx_hal.h"
163
164 /** @addtogroup STM32WBAxx_HAL_Driver
165 * @{
166 */
167
168 /** @defgroup LPTIM LPTIM
169 * @brief LPTIM HAL module driver.
170 * @{
171 */
172
173 #ifdef HAL_LPTIM_MODULE_ENABLED
174
175 #if defined (LPTIM1) || defined (LPTIM2)
176
177 /* Private typedef -----------------------------------------------------------*/
178 /* Private define ------------------------------------------------------------*/
179 /** @addtogroup LPTIM_Private_Constants
180 * @{
181 */
182 #define TIMEOUT 1000UL /* Timeout is 1s */
183 /**
184 * @}
185 */
186
187 /* Private macro -------------------------------------------------------------*/
188 /* Private variables ---------------------------------------------------------*/
189 /* Private function prototypes -----------------------------------------------*/
190 static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig);
191 static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig);
192 static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig);
193 static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig);
194 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
195 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
196 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
197 static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag);
198 void LPTIM_DMAError(DMA_HandleTypeDef *hdma);
199 void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
200 void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
201 void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma);
202 void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma);
203 HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
204 uint32_t length);
205
206 /* Exported functions --------------------------------------------------------*/
207
208 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
209 * @{
210 */
211
212 /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
213 * @brief Initialization and Configuration functions.
214 *
215 @verbatim
216 ==============================================================================
217 ##### Initialization and de-initialization functions #####
218 ==============================================================================
219 [..] This section provides functions allowing to:
220 (+) Initialize the LPTIM according to the specified parameters in the
221 LPTIM_InitTypeDef and initialize the associated handle.
222 (+) DeInitialize the LPTIM peripheral.
223 (+) Initialize the LPTIM MSP.
224 (+) DeInitialize the LPTIM MSP.
225
226 @endverbatim
227 * @{
228 */
229
230 /**
231 * @brief Initialize the LPTIM according to the specified parameters in the
232 * LPTIM_InitTypeDef and initialize the associated handle.
233 * @param hlptim LPTIM handle
234 * @retval HAL status
235 */
HAL_LPTIM_Init(LPTIM_HandleTypeDef * hlptim)236 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
237 {
238 uint32_t tmpcfgr;
239
240 /* Check the LPTIM handle allocation */
241 if (hlptim == NULL)
242 {
243 return HAL_ERROR;
244 }
245
246 /* Check the parameters */
247 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
248 assert_param(IS_LPTIM_PERIOD(hlptim->Init.Period));
249
250 assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
251 assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
252 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
253 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
254 {
255 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
256 assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
257 }
258 assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
259 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
260 {
261 assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
262 assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
263 }
264 assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
265 assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
266 assert_param(IS_LPTIM_REPETITION(hlptim->Init.RepetitionCounter));
267
268 if (hlptim->State == HAL_LPTIM_STATE_RESET)
269 {
270 /* Allocate lock resource and initialize it */
271 hlptim->Lock = HAL_UNLOCKED;
272
273 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
274 /* Reset interrupt callbacks to legacy weak callbacks */
275 LPTIM_ResetCallback(hlptim);
276
277 if (hlptim->MspInitCallback == NULL)
278 {
279 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
280 }
281
282 /* Init the low level hardware : GPIO, CLOCK, NVIC */
283 hlptim->MspInitCallback(hlptim);
284 #else
285 /* Init the low level hardware : GPIO, CLOCK, NVIC */
286 HAL_LPTIM_MspInit(hlptim);
287 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
288 }
289
290 /* Change the LPTIM state */
291 hlptim->State = HAL_LPTIM_STATE_BUSY;
292
293 /* Enable the Peripheral */
294 __HAL_LPTIM_ENABLE(hlptim);
295
296 /* Clear flag */
297 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
298
299 /* Set the repetition counter */
300 __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter);
301
302 /* Wait for the completion of the write operation to the LPTIM_RCR register */
303 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_REPOK) == HAL_TIMEOUT)
304 {
305 return HAL_TIMEOUT;
306 }
307
308
309 /* Clear flag */
310 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
311
312 /* Set LPTIM Period */
313 __HAL_LPTIM_AUTORELOAD_SET(hlptim, hlptim->Init.Period);
314
315 /* Wait for the completion of the write operation to the LPTIM_ARR register */
316 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
317 {
318 return HAL_TIMEOUT;
319 }
320
321 /* Disable the Peripheral */
322 __HAL_LPTIM_DISABLE(hlptim);
323
324 /* Get the LPTIMx CFGR value */
325 tmpcfgr = hlptim->Instance->CFGR;
326
327 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
328 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
329 {
330 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
331 }
332 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
333 {
334 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
335 }
336
337 /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
338 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
339 LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
340
341 /* Set initialization parameters */
342 tmpcfgr |= (hlptim->Init.Clock.Source |
343 hlptim->Init.Clock.Prescaler |
344 hlptim->Init.UpdateMode |
345 hlptim->Init.CounterSource);
346
347 /* Glitch filters for internal triggers and external inputs are configured
348 * only if an internal clock source is provided to the LPTIM
349 */
350 if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
351 {
352 tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
353 hlptim->Init.UltraLowPowerClock.SampleTime);
354 }
355
356 /* Configure LPTIM external clock polarity and digital filter */
357 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
358 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
359 {
360 tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
361 hlptim->Init.UltraLowPowerClock.SampleTime);
362 }
363
364 /* Configure LPTIM external trigger */
365 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
366 {
367 /* Enable External trigger and set the trigger source */
368 tmpcfgr |= (hlptim->Init.Trigger.Source |
369 hlptim->Init.Trigger.ActiveEdge |
370 hlptim->Init.Trigger.SampleTime);
371 }
372
373 /* Write to LPTIMx CFGR */
374 hlptim->Instance->CFGR = tmpcfgr;
375
376 /* Check LPTIM Input1 and Input2 sources */
377 assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
378 assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source));
379
380 /* Configure LPTIM Input1 and Input2 sources */
381 hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
382
383 /* Initialize the LPTIM channels state */
384 LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_READY);
385
386 /* Change the LPTIM state */
387 hlptim->State = HAL_LPTIM_STATE_READY;
388
389 /* Return function status */
390 return HAL_OK;
391 }
392
393 /**
394 * @brief DeInitialize the LPTIM peripheral.
395 * @param hlptim LPTIM handle
396 * @retval HAL status
397 */
HAL_LPTIM_DeInit(LPTIM_HandleTypeDef * hlptim)398 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
399 {
400 /* Check the LPTIM handle allocation */
401 if (hlptim == NULL)
402 {
403 return HAL_ERROR;
404 }
405
406 /* Change the LPTIM state */
407 hlptim->State = HAL_LPTIM_STATE_BUSY;
408
409 __HAL_LPTIM_ENABLE(hlptim);
410 if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
411 {
412 hlptim->Instance->CCMR1 = 0;
413 }
414
415 /* Clear flag */
416 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
417
418 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, 0);
419 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
420 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
421 {
422 return HAL_TIMEOUT;
423 }
424
425 if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
426 {
427 /* Clear flag */
428 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
429
430 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, 0);
431 /* Wait for the completion of the write operation to the LPTIM_CCR2 register */
432 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) == HAL_TIMEOUT)
433 {
434 return HAL_TIMEOUT;
435 }
436 }
437
438 /* Clear flag */
439 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
440
441 __HAL_LPTIM_AUTORELOAD_SET(hlptim, 0);
442
443 /* Wait for the completion of the write operation to the LPTIM_ARR register */
444 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
445 {
446 return HAL_TIMEOUT;
447 }
448
449 /* Disable the LPTIM Peripheral Clock */
450 __HAL_LPTIM_DISABLE(hlptim);
451
452 hlptim->Instance->CFGR = 0;
453 hlptim->Instance->CFGR2 = 0;
454
455 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
456 if (hlptim->MspDeInitCallback == NULL)
457 {
458 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
459 }
460
461 /* DeInit the low level hardware: CLOCK, NVIC.*/
462 hlptim->MspDeInitCallback(hlptim);
463 #else
464 /* DeInit the low level hardware: CLOCK, NVIC.*/
465 HAL_LPTIM_MspDeInit(hlptim);
466 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
467
468 /* Change the LPTIM channels state */
469 LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_RESET);
470
471 /* Change the LPTIM state */
472 hlptim->State = HAL_LPTIM_STATE_RESET;
473
474 /* Release Lock */
475 __HAL_UNLOCK(hlptim);
476
477 /* Return function status */
478 return HAL_OK;
479 }
480
481 /**
482 * @brief Initialize the LPTIM MSP.
483 * @param hlptim LPTIM handle
484 * @retval None
485 */
HAL_LPTIM_MspInit(LPTIM_HandleTypeDef * hlptim)486 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
487 {
488 /* Prevent unused argument(s) compilation warning */
489 UNUSED(hlptim);
490
491 /* NOTE : This function should not be modified, when the callback is needed,
492 the HAL_LPTIM_MspInit could be implemented in the user file
493 */
494 }
495
496 /**
497 * @brief DeInitialize LPTIM MSP.
498 * @param hlptim LPTIM handle
499 * @retval None
500 */
HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef * hlptim)501 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
502 {
503 /* Prevent unused argument(s) compilation warning */
504 UNUSED(hlptim);
505
506 /* NOTE : This function should not be modified, when the callback is needed,
507 the HAL_LPTIM_MspDeInit could be implemented in the user file
508 */
509 }
510
511 /**
512 * @}
513 */
514
515 /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
516 * @brief Start-Stop operation functions.
517 *
518 @verbatim
519 ==============================================================================
520 ##### LPTIM Start Stop operation functions #####
521 ==============================================================================
522 [..] This section provides functions allowing to:
523 (+) Start the PWM mode.
524 (+) Stop the PWM mode.
525 (+) Start the One pulse mode.
526 (+) Stop the One pulse mode.
527 (+) Start the Set once mode.
528 (+) Stop the Set once mode.
529 (+) Start the Encoder mode.
530 (+) Stop the Encoder mode.
531 (+) Start the Timeout mode.
532 (+) Stop the Timeout mode.
533 (+) Start the Counter mode.
534 (+) Stop the Counter mode.
535
536
537 @endverbatim
538 * @{
539 */
540
541 /**
542 * @brief Start the LPTIM PWM generation.
543 * @param hlptim LPTIM handle
544 * @param Channel LPTIM Channel to be enabled
545 * This parameter can be one of the following values:
546 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
547 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
548 * @retval HAL status
549 */
HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)550 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
551 {
552 /* Check the parameters */
553 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
554
555 /* Check LPTIM channel state */
556 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
557 {
558 return HAL_ERROR;
559 }
560
561 /* Set the LPTIM state */
562 hlptim->State = HAL_LPTIM_STATE_BUSY;
563
564 /* Set the LPTIM channel state */
565 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
566
567 /* Reset WAVE bit to set PWM mode */
568 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
569
570 /* Enable the Peripheral */
571 __HAL_LPTIM_ENABLE(hlptim);
572
573 /* Enable LPTIM signal on the corresponding output pin */
574 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
575
576 /* Start timer in continuous mode */
577 __HAL_LPTIM_START_CONTINUOUS(hlptim);
578
579 /* Change the LPTIM state */
580 hlptim->State = HAL_LPTIM_STATE_READY;
581
582 /* Return function status */
583 return HAL_OK;
584 }
585
586 /**
587 * @brief Stop the LPTIM PWM generation.
588 * @param hlptim LPTIM handle
589 * @param Channel LPTIM Channel to be disabled
590 * This parameter can be one of the following values:
591 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
592 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
593 * @retval HAL status
594 */
HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)595 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
596 {
597 /* Check the parameters */
598 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
599
600 /* Change the LPTIM state */
601 hlptim->State = HAL_LPTIM_STATE_BUSY;
602
603 /* Disable LPTIM signal from the corresponding output pin */
604 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
605
606 /* Disable the Peripheral */
607 __HAL_LPTIM_DISABLE(hlptim);
608
609 /* Set the LPTIM channel state */
610 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
611
612 /* Set the LPTIM state */
613 hlptim->State = HAL_LPTIM_STATE_READY;
614
615 /* Return function status */
616 return HAL_OK;
617 }
618
619 /**
620 * @brief Start the LPTIM PWM generation in interrupt mode.
621 * @param hlptim LPTIM handle
622 * @param Channel LPTIM Channel to be enabled
623 * This parameter can be one of the following values:
624 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
625 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
626 * @retval HAL status
627 */
HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)628 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
629 {
630 /* Check the parameters */
631 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
632
633 /* Check LPTIM channel state */
634 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
635 {
636 return HAL_ERROR;
637 }
638
639 /* Set the LPTIM state */
640 hlptim->State = HAL_LPTIM_STATE_BUSY;
641
642 /* Set the LPTIM channel state */
643 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
644
645 /* Reset WAVE bit to set PWM mode */
646 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
647
648 /* Enable the Peripheral */
649 __HAL_LPTIM_ENABLE(hlptim);
650 /* Clear flag */
651 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
652
653 switch (Channel)
654 {
655 case LPTIM_CHANNEL_1:
656 /* Enable interrupt */
657 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
658 LPTIM_IT_UPDATE);
659 break;
660 case LPTIM_CHANNEL_2:
661 /* Enable interrupt */
662 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
663 LPTIM_IT_UPDATE);
664 break;
665 default:
666 break;
667 }
668
669 /* Wait for the completion of the write operation to the LPTIM_DIER register */
670 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
671 {
672 return HAL_TIMEOUT;
673 }
674
675 /* If external trigger source is used, then enable external trigger interrupt */
676 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
677 {
678 /* Clear flag */
679 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
680
681 /* Enable external trigger interrupt */
682 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
683
684 /* Wait for the completion of the write operation to the LPTIM_DIER register */
685 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
686 {
687 return HAL_TIMEOUT;
688 }
689 }
690
691 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
692
693 /* Start timer in continuous mode */
694 __HAL_LPTIM_START_CONTINUOUS(hlptim);
695
696 /* Change the LPTIM state */
697 hlptim->State = HAL_LPTIM_STATE_READY;
698
699 /* Return function status */
700 return HAL_OK;
701 }
702
703 /**
704 * @brief Stop the LPTIM PWM generation in interrupt mode.
705 * @param hlptim LPTIM handle
706 * @param Channel LPTIM Channel to be disabled
707 * This parameter can be one of the following values:
708 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
709 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
710 * @retval HAL status
711 */
HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)712 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
713 {
714 /* Check the parameters */
715 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
716
717 /* Change the LPTIM state */
718 hlptim->State = HAL_LPTIM_STATE_BUSY;
719
720 /* Disable LPTIM signal from the corresponding output pin */
721 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
722
723 /* Disable the Peripheral */
724 __HAL_LPTIM_DISABLE(hlptim);
725
726 /* Enable the Peripheral */
727 __HAL_LPTIM_ENABLE(hlptim);
728
729 /* Clear flag */
730 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
731
732 switch (Channel)
733 {
734 case LPTIM_CHANNEL_1:
735 /* Disable interrupt */
736 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
737 LPTIM_IT_UPDATE);
738 break;
739 case LPTIM_CHANNEL_2:
740 /* Disable interrupt */
741 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
742 LPTIM_IT_UPDATE);
743 break;
744 default:
745 break;
746 }
747
748 /* Wait for the completion of the write operation to the LPTIM_DIER register */
749 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
750 {
751 return HAL_TIMEOUT;
752 }
753
754 /* If external trigger source is used, then enable external trigger interrupt */
755 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
756 {
757 /* Clear flag */
758 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
759
760 /* Enable external trigger interrupt */
761 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
762
763 /* Wait for the completion of the write operation to the LPTIM_DIER register */
764 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
765 {
766 return HAL_TIMEOUT;
767 }
768 }
769
770 /* Disable the Peripheral */
771 __HAL_LPTIM_DISABLE(hlptim);
772
773 /* Set the LPTIM channel state */
774 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
775
776 /* Set the LPTIM state */
777 hlptim->State = HAL_LPTIM_STATE_READY;
778
779 /* Return function status */
780 return HAL_OK;
781 }
782
783 /**
784 * @brief Start the LPTIM PWM generation in DMA mode.
785 * @param hlptim LPTIM handle
786 * @param Channel LPTIM Channel to be enabled
787 * This parameter can be one of the following values:
788 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
789 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
790 * @param pData The destination Buffer address
791 * @param Length The length of data to be transferred from LPTIM peripheral to memory
792 * @retval HAL status
793 */
HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel,const uint32_t * pData,uint32_t Length)794 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, const uint32_t *pData,
795 uint32_t Length)
796 {
797 DMA_HandleTypeDef *hdma;
798
799 /* Check the parameters */
800 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
801 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
802
803 if ((pData == NULL) || (Length == 0U))
804 {
805 return HAL_ERROR;
806 }
807
808 /* Check LPTIM channel state */
809 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
810 {
811 return HAL_ERROR;
812 }
813
814 /* Set the LPTIM state */
815 hlptim->State = HAL_LPTIM_STATE_BUSY;
816
817 /* Set the LPTIM channel state */
818 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
819
820 /* Reset WAVE bit to set PWM mode */
821 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
822
823 /* Enable the Peripheral */
824 __HAL_LPTIM_ENABLE(hlptim);
825
826 /* Enable update event DMA request */
827 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
828
829 /* Wait for the completion of the write operation to the LPTIM_DIER register */
830 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
831 {
832 return HAL_TIMEOUT;
833 }
834
835 switch (Channel)
836 {
837 case LPTIM_CHANNEL_1:
838 /* Set the DMA update event callbacks */
839 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
840 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
841
842 /* Set the DMA error callback */
843 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
844
845 /* Enable the DMA Channel */
846 hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
847 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR1, Length) != HAL_OK)
848 {
849 /* Return error status */
850 return HAL_ERROR;
851 }
852 break;
853 case LPTIM_CHANNEL_2:
854 /* Set the DMA update event callbacks */
855 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
856 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
857
858 /* Set the DMA error callback */
859 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
860
861 /* Enable the DMA Channel */
862 hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
863 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR2, Length) != HAL_OK)
864 {
865 /* Return error status */
866 return HAL_ERROR;
867 }
868 break;
869 default:
870 break;
871 }
872
873 /* Enable LPTIM signal on the corresponding output pin */
874 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
875
876 /* Start timer in continuous mode */
877 __HAL_LPTIM_START_CONTINUOUS(hlptim);
878
879 /* Change the LPTIM state */
880 hlptim->State = HAL_LPTIM_STATE_READY;
881
882 /* Return function status */
883 return HAL_OK;
884 }
885
886 /**
887 * @brief Stop the LPTIM PWM generation in DMA mode.
888 * @param hlptim LPTIM handle
889 * @param Channel LPTIM Channel to be disabled
890 * This parameter can be one of the following values:
891 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
892 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
893 * @retval HAL status
894 */
HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)895 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
896 {
897 /* Check the parameters */
898 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
899 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
900
901 /* Change the LPTIM state */
902 hlptim->State = HAL_LPTIM_STATE_BUSY;
903
904 /* Disable update event DMA request */
905 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
906
907 switch (Channel)
908 {
909 case LPTIM_CHANNEL_1:
910 /* Disable update event DMA request */
911 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
912 break;
913 case LPTIM_CHANNEL_2:
914 /* Disable update event DMA request */
915 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
916 break;
917 default:
918 break;
919 }
920
921 /* Disable LPTIM signal from the corresponding output pin */
922 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
923
924 /* Disable the Peripheral */
925 __HAL_LPTIM_DISABLE(hlptim);
926
927 /* Set the LPTIM channel state */
928 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
929
930 /* Set the LPTIM state */
931 hlptim->State = HAL_LPTIM_STATE_READY;
932
933 /* Return function status */
934 return HAL_OK;
935 }
936
937 /**
938 * @brief Start the LPTIM One pulse generation.
939 * @param hlptim LPTIM handle
940 * @param Channel LPTIM Channel to be enabled
941 * This parameter can be one of the following values:
942 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
943 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
944 * @retval HAL status
945 */
HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)946 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
947 {
948 /* Check the parameters */
949 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
950
951 /* Check LPTIM channel state */
952 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
953 {
954 return HAL_ERROR;
955 }
956
957 /* Set the LPTIM state */
958 hlptim->State = HAL_LPTIM_STATE_BUSY;
959
960 /* Set the LPTIM channel state */
961 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
962
963 /* Reset WAVE bit to set one pulse mode */
964 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
965
966 /* Enable the Peripheral */
967 __HAL_LPTIM_ENABLE(hlptim);
968
969 /* Enable LPTIM signal on the corresponding output pin */
970 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
971
972 /* Start timer in single (one shot) mode */
973 __HAL_LPTIM_START_SINGLE(hlptim);
974
975 /* Change the LPTIM state */
976 hlptim->State = HAL_LPTIM_STATE_READY;
977
978 /* Return function status */
979 return HAL_OK;
980 }
981
982 /**
983 * @brief Stop the LPTIM One pulse generation.
984 * @param hlptim LPTIM handle
985 * @param Channel LPTIM Channel to be disabled
986 * This parameter can be one of the following values:
987 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
988 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
989 * @retval HAL status
990 */
HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)991 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
992 {
993 /* Check the parameters */
994 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
995
996 /* Set the LPTIM state */
997 hlptim->State = HAL_LPTIM_STATE_BUSY;
998
999 /* Disable LPTIM signal on the corresponding output pin */
1000 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1001
1002 /* Disable the Peripheral */
1003 __HAL_LPTIM_DISABLE(hlptim);
1004
1005 /* Set the LPTIM channel state */
1006 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1007
1008 /* Set the LPTIM state */
1009 hlptim->State = HAL_LPTIM_STATE_READY;
1010
1011 /* Return function status */
1012 return HAL_OK;
1013 }
1014
1015 /**
1016 * @brief Start the LPTIM One pulse generation in interrupt mode.
1017 * @param hlptim LPTIM handle
1018 * @param Channel LPTIM Channel to be enabled
1019 * This parameter can be one of the following values:
1020 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1021 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1022 * @retval HAL status
1023 */
HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1024 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1025 {
1026 /* Check the parameters */
1027 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1028
1029 /* Check LPTIM channel state */
1030 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1031 {
1032 return HAL_ERROR;
1033 }
1034
1035 /* Set the LPTIM state */
1036 hlptim->State = HAL_LPTIM_STATE_BUSY;
1037
1038 /* Set the LPTIM channel state */
1039 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1040
1041 /* Reset WAVE bit to set one pulse mode */
1042 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
1043
1044 /* Enable the Peripheral */
1045 __HAL_LPTIM_ENABLE(hlptim);
1046
1047 /* Clear flag */
1048 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1049
1050 switch (Channel)
1051 {
1052 case LPTIM_CHANNEL_1:
1053 /* Enable interrupt */
1054 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1055 LPTIM_IT_UPDATE);
1056 break;
1057 case LPTIM_CHANNEL_2:
1058 /* Enable interrupt */
1059 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1060 LPTIM_IT_UPDATE);
1061 break;
1062 default:
1063 break;
1064 }
1065
1066 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1067 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1068 {
1069 return HAL_TIMEOUT;
1070 }
1071
1072 /* If external trigger source is used, then enable external trigger interrupt */
1073 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1074 {
1075 /* Clear flag */
1076 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1077 /* Enable external trigger interrupt */
1078 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1079 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1080 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1081 {
1082 return HAL_TIMEOUT;
1083 }
1084 }
1085
1086 /* Enable LPTIM signal on the corresponding output pin */
1087 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1088
1089 /* Start timer in single (one shot) mode */
1090 __HAL_LPTIM_START_SINGLE(hlptim);
1091
1092 /* Change the LPTIM state */
1093 hlptim->State = HAL_LPTIM_STATE_READY;
1094
1095 /* Return function status */
1096 return HAL_OK;
1097 }
1098
1099 /**
1100 * @brief Stop the LPTIM One pulse generation in interrupt mode.
1101 * @param hlptim LPTIM handle
1102 * @param Channel LPTIM Channel to be disabled
1103 * This parameter can be one of the following values:
1104 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1105 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1106 * @retval HAL status
1107 */
HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1108 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1109 {
1110 /* Check the parameters */
1111 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1112
1113 /* Set the LPTIM state */
1114 hlptim->State = HAL_LPTIM_STATE_BUSY;
1115
1116 /* Disable LPTIM signal on the corresponding output pin */
1117 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1118
1119 /* Disable the Peripheral */
1120 __HAL_LPTIM_DISABLE(hlptim);
1121
1122
1123 /* Enable the Peripheral */
1124 __HAL_LPTIM_ENABLE(hlptim);
1125
1126 /* Clear flag */
1127 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1128
1129 switch (Channel)
1130 {
1131 case LPTIM_CHANNEL_1:
1132 /* Disable interrupt */
1133 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1134 LPTIM_IT_UPDATE);
1135 break;
1136 case LPTIM_CHANNEL_2:
1137 /* Disable interrupt */
1138 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1139 LPTIM_IT_UPDATE);
1140 break;
1141 default:
1142 break;
1143 }
1144
1145 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1146 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1147 {
1148 return HAL_TIMEOUT;
1149 }
1150
1151 /* If external trigger source is used, then enable external trigger interrupt */
1152 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1153 {
1154 /* Clear flag */
1155 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1156 /* Enable external trigger interrupt */
1157 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1158 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1159 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1160 {
1161 return HAL_TIMEOUT;
1162 }
1163 }
1164
1165 /* Disable the Peripheral */
1166 __HAL_LPTIM_DISABLE(hlptim);
1167
1168 /* Set the LPTIM channel state */
1169 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1170
1171 /* Set the LPTIM state */
1172 hlptim->State = HAL_LPTIM_STATE_READY;
1173
1174 /* Return function status */
1175 return HAL_OK;
1176 }
1177
1178 /**
1179 * @brief Start the LPTIM in Set once mode.
1180 * @param hlptim LPTIM handle
1181 * @param Channel LPTIM Channel to be enabled
1182 * This parameter can be one of the following values:
1183 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1184 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1185 * @retval HAL status
1186 */
HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1187 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1188 {
1189 /* Check the parameters */
1190 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1191
1192 /* Check LPTIM channel state */
1193 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1194 {
1195 return HAL_ERROR;
1196 }
1197
1198 /* Set the LPTIM state */
1199 hlptim->State = HAL_LPTIM_STATE_BUSY;
1200
1201 /* Set the LPTIM channel state */
1202 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1203
1204 /* Set WAVE bit to enable the set once mode */
1205 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
1206
1207 /* Enable the Peripheral */
1208 __HAL_LPTIM_ENABLE(hlptim);
1209
1210 /* Enable LPTIM signal on the corresponding output pin */
1211 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1212
1213 /* Start timer in single (one shot) mode */
1214 __HAL_LPTIM_START_SINGLE(hlptim);
1215
1216 /* Change the LPTIM state */
1217 hlptim->State = HAL_LPTIM_STATE_READY;
1218
1219 /* Return function status */
1220 return HAL_OK;
1221 }
1222
1223 /**
1224 * @brief Stop the LPTIM Set once mode.
1225 * @param hlptim LPTIM handle
1226 * @param Channel LPTIM Channel to be disabled
1227 * This parameter can be one of the following values:
1228 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1229 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1230 * @retval HAL status
1231 */
HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1232 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1233 {
1234 /* Check the parameters */
1235 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1236
1237 /* Set the LPTIM state */
1238 hlptim->State = HAL_LPTIM_STATE_BUSY;
1239
1240 /* Disable LPTIM signal on the corresponding output pin */
1241 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1242
1243 /* Disable the Peripheral */
1244 __HAL_LPTIM_DISABLE(hlptim);
1245
1246 /* Set the LPTIM channel state */
1247 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1248
1249 /* Set the LPTIM state */
1250 hlptim->State = HAL_LPTIM_STATE_READY;
1251
1252 /* Return function status */
1253 return HAL_OK;
1254 }
1255
1256 /**
1257 * @brief Start the LPTIM Set once mode in interrupt mode.
1258 * @param hlptim LPTIM handle
1259 * @param Channel LPTIM Channel to be enabled
1260 * This parameter can be one of the following values:
1261 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1262 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1263 * @retval HAL status
1264 */
HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1265 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1266 {
1267 /* Check the parameters */
1268 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1269
1270 /* Check LPTIM channel state */
1271 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1272 {
1273 return HAL_ERROR;
1274 }
1275
1276 /* Set the LPTIM state */
1277 hlptim->State = HAL_LPTIM_STATE_BUSY;
1278
1279 /* Set the LPTIM channel state */
1280 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1281
1282 /* Set WAVE bit to enable the set once mode */
1283 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
1284
1285 /* Enable the Peripheral */
1286 __HAL_LPTIM_ENABLE(hlptim);
1287
1288 /* Clear flag */
1289 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1290
1291 switch (Channel)
1292 {
1293 case LPTIM_CHANNEL_1:
1294 /* Enable interrupt */
1295 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
1296 break;
1297 case LPTIM_CHANNEL_2:
1298 /* Enable interrupt */
1299 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
1300 break;
1301 default:
1302 break;
1303 }
1304
1305 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1306 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1307 {
1308 return HAL_TIMEOUT;
1309 }
1310
1311 /* If external trigger source is used, then enable external trigger interrupt */
1312 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1313 {
1314 /* Clear flag */
1315 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1316 /* Enable external trigger interrupt */
1317 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1318 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1319 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1320 {
1321 return HAL_TIMEOUT;
1322 }
1323 }
1324
1325 /* Enable LPTIM signal on the corresponding output pin */
1326 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1327
1328 /* Start timer in single (one shot) mode */
1329 __HAL_LPTIM_START_SINGLE(hlptim);
1330
1331 /* Change the LPTIM state */
1332 hlptim->State = HAL_LPTIM_STATE_READY;
1333
1334 /* Return function status */
1335 return HAL_OK;
1336 }
1337
1338 /**
1339 * @brief Stop the LPTIM Set once mode in interrupt mode.
1340 * @param hlptim LPTIM handle
1341 * @param Channel LPTIM Channel to be disabled
1342 * This parameter can be one of the following values:
1343 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1344 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1345 * @retval HAL status
1346 */
HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1347 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1348 {
1349 /* Check the parameters */
1350 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1351
1352 /* Set the LPTIM state */
1353 hlptim->State = HAL_LPTIM_STATE_BUSY;
1354
1355 /* Disable LPTIM signal on the corresponding output pin */
1356 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1357
1358 /* Disable the Peripheral */
1359 __HAL_LPTIM_DISABLE(hlptim);
1360
1361 /* Enable the Peripheral */
1362 __HAL_LPTIM_ENABLE(hlptim);
1363
1364 /* Clear flag */
1365 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1366
1367 switch (Channel)
1368 {
1369 case LPTIM_CHANNEL_1:
1370 /* Disable interrupt */
1371 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
1372 break;
1373 case LPTIM_CHANNEL_2:
1374 /* Disable interrupt */
1375 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
1376 break;
1377 default:
1378 break;
1379 }
1380
1381 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1382 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1383 {
1384 return HAL_TIMEOUT;
1385 }
1386
1387 /* If external trigger source is used, then enable external trigger interrupt */
1388 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1389 {
1390 /* Clear flag */
1391 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1392 /* Enable external trigger interrupt */
1393 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1394
1395 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1396 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1397 {
1398 return HAL_TIMEOUT;
1399 }
1400 }
1401
1402 /* Disable the Peripheral */
1403 __HAL_LPTIM_DISABLE(hlptim);
1404
1405 /* Set the LPTIM channel state */
1406 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1407
1408 /* Set the LPTIM state */
1409 hlptim->State = HAL_LPTIM_STATE_READY;
1410
1411 /* Return function status */
1412 return HAL_OK;
1413 }
1414
1415 /**
1416 * @brief Start the Encoder interface.
1417 * @param hlptim LPTIM handle
1418 * @retval HAL status
1419 */
HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef * hlptim)1420 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim)
1421 {
1422 uint32_t tmpcfgr;
1423
1424 /* Check the parameters */
1425 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1426 assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
1427 assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
1428 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
1429
1430 /* Set the LPTIM state */
1431 hlptim->State = HAL_LPTIM_STATE_BUSY;
1432
1433 /* Get the LPTIMx CFGR value */
1434 tmpcfgr = hlptim->Instance->CFGR;
1435
1436 /* Clear CKPOL bits */
1437 tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
1438
1439 /* Set Input polarity */
1440 tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
1441
1442 /* Write to LPTIMx CFGR */
1443 hlptim->Instance->CFGR = tmpcfgr;
1444
1445 /* Set ENC bit to enable the encoder interface */
1446 hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
1447
1448 /* Enable the Peripheral */
1449 __HAL_LPTIM_ENABLE(hlptim);
1450
1451 /* Start timer in continuous mode */
1452 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1453
1454 /* Change the LPTIM state */
1455 hlptim->State = HAL_LPTIM_STATE_READY;
1456
1457 /* Return function status */
1458 return HAL_OK;
1459 }
1460
1461 /**
1462 * @brief Stop the Encoder interface.
1463 * @param hlptim LPTIM handle
1464 * @retval HAL status
1465 */
HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef * hlptim)1466 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
1467 {
1468 /* Check the parameters */
1469 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1470
1471 /* Set the LPTIM state */
1472 hlptim->State = HAL_LPTIM_STATE_BUSY;
1473
1474 /* Disable the Peripheral */
1475 __HAL_LPTIM_DISABLE(hlptim);
1476
1477 /* Reset ENC bit to disable the encoder interface */
1478 hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
1479
1480 /* Change the LPTIM state */
1481 hlptim->State = HAL_LPTIM_STATE_READY;
1482
1483 /* Return function status */
1484 return HAL_OK;
1485 }
1486
1487 /**
1488 * @brief Start the Encoder interface in interrupt mode.
1489 * @param hlptim LPTIM handle
1490 * @retval HAL status
1491 */
HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef * hlptim)1492 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim)
1493 {
1494 uint32_t tmpcfgr;
1495
1496 /* Check the parameters */
1497 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1498 assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
1499 assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
1500 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
1501
1502 /* Set the LPTIM state */
1503 hlptim->State = HAL_LPTIM_STATE_BUSY;
1504
1505 /* Configure edge sensitivity for encoder mode */
1506 /* Get the LPTIMx CFGR value */
1507 tmpcfgr = hlptim->Instance->CFGR;
1508
1509 /* Clear CKPOL bits */
1510 tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
1511
1512 /* Set Input polarity */
1513 tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
1514
1515 /* Write to LPTIMx CFGR */
1516 hlptim->Instance->CFGR = tmpcfgr;
1517
1518 /* Set ENC bit to enable the encoder interface */
1519 hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
1520
1521 /* Enable the Peripheral */
1522 __HAL_LPTIM_ENABLE(hlptim);
1523
1524 /* Clear flag */
1525 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1526
1527 /* Enable "switch to up/down direction" interrupt */
1528 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
1529
1530 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1531 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1532 {
1533 return HAL_TIMEOUT;
1534 }
1535
1536
1537 /* Start timer in continuous mode */
1538 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1539
1540 /* Change the LPTIM state */
1541 hlptim->State = HAL_LPTIM_STATE_READY;
1542
1543 /* Return function status */
1544 return HAL_OK;
1545 }
1546
1547 /**
1548 * @brief Stop the Encoder interface in interrupt mode.
1549 * @param hlptim LPTIM handle
1550 * @retval HAL status
1551 */
HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef * hlptim)1552 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1553 {
1554 /* Check the parameters */
1555 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1556
1557 /* Set the LPTIM state */
1558 hlptim->State = HAL_LPTIM_STATE_BUSY;
1559
1560 /* Disable the Peripheral */
1561 __HAL_LPTIM_DISABLE(hlptim);
1562
1563 /* Reset ENC bit to disable the encoder interface */
1564 hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
1565 /* Enable the Peripheral */
1566 __HAL_LPTIM_ENABLE(hlptim);
1567
1568 /* Clear flag */
1569 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1570
1571 /* Disable "switch to down/up direction" interrupt */
1572 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
1573
1574 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1575 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1576 {
1577 return HAL_TIMEOUT;
1578 }
1579
1580 /* Disable the Peripheral */
1581 __HAL_LPTIM_DISABLE(hlptim);
1582
1583 /* Change the LPTIM state */
1584 hlptim->State = HAL_LPTIM_STATE_READY;
1585
1586 /* Return function status */
1587 return HAL_OK;
1588 }
1589
1590 /**
1591 * @brief Start the Timeout function.
1592 * @note The first trigger event will start the timer, any successive
1593 * trigger event will reset the counter and the timer restarts.
1594 * @param hlptim LPTIM handle
1595 * @param Timeout Specifies the TimeOut value to reset the counter.
1596 * This parameter must be a value between 0x0000 and 0xFFFF.
1597 * @retval HAL status
1598 */
HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Timeout)1599 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
1600 {
1601 /* Check the parameters */
1602 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1603 assert_param(IS_LPTIM_PULSE(Timeout));
1604
1605 /* Set the LPTIM state */
1606 hlptim->State = HAL_LPTIM_STATE_BUSY;
1607
1608 /* Set TIMOUT bit to enable the timeout function */
1609 hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
1610
1611 /* Enable the Peripheral */
1612 __HAL_LPTIM_ENABLE(hlptim);
1613
1614 /* Clear flag */
1615 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
1616
1617 /* Load the Timeout value in the compare register */
1618 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
1619
1620 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
1621 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
1622 {
1623 return HAL_TIMEOUT;
1624 }
1625
1626 /* Start timer in continuous mode */
1627 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1628
1629 /* Change the LPTIM state */
1630 hlptim->State = HAL_LPTIM_STATE_READY;
1631
1632 /* Return function status */
1633 return HAL_OK;
1634 }
1635
1636 /**
1637 * @brief Stop the Timeout function.
1638 * @param hlptim LPTIM handle
1639 * @retval HAL status
1640 */
HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef * hlptim)1641 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
1642 {
1643 /* Check the parameters */
1644 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1645
1646 /* Set the LPTIM state */
1647 hlptim->State = HAL_LPTIM_STATE_BUSY;
1648
1649 /* Disable the Peripheral */
1650 __HAL_LPTIM_DISABLE(hlptim);
1651
1652 /* Reset TIMOUT bit to enable the timeout function */
1653 hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
1654
1655 /* Change the LPTIM state */
1656 hlptim->State = HAL_LPTIM_STATE_READY;
1657
1658 /* Return function status */
1659 return HAL_OK;
1660 }
1661
1662 /**
1663 * @brief Start the Timeout function in interrupt mode.
1664 * @note The first trigger event will start the timer, any successive
1665 * trigger event will reset the counter and the timer restarts.
1666 * @param hlptim LPTIM handle
1667 * @param Timeout Specifies the TimeOut value to reset the counter.
1668 * This parameter must be a value between 0x0000 and 0xFFFF.
1669 * @retval HAL status
1670 */
HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Timeout)1671 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
1672 {
1673 /* Check the parameters */
1674 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1675 assert_param(IS_LPTIM_PULSE(Timeout));
1676
1677 /* Set the LPTIM state */
1678 hlptim->State = HAL_LPTIM_STATE_BUSY;
1679
1680 /* Set TIMOUT bit to enable the timeout function */
1681 hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
1682
1683 /* Enable the Peripheral */
1684 __HAL_LPTIM_ENABLE(hlptim);
1685
1686 /* Clear flag */
1687 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1688
1689 /* Enable Compare match CH1 interrupt */
1690 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
1691
1692 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1693 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1694 {
1695 return HAL_TIMEOUT;
1696 }
1697
1698 /* Clear flag */
1699 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
1700
1701 /* Load the Timeout value in the compare register */
1702 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
1703
1704 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
1705 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
1706 {
1707 return HAL_TIMEOUT;
1708 }
1709
1710 /* Start timer in continuous mode */
1711 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1712
1713 /* Change the LPTIM state */
1714 hlptim->State = HAL_LPTIM_STATE_READY;
1715
1716 /* Return function status */
1717 return HAL_OK;
1718 }
1719
1720 /**
1721 * @brief Stop the Timeout function in interrupt mode.
1722 * @param hlptim LPTIM handle
1723 * @retval HAL status
1724 */
HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef * hlptim)1725 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1726 {
1727 /* Check the parameters */
1728 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1729
1730 /* Set the LPTIM state */
1731 hlptim->State = HAL_LPTIM_STATE_BUSY;
1732
1733 /* Disable the Peripheral */
1734 __HAL_LPTIM_DISABLE(hlptim);
1735
1736 /* Reset TIMOUT bit to enable the timeout function */
1737 hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
1738
1739 /* Enable the Peripheral */
1740 __HAL_LPTIM_ENABLE(hlptim);
1741
1742 /* Clear flag */
1743 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1744
1745 /* Disable Compare match CH1 interrupt */
1746 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
1747
1748 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1749 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1750 {
1751 return HAL_TIMEOUT;
1752 }
1753
1754 /* Disable the Peripheral */
1755 __HAL_LPTIM_DISABLE(hlptim);
1756
1757 /* Change the LPTIM state */
1758 hlptim->State = HAL_LPTIM_STATE_READY;
1759
1760 /* Return function status */
1761 return HAL_OK;
1762 }
1763
1764 /**
1765 * @brief Start the Counter mode.
1766 * @param hlptim LPTIM handle
1767 * @retval HAL status
1768 */
HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef * hlptim)1769 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim)
1770 {
1771 /* Check the parameters */
1772 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1773
1774 /* Set the LPTIM state */
1775 hlptim->State = HAL_LPTIM_STATE_BUSY;
1776
1777 /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
1778 if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
1779 && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
1780 {
1781 /* Check if clock is prescaled */
1782 assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
1783 /* Set clock prescaler to 0 */
1784 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
1785 }
1786
1787 /* Enable the Peripheral */
1788 __HAL_LPTIM_ENABLE(hlptim);
1789
1790 /* Start timer in continuous mode */
1791 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1792
1793 /* Change the LPTIM state */
1794 hlptim->State = HAL_LPTIM_STATE_READY;
1795
1796 /* Return function status */
1797 return HAL_OK;
1798 }
1799
1800 /**
1801 * @brief Stop the Counter mode.
1802 * @param hlptim LPTIM handle
1803 * @retval HAL status
1804 */
HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef * hlptim)1805 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
1806 {
1807 /* Check the parameters */
1808 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1809
1810 /* Set the LPTIM state */
1811 hlptim->State = HAL_LPTIM_STATE_BUSY;
1812
1813 /* Disable the Peripheral */
1814 __HAL_LPTIM_DISABLE(hlptim);
1815
1816 /* Change the LPTIM state */
1817 hlptim->State = HAL_LPTIM_STATE_READY;
1818
1819 /* Return function status */
1820 return HAL_OK;
1821 }
1822
1823 /**
1824 * @brief Start the Counter mode in interrupt mode.
1825 * @param hlptim LPTIM handle
1826 * @retval HAL status
1827 */
HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef * hlptim)1828 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim)
1829 {
1830 /* Check the parameters */
1831 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1832
1833 /* Set the LPTIM state */
1834 hlptim->State = HAL_LPTIM_STATE_BUSY;
1835
1836 /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
1837 if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
1838 && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
1839 {
1840 /* Check if clock is prescaled */
1841 assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
1842 /* Set clock prescaler to 0 */
1843 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
1844 }
1845
1846 /* Enable the Peripheral */
1847 __HAL_LPTIM_ENABLE(hlptim);
1848
1849 /* Clear flag */
1850 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1851
1852 /* Enable interrupt */
1853 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
1854
1855 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1856 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1857 {
1858 return HAL_TIMEOUT;
1859 }
1860
1861 /* Start timer in continuous mode */
1862 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1863
1864 /* Change the LPTIM state */
1865 hlptim->State = HAL_LPTIM_STATE_READY;
1866
1867 /* Return function status */
1868 return HAL_OK;
1869 }
1870
1871 /**
1872 * @brief Stop the Counter mode in interrupt mode.
1873 * @param hlptim LPTIM handle
1874 * @retval HAL status
1875 */
HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef * hlptim)1876 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1877 {
1878 /* Check the parameters */
1879 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1880
1881 /* Set the LPTIM state */
1882 hlptim->State = HAL_LPTIM_STATE_BUSY;
1883
1884 /* Disable the Peripheral */
1885 __HAL_LPTIM_DISABLE(hlptim);
1886
1887
1888 /* Enable the Peripheral */
1889 __HAL_LPTIM_ENABLE(hlptim);
1890
1891 /* Clear flag */
1892 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1893
1894 /* Disable interrupt */
1895 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
1896
1897 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1898 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1899 {
1900 return HAL_TIMEOUT;
1901 }
1902
1903 /* Disable the Peripheral */
1904 __HAL_LPTIM_DISABLE(hlptim);
1905
1906 /* Change the LPTIM state */
1907 hlptim->State = HAL_LPTIM_STATE_READY;
1908
1909 /* Return function status */
1910 return HAL_OK;
1911 }
1912
1913 /**
1914 * @brief Starts the LPTIM Input Capture measurement.
1915 * @param hlptim LPTIM Input Capture handle
1916 * @param Channel LPTIM Channels to be enabled
1917 * This parameter can be one of the following values:
1918 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
1919 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
1920 * @retval HAL status
1921 */
HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1922 HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1923 {
1924 /* Check the parameters */
1925 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
1926 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1927
1928 /* Check LPTIM channel state */
1929 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1930 {
1931 return HAL_ERROR;
1932 }
1933
1934 /* Set the LPTIM state */
1935 hlptim->State = HAL_LPTIM_STATE_BUSY;
1936
1937 /* Set the LPTIM channel state */
1938 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1939
1940 /* Enable the Peripheral */
1941 __HAL_LPTIM_ENABLE(hlptim);
1942
1943 /* Start timer in continuous mode */
1944 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1945
1946 /* Enable capture */
1947 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1948
1949 /* Change the LPTIM state */
1950 hlptim->State = HAL_LPTIM_STATE_READY;
1951
1952 /* Return function status */
1953 return HAL_OK;
1954 }
1955
1956 /**
1957 * @brief Stops the LPTIM Input Capture measurement.
1958 * @param hlptim LPTIM Input Capture handle
1959 * @param Channel LPTIM Channels to be disabled
1960 * This parameter can be one of the following values:
1961 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
1962 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
1963 * @retval HAL status
1964 */
HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1965 HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1966 {
1967 /* Check the parameters */
1968 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
1969 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1970
1971 /* Set the LPTIM state */
1972 hlptim->State = HAL_LPTIM_STATE_BUSY;
1973
1974 /* Disable capture */
1975 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1976
1977 /* Disable the Peripheral */
1978 __HAL_LPTIM_DISABLE(hlptim);
1979
1980 /* Set the LPTIM channel state */
1981 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1982
1983 /* Set the LPTIM state */
1984 hlptim->State = HAL_LPTIM_STATE_READY;
1985
1986 /* Return function status */
1987 return HAL_OK;
1988 }
1989
1990 /**
1991 * @brief Starts the LPTIM Input Capture measurement in interrupt mode.
1992 * @param hlptim LPTIM Input Capture handle
1993 * @param Channel LPTIM Channels to be enabled
1994 * This parameter can be one of the following values:
1995 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
1996 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
1997 * @retval HAL status
1998 */
HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1999 HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2000 {
2001 /* Check the parameters */
2002 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
2003 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2004
2005 /* Check LPTIM channel state */
2006 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
2007 {
2008 return HAL_ERROR;
2009 }
2010
2011 /* Set the LPTIM state */
2012 hlptim->State = HAL_LPTIM_STATE_BUSY;
2013
2014 /* Set the LPTIM channel state */
2015 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
2016
2017 /* Enable the Peripheral */
2018 __HAL_LPTIM_ENABLE(hlptim);
2019
2020 switch (Channel)
2021 {
2022 case LPTIM_CHANNEL_1:
2023 /* Enable Capture/Compare 1 interrupt */
2024 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
2025 break;
2026 case LPTIM_CHANNEL_2:
2027 /* Disable Capture/Compare 2 interrupt */
2028 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC2);
2029 break;
2030 default:
2031 break;
2032 }
2033
2034 /* Wait for the completion of the write operation to the LPTIM_DIER register */
2035 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
2036 {
2037 return HAL_TIMEOUT;
2038 }
2039
2040 /* Start timer in continuous mode */
2041 __HAL_LPTIM_START_CONTINUOUS(hlptim);
2042
2043 /* Enable capture */
2044 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
2045
2046 /* Set the LPTIM state */
2047 hlptim->State = HAL_LPTIM_STATE_READY;
2048
2049 /* Return function status */
2050 return HAL_OK;
2051 }
2052
2053 /**
2054 * @brief Stops the LPTIM Input Capture measurement in interrupt mode.
2055 * @param hlptim LPTIM Input Capture handle
2056 * @param Channel LPTIM Channels to be disabled
2057 * This parameter can be one of the following values:
2058 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2059 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2060 * @retval HAL status
2061 */
HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2062 HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2063 {
2064 /* Check the parameters */
2065 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
2066 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2067
2068 /* Set the LPTIM state */
2069 hlptim->State = HAL_LPTIM_STATE_BUSY;
2070
2071 switch (Channel)
2072 {
2073 case LPTIM_CHANNEL_1:
2074 /* Disable Capture/Compare 1 interrupt */
2075 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
2076 break;
2077 case LPTIM_CHANNEL_2:
2078 /* Disable Capture/Compare 2 interrupt */
2079 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC2);
2080 break;
2081 default:
2082 return HAL_ERROR;
2083 break;
2084 }
2085 /* Disable capture */
2086 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
2087
2088 /* Disable the Peripheral */
2089 __HAL_LPTIM_DISABLE(hlptim);
2090
2091 /* Set the LPTIM channel state */
2092 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
2093
2094 /* Set the LPTIM state */
2095 hlptim->State = HAL_LPTIM_STATE_READY;
2096
2097 /* Return function status */
2098 return HAL_OK;
2099 }
2100
2101 /**
2102 * @brief Starts the LPTIM Input Capture measurement in DMA mode.
2103 * @param hlptim LPTIM Input Capture handle
2104 * @param Channel LPTIM Channels to be enabled
2105 * This parameter can be one of the following values:
2106 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2107 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2108 * @param pData The destination Buffer address
2109 * @param Length The length of data to be transferred from LPTIM peripheral to memory
2110 * @retval HAL status
2111 */
HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel,uint32_t * pData,uint32_t Length)2112 HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData,
2113 uint32_t Length)
2114 {
2115 DMA_HandleTypeDef *hdma;
2116
2117 /* Check the parameters */
2118 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
2119 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2120
2121 if ((pData == NULL) || (Length == 0U))
2122 {
2123 return HAL_ERROR;
2124 }
2125
2126 /* Check LPTIM channel state */
2127 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
2128 {
2129 return HAL_ERROR;
2130 }
2131
2132 /* Set the LPTIM state */
2133 hlptim->State = HAL_LPTIM_STATE_BUSY;
2134
2135 /* Set the LPTIM channel state */
2136 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
2137
2138 /* Enable the Peripheral */
2139 __HAL_LPTIM_ENABLE(hlptim);
2140
2141 switch (Channel)
2142 {
2143 case LPTIM_CHANNEL_1:
2144 /* Set the DMA capture callbacks */
2145 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMACaptureCplt;
2146 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
2147
2148 /* Set the DMA error callback */
2149 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
2150
2151 /* Enable the DMA Channel */
2152 hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
2153 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
2154 {
2155 /* Return error status */
2156 return HAL_ERROR;
2157 }
2158
2159 /* Enable Capture/Compare 1 DMA request */
2160 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC1);
2161 break;
2162
2163 case LPTIM_CHANNEL_2:
2164 /* Set the DMA capture callbacks */
2165 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMACaptureCplt;
2166 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
2167
2168 /* Set the DMA error callback */
2169 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
2170
2171 /* Enable the DMA Channel */
2172 hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
2173 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
2174 {
2175 /* Return error status */
2176 return HAL_ERROR;
2177 }
2178
2179 /* Enable Capture/Compare 2 DMA request */
2180 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC2);
2181 break;
2182
2183 default:
2184 break;
2185 }
2186
2187 /* Wait for the completion of the write operation to the LPTIM_DIER register */
2188 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
2189 {
2190 return HAL_TIMEOUT;
2191 }
2192
2193 /* Start timer in continuous mode */
2194 __HAL_LPTIM_START_CONTINUOUS(hlptim);
2195
2196 /* Enable capture */
2197 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
2198
2199 /* Set the LPTIM state */
2200 hlptim->State = HAL_LPTIM_STATE_READY;
2201
2202 /* Return function status */
2203 return HAL_OK;
2204 }
2205
2206 /**
2207 * @brief Stops the LPTIM Input Capture measurement in DMA mode.
2208 * @param hlptim LPTIM Input Capture handle
2209 * @param Channel LPTIM Channels to be disabled
2210 * This parameter can be one of the following values:
2211 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2212 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2213 * @retval HAL status
2214 */
HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2215 HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2216 {
2217 /* Check the parameters */
2218 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
2219 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2220
2221 /* Set the LPTIM state */
2222 hlptim->State = HAL_LPTIM_STATE_BUSY;
2223
2224 switch (Channel)
2225 {
2226 case LPTIM_CHANNEL_1:
2227 /* Disable Capture/Compare 1 DMA request */
2228 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC1);
2229 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
2230 break;
2231
2232 case LPTIM_CHANNEL_2:
2233 /* Disable Capture/Compare 2 DMA request */
2234 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC2);
2235 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
2236 break;
2237 default:
2238 return HAL_ERROR;
2239 break;
2240 }
2241
2242 /* Disable capture */
2243 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
2244
2245 /* Disable the Peripheral */
2246 __HAL_LPTIM_DISABLE(hlptim);
2247
2248 /* Set the LPTIM channel state */
2249 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
2250
2251 /* Set the LPTIM state */
2252 hlptim->State = HAL_LPTIM_STATE_READY;
2253
2254 /* Return function status */
2255 return HAL_OK;
2256 }
2257 /**
2258 * @}
2259 */
2260
2261 /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
2262 * @brief Read operation functions.
2263 *
2264 @verbatim
2265 ==============================================================================
2266 ##### LPTIM Read operation functions #####
2267 ==============================================================================
2268 [..] This section provides LPTIM Reading functions.
2269 (+) Read the counter value.
2270 (+) Read the period (Auto-reload) value.
2271 (+) Read the pulse (Compare)value.
2272 @endverbatim
2273 * @{
2274 */
2275
2276 /**
2277 * @brief Return the current counter value.
2278 * @param hlptim LPTIM handle
2279 * @retval Counter value.
2280 */
HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef * hlptim)2281 uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim)
2282 {
2283 /* Check the parameters */
2284 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
2285
2286 return (hlptim->Instance->CNT);
2287 }
2288
2289 /**
2290 * @brief Return the current Autoreload (Period) value.
2291 * @param hlptim LPTIM handle
2292 * @retval Autoreload value.
2293 */
HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef * hlptim)2294 uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim)
2295 {
2296 /* Check the parameters */
2297 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
2298
2299 return (hlptim->Instance->ARR);
2300 }
2301
2302 /**
2303 * @brief Return the current Compare (Pulse) value.
2304 * @param hlptim LPTIM handle
2305 * @param Channel LPTIM Channel to be selected
2306 * This parameter can be one of the following values:
2307 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2308 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2309 * @retval Compare value.
2310 */
HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2311 uint32_t HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2312 {
2313 uint32_t tmpccr;
2314
2315 /* Check the parameters */
2316 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2317
2318 switch (Channel)
2319 {
2320 case LPTIM_CHANNEL_1:
2321 tmpccr = hlptim->Instance->CCR1;
2322 break;
2323 case LPTIM_CHANNEL_2:
2324 tmpccr = hlptim->Instance->CCR2;
2325 break;
2326 default:
2327 tmpccr = 0;
2328 break;
2329 }
2330 return tmpccr;
2331 }
2332
2333 /**
2334 * @brief LPTimer Input Capture Get Offset(in counter step unit)
2335 * @note The real capture value corresponding to the input capture trigger can be calculated using
2336 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
2337 * The Offset value is depending on the glitch filter value for the channel
2338 * and the value of the prescaler for the kernel clock.
2339 * Please check Errata Sheet V1_8 for more details under "variable latency
2340 * on input capture channel" section.
2341 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
2342 * the configuration information for LPTIM module.
2343 * @param Channel This parameter can be one of the following values:
2344 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2345 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2346 * @retval The offset value
2347 */
HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2348 uint8_t HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2349 {
2350
2351 uint8_t offset ;
2352 uint32_t prescaler;
2353 uint32_t filter ;
2354
2355 /* Get prescaler value */
2356 prescaler = LL_LPTIM_GetPrescaler(hlptim->Instance);
2357
2358 /* Get filter value */
2359 filter = LL_LPTIM_IC_GetFilter(hlptim->Instance, Channel);
2360
2361 /* Get offset value */
2362 offset = LL_LPTIM_IC_GET_OFFSET(prescaler, filter);
2363
2364 /* return offset value */
2365 return offset;
2366 }
2367
2368 /**
2369 * @}
2370 */
2371 /** @defgroup LPTIM_Exported_Functions_Group5 LPTIM Config function
2372 * @brief Config channel
2373 *
2374 @verbatim
2375 ==============================================================================
2376 ##### LPTIM Config function #####
2377 ==============================================================================
2378 [..] This section provides LPTIM Config function.
2379 (+) Configure channel: Output Compare mode, Period, Polarity.
2380 @endverbatim
2381 * @{
2382 */
2383
2384 /**
2385 * @brief
2386 * @param hlptim LPTIM handle
2387 * @param sConfig The output configuration structure
2388 * @param Channel LPTIM Channel to be configured
2389 * This parameter can be one of the following values:
2390 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2391 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2392 * @note Successive calls to HAL_LPTIM_OC_ConfigChannel can only be performed
2393 * after a delay that must be greater or equal than the value of
2394 * (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal
2395 * division factor (1, 2, 4, ..., 128). Any successive call violating
2396 * this delay, leads to unpredictable results.
2397 * @retval HAL status
2398 */
HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig,uint32_t Channel)2399 HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig,
2400 uint32_t Channel)
2401 {
2402 HAL_StatusTypeDef status;
2403 /* Check the parameters */
2404 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2405 assert_param(IS_LPTIM_OC_POLARITY(sConfig->OCPolarity));
2406 assert_param(IS_LPTIM_PULSE(sConfig->Pulse));
2407
2408 hlptim->State = HAL_LPTIM_STATE_BUSY;
2409
2410 switch (Channel)
2411 {
2412 case LPTIM_CHANNEL_1:
2413 {
2414 /* Check the parameters */
2415 assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
2416
2417 /* Configure the LPTIM Channel 1 in Output Compare */
2418 status = LPTIM_OC1_SetConfig(hlptim, sConfig);
2419 if (status != HAL_OK)
2420 {
2421 return status;
2422 }
2423 break;
2424 }
2425 case LPTIM_CHANNEL_2:
2426 {
2427 /* Check the parameters */
2428 assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
2429
2430 /* Configure the LPTIM Channel 2 in Output Compare */
2431 status = LPTIM_OC2_SetConfig(hlptim, sConfig);
2432 if (status != HAL_OK)
2433 {
2434 return status;
2435 }
2436 break;
2437 }
2438 default:
2439 break;
2440 }
2441
2442 /* Change the LPTIM state */
2443 hlptim->State = HAL_LPTIM_STATE_READY;
2444
2445 /* Return function status */
2446 return HAL_OK;
2447 }
2448
2449 /**
2450 * @brief
2451 * @param hlptim LPTIM handle
2452 * @param sConfig The input configuration structure
2453 * @param Channel LPTIM Channel to be configured
2454 * This parameter can be one of the following values:
2455 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2456 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2457 * @note Successive calls to HAL_LPTIM_IC_ConfigChannel can only be performed
2458 * after a delay that must be greater or equal than the value of
2459 * (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal
2460 * division factor (1, 2, 4, ..., 128). Any successive call violating
2461 * this delay, leads to unpredictable results.
2462 * @retval HAL status
2463 */
HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig,uint32_t Channel)2464 HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig,
2465 uint32_t Channel)
2466 {
2467 /* Check the parameters */
2468 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2469 assert_param(IS_LPTIM_IC_PRESCALER(sConfig->ICPrescaler));
2470 assert_param(IS_LPTIM_IC_POLARITY(sConfig->ICPolarity));
2471 assert_param(IS_LPTIM_IC_FILTER(sConfig->ICFilter));
2472
2473 hlptim->State = HAL_LPTIM_STATE_BUSY;
2474
2475 switch (Channel)
2476 {
2477 case LPTIM_CHANNEL_1:
2478 {
2479 /* Check the parameters */
2480 assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
2481 assert_param(IS_LPTIM_IC1_SOURCE(hlptim->Instance, sConfig->ICInputSource));
2482
2483 /* Configure the LPTIM Channel 1 in Input Capture */
2484 LPTIM_IC1_SetConfig(hlptim, sConfig);
2485 break;
2486 }
2487 case LPTIM_CHANNEL_2:
2488 {
2489 /* Check the parameters */
2490 assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
2491 assert_param(IS_LPTIM_IC2_SOURCE(hlptim->Instance, sConfig->ICInputSource));
2492
2493 /* Configure the LPTIM Channel 2 in Input Capture */
2494 LPTIM_IC2_SetConfig(hlptim, sConfig);
2495 break;
2496 }
2497 default:
2498 break;
2499 }
2500
2501 /* Change the LPTIM state */
2502 hlptim->State = HAL_LPTIM_STATE_READY;
2503 /* Return function status */
2504 return HAL_OK;
2505 }
2506 /**
2507 * @}
2508 */
2509
2510 /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
2511 * @brief LPTIM IRQ handler.
2512 *
2513 @verbatim
2514 ==============================================================================
2515 ##### LPTIM IRQ handler and callbacks #####
2516 ==============================================================================
2517 [..] This section provides LPTIM IRQ handler and callback functions called within
2518 the IRQ handler:
2519 (+) LPTIM interrupt request handler
2520 (+) Compare match Callback
2521 (+) Auto-reload match Callback
2522 (+) External trigger event detection Callback
2523 (+) Compare register write complete Callback
2524 (+) Auto-reload register write complete Callback
2525 (+) Up-counting direction change Callback
2526 (+) Down-counting direction change Callback
2527
2528 @endverbatim
2529 * @{
2530 */
2531
2532 /**
2533 * @brief Handle LPTIM interrupt request.
2534 * @param hlptim LPTIM handle
2535 * @retval None
2536 */
HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef * hlptim)2537 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
2538 {
2539 /* Capture Compare 1 interrupt */
2540 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1) != RESET)
2541 {
2542 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1) != RESET)
2543 {
2544 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1);
2545 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
2546
2547 /* Input capture event */
2548 if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC1SEL) != 0x00U)
2549 {
2550 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2551 hlptim->IC_CaptureCallback(hlptim);
2552 #else
2553 HAL_LPTIM_IC_CaptureCallback(hlptim);
2554 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2555 }
2556 /* Output compare event */
2557 else
2558 {
2559 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2560 hlptim->CompareMatchCallback(hlptim);
2561 #else
2562 HAL_LPTIM_CompareMatchCallback(hlptim);
2563 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2564 }
2565 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2566 }
2567 }
2568
2569 /* Capture Compare 2 interrupt */
2570 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2) != RESET)
2571 {
2572 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2) != RESET)
2573 {
2574 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2);
2575 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
2576
2577 /* Input capture event */
2578 if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC2SEL) != 0x00U)
2579 {
2580 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2581 hlptim->IC_CaptureCallback(hlptim);
2582 #else
2583 HAL_LPTIM_IC_CaptureCallback(hlptim);
2584 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2585 }
2586 /* Output compare event */
2587 else
2588 {
2589 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2590 hlptim->CompareMatchCallback(hlptim);
2591 #else
2592 HAL_LPTIM_CompareMatchCallback(hlptim);
2593 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2594 }
2595 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2596 }
2597 }
2598
2599 /* Over Capture 1 interrupt */
2600 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1O) != RESET)
2601 {
2602 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1O) != RESET)
2603 {
2604 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1O);
2605 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
2606
2607 /* Over capture event */
2608 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2609 hlptim->IC_OverCaptureCallback(hlptim);
2610 #else
2611 HAL_LPTIM_IC_OverCaptureCallback(hlptim);
2612 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2613 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2614 }
2615 }
2616
2617 /* Over Capture 2 interrupt */
2618 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2O) != RESET)
2619 {
2620 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2O) != RESET)
2621 {
2622 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2O);
2623 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
2624
2625 /* Over capture event */
2626 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2627 hlptim->IC_OverCaptureCallback(hlptim);
2628 #else
2629 HAL_LPTIM_IC_OverCaptureCallback(hlptim);
2630 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2631 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2632 }
2633 }
2634
2635 /* Autoreload match interrupt */
2636 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
2637 {
2638 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
2639 {
2640 /* Clear Autoreload match flag */
2641 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
2642
2643 /* Autoreload match Callback */
2644 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2645 hlptim->AutoReloadMatchCallback(hlptim);
2646 #else
2647 HAL_LPTIM_AutoReloadMatchCallback(hlptim);
2648 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2649 }
2650 }
2651
2652 /* Trigger detected interrupt */
2653 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
2654 {
2655 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
2656 {
2657 /* Clear Trigger detected flag */
2658 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
2659
2660 /* Trigger detected callback */
2661 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2662 hlptim->TriggerCallback(hlptim);
2663 #else
2664 HAL_LPTIM_TriggerCallback(hlptim);
2665 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2666 }
2667 }
2668
2669 /* Compare write interrupt */
2670 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP1OK) != RESET)
2671 {
2672 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP1OK) != RESET)
2673 {
2674 /* Clear Compare write flag */
2675 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
2676 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
2677 /* Compare write Callback */
2678 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2679 hlptim->CompareWriteCallback(hlptim);
2680 #else
2681 HAL_LPTIM_CompareWriteCallback(hlptim);
2682 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2683 }
2684 }
2685
2686 /* Compare write interrupt */
2687 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP2OK) != RESET)
2688 {
2689 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP2OK) != RESET)
2690 {
2691 /* Clear Compare write flag */
2692 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
2693 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
2694 /* Compare write Callback */
2695 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2696 hlptim->CompareWriteCallback(hlptim);
2697 #else
2698 HAL_LPTIM_CompareWriteCallback(hlptim);
2699 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2700 }
2701 }
2702
2703 /* Autoreload write interrupt */
2704 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
2705 {
2706 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
2707 {
2708 /* Clear Autoreload write flag */
2709 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
2710
2711 /* Autoreload write Callback */
2712 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2713 hlptim->AutoReloadWriteCallback(hlptim);
2714 #else
2715 HAL_LPTIM_AutoReloadWriteCallback(hlptim);
2716 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2717 }
2718 }
2719
2720 /* Direction counter changed from Down to Up interrupt */
2721 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
2722 {
2723 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
2724 {
2725 /* Clear Direction counter changed from Down to Up flag */
2726 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
2727
2728 /* Direction counter changed from Down to Up Callback */
2729 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2730 hlptim->DirectionUpCallback(hlptim);
2731 #else
2732 HAL_LPTIM_DirectionUpCallback(hlptim);
2733 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2734 }
2735 }
2736
2737 /* Direction counter changed from Up to Down interrupt */
2738 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
2739 {
2740 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
2741 {
2742 /* Clear Direction counter changed from Up to Down flag */
2743 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
2744
2745 /* Direction counter changed from Up to Down Callback */
2746 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2747 hlptim->DirectionDownCallback(hlptim);
2748 #else
2749 HAL_LPTIM_DirectionDownCallback(hlptim);
2750 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2751 }
2752 }
2753
2754 /* Repetition counter underflowed (or contains zero) and the LPTIM counter
2755 overflowed */
2756 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UPDATE) != RESET)
2757 {
2758 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UPDATE) != RESET)
2759 {
2760 /* Clear update event flag */
2761 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UPDATE);
2762
2763 /* Update event Callback */
2764 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2765 hlptim->UpdateEventCallback(hlptim);
2766 #else
2767 HAL_LPTIM_UpdateEventCallback(hlptim);
2768 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2769 }
2770 }
2771
2772 /* Successful APB bus write to repetition counter register */
2773 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPOK) != RESET)
2774 {
2775 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPOK) != RESET)
2776 {
2777 /* Clear successful APB bus write to repetition counter flag */
2778 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
2779
2780 /* Successful APB bus write to repetition counter Callback */
2781 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2782 hlptim->RepCounterWriteCallback(hlptim);
2783 #else
2784 HAL_LPTIM_RepCounterWriteCallback(hlptim);
2785 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2786 }
2787 }
2788 }
2789
2790 /**
2791 * @brief Compare match callback in non-blocking mode.
2792 * @param hlptim LPTIM handle
2793 * @retval None
2794 */
HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef * hlptim)2795 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
2796 {
2797 /* Prevent unused argument(s) compilation warning */
2798 UNUSED(hlptim);
2799
2800 /* NOTE : This function should not be modified, when the callback is needed,
2801 the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
2802 */
2803 }
2804
2805 /**
2806 * @brief Autoreload match callback in non-blocking mode.
2807 * @param hlptim LPTIM handle
2808 * @retval None
2809 */
HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef * hlptim)2810 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
2811 {
2812 /* Prevent unused argument(s) compilation warning */
2813 UNUSED(hlptim);
2814
2815 /* NOTE : This function should not be modified, when the callback is needed,
2816 the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
2817 */
2818 }
2819
2820 /**
2821 * @brief Trigger detected callback in non-blocking mode.
2822 * @param hlptim LPTIM handle
2823 * @retval None
2824 */
HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef * hlptim)2825 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
2826 {
2827 /* Prevent unused argument(s) compilation warning */
2828 UNUSED(hlptim);
2829
2830 /* NOTE : This function should not be modified, when the callback is needed,
2831 the HAL_LPTIM_TriggerCallback could be implemented in the user file
2832 */
2833 }
2834
2835 /**
2836 * @brief Compare write callback in non-blocking mode.
2837 * @param hlptim LPTIM handle
2838 * @retval None
2839 */
HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef * hlptim)2840 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
2841 {
2842 /* Prevent unused argument(s) compilation warning */
2843 UNUSED(hlptim);
2844
2845 /* NOTE : This function should not be modified, when the callback is needed,
2846 the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
2847 */
2848 }
2849
2850 /**
2851 * @brief Autoreload write callback in non-blocking mode.
2852 * @param hlptim LPTIM handle
2853 * @retval None
2854 */
HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef * hlptim)2855 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
2856 {
2857 /* Prevent unused argument(s) compilation warning */
2858 UNUSED(hlptim);
2859
2860 /* NOTE : This function should not be modified, when the callback is needed,
2861 the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
2862 */
2863 }
2864
2865 /**
2866 * @brief Direction counter changed from Down to Up callback in non-blocking mode.
2867 * @param hlptim LPTIM handle
2868 * @retval None
2869 */
HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef * hlptim)2870 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
2871 {
2872 /* Prevent unused argument(s) compilation warning */
2873 UNUSED(hlptim);
2874
2875 /* NOTE : This function should not be modified, when the callback is needed,
2876 the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
2877 */
2878 }
2879
2880 /**
2881 * @brief Direction counter changed from Up to Down callback in non-blocking mode.
2882 * @param hlptim LPTIM handle
2883 * @retval None
2884 */
HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef * hlptim)2885 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
2886 {
2887 /* Prevent unused argument(s) compilation warning */
2888 UNUSED(hlptim);
2889
2890 /* NOTE : This function should not be modified, when the callback is needed,
2891 the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
2892 */
2893 }
2894
2895 /**
2896 * @brief Repetition counter underflowed (or contains zero) and LPTIM counter overflowed callback in non-blocking mode.
2897 * @param hlptim LPTIM handle
2898 * @retval None
2899 */
HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef * hlptim)2900 __weak void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim)
2901 {
2902 /* Prevent unused argument(s) compilation warning */
2903 UNUSED(hlptim);
2904
2905 /* NOTE : This function should not be modified, when the callback is needed,
2906 the HAL_LPTIM_UpdateEventCallback could be implemented in the user file
2907 */
2908 }
2909
2910 /**
2911 * @brief Successful APB bus write to repetition counter register callback in non-blocking mode.
2912 * @param hlptim LPTIM handle
2913 * @retval None
2914 */
HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef * hlptim)2915 __weak void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim)
2916 {
2917 /* Prevent unused argument(s) compilation warning */
2918 UNUSED(hlptim);
2919
2920 /* NOTE : This function should not be modified, when the callback is needed,
2921 the HAL_LPTIM_RepCounterWriteCallback could be implemented in the user file
2922 */
2923 }
2924
2925 /**
2926 * @brief Input Capture callback in non-blocking mode
2927 * @param hlptim LPTIM handle
2928 * @retval None
2929 */
HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef * hlptim)2930 __weak void HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef *hlptim)
2931 {
2932 /* Prevent unused argument(s) compilation warning */
2933 UNUSED(hlptim);
2934
2935 /* NOTE : This function should not be modified, when the callback is needed,
2936 the HAL_LPTIM_IC_CaptureCallback could be implemented in the user file
2937 */
2938 }
2939
2940 /**
2941 * @brief Over Capture callback in non-blocking mode
2942 * @param hlptim LPTIM handle
2943 * @retval None
2944 */
HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef * hlptim)2945 __weak void HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef *hlptim)
2946 {
2947 /* Prevent unused argument(s) compilation warning */
2948 UNUSED(hlptim);
2949
2950 /* NOTE : This function should not be modified, when the callback is needed,
2951 the HAL_LPTIM_IC_OverCaptureCallback could be implemented in the user file
2952 */
2953 }
2954
2955 /**
2956 * @brief Input Capture half complete callback in non-blocking mode
2957 * @param hlptim LPTIM IC handle
2958 * @retval None
2959 */
HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef * hlptim)2960 __weak void HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
2961 {
2962 /* Prevent unused argument(s) compilation warning */
2963 UNUSED(hlptim);
2964
2965 /* NOTE : This function should not be modified, when the callback is needed,
2966 the HAL_LPTIM_IC_CaptureHalfCpltCallback could be implemented in the user file
2967 */
2968 }
2969
2970 /**
2971 * @brief Update event half complete callback in non-blocking mode
2972 * @param hlptim LPTIM handle
2973 * @retval None
2974 */
HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef * hlptim)2975 __weak void HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
2976 {
2977 /* Prevent unused argument(s) compilation warning */
2978 UNUSED(hlptim);
2979
2980 /* NOTE : This function should not be modified, when the callback is needed,
2981 the HAL_LPTIM_UpdateEventHalfCpltCallback could be implemented in the user file
2982 */
2983 }
2984
2985 /**
2986 * @brief Error callback in non-blocking mode
2987 * @param hlptim LPTIM handle
2988 * @retval None
2989 */
HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef * hlptim)2990 __weak void HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef *hlptim)
2991 {
2992 /* Prevent unused argument(s) compilation warning */
2993 UNUSED(hlptim);
2994
2995 /* NOTE : This function should not be modified, when the callback is needed,
2996 the HAL_LPTIM_ErrorCallback could be implemented in the user file
2997 */
2998 }
2999
3000
3001 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3002 /**
3003 * @brief Register a User LPTIM callback to be used instead of the weak predefined callback
3004 * @param hlptim LPTIM handle
3005 * @param CallbackID ID of the callback to be registered
3006 * This parameter can be one of the following values:
3007 * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
3008 * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
3009 * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
3010 * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
3011 * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
3012 * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
3013 * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
3014 * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
3015 * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
3016 * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID
3017 * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
3018 * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID
3019 * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID
3020 * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID
3021 * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
3022 * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID
3023 * @param pCallback pointer to the callback function
3024 * @retval status
3025 */
HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef * hlptim,HAL_LPTIM_CallbackIDTypeDef CallbackID,pLPTIM_CallbackTypeDef pCallback)3026 HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim,
3027 HAL_LPTIM_CallbackIDTypeDef CallbackID,
3028 pLPTIM_CallbackTypeDef pCallback)
3029 {
3030 HAL_StatusTypeDef status = HAL_OK;
3031
3032 if (pCallback == NULL)
3033 {
3034 return HAL_ERROR;
3035 }
3036
3037 if (hlptim->State == HAL_LPTIM_STATE_READY)
3038 {
3039 switch (CallbackID)
3040 {
3041 case HAL_LPTIM_MSPINIT_CB_ID :
3042 hlptim->MspInitCallback = pCallback;
3043 break;
3044
3045 case HAL_LPTIM_MSPDEINIT_CB_ID :
3046 hlptim->MspDeInitCallback = pCallback;
3047 break;
3048
3049 case HAL_LPTIM_COMPARE_MATCH_CB_ID :
3050 hlptim->CompareMatchCallback = pCallback;
3051 break;
3052
3053 case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
3054 hlptim->AutoReloadMatchCallback = pCallback;
3055 break;
3056
3057 case HAL_LPTIM_TRIGGER_CB_ID :
3058 hlptim->TriggerCallback = pCallback;
3059 break;
3060
3061 case HAL_LPTIM_COMPARE_WRITE_CB_ID :
3062 hlptim->CompareWriteCallback = pCallback;
3063 break;
3064
3065 case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
3066 hlptim->AutoReloadWriteCallback = pCallback;
3067 break;
3068
3069 case HAL_LPTIM_DIRECTION_UP_CB_ID :
3070 hlptim->DirectionUpCallback = pCallback;
3071 break;
3072
3073 case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
3074 hlptim->DirectionDownCallback = pCallback;
3075 break;
3076
3077 case HAL_LPTIM_UPDATE_EVENT_CB_ID :
3078 hlptim->UpdateEventCallback = pCallback;
3079 break;
3080
3081 case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
3082 hlptim->RepCounterWriteCallback = pCallback;
3083 break;
3084
3085 case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
3086 hlptim->UpdateEventHalfCpltCallback = pCallback;
3087 break;
3088
3089 case HAL_LPTIM_ERROR_CB_ID :
3090 hlptim->ErrorCallback = pCallback;
3091 break;
3092
3093 case HAL_LPTIM_IC_CAPTURE_CB_ID :
3094 hlptim->IC_CaptureCallback = pCallback;
3095 break;
3096
3097 case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
3098 hlptim->IC_CaptureHalfCpltCallback = pCallback;
3099 break;
3100
3101 case HAL_LPTIM_OVER_CAPTURE_CB_ID :
3102 hlptim->IC_OverCaptureCallback = pCallback;
3103 break;
3104
3105 default :
3106 /* Return error status */
3107 status = HAL_ERROR;
3108 break;
3109 }
3110 }
3111 else if (hlptim->State == HAL_LPTIM_STATE_RESET)
3112 {
3113 switch (CallbackID)
3114 {
3115 case HAL_LPTIM_MSPINIT_CB_ID :
3116 hlptim->MspInitCallback = pCallback;
3117 break;
3118
3119 case HAL_LPTIM_MSPDEINIT_CB_ID :
3120 hlptim->MspDeInitCallback = pCallback;
3121 break;
3122
3123 default :
3124 /* Return error status */
3125 status = HAL_ERROR;
3126 break;
3127 }
3128 }
3129 else
3130 {
3131 /* Return error status */
3132 status = HAL_ERROR;
3133 }
3134
3135 return status;
3136 }
3137
3138 /**
3139 * @brief Unregister a LPTIM callback
3140 * LLPTIM callback is redirected to the weak predefined callback
3141 * @param hlptim LPTIM handle
3142 * @param CallbackID ID of the callback to be unregistered
3143 * This parameter can be one of the following values:
3144 * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
3145 * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
3146 * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
3147 * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
3148 * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
3149 * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
3150 * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
3151 * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
3152 * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
3153 * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID
3154 * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
3155 * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID
3156 * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID
3157 * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID
3158 * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
3159 * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID
3160 * @retval status
3161 */
HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef * hlptim,HAL_LPTIM_CallbackIDTypeDef CallbackID)3162 HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim,
3163 HAL_LPTIM_CallbackIDTypeDef CallbackID)
3164 {
3165 HAL_StatusTypeDef status = HAL_OK;
3166
3167 if (hlptim->State == HAL_LPTIM_STATE_READY)
3168 {
3169 switch (CallbackID)
3170 {
3171 case HAL_LPTIM_MSPINIT_CB_ID :
3172 /* Legacy weak MspInit Callback */
3173 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
3174 break;
3175
3176 case HAL_LPTIM_MSPDEINIT_CB_ID :
3177 /* Legacy weak Msp DeInit Callback */
3178 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
3179 break;
3180
3181 case HAL_LPTIM_COMPARE_MATCH_CB_ID :
3182 /* Legacy weak Compare match Callback */
3183 hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
3184 break;
3185
3186 case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
3187 /* Legacy weak Auto-reload match Callback */
3188 hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
3189 break;
3190
3191 case HAL_LPTIM_TRIGGER_CB_ID :
3192 /* Legacy weak External trigger event detection Callback */
3193 hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
3194 break;
3195
3196 case HAL_LPTIM_COMPARE_WRITE_CB_ID :
3197 /* Legacy weak Compare register write complete Callback */
3198 hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
3199 break;
3200
3201 case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
3202 /* Legacy weak Auto-reload register write complete Callback */
3203 hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
3204 break;
3205
3206 case HAL_LPTIM_DIRECTION_UP_CB_ID :
3207 /* Legacy weak Up-counting direction change Callback */
3208 hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
3209 break;
3210
3211 case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
3212 /* Legacy weak Down-counting direction change Callback */
3213 hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
3214 break;
3215
3216 case HAL_LPTIM_UPDATE_EVENT_CB_ID :
3217 /* Legacy weak Update event detection Callback */
3218 hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
3219 break;
3220
3221 case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
3222 /* Legacy weak Repetition counter register write complete Callback */
3223 hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
3224 break;
3225
3226 case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
3227 /* Legacy weak Update event half complete detection Callback */
3228 hlptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
3229 break;
3230
3231 case HAL_LPTIM_ERROR_CB_ID :
3232 /* Legacy weak error Callback */
3233 hlptim->ErrorCallback = HAL_LPTIM_ErrorCallback;
3234 break;
3235
3236 case HAL_LPTIM_IC_CAPTURE_CB_ID :
3237 /* Legacy weak IC Capture Callback */
3238 hlptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback;
3239 break;
3240
3241 case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
3242 /* Legacy weak IC Capture half complete Callback */
3243 hlptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
3244 break;
3245
3246 case HAL_LPTIM_OVER_CAPTURE_CB_ID :
3247 /* Legacy weak IC over capture Callback */
3248 hlptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback;
3249 break;
3250
3251 default :
3252 /* Return error status */
3253 status = HAL_ERROR;
3254 break;
3255 }
3256 }
3257 else if (hlptim->State == HAL_LPTIM_STATE_RESET)
3258 {
3259 switch (CallbackID)
3260 {
3261 case HAL_LPTIM_MSPINIT_CB_ID :
3262 /* Legacy weak MspInit Callback */
3263 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
3264 break;
3265
3266 case HAL_LPTIM_MSPDEINIT_CB_ID :
3267 /* Legacy weak Msp DeInit Callback */
3268 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
3269 break;
3270
3271 default :
3272 /* Return error status */
3273 status = HAL_ERROR;
3274 break;
3275 }
3276 }
3277 else
3278 {
3279 /* Return error status */
3280 status = HAL_ERROR;
3281 }
3282
3283 return status;
3284 }
3285 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3286
3287 /**
3288 * @}
3289 */
3290
3291 /** @defgroup LPTIM_Group5 Peripheral State functions
3292 * @brief Peripheral State functions.
3293 *
3294 @verbatim
3295 ==============================================================================
3296 ##### Peripheral State functions #####
3297 ==============================================================================
3298 [..]
3299 This subsection permits to get in run-time the status of the peripheral.
3300
3301 @endverbatim
3302 * @{
3303 */
3304
3305 /**
3306 * @brief Return the LPTIM handle state.
3307 * @param hlptim LPTIM handle
3308 * @retval HAL state
3309 */
HAL_LPTIM_GetState(const LPTIM_HandleTypeDef * hlptim)3310 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim)
3311 {
3312 /* Return LPTIM handle state */
3313 return hlptim->State;
3314 }
3315
3316 /**
3317 * @}
3318 */
3319
3320
3321 /**
3322 * @}
3323 */
3324
3325 /* Private functions ---------------------------------------------------------*/
3326
3327 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
3328 * @{
3329 */
3330 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3331 /**
3332 * @brief Reset interrupt callbacks to the legacy weak callbacks.
3333 * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains
3334 * the configuration information for LPTIM module.
3335 * @retval None
3336 */
LPTIM_ResetCallback(LPTIM_HandleTypeDef * lptim)3337 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
3338 {
3339 /* Reset the LPTIM callback to the legacy weak callbacks */
3340 lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
3341 lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
3342 lptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
3343 lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
3344 lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
3345 lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
3346 lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
3347 lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
3348 lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
3349 lptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
3350 lptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback;
3351 lptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
3352 lptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback;
3353 lptim->ErrorCallback = HAL_LPTIM_ErrorCallback;
3354 }
3355 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3356
3357 /**
3358 * @brief LPTimer Wait for flag set
3359 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3360 * the configuration information for LPTIM module.
3361 * @param flag The lptim flag
3362 * @retval HAL status
3363 */
LPTIM_WaitForFlag(const LPTIM_HandleTypeDef * hlptim,uint32_t flag)3364 static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag)
3365 {
3366 HAL_StatusTypeDef result = HAL_OK;
3367 uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
3368 do
3369 {
3370 count--;
3371 if (count == 0UL)
3372 {
3373 result = HAL_TIMEOUT;
3374 }
3375 } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
3376
3377 return result;
3378 }
3379
3380 /**
3381 * @brief LPTIM DMA error callback
3382 * @param hdma pointer to DMA handle.
3383 * @retval None
3384 */
LPTIM_DMAError(DMA_HandleTypeDef * hdma)3385 void LPTIM_DMAError(DMA_HandleTypeDef *hdma)
3386 {
3387 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3388
3389 hlptim->State = HAL_LPTIM_STATE_READY;
3390
3391 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3392 hlptim->ErrorCallback(hlptim);
3393 #else
3394 HAL_LPTIM_ErrorCallback(hlptim);
3395 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3396 }
3397
3398 /**
3399 * @brief LPTIM DMA Capture complete callback.
3400 * @param hdma pointer to DMA handle.
3401 * @retval None
3402 */
LPTIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)3403 void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
3404 {
3405 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3406
3407 hlptim->State = HAL_LPTIM_STATE_READY;
3408
3409 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3410 {
3411 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3412 }
3413 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3414 {
3415 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3416 }
3417 else
3418 {
3419 /* nothing to do */
3420 }
3421
3422 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3423 hlptim->IC_CaptureCallback(hlptim);
3424 #else
3425 HAL_LPTIM_IC_CaptureCallback(hlptim);
3426 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3427
3428 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3429 }
3430
3431 /**
3432 * @brief LPTIM DMA Capture half complete callback.
3433 * @param hdma pointer to DMA handle.
3434 * @retval None
3435 */
LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)3436 void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
3437 {
3438 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3439
3440 hlptim->State = HAL_LPTIM_STATE_READY;
3441
3442 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3443 {
3444 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3445 }
3446 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3447 {
3448 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3449 }
3450 else
3451 {
3452 /* nothing to do */
3453 }
3454
3455 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3456 hlptim->IC_CaptureHalfCpltCallback(hlptim);
3457 #else
3458 HAL_LPTIM_IC_CaptureHalfCpltCallback(hlptim);
3459 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3460
3461 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3462 }
3463
3464 /**
3465 * @brief LPTIM DMA Update event complete callback.
3466 * @param hdma pointer to DMA handle.
3467 * @retval None
3468 */
LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef * hdma)3469 void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma)
3470 {
3471 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3472
3473 hlptim->State = HAL_LPTIM_STATE_READY;
3474
3475 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3476 {
3477 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3478 }
3479 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3480 {
3481 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3482 }
3483 else
3484 {
3485 /* nothing to do */
3486 }
3487
3488 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3489 hlptim->UpdateEventCallback(hlptim);
3490 #else
3491 HAL_LPTIM_UpdateEventCallback(hlptim);
3492 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3493
3494 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3495 }
3496
3497 /**
3498 * @brief LPTIM DMA Capture half complete callback.
3499 * @param hdma pointer to DMA handle.
3500 * @retval None
3501 */
LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef * hdma)3502 void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma)
3503 {
3504 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3505
3506 hlptim->State = HAL_LPTIM_STATE_READY;
3507
3508 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3509 {
3510 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3511 }
3512 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3513 {
3514 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3515 }
3516 else
3517 {
3518 /* nothing to do */
3519 }
3520
3521 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3522 hlptim->UpdateEventHalfCpltCallback(hlptim);
3523 #else
3524 HAL_LPTIM_UpdateEventHalfCpltCallback(hlptim);
3525 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3526
3527 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3528 }
3529 /**
3530 * @brief LPTimer Output Compare 1 configuration
3531 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3532 * the configuration information for LPTIM module.
3533 * @param sConfig The output configuration structure
3534 * @retval None
3535 */
LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig)3536 static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig)
3537 {
3538 uint32_t tmpccmr1;
3539
3540 tmpccmr1 = hlptim->Instance->CCMR1;
3541 tmpccmr1 &= ~(LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_CC1SEL_Msk);
3542
3543 tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC1P_Pos;
3544
3545 /* Enable the Peripheral */
3546 __HAL_LPTIM_ENABLE(hlptim);
3547
3548 /* Clear flag */
3549 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
3550
3551 /* Write to CCR1 register */
3552 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, sConfig->Pulse);
3553
3554 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
3555 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
3556 {
3557 return HAL_TIMEOUT;
3558 }
3559
3560 /* Disable the Peripheral */
3561 __HAL_LPTIM_DISABLE(hlptim);
3562
3563 /* Write to CCMR1 register */
3564 hlptim->Instance->CCMR1 = tmpccmr1;
3565
3566 return HAL_OK;
3567 }
3568
3569 /**
3570 * @brief LPTimer Output Compare 2 configuration
3571 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3572 * the configuration information for LPTIM module.
3573 * @param sConfig The output configuration structure
3574 * @retval None
3575 */
LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig)3576 static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig)
3577 {
3578 uint32_t tmpccmr1;
3579
3580 tmpccmr1 = hlptim->Instance->CCMR1;
3581 tmpccmr1 &= ~(LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_CC2SEL_Msk);
3582 tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC2P_Pos;
3583
3584 /* Enable the Peripheral */
3585 __HAL_LPTIM_ENABLE(hlptim);
3586
3587 /* Clear flag */
3588 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
3589
3590 /* Write to CCR2 register */
3591 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, sConfig->Pulse);
3592
3593 /* Wait for the completion of the write operation to the LPTIM_CCR2 register */
3594 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) != HAL_OK)
3595 {
3596 return HAL_TIMEOUT;
3597 }
3598
3599 /* Disable the Peripheral */
3600 __HAL_LPTIM_DISABLE(hlptim);
3601
3602 /* Write to CCMR1 register */
3603 hlptim->Instance->CCMR1 = tmpccmr1;
3604
3605 return HAL_OK;
3606 }
3607
3608 /**
3609 * @brief LPTimer Input Capture 1 configuration
3610 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3611 * the configuration information for LPTIM module.
3612 * @param sConfig The input configuration structure
3613 * @retval None
3614 */
LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig)3615 static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig)
3616 {
3617 uint32_t tmpccmr1;
3618 uint32_t tmpcfgr2;
3619
3620 tmpccmr1 = hlptim->Instance->CCMR1;
3621 tmpccmr1 &= ~(LPTIM_CCMR1_IC1PSC_Msk | LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_IC1F_Msk);
3622 tmpccmr1 |= sConfig->ICPrescaler |
3623 sConfig->ICPolarity |
3624 sConfig->ICFilter |
3625 LPTIM_CCMR1_CC1SEL;
3626
3627 tmpcfgr2 = hlptim->Instance->CFGR2;
3628 tmpcfgr2 &= ~(LPTIM_CFGR2_IC1SEL_Msk);
3629 tmpcfgr2 |= sConfig->ICInputSource;
3630
3631 /* Write to CCMR1 register */
3632 hlptim->Instance->CCMR1 = tmpccmr1;
3633
3634 /* Write to CFGR2 register */
3635 hlptim->Instance->CFGR2 = tmpcfgr2;
3636 }
3637
3638 /**
3639 * @brief LPTimer Input Capture 2 configuration
3640 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3641 * the configuration information for LPTIM module.
3642 * @param sConfig The input configuration structure
3643 * @retval None
3644 */
LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig)3645 static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig)
3646 {
3647 uint32_t tmpccmr1;
3648 uint32_t tmpcfgr2;
3649
3650 tmpccmr1 = hlptim->Instance->CCMR1;
3651 tmpccmr1 &= ~(LPTIM_CCMR1_IC2PSC_Msk | LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_IC2F_Msk);
3652 tmpccmr1 |= (sConfig->ICPrescaler << (LPTIM_CCMR1_IC2PSC_Pos - LPTIM_CCMR1_IC1PSC_Pos)) |
3653 (sConfig->ICPolarity << (LPTIM_CCMR1_CC2P_Pos - LPTIM_CCMR1_CC1P_Pos)) |
3654 (sConfig->ICFilter << (LPTIM_CCMR1_IC2F_Pos - LPTIM_CCMR1_IC1F_Pos)) |
3655 LPTIM_CCMR1_CC2SEL;
3656
3657 tmpcfgr2 = hlptim->Instance->CFGR2;
3658 tmpcfgr2 &= ~(LPTIM_CFGR2_IC2SEL_Msk);
3659 tmpcfgr2 |= sConfig->ICInputSource;
3660
3661 /* Write to CCMR1 register */
3662 hlptim->Instance->CCMR1 = tmpccmr1;
3663
3664 /* Write to CFGR2 register */
3665 hlptim->Instance->CFGR2 = tmpcfgr2;
3666 }
3667
3668 /**
3669 * @brief Start the DMA data transfer.
3670 * @param hdma DMA handle
3671 * @param src The source memory Buffer address.
3672 * @param dst The destination memory Buffer address.
3673 * @param length The size of a source block transfer in byte.
3674 * @retval HAL status
3675 */
LPTIM_DMA_Start_IT(DMA_HandleTypeDef * hdma,uint32_t src,uint32_t dst,uint32_t length)3676 HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
3677 uint32_t length)
3678 {
3679 HAL_StatusTypeDef status;
3680
3681 /* Enable the DMA channel */
3682 if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3683 {
3684 if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U))
3685 {
3686 /* Enable the DMA channel */
3687 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length;
3688 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)src;
3689 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)dst;
3690
3691 status = HAL_DMAEx_List_Start_IT(hdma);
3692 }
3693 else
3694 {
3695 status = HAL_ERROR;
3696 }
3697 }
3698 else
3699 {
3700 status = HAL_DMA_Start_IT(hdma, src, dst, length);
3701 }
3702
3703 return status;
3704 }
3705 /**
3706 * @}
3707 */
3708 #endif /* LPTIM1 || LPTIM2 */
3709
3710 #endif /* HAL_LPTIM_MODULE_ENABLED */
3711 /**
3712 * @}
3713 */
3714
3715 /**
3716 * @}
3717 */
3718
