1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBAxx_LL_SPI_H
21 #define STM32WBAxx_LL_SPI_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined(SPI1) || defined(SPI3)
35
36 /** @defgroup SPI_LL SPI
37 * @{
38 */
39
40 /* Private variables ---------------------------------------------------------*/
41
42 /* Private constants ---------------------------------------------------------*/
43
44 /* Private macros ------------------------------------------------------------*/
45 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
46 * @{
47 */
48 #if defined(IS_SPI_GRP1_INSTANCE)
49 #define IS_LL_SPI_GRP1_INSTANCE(__INSTANCE__) IS_SPI_GRP1_INSTANCE(__INSTANCE__)
50 #endif /* SPI_TRIG_GRP1 */
51 #define IS_LL_SPI_GRP2_INSTANCE(__INSTANCE__) IS_SPI_GRP2_INSTANCE(__INSTANCE__)
52 /**
53 * @}
54 */
55
56 /* Exported types ------------------------------------------------------------*/
57 #if defined(USE_FULL_LL_DRIVER)
58 /** @defgroup SPI_LL_Exported_Types SPI Exported Types
59 * @{
60 */
61
62 /**
63 * @brief SPI Init structures definition
64 */
65 typedef struct
66 {
67 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
68 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
69
70 This feature can be modified afterwards using unitary function
71 @ref LL_SPI_SetTransferDirection().*/
72
73 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
74 This parameter can be a value of @ref SPI_LL_EC_MODE.
75
76 This feature can be modified afterwards using unitary function
77 @ref LL_SPI_SetMode().*/
78
79 uint32_t DataWidth; /*!< Specifies the SPI data width.
80 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
81
82 This feature can be modified afterwards using unitary function
83 @ref LL_SPI_SetDataWidth().*/
84
85 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
86 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
87
88 This feature can be modified afterwards using unitary function
89 @ref LL_SPI_SetClockPolarity().*/
90
91 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
92 This parameter can be a value of @ref SPI_LL_EC_PHASE.
93
94 This feature can be modified afterwards using unitary function
95 @ref LL_SPI_SetClockPhase().*/
96
97 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
98 or by software using the SSI bit.
99
100 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
101
102 This feature can be modified afterwards using unitary function
103 @ref LL_SPI_SetNSSMode().*/
104
105 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure
106 the transmit and receive SCK clock.
107 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
108 @note The communication clock is derived from the master clock.
109 The slave clock does not need to be set.
110
111 This feature can be modified afterwards using unitary function
112 @ref LL_SPI_SetBaudRatePrescaler().*/
113
114 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
115 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
116
117 This feature can be modified afterwards using unitary function
118 @ref LL_SPI_SetTransferBitOrder().*/
119
120 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
121 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
122
123 This feature can be modified afterwards using unitary functions
124 @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
125
126 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
127 This parameter must be a number between Min_Data = 0x00
128 and Max_Data = 0xFFFFFFFF.
129
130 This feature can be modified afterwards using unitary function
131 @ref LL_SPI_SetCRCPolynomial().*/
132
133 } LL_SPI_InitTypeDef;
134
135 /**
136 * @}
137 */
138 #endif /*USE_FULL_LL_DRIVER*/
139
140 /* Exported types ------------------------------------------------------------*/
141
142 /* Exported constants --------------------------------------------------------*/
143 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
144 * @{
145 */
146
147 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
148 * @brief Flags defines which can be used with LL_SPI_ReadReg function
149 * @{
150 */
151 #define LL_SPI_SR_RXP (SPI_SR_RXP)
152 #define LL_SPI_SR_TXP (SPI_SR_TXP)
153 #define LL_SPI_SR_DXP (SPI_SR_DXP)
154 #define LL_SPI_SR_EOT (SPI_SR_EOT)
155 #define LL_SPI_SR_TXTF (SPI_SR_TXTF)
156 #define LL_SPI_SR_UDR (SPI_SR_UDR)
157 #define LL_SPI_SR_CRCE (SPI_SR_CRCE)
158 #define LL_SPI_SR_MODF (SPI_SR_MODF)
159 #define LL_SPI_SR_OVR (SPI_SR_OVR)
160 #define LL_SPI_SR_TIFRE (SPI_SR_TIFRE)
161 #define LL_SPI_SR_SUSP (SPI_SR_SUSP)
162 #define LL_SPI_SR_TXC (SPI_SR_TXC)
163 #define LL_SPI_SR_RXWNE (SPI_SR_RXWNE)
164 /**
165 * @}
166 */
167
168 /** @defgroup SPI_LL_EC_IT IT Defines
169 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
170 * @{
171 */
172 #define LL_SPI_IER_RXPIE (SPI_IER_RXPIE)
173 #define LL_SPI_IER_TXPIE (SPI_IER_TXPIE)
174 #define LL_SPI_IER_DXPIE (SPI_IER_DXPIE)
175 #define LL_SPI_IER_EOTIE (SPI_IER_EOTIE)
176 #define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE)
177 #define LL_SPI_IER_UDRIE (SPI_IER_UDRIE)
178 #define LL_SPI_IER_OVRIE (SPI_IER_OVRIE)
179 #define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE)
180 #define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE)
181 #define LL_SPI_IER_MODFIE (SPI_IER_MODFIE)
182 /**
183 * @}
184 */
185
186 /** @defgroup SPI_LL_EC_MODE Mode
187 * @{
188 */
189 #define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
190 #define LL_SPI_MODE_SLAVE (0x00000000UL)
191 /**
192 * @}
193 */
194
195 /** @defgroup SPI_LL_EC_SS_LEVEL SS Level
196 * @{
197 */
198 #define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
199 #define LL_SPI_SS_LEVEL_LOW (0x00000000UL)
200 /**
201 * @}
202 */
203
204 /** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness
205 * @{
206 */
207 #define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)
208 #define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0)
209 #define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1)
210 #define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)
211 #define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2)
212 #define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
213 #define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
214 #define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
215 #define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3)
216 #define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)
217 #define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)
218 #define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
219 #define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
220 #define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
221 #define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
222 #define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\
223 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
224 /**
225 * @}
226 */
227
228 /** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness
229 * @{
230 */
231 #define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)
232 #define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0)
233 #define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1)
234 #define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)
235 #define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2)
236 #define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
237 #define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
238 #define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
239 #define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3)
240 #define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)
241 #define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)
242 #define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
243 #define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
244 #define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
245 #define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
246 #define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\
247 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
248 /**
249 * @}
250 */
251
252 /** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All
253 * @{
254 */
255 #define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
256 #define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI)
257 /**
258 * @}
259 */
260
261 /** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All
262 * @{
263 */
264 #define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
265 #define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI)
266 /**
267 * @}
268 */
269
270 /** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register
271 * @{
272 */
273 #define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)
274 #define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG)
275 /**
276 * @}
277 */
278
279 /** @defgroup SPI_LL_EC_PROTOCOL Protocol
280 * @{
281 */
282 #define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)
283 #define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)
284 /**
285 * @}
286 */
287
288 /** @defgroup SPI_LL_EC_PHASE Phase
289 * @{
290 */
291 #define LL_SPI_PHASE_1EDGE (0x00000000UL)
292 #define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA)
293 /**
294 * @}
295 */
296
297 /** @defgroup SPI_LL_EC_POLARITY Polarity
298 * @{
299 */
300 #define LL_SPI_POLARITY_LOW (0x00000000UL)
301 #define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL)
302 /**
303 * @}
304 */
305
306 /** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity
307 * @{
308 */
309 #define LL_SPI_NSS_POLARITY_LOW (0x00000000UL)
310 #define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)
311 /**
312 * @}
313 */
314
315 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
316 * @{
317 */
318 #define LL_SPI_BAUDRATEPRESCALER_BYPASS (SPI_CFG1_BPASS)
319 #define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)
320 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0)
321 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1)
322 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
323 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2)
324 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)
325 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)
326 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
327 /**
328 * @}
329 */
330
331 /** @defgroup SPI_LL_EC_BIT_ORDER Bit Order
332 * @{
333 */
334 #define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)
335 #define LL_SPI_MSB_FIRST (0x00000000UL)
336 /**
337 * @}
338 */
339
340 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
341 * @{
342 */
343 #define LL_SPI_FULL_DUPLEX (0x00000000UL)
344 #define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)
345 #define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)
346 #define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)
347 #define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)
348 /**
349 * @}
350 */
351
352 /** @defgroup SPI_LL_EC_DATAWIDTH Data Width
353 * @{
354 */
355 #define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
356 #define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2)
357 #define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
358 #define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
359 #define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
360 #define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3)
361 #define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
362 #define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
363 #define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
364 #define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
365 #define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
366 #define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
367 #define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\
368 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
369 #define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)
370 #define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
371 #define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
372 #define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
373 #define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
374 #define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
375 #define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
376 #define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\
377 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
378 #define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
379 #define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
380 #define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
381 #define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\
382 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
383 #define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
384 #define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\
385 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
386 #define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\
387 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
388 #define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\
389 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
390 /**
391 * @}
392 */
393
394 /** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold
395 * @{
396 */
397 #define LL_SPI_FIFO_TH_01DATA (0x00000000UL)
398 #define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0)
399 #define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1)
400 #define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
401 #define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2)
402 #define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
403 #define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
404 #define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
405 #define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3)
406 #define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
407 #define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
408 #define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
409 #define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
410 #define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
411 #define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
412 #define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\
413 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
414 /**
415 * @}
416 */
417
418 #if defined(USE_FULL_LL_DRIVER)
419
420 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
421 * @{
422 */
423 #define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */
424 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /*!< CRC calculation enabled */
425 /**
426 * @}
427 */
428 #endif /* USE_FULL_LL_DRIVER */
429
430 /** @defgroup SPI_LL_EC_CRC CRC
431 * @{
432 */
433 #define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
434 #define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2)
435 #define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
436 #define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
437 #define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
438 #define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3)
439 #define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
440 #define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
441 #define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
442 #define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
443 #define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
444 #define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
445 #define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\
446 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
447 #define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)
448 #define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
449 #define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
450 #define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
451 #define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
452 #define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
453 #define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
454 #define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\
455 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
456 #define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
457 #define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
458 #define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
459 #define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\
460 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
461 #define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
462 #define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\
463 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
464 #define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\
465 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
466 #define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\
467 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
468 /**
469 * @}
470 */
471
472 /** @defgroup SPI_LL_EC_NSS_MODE NSS Mode
473 * @{
474 */
475 #define LL_SPI_NSS_SOFT (SPI_CFG2_SSM)
476 #define LL_SPI_NSS_HARD_INPUT (0x00000000UL)
477 #define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)
478 /**
479 * @}
480 */
481
482 /** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
483 * @{
484 */
485 #define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
486 #define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
487 #define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
488 #define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
489 /**
490 * @}
491 */
492
493 /** @defgroup SPI_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection
494 * @brief SPI Autonomous Trigger selection
495 * @{
496 */
497 #if defined(SPI1)
498 #define LL_SPI_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for SPI1 */
499 #endif /* SPI1 */
500 #define LL_SPI_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for SPI3 */
501
502 #if defined(LL_SPI_TRIG_GRP1)
503 /*!< HW Trigger signal is GPDMA_CH0_TRG */
504 #define LL_SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x00000000U))
505 /*!< HW Trigger signal is GPDMA_CH1_TRG */
506 #define LL_SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))
507 /*!< HW Trigger signal is GPDMA_CH2_TRG */
508 #define LL_SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))
509 /*!< HW Trigger signal is GPDMA_CH3_TRG */
510 #define LL_SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))
511 /*!< HW Trigger signal is EXTI4_TRG */
512 #define LL_SPI_GRP1_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))
513 /*!< HW Trigger signal is EXTI9_TRG */
514 #define LL_SPI_GRP1_EXTI9_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))
515 /*!< HW Trigger signal is LPTIM1_CH1_TRG */
516 #define LL_SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))
517 #if defined (LPTIM2)
518 /*!< HW Trigger signal is LPTIM2_CH1_TRG */
519 #define LL_SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos))
520 #endif /* LPTIM2 */
521 #if defined (COMP1)
522 /*!< HW Trigger signal is COMP1_TRG */
523 #define LL_SPI_GRP1_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))
524 #endif /* COMP1 */
525 #if defined (COMP2)
526 /*!< HW Trigger signal is COMP2_TRG */
527 #define LL_SPI_GRP1_COMP2_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos))
528 #endif /* COMP2 */
529 /*!< HW Trigger signal is RTC_ALRA_TRG */
530 #define LL_SPI_GRP1_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))
531 /*!< HW Trigger signal is RTC_WUT_TRG */
532 #define LL_SPI_GRP1_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))
533 #endif /* LL_SPI_TRIG_GRP1 */
534
535 /*!< HW Trigger signal is LPDMA_CH0_TRG */
536 #define LL_SPI_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x00000000U))
537 /*!< HW Trigger signal is LPDMA_CH1_TRG */
538 #define LL_SPI_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))
539 /*!< HW Trigger signal is LPDMA_CH2_TRG */
540 #define LL_SPI_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))
541 /*!< HW Trigger signal is LPDMA_CH3_TRG */
542 #define LL_SPI_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))
543 /*!< HW Trigger signal is EXTI4_TRG */
544 #define LL_SPI_GRP2_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))
545 /*!< HW Trigger signal is EXTI8_TRG */
546 #define LL_SPI_GRP2_EXTI8_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))
547 /*!< HW Trigger signal is LPTIM1_CH1_TRG */
548 #define LL_SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))
549 #if defined (COMP1)
550 /*!< HW Trigger signal is COMP1_TRG */
551 #define LL_SPI_GRP2_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))
552 #endif /* COMP1 */
553 /*!< HW Trigger signal is RTC_ALRA_TRG */
554 #define LL_SPI_GRP2_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))
555 /*!< HW Trigger signal is RTC_WUT_TRG */
556 #define LL_SPI_GRP2_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))
557 /**
558 * @}
559 */
560
561 /** @defgroup SPI_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity
562 * @brief SPI Autonomous Trigger Polarity
563 * @{
564 */
565 #define LL_SPI_TRIG_POLARITY_RISING 0x00000000U /*!< SPI triggered on rising edge */
566 #define LL_SPI_TRIG_POLARITY_FALLING SPI_AUTOCR_TRIGPOL /*!< SPI triggered on falling edge */
567 /**
568 * @}
569 */
570
571 /**
572 * @}
573 */
574
575 /* Exported macro ------------------------------------------------------------*/
576 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
577 * @{
578 */
579
580 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
581 * @{
582 */
583
584 /**
585 * @brief Write a value in SPI register
586 * @param __INSTANCE__ SPI Instance
587 * @param __REG__ Register to be written
588 * @param __VALUE__ Value to be written in the register
589 * @retval None
590 */
591 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
592
593 /**
594 * @brief Read a value in SPI register
595 * @param __INSTANCE__ SPI Instance
596 * @param __REG__ Register to be read
597 * @retval Register value
598 */
599 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
600 /**
601 * @}
602 */
603
604 /**
605 * @}
606 */
607
608
609 /* Exported functions --------------------------------------------------------*/
610
611 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
612 * @{
613 */
614
615 /** @defgroup SPI_LL_EF_Configuration Configuration
616 * @{
617 */
618
619 /**
620 * @brief Enable SPI peripheral
621 * @rmtoll CR1 SPE LL_SPI_Enable
622 * @param SPIx SPI Instance
623 * @retval None
624 */
LL_SPI_Enable(SPI_TypeDef * SPIx)625 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
626 {
627 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
628 }
629
630 /**
631 * @brief Disable SPI peripheral
632 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
633 * @rmtoll CR1 SPE LL_SPI_Disable
634 * @param SPIx SPI Instance
635 * @retval None
636 */
LL_SPI_Disable(SPI_TypeDef * SPIx)637 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
638 {
639 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
640 }
641
642 /**
643 * @brief Check if SPI peripheral is enabled
644 * @rmtoll CR1 SPE LL_SPI_IsEnabled
645 * @param SPIx SPI Instance
646 * @retval State of bit (1 or 0)
647 */
LL_SPI_IsEnabled(const SPI_TypeDef * SPIx)648 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
649 {
650 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
651 }
652
653 /**
654 * @brief Swap the MOSI and MISO pin
655 * @note This configuration can not be changed when SPI is enabled.
656 * @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap
657 * @param SPIx SPI Instance
658 * @retval None
659 */
LL_SPI_EnableIOSwap(SPI_TypeDef * SPIx)660 __STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx)
661 {
662 SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
663 }
664
665 /**
666 * @brief Restore default function for MOSI and MISO pin
667 * @note This configuration can not be changed when SPI is enabled.
668 * @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap
669 * @param SPIx SPI Instance
670 * @retval None
671 */
LL_SPI_DisableIOSwap(SPI_TypeDef * SPIx)672 __STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
673 {
674 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
675 }
676
677 /**
678 * @brief Check if MOSI and MISO pin are swapped
679 * @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap
680 * @param SPIx SPI Instance
681 * @retval State of bit (1 or 0)
682 */
LL_SPI_IsEnabledIOSwap(const SPI_TypeDef * SPIx)683 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(const SPI_TypeDef *SPIx)
684 {
685 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
686 }
687
688 /**
689 * @brief Enable GPIO control
690 * @note This configuration can not be changed when SPI is enabled.
691 * @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl
692 * @param SPIx SPI Instance
693 * @retval None
694 */
LL_SPI_EnableGPIOControl(SPI_TypeDef * SPIx)695 __STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx)
696 {
697 SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
698 }
699
700 /**
701 * @brief Disable GPIO control
702 * @note This configuration can not be changed when SPI is enabled.
703 * @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl
704 * @param SPIx SPI Instance
705 * @retval None
706 */
LL_SPI_DisableGPIOControl(SPI_TypeDef * SPIx)707 __STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
708 {
709 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
710 }
711
712 /**
713 * @brief Check if GPIO control is active
714 * @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl
715 * @param SPIx SPI Instance
716 * @retval State of bit (1 or 0)
717 */
LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef * SPIx)718 __STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef *SPIx)
719 {
720 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
721 }
722
723 /**
724 * @brief Set SPI Mode to Master or Slave
725 * @note This configuration can not be changed when SPI is enabled.
726 * @rmtoll CFG2 MASTER LL_SPI_SetMode
727 * @param SPIx SPI Instance
728 * @param Mode This parameter can be one of the following values:
729 * @arg @ref LL_SPI_MODE_MASTER
730 * @arg @ref LL_SPI_MODE_SLAVE
731 * @retval None
732 */
LL_SPI_SetMode(SPI_TypeDef * SPIx,uint32_t Mode)733 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
734 {
735 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode);
736 }
737
738 /**
739 * @brief Get SPI Mode (Master or Slave)
740 * @rmtoll CFG2 MASTER LL_SPI_GetMode
741 * @param SPIx SPI Instance
742 * @retval Returned value can be one of the following values:
743 * @arg @ref LL_SPI_MODE_MASTER
744 * @arg @ref LL_SPI_MODE_SLAVE
745 */
LL_SPI_GetMode(const SPI_TypeDef * SPIx)746 __STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
747 {
748 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
749 }
750
751 /**
752 * @brief Configure the Idleness applied by master between active edge of SS and first send data
753 * @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness
754 * @param SPIx SPI Instance
755 * @param MasterSSIdleness This parameter can be one of the following values:
756 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
757 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
758 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
759 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
760 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
761 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
762 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
763 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
764 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
765 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
766 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
767 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
768 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
769 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
770 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
771 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
772 * @retval None
773 */
LL_SPI_SetMasterSSIdleness(SPI_TypeDef * SPIx,uint32_t MasterSSIdleness)774 __STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
775 {
776 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness);
777 }
778
779 /**
780 * @brief Get the configured Idleness applied by master
781 * @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness
782 * @param SPIx SPI Instance
783 * @retval Returned value can be one of the following values:
784 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
785 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
786 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
787 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
788 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
789 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
790 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
791 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
792 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
793 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
794 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
795 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
796 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
797 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
798 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
799 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
800 */
LL_SPI_GetMasterSSIdleness(const SPI_TypeDef * SPIx)801 __STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(const SPI_TypeDef *SPIx)
802 {
803 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
804 }
805
806 /**
807 * @brief Configure the idleness applied by master between data frame
808 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
809 * @param SPIx SPI Instance
810 * @param MasterInterDataIdleness This parameter can be one of the following values:
811 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
812 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
813 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
814 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
815 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
816 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
817 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
818 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
819 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
820 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
821 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
822 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
823 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
824 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
825 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
826 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
827 * @retval None
828 */
LL_SPI_SetInterDataIdleness(SPI_TypeDef * SPIx,uint32_t MasterInterDataIdleness)829 __STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
830 {
831 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness);
832 }
833
834 /**
835 * @brief Get the configured inter data idleness
836 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
837 * @param SPIx SPI Instance
838 * @retval Returned value can be one of the following values:
839 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
840 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
841 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
842 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
843 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
844 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
845 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
846 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
847 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
848 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
849 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
850 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
851 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
852 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
853 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
854 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
855 */
LL_SPI_GetInterDataIdleness(const SPI_TypeDef * SPIx)856 __STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(const SPI_TypeDef *SPIx)
857 {
858 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
859 }
860
861 /**
862 * @brief Set transfer size
863 * @note Count is the number of frame to be transferred
864 * @rmtoll CR2 TSIZE LL_SPI_SetTransferSize
865 * @param SPIx SPI Instance
866 * @param Count 0..0xFFFF
867 * @retval None
868 */
LL_SPI_SetTransferSize(SPI_TypeDef * SPIx,uint32_t Count)869 __STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
870 {
871 MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);
872 }
873
874 /**
875 * @brief Get transfer size
876 * @note Count is the number of frame to be transferred
877 * @rmtoll CR2 TSIZE LL_SPI_GetTransferSize
878 * @param SPIx SPI Instance
879 * @retval 0..0xFFFF
880 */
LL_SPI_GetTransferSize(const SPI_TypeDef * SPIx)881 __STATIC_INLINE uint32_t LL_SPI_GetTransferSize(const SPI_TypeDef *SPIx)
882 {
883 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
884 }
885
886 /**
887 * @brief Lock the AF configuration of associated IOs
888 * @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs.
889 * the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
890 * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
891 * @param SPIx SPI Instance
892 * @retval None
893 */
LL_SPI_EnableIOLock(SPI_TypeDef * SPIx)894 __STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
895 {
896 SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK);
897 }
898
899 /**
900 * @brief Check if the AF configuration is locked.
901 * @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock
902 * @param SPIx SPI Instance
903 * @retval State of bit (1 or 0)
904 */
LL_SPI_IsEnabledIOLock(const SPI_TypeDef * SPIx)905 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx)
906 {
907 return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
908 }
909
910 /**
911 * @brief Set Tx CRC Initialization Pattern
912 * @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern
913 * @param SPIx SPI Instance
914 * @param TXCRCInitAll This parameter can be one of the following values:
915 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
916 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
917 * @retval None
918 */
LL_SPI_SetTxCRCInitPattern(SPI_TypeDef * SPIx,uint32_t TXCRCInitAll)919 __STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
920 {
921 MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll);
922 }
923
924 /**
925 * @brief Get Tx CRC Initialization Pattern
926 * @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern
927 * @param SPIx SPI Instance
928 * @retval Returned value can be one of the following values:
929 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
930 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
931 */
LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef * SPIx)932 __STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef *SPIx)
933 {
934 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
935 }
936
937 /**
938 * @brief Set Rx CRC Initialization Pattern
939 * @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern
940 * @param SPIx SPI Instance
941 * @param RXCRCInitAll This parameter can be one of the following values:
942 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
943 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
944 * @retval None
945 */
LL_SPI_SetRxCRCInitPattern(SPI_TypeDef * SPIx,uint32_t RXCRCInitAll)946 __STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
947 {
948 MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll);
949 }
950
951 /**
952 * @brief Get Rx CRC Initialization Pattern
953 * @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern
954 * @param SPIx SPI Instance
955 * @retval Returned value can be one of the following values:
956 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
957 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
958 */
LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef * SPIx)959 __STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef *SPIx)
960 {
961 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
962 }
963
964 /**
965 * @brief Set internal SS input level ignoring what comes from PIN.
966 * @note This configuration has effect only with config LL_SPI_NSS_SOFT
967 * @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel
968 * @param SPIx SPI Instance
969 * @param SSLevel This parameter can be one of the following values:
970 * @arg @ref LL_SPI_SS_LEVEL_HIGH
971 * @arg @ref LL_SPI_SS_LEVEL_LOW
972 * @retval None
973 */
LL_SPI_SetInternalSSLevel(SPI_TypeDef * SPIx,uint32_t SSLevel)974 __STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel)
975 {
976 MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);
977 }
978
979 /**
980 * @brief Get internal SS input level
981 * @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel
982 * @param SPIx SPI Instance
983 * @retval Returned value can be one of the following values:
984 * @arg @ref LL_SPI_SS_LEVEL_HIGH
985 * @arg @ref LL_SPI_SS_LEVEL_LOW
986 */
LL_SPI_GetInternalSSLevel(const SPI_TypeDef * SPIx)987 __STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(const SPI_TypeDef *SPIx)
988 {
989 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
990 }
991
992 /**
993 * @brief Enable CRC computation on 33/17 bits
994 * @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC
995 * @param SPIx SPI Instance
996 * @retval None
997 */
LL_SPI_EnableFullSizeCRC(SPI_TypeDef * SPIx)998 __STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx)
999 {
1000 SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
1001 }
1002
1003 /**
1004 * @brief Disable CRC computation on 33/17 bits
1005 * @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC
1006 * @param SPIx SPI Instance
1007 * @retval None
1008 */
LL_SPI_DisableFullSizeCRC(SPI_TypeDef * SPIx)1009 __STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
1010 {
1011 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
1012 }
1013
1014 /**
1015 * @brief Check if Enable CRC computation on 33/17 bits is enabled
1016 * @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC
1017 * @param SPIx SPI Instance
1018 * @retval State of bit (1 or 0)
1019 */
LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef * SPIx)1020 __STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef *SPIx)
1021 {
1022 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
1023 }
1024
1025 /**
1026 * @brief Suspend an ongoing transfer for Master configuration
1027 * @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer
1028 * @param SPIx SPI Instance
1029 * @retval None
1030 */
LL_SPI_SuspendMasterTransfer(SPI_TypeDef * SPIx)1031 __STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx)
1032 {
1033 SET_BIT(SPIx->CR1, SPI_CR1_CSUSP);
1034 }
1035
1036 /**
1037 * @brief Start effective transfer on wire for Master configuration
1038 * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer
1039 * @param SPIx SPI Instance
1040 * @retval None
1041 */
LL_SPI_StartMasterTransfer(SPI_TypeDef * SPIx)1042 __STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
1043 {
1044 SET_BIT(SPIx->CR1, SPI_CR1_CSTART);
1045 }
1046
1047 /**
1048 * @brief Check if there is an unfinished master transfer
1049 * @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer
1050 * @param SPIx SPI Instance
1051 * @retval State of bit (1 or 0)
1052 */
LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef * SPIx)1053 __STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef *SPIx)
1054 {
1055 return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
1056 }
1057
1058 /**
1059 * @brief Enable Master Rx auto suspend in case of overrun
1060 * @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend
1061 * @param SPIx SPI Instance
1062 * @retval None
1063 */
LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef * SPIx)1064 __STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1065 {
1066 SET_BIT(SPIx->CR1, SPI_CR1_MASRX);
1067 }
1068
1069 /**
1070 * @brief Disable Master Rx auto suspend in case of overrun
1071 * @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend
1072 * @param SPIx SPI Instance
1073 * @retval None
1074 */
LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef * SPIx)1075 __STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1076 {
1077 CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX);
1078 }
1079
1080 /**
1081 * @brief Check if Master Rx auto suspend is activated
1082 * @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend
1083 * @param SPIx SPI Instance
1084 * @retval State of bit (1 or 0)
1085 */
LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef * SPIx)1086 __STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef *SPIx)
1087 {
1088 return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
1089 }
1090
1091 /**
1092 * @brief Set Underrun behavior
1093 * @note This configuration can not be changed when SPI is enabled.
1094 * @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration
1095 * @param SPIx SPI Instance
1096 * @param UDRConfig This parameter can be one of the following values:
1097 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1098 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1099 * @retval None
1100 */
LL_SPI_SetUDRConfiguration(SPI_TypeDef * SPIx,uint32_t UDRConfig)1101 __STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig)
1102 {
1103 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);
1104 }
1105
1106 /**
1107 * @brief Get Underrun behavior
1108 * @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration
1109 * @param SPIx SPI Instance
1110 * @retval Returned value can be one of the following values:
1111 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1112 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1113 */
LL_SPI_GetUDRConfiguration(const SPI_TypeDef * SPIx)1114 __STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(const SPI_TypeDef *SPIx)
1115 {
1116 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
1117 }
1118
1119
1120 /**
1121 * @brief Set Serial protocol used
1122 * @note This configuration can not be changed when SPI is enabled.
1123 * @rmtoll CFG2 SP LL_SPI_SetStandard
1124 * @param SPIx SPI Instance
1125 * @param Standard This parameter can be one of the following values:
1126 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1127 * @arg @ref LL_SPI_PROTOCOL_TI
1128 * @retval None
1129 */
LL_SPI_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)1130 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1131 {
1132 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);
1133 }
1134
1135 /**
1136 * @brief Get Serial protocol used
1137 * @rmtoll CFG2 SP LL_SPI_GetStandard
1138 * @param SPIx SPI Instance
1139 * @retval Returned value can be one of the following values:
1140 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1141 * @arg @ref LL_SPI_PROTOCOL_TI
1142 */
LL_SPI_GetStandard(const SPI_TypeDef * SPIx)1143 __STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx)
1144 {
1145 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
1146 }
1147
1148 /**
1149 * @brief Set Clock phase
1150 * @note This configuration can not be changed when SPI is enabled.
1151 * This bit is not used in SPI TI mode.
1152 * @rmtoll CFG2 CPHA LL_SPI_SetClockPhase
1153 * @param SPIx SPI Instance
1154 * @param ClockPhase This parameter can be one of the following values:
1155 * @arg @ref LL_SPI_PHASE_1EDGE
1156 * @arg @ref LL_SPI_PHASE_2EDGE
1157 * @retval None
1158 */
LL_SPI_SetClockPhase(SPI_TypeDef * SPIx,uint32_t ClockPhase)1159 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
1160 {
1161 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase);
1162 }
1163
1164 /**
1165 * @brief Get Clock phase
1166 * @rmtoll CFG2 CPHA LL_SPI_GetClockPhase
1167 * @param SPIx SPI Instance
1168 * @retval Returned value can be one of the following values:
1169 * @arg @ref LL_SPI_PHASE_1EDGE
1170 * @arg @ref LL_SPI_PHASE_2EDGE
1171 */
LL_SPI_GetClockPhase(const SPI_TypeDef * SPIx)1172 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
1173 {
1174 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
1175 }
1176
1177 /**
1178 * @brief Set Clock polarity
1179 * @note This configuration can not be changed when SPI is enabled.
1180 * This bit is not used in SPI TI mode.
1181 * @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity
1182 * @param SPIx SPI Instance
1183 * @param ClockPolarity This parameter can be one of the following values:
1184 * @arg @ref LL_SPI_POLARITY_LOW
1185 * @arg @ref LL_SPI_POLARITY_HIGH
1186 * @retval None
1187 */
LL_SPI_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)1188 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1189 {
1190 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity);
1191 }
1192
1193 /**
1194 * @brief Get Clock polarity
1195 * @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity
1196 * @param SPIx SPI Instance
1197 * @retval Returned value can be one of the following values:
1198 * @arg @ref LL_SPI_POLARITY_LOW
1199 * @arg @ref LL_SPI_POLARITY_HIGH
1200 */
LL_SPI_GetClockPolarity(const SPI_TypeDef * SPIx)1201 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
1202 {
1203 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
1204 }
1205
1206 /**
1207 * @brief Set NSS polarity
1208 * @note This configuration can not be changed when SPI is enabled.
1209 * This bit is not used in SPI TI mode.
1210 * @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity
1211 * @param SPIx SPI Instance
1212 * @param NSSPolarity This parameter can be one of the following values:
1213 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1214 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1215 * @retval None
1216 */
LL_SPI_SetNSSPolarity(SPI_TypeDef * SPIx,uint32_t NSSPolarity)1217 __STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity)
1218 {
1219 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity);
1220 }
1221
1222 /**
1223 * @brief Get NSS polarity
1224 * @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity
1225 * @param SPIx SPI Instance
1226 * @retval Returned value can be one of the following values:
1227 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1228 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1229 */
LL_SPI_GetNSSPolarity(const SPI_TypeDef * SPIx)1230 __STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx)
1231 {
1232 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
1233 }
1234
1235 /**
1236 * @brief Set Baudrate Prescaler
1237 * @note This configuration can not be changed when SPI is enabled.
1238 * SPI BaudRate = fPCLK/Pescaler.
1239 * @rmtoll CFG1 MBR BPASS LL_SPI_SetBaudRatePrescaler
1240 * @param SPIx SPI Instance
1241 * @param Baudrate This parameter can be one of the following values:
1242 * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
1243 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1244 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1245 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1246 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1247 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1248 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1249 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1250 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1251 * @retval None
1252 */
LL_SPI_SetBaudRatePrescaler(SPI_TypeDef * SPIx,uint32_t Baudrate)1253 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)
1254 {
1255 MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate);
1256 }
1257
1258 /**
1259 * @brief Get Baudrate Prescaler
1260 * @rmtoll CFG1 MBR BPASS LL_SPI_GetBaudRatePrescaler
1261 * @param SPIx SPI Instance
1262 * @retval Returned value can be one of the following values:
1263 * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
1264 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1265 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1266 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1267 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1268 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1269 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1270 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1271 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1272 */
LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef * SPIx)1273 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
1274 {
1275 return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS)));
1276 }
1277
1278 /**
1279 * @brief Set Transfer Bit Order
1280 * @note This configuration can not be changed when SPI is enabled.
1281 * This bit is not used in SPI TI mode.
1282 * @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder
1283 * @param SPIx SPI Instance
1284 * @param BitOrder This parameter can be one of the following values:
1285 * @arg @ref LL_SPI_LSB_FIRST
1286 * @arg @ref LL_SPI_MSB_FIRST
1287 * @retval None
1288 */
LL_SPI_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)1289 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
1290 {
1291 MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder);
1292 }
1293
1294 /**
1295 * @brief Get Transfer Bit Order
1296 * @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder
1297 * @param SPIx SPI Instance
1298 * @retval Returned value can be one of the following values:
1299 * @arg @ref LL_SPI_LSB_FIRST
1300 * @arg @ref LL_SPI_MSB_FIRST
1301 */
LL_SPI_GetTransferBitOrder(const SPI_TypeDef * SPIx)1302 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
1303 {
1304 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
1305 }
1306
1307 /**
1308 * @brief Set Transfer Mode
1309 * @note This configuration can not be changed when SPI is enabled except for half duplex direction
1310 * using LL_SPI_SetHalfDuplexDirection.
1311 * @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n
1312 * CFG2 COMM LL_SPI_SetTransferDirection
1313 * @param SPIx SPI Instance
1314 * @param TransferDirection This parameter can be one of the following values:
1315 * @arg @ref LL_SPI_FULL_DUPLEX
1316 * @arg @ref LL_SPI_SIMPLEX_TX
1317 * @arg @ref LL_SPI_SIMPLEX_RX
1318 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1319 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1320 * @retval None
1321 */
LL_SPI_SetTransferDirection(SPI_TypeDef * SPIx,uint32_t TransferDirection)1322 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
1323 {
1324 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR);
1325 MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM);
1326 }
1327
1328 /**
1329 * @brief Get Transfer Mode
1330 * @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n
1331 * CFG2 COMM LL_SPI_GetTransferDirection
1332 * @param SPIx SPI Instance
1333 * @retval Returned value can be one of the following values:
1334 * @arg @ref LL_SPI_FULL_DUPLEX
1335 * @arg @ref LL_SPI_SIMPLEX_TX
1336 * @arg @ref LL_SPI_SIMPLEX_RX
1337 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1338 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1339 */
LL_SPI_GetTransferDirection(const SPI_TypeDef * SPIx)1340 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
1341 {
1342 uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
1343 uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
1344 return (Hddir | Comm);
1345 }
1346
1347 /**
1348 * @brief Set direction for Half-Duplex Mode
1349 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1350 * @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection
1351 * @param SPIx SPI Instance
1352 * @param HalfDuplexDirection This parameter can be one of the following values:
1353 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1354 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1355 * @retval None
1356 */
LL_SPI_SetHalfDuplexDirection(SPI_TypeDef * SPIx,uint32_t HalfDuplexDirection)1357 __STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
1358 {
1359 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR);
1360 }
1361
1362 /**
1363 * @brief Get direction for Half-Duplex Mode
1364 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1365 * @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection
1366 * @param SPIx SPI Instance
1367 * @retval Returned value can be one of the following values:
1368 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1369 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1370 */
LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef * SPIx)1371 __STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef *SPIx)
1372 {
1373 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
1374 }
1375
1376 /**
1377 * @brief Set Frame Data Size
1378 * @note This configuration can not be changed when SPI is enabled.
1379 * @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth
1380 * @param SPIx SPI Instance
1381 * @param DataWidth This parameter can be one of the following values:
1382 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1383 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1384 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1385 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1386 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1387 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1388 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1389 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1390 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1391 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1392 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1393 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1394 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1395 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1396 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1397 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1398 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1399 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1400 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1401 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1402 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1403 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1404 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1405 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1406 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1407 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1408 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1409 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1410 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1411 * @retval None
1412 */
LL_SPI_SetDataWidth(SPI_TypeDef * SPIx,uint32_t DataWidth)1413 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
1414 {
1415 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);
1416 }
1417
1418 /**
1419 * @brief Get Frame Data Size
1420 * @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth
1421 * @param SPIx SPI Instance
1422 * @retval Returned value can be one of the following values:
1423 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1424 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1425 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1426 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1427 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1428 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1429 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1430 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1431 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1432 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1433 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1434 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1435 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1436 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1437 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1438 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1439 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1440 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1441 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1442 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1443 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1444 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1445 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1446 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1447 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1448 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1449 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1450 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1451 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1452 */
LL_SPI_GetDataWidth(const SPI_TypeDef * SPIx)1453 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
1454 {
1455 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
1456 }
1457
1458 /**
1459 * @brief Set threshold of FIFO that triggers a transfer event
1460 * @note This configuration can not be changed when SPI is enabled.
1461 * @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold
1462 * @param SPIx SPI Instance
1463 * @param Threshold This parameter can be one of the following values:
1464 * @arg @ref LL_SPI_FIFO_TH_01DATA
1465 * @arg @ref LL_SPI_FIFO_TH_02DATA
1466 * @arg @ref LL_SPI_FIFO_TH_03DATA
1467 * @arg @ref LL_SPI_FIFO_TH_04DATA
1468 * @arg @ref LL_SPI_FIFO_TH_05DATA
1469 * @arg @ref LL_SPI_FIFO_TH_06DATA
1470 * @arg @ref LL_SPI_FIFO_TH_07DATA
1471 * @arg @ref LL_SPI_FIFO_TH_08DATA
1472 * @arg @ref LL_SPI_FIFO_TH_09DATA
1473 * @arg @ref LL_SPI_FIFO_TH_10DATA
1474 * @arg @ref LL_SPI_FIFO_TH_11DATA
1475 * @arg @ref LL_SPI_FIFO_TH_12DATA
1476 * @arg @ref LL_SPI_FIFO_TH_13DATA
1477 * @arg @ref LL_SPI_FIFO_TH_14DATA
1478 * @arg @ref LL_SPI_FIFO_TH_15DATA
1479 * @arg @ref LL_SPI_FIFO_TH_16DATA
1480 * @retval None
1481 */
LL_SPI_SetFIFOThreshold(SPI_TypeDef * SPIx,uint32_t Threshold)1482 __STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
1483 {
1484 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);
1485 }
1486
1487 /**
1488 * @brief Get threshold of FIFO that triggers a transfer event
1489 * @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold
1490 * @param SPIx SPI Instance
1491 * @retval Returned value can be one of the following values:
1492 * @arg @ref LL_SPI_FIFO_TH_01DATA
1493 * @arg @ref LL_SPI_FIFO_TH_02DATA
1494 * @arg @ref LL_SPI_FIFO_TH_03DATA
1495 * @arg @ref LL_SPI_FIFO_TH_04DATA
1496 * @arg @ref LL_SPI_FIFO_TH_05DATA
1497 * @arg @ref LL_SPI_FIFO_TH_06DATA
1498 * @arg @ref LL_SPI_FIFO_TH_07DATA
1499 * @arg @ref LL_SPI_FIFO_TH_08DATA
1500 * @arg @ref LL_SPI_FIFO_TH_09DATA
1501 * @arg @ref LL_SPI_FIFO_TH_10DATA
1502 * @arg @ref LL_SPI_FIFO_TH_11DATA
1503 * @arg @ref LL_SPI_FIFO_TH_12DATA
1504 * @arg @ref LL_SPI_FIFO_TH_13DATA
1505 * @arg @ref LL_SPI_FIFO_TH_14DATA
1506 * @arg @ref LL_SPI_FIFO_TH_15DATA
1507 * @arg @ref LL_SPI_FIFO_TH_16DATA
1508 */
LL_SPI_GetFIFOThreshold(const SPI_TypeDef * SPIx)1509 __STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(const SPI_TypeDef *SPIx)
1510 {
1511 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
1512 }
1513
1514 /**
1515 * @brief Enable CRC
1516 * @note This configuration can not be changed when SPI is enabled.
1517 * @rmtoll CFG1 CRCEN LL_SPI_EnableCRC
1518 * @param SPIx SPI Instance
1519 * @retval None
1520 */
LL_SPI_EnableCRC(SPI_TypeDef * SPIx)1521 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
1522 {
1523 SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1524 }
1525
1526 /**
1527 * @brief Disable CRC
1528 * @rmtoll CFG1 CRCEN LL_SPI_DisableCRC
1529 * @param SPIx SPI Instance
1530 * @retval None
1531 */
LL_SPI_DisableCRC(SPI_TypeDef * SPIx)1532 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
1533 {
1534 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1535 }
1536
1537 /**
1538 * @brief Check if CRC is enabled
1539 * @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC
1540 * @param SPIx SPI Instance
1541 * @retval State of bit (1 or 0).
1542 */
LL_SPI_IsEnabledCRC(const SPI_TypeDef * SPIx)1543 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
1544 {
1545 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
1546 }
1547
1548 /**
1549 * @brief Set CRC Length
1550 * @note This configuration can not be changed when SPI is enabled.
1551 * @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth
1552 * @param SPIx SPI Instance
1553 * @param CRCLength This parameter can be one of the following values:
1554 * @arg @ref LL_SPI_CRC_4BIT
1555 * @arg @ref LL_SPI_CRC_5BIT
1556 * @arg @ref LL_SPI_CRC_6BIT
1557 * @arg @ref LL_SPI_CRC_7BIT
1558 * @arg @ref LL_SPI_CRC_8BIT
1559 * @arg @ref LL_SPI_CRC_9BIT
1560 * @arg @ref LL_SPI_CRC_10BIT
1561 * @arg @ref LL_SPI_CRC_11BIT
1562 * @arg @ref LL_SPI_CRC_12BIT
1563 * @arg @ref LL_SPI_CRC_13BIT
1564 * @arg @ref LL_SPI_CRC_14BIT
1565 * @arg @ref LL_SPI_CRC_15BIT
1566 * @arg @ref LL_SPI_CRC_16BIT
1567 * @arg @ref LL_SPI_CRC_17BIT
1568 * @arg @ref LL_SPI_CRC_18BIT
1569 * @arg @ref LL_SPI_CRC_19BIT
1570 * @arg @ref LL_SPI_CRC_20BIT
1571 * @arg @ref LL_SPI_CRC_21BIT
1572 * @arg @ref LL_SPI_CRC_22BIT
1573 * @arg @ref LL_SPI_CRC_23BIT
1574 * @arg @ref LL_SPI_CRC_24BIT
1575 * @arg @ref LL_SPI_CRC_25BIT
1576 * @arg @ref LL_SPI_CRC_26BIT
1577 * @arg @ref LL_SPI_CRC_27BIT
1578 * @arg @ref LL_SPI_CRC_28BIT
1579 * @arg @ref LL_SPI_CRC_29BIT
1580 * @arg @ref LL_SPI_CRC_30BIT
1581 * @arg @ref LL_SPI_CRC_31BIT
1582 * @arg @ref LL_SPI_CRC_32BIT
1583 * @retval None
1584 */
LL_SPI_SetCRCWidth(SPI_TypeDef * SPIx,uint32_t CRCLength)1585 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
1586 {
1587 MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);
1588 }
1589
1590 /**
1591 * @brief Get CRC Length
1592 * @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth
1593 * @param SPIx SPI Instance
1594 * @retval Returned value can be one of the following values:
1595 * @arg @ref LL_SPI_CRC_4BIT
1596 * @arg @ref LL_SPI_CRC_5BIT
1597 * @arg @ref LL_SPI_CRC_6BIT
1598 * @arg @ref LL_SPI_CRC_7BIT
1599 * @arg @ref LL_SPI_CRC_8BIT
1600 * @arg @ref LL_SPI_CRC_9BIT
1601 * @arg @ref LL_SPI_CRC_10BIT
1602 * @arg @ref LL_SPI_CRC_11BIT
1603 * @arg @ref LL_SPI_CRC_12BIT
1604 * @arg @ref LL_SPI_CRC_13BIT
1605 * @arg @ref LL_SPI_CRC_14BIT
1606 * @arg @ref LL_SPI_CRC_15BIT
1607 * @arg @ref LL_SPI_CRC_16BIT
1608 * @arg @ref LL_SPI_CRC_17BIT
1609 * @arg @ref LL_SPI_CRC_18BIT
1610 * @arg @ref LL_SPI_CRC_19BIT
1611 * @arg @ref LL_SPI_CRC_20BIT
1612 * @arg @ref LL_SPI_CRC_21BIT
1613 * @arg @ref LL_SPI_CRC_22BIT
1614 * @arg @ref LL_SPI_CRC_23BIT
1615 * @arg @ref LL_SPI_CRC_24BIT
1616 * @arg @ref LL_SPI_CRC_25BIT
1617 * @arg @ref LL_SPI_CRC_26BIT
1618 * @arg @ref LL_SPI_CRC_27BIT
1619 * @arg @ref LL_SPI_CRC_28BIT
1620 * @arg @ref LL_SPI_CRC_29BIT
1621 * @arg @ref LL_SPI_CRC_30BIT
1622 * @arg @ref LL_SPI_CRC_31BIT
1623 * @arg @ref LL_SPI_CRC_32BIT
1624 */
LL_SPI_GetCRCWidth(const SPI_TypeDef * SPIx)1625 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx)
1626 {
1627 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
1628 }
1629
1630 /**
1631 * @brief Set NSS Mode
1632 * @note This configuration can not be changed when SPI is enabled.
1633 * This bit is not used in SPI TI mode.
1634 * @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n
1635 * CFG2 SSOE LL_SPI_SetNSSMode
1636 * @param SPIx SPI Instance
1637 * @param NSS This parameter can be one of the following values:
1638 * @arg @ref LL_SPI_NSS_SOFT
1639 * @arg @ref LL_SPI_NSS_HARD_INPUT
1640 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1641 * @retval None
1642 */
LL_SPI_SetNSSMode(SPI_TypeDef * SPIx,uint32_t NSS)1643 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
1644 {
1645 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS);
1646 }
1647
1648 /**
1649 * @brief Set NSS Mode
1650 * @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n
1651 * CFG2 SSOE LL_SPI_GetNSSMode
1652 * @param SPIx SPI Instance
1653 * @retval Returned value can be one of the following values:
1654 * @arg @ref LL_SPI_NSS_SOFT
1655 * @arg @ref LL_SPI_NSS_HARD_INPUT
1656 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1657 */
LL_SPI_GetNSSMode(const SPI_TypeDef * SPIx)1658 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
1659 {
1660 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
1661 }
1662
1663 /**
1664 * @brief Enable NSS pulse mgt
1665 * @note This configuration can not be changed when SPI is enabled.
1666 * This bit is not used in SPI TI mode.
1667 * @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt
1668 * @param SPIx SPI Instance
1669 * @retval None
1670 */
LL_SPI_EnableNSSPulseMgt(SPI_TypeDef * SPIx)1671 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
1672 {
1673 SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1674 }
1675
1676 /**
1677 * @brief Disable NSS pulse mgt
1678 * @note This configuration can not be changed when SPI is enabled.
1679 * This bit is not used in SPI TI mode.
1680 * @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt
1681 * @param SPIx SPI Instance
1682 * @retval None
1683 */
LL_SPI_DisableNSSPulseMgt(SPI_TypeDef * SPIx)1684 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
1685 {
1686 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1687 }
1688
1689 /**
1690 * @brief Check if NSS pulse is enabled
1691 * @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse
1692 * @param SPIx SPI Instance
1693 * @retval State of bit (1 or 0)
1694 */
LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef * SPIx)1695 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx)
1696 {
1697 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
1698 }
1699
1700 /**
1701 * @}
1702 */
1703
1704 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
1705 * @{
1706 */
1707
1708 /**
1709 * @brief Check if there is enough data in FIFO to read a full packet
1710 * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP
1711 * @param SPIx SPI Instance
1712 * @retval State of bit (1 or 0)
1713 */
LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef * SPIx)1714 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef *SPIx)
1715 {
1716 return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
1717 }
1718
1719 /**
1720 * @brief Check if there is enough space in FIFO to hold a full packet
1721 * @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP
1722 * @param SPIx SPI Instance
1723 * @retval State of bit (1 or 0)
1724 */
LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef * SPIx)1725 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef *SPIx)
1726 {
1727 return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
1728 }
1729
1730 /**
1731 * @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet
1732 * @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP
1733 * @param SPIx SPI Instance
1734 * @retval State of bit (1 or 0)
1735 */
LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef * SPIx)1736 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef *SPIx)
1737 {
1738 return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
1739 }
1740
1741 /**
1742 * @brief Check that end of transfer event occurred
1743 * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT
1744 * @param SPIx SPI Instance
1745 * @retval State of bit (1 or 0).
1746 */
LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef * SPIx)1747 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef *SPIx)
1748 {
1749 return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
1750 }
1751
1752 /**
1753 * @brief Check that all required data has been filled in the fifo according to transfer size
1754 * @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF
1755 * @param SPIx SPI Instance
1756 * @retval State of bit (1 or 0).
1757 */
LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef * SPIx)1758 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef *SPIx)
1759 {
1760 return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
1761 }
1762
1763 /**
1764 * @brief Get Underrun error flag
1765 * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR
1766 * @param SPIx SPI Instance
1767 * @retval State of bit (1 or 0).
1768 */
LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef * SPIx)1769 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
1770 {
1771 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1772 }
1773
1774 /**
1775 * @brief Get CRC error flag
1776 * @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR
1777 * @param SPIx SPI Instance
1778 * @retval State of bit (1 or 0).
1779 */
LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef * SPIx)1780 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
1781 {
1782 return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
1783 }
1784
1785 /**
1786 * @brief Get Mode fault error flag
1787 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
1788 * @param SPIx SPI Instance
1789 * @retval State of bit (1 or 0).
1790 */
LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef * SPIx)1791 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
1792 {
1793 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
1794 }
1795
1796 /**
1797 * @brief Get Overrun error flag
1798 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
1799 * @param SPIx SPI Instance
1800 * @retval State of bit (1 or 0).
1801 */
LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef * SPIx)1802 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
1803 {
1804 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
1805 }
1806
1807 /**
1808 * @brief Get TI Frame format error flag
1809 * @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE
1810 * @param SPIx SPI Instance
1811 * @retval State of bit (1 or 0).
1812 */
LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef * SPIx)1813 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
1814 {
1815 return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
1816 }
1817
1818 /**
1819 * @brief Check if a suspend operation is done
1820 * @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP
1821 * @param SPIx SPI Instance
1822 * @retval State of bit (1 or 0)
1823 */
LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef * SPIx)1824 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef *SPIx)
1825 {
1826 return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
1827 }
1828
1829 /**
1830 * @brief Check if last TxFIFO or CRC frame transmission is completed
1831 * @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC
1832 * @param SPIx SPI Instance
1833 * @retval State of bit (1 or 0).
1834 */
LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef * SPIx)1835 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef *SPIx)
1836 {
1837 return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
1838 }
1839
1840 /**
1841 * @brief Check if at least one 32-bit data is available in RxFIFO
1842 * @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE
1843 * @param SPIx SPI Instance
1844 * @retval State of bit (1 or 0)
1845 */
LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef * SPIx)1846 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef *SPIx)
1847 {
1848 return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
1849 }
1850
1851 /**
1852 * @brief Get number of data framed remaining in current TSIZE
1853 * @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames
1854 * @param SPIx SPI Instance
1855 * @retval 0..0xFFFF
1856 */
LL_SPI_GetRemainingDataFrames(const SPI_TypeDef * SPIx)1857 __STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(const SPI_TypeDef *SPIx)
1858 {
1859 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
1860 }
1861
1862 /**
1863 * @brief Get RxFIFO packing Level
1864 * @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel
1865 * @param SPIx SPI Instance
1866 * @retval Returned value can be one of the following values:
1867 * @arg @ref LL_SPI_RX_FIFO_0PACKET
1868 * @arg @ref LL_SPI_RX_FIFO_1PACKET
1869 * @arg @ref LL_SPI_RX_FIFO_2PACKET
1870 * @arg @ref LL_SPI_RX_FIFO_3PACKET
1871 */
LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef * SPIx)1872 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef *SPIx)
1873 {
1874 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
1875 }
1876
1877 /**
1878 * @brief Clear End Of Transfer flag
1879 * @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT
1880 * @param SPIx SPI Instance
1881 * @retval None
1882 */
LL_SPI_ClearFlag_EOT(SPI_TypeDef * SPIx)1883 __STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx)
1884 {
1885 SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC);
1886 }
1887
1888 /**
1889 * @brief Clear TXTF flag
1890 * @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF
1891 * @param SPIx SPI Instance
1892 * @retval None
1893 */
LL_SPI_ClearFlag_TXTF(SPI_TypeDef * SPIx)1894 __STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx)
1895 {
1896 SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC);
1897 }
1898
1899 /**
1900 * @brief Clear Underrun error flag
1901 * @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR
1902 * @param SPIx SPI Instance
1903 * @retval None
1904 */
LL_SPI_ClearFlag_UDR(SPI_TypeDef * SPIx)1905 __STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)
1906 {
1907 SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC);
1908 }
1909
1910 /**
1911 * @brief Clear Overrun error flag
1912 * @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR
1913 * @param SPIx SPI Instance
1914 * @retval None
1915 */
LL_SPI_ClearFlag_OVR(SPI_TypeDef * SPIx)1916 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
1917 {
1918 SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC);
1919 }
1920
1921 /**
1922 * @brief Clear CRC error flag
1923 * @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR
1924 * @param SPIx SPI Instance
1925 * @retval None
1926 */
LL_SPI_ClearFlag_CRCERR(SPI_TypeDef * SPIx)1927 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
1928 {
1929 SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC);
1930 }
1931
1932 /**
1933 * @brief Clear Mode fault error flag
1934 * @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF
1935 * @param SPIx SPI Instance
1936 * @retval None
1937 */
LL_SPI_ClearFlag_MODF(SPI_TypeDef * SPIx)1938 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
1939 {
1940 SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC);
1941 }
1942
1943 /**
1944 * @brief Clear Frame format error flag
1945 * @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE
1946 * @param SPIx SPI Instance
1947 * @retval None
1948 */
LL_SPI_ClearFlag_FRE(SPI_TypeDef * SPIx)1949 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
1950 {
1951 SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC);
1952 }
1953
1954 /**
1955 * @brief Clear SUSP flag
1956 * @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP
1957 * @param SPIx SPI Instance
1958 * @retval None
1959 */
LL_SPI_ClearFlag_SUSP(SPI_TypeDef * SPIx)1960 __STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx)
1961 {
1962 SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC);
1963 }
1964
1965 /**
1966 * @}
1967 */
1968
1969 /** @defgroup SPI_LL_EF_IT_Management IT_Management
1970 * @{
1971 */
1972
1973 /**
1974 * @brief Enable Rx Packet available IT
1975 * @rmtoll IER RXPIE LL_SPI_EnableIT_RXP
1976 * @param SPIx SPI Instance
1977 * @retval None
1978 */
LL_SPI_EnableIT_RXP(SPI_TypeDef * SPIx)1979 __STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx)
1980 {
1981 SET_BIT(SPIx->IER, SPI_IER_RXPIE);
1982 }
1983
1984 /**
1985 * @brief Enable Tx Packet space available IT
1986 * @rmtoll IER TXPIE LL_SPI_EnableIT_TXP
1987 * @param SPIx SPI Instance
1988 * @retval None
1989 */
LL_SPI_EnableIT_TXP(SPI_TypeDef * SPIx)1990 __STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx)
1991 {
1992 SET_BIT(SPIx->IER, SPI_IER_TXPIE);
1993 }
1994
1995 /**
1996 * @brief Enable Duplex Packet available IT
1997 * @rmtoll IER DXPIE LL_SPI_EnableIT_DXP
1998 * @param SPIx SPI Instance
1999 * @retval None
2000 */
LL_SPI_EnableIT_DXP(SPI_TypeDef * SPIx)2001 __STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx)
2002 {
2003 SET_BIT(SPIx->IER, SPI_IER_DXPIE);
2004 }
2005
2006 /**
2007 * @brief Enable End Of Transfer IT
2008 * @rmtoll IER EOTIE LL_SPI_EnableIT_EOT
2009 * @param SPIx SPI Instance
2010 * @retval None
2011 */
LL_SPI_EnableIT_EOT(SPI_TypeDef * SPIx)2012 __STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx)
2013 {
2014 SET_BIT(SPIx->IER, SPI_IER_EOTIE);
2015 }
2016
2017 /**
2018 * @brief Enable TXTF IT
2019 * @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF
2020 * @param SPIx SPI Instance
2021 * @retval None
2022 */
LL_SPI_EnableIT_TXTF(SPI_TypeDef * SPIx)2023 __STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx)
2024 {
2025 SET_BIT(SPIx->IER, SPI_IER_TXTFIE);
2026 }
2027
2028 /**
2029 * @brief Enable Underrun IT
2030 * @rmtoll IER UDRIE LL_SPI_EnableIT_UDR
2031 * @param SPIx SPI Instance
2032 * @retval None
2033 */
LL_SPI_EnableIT_UDR(SPI_TypeDef * SPIx)2034 __STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx)
2035 {
2036 SET_BIT(SPIx->IER, SPI_IER_UDRIE);
2037 }
2038
2039 /**
2040 * @brief Enable Overrun IT
2041 * @rmtoll IER OVRIE LL_SPI_EnableIT_OVR
2042 * @param SPIx SPI Instance
2043 * @retval None
2044 */
LL_SPI_EnableIT_OVR(SPI_TypeDef * SPIx)2045 __STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx)
2046 {
2047 SET_BIT(SPIx->IER, SPI_IER_OVRIE);
2048 }
2049
2050 /**
2051 * @brief Enable CRC Error IT
2052 * @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR
2053 * @param SPIx SPI Instance
2054 * @retval None
2055 */
LL_SPI_EnableIT_CRCERR(SPI_TypeDef * SPIx)2056 __STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx)
2057 {
2058 SET_BIT(SPIx->IER, SPI_IER_CRCEIE);
2059 }
2060
2061 /**
2062 * @brief Enable TI Frame Format Error IT
2063 * @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE
2064 * @param SPIx SPI Instance
2065 * @retval None
2066 */
LL_SPI_EnableIT_FRE(SPI_TypeDef * SPIx)2067 __STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx)
2068 {
2069 SET_BIT(SPIx->IER, SPI_IER_TIFREIE);
2070 }
2071
2072 /**
2073 * @brief Enable MODF IT
2074 * @rmtoll IER MODFIE LL_SPI_EnableIT_MODF
2075 * @param SPIx SPI Instance
2076 * @retval None
2077 */
LL_SPI_EnableIT_MODF(SPI_TypeDef * SPIx)2078 __STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx)
2079 {
2080 SET_BIT(SPIx->IER, SPI_IER_MODFIE);
2081 }
2082
2083 /**
2084 * @brief Disable Rx Packet available IT
2085 * @rmtoll IER RXPIE LL_SPI_DisableIT_RXP
2086 * @param SPIx SPI Instance
2087 * @retval None
2088 */
LL_SPI_DisableIT_RXP(SPI_TypeDef * SPIx)2089 __STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx)
2090 {
2091 CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE);
2092 }
2093
2094 /**
2095 * @brief Disable Tx Packet space available IT
2096 * @rmtoll IER TXPIE LL_SPI_DisableIT_TXP
2097 * @param SPIx SPI Instance
2098 * @retval None
2099 */
LL_SPI_DisableIT_TXP(SPI_TypeDef * SPIx)2100 __STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx)
2101 {
2102 CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE);
2103 }
2104
2105 /**
2106 * @brief Disable Duplex Packet available IT
2107 * @rmtoll IER DXPIE LL_SPI_DisableIT_DXP
2108 * @param SPIx SPI Instance
2109 * @retval None
2110 */
LL_SPI_DisableIT_DXP(SPI_TypeDef * SPIx)2111 __STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx)
2112 {
2113 CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE);
2114 }
2115
2116 /**
2117 * @brief Disable End Of Transfer IT
2118 * @rmtoll IER EOTIE LL_SPI_DisableIT_EOT
2119 * @param SPIx SPI Instance
2120 * @retval None
2121 */
LL_SPI_DisableIT_EOT(SPI_TypeDef * SPIx)2122 __STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx)
2123 {
2124 CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE);
2125 }
2126
2127 /**
2128 * @brief Disable TXTF IT
2129 * @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF
2130 * @param SPIx SPI Instance
2131 * @retval None
2132 */
LL_SPI_DisableIT_TXTF(SPI_TypeDef * SPIx)2133 __STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx)
2134 {
2135 CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE);
2136 }
2137
2138 /**
2139 * @brief Disable Underrun IT
2140 * @rmtoll IER UDRIE LL_SPI_DisableIT_UDR
2141 * @param SPIx SPI Instance
2142 * @retval None
2143 */
LL_SPI_DisableIT_UDR(SPI_TypeDef * SPIx)2144 __STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx)
2145 {
2146 CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE);
2147 }
2148
2149 /**
2150 * @brief Disable Overrun IT
2151 * @rmtoll IER OVRIE LL_SPI_DisableIT_OVR
2152 * @param SPIx SPI Instance
2153 * @retval None
2154 */
LL_SPI_DisableIT_OVR(SPI_TypeDef * SPIx)2155 __STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx)
2156 {
2157 CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE);
2158 }
2159
2160 /**
2161 * @brief Disable CRC Error IT
2162 * @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR
2163 * @param SPIx SPI Instance
2164 * @retval None
2165 */
LL_SPI_DisableIT_CRCERR(SPI_TypeDef * SPIx)2166 __STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx)
2167 {
2168 CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE);
2169 }
2170
2171 /**
2172 * @brief Disable TI Frame Format Error IT
2173 * @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE
2174 * @param SPIx SPI Instance
2175 * @retval None
2176 */
LL_SPI_DisableIT_FRE(SPI_TypeDef * SPIx)2177 __STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx)
2178 {
2179 CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE);
2180 }
2181
2182 /**
2183 * @brief Disable MODF IT
2184 * @rmtoll IER MODFIE LL_SPI_DisableIT_MODF
2185 * @param SPIx SPI Instance
2186 * @retval None
2187 */
LL_SPI_DisableIT_MODF(SPI_TypeDef * SPIx)2188 __STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx)
2189 {
2190 CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE);
2191 }
2192
2193 /**
2194 * @brief Check if Rx Packet available IT is enabled
2195 * @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP
2196 * @param SPIx SPI Instance
2197 * @retval State of bit (1 or 0)
2198 */
LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef * SPIx)2199 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef *SPIx)
2200 {
2201 return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
2202 }
2203
2204 /**
2205 * @brief Check if Tx Packet space available IT is enabled
2206 * @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP
2207 * @param SPIx SPI Instance
2208 * @retval State of bit (1 or 0)
2209 */
LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef * SPIx)2210 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef *SPIx)
2211 {
2212 return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
2213 }
2214
2215 /**
2216 * @brief Check if Duplex Packet available IT is enabled
2217 * @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP
2218 * @param SPIx SPI Instance
2219 * @retval State of bit (1 or 0)
2220 */
LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef * SPIx)2221 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef *SPIx)
2222 {
2223 return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
2224 }
2225
2226 /**
2227 * @brief Check if End Of Transfer IT is enabled
2228 * @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT
2229 * @param SPIx SPI Instance
2230 * @retval State of bit (1 or 0)
2231 */
LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef * SPIx)2232 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef *SPIx)
2233 {
2234 return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
2235 }
2236
2237 /**
2238 * @brief Check if TXTF IT is enabled
2239 * @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF
2240 * @param SPIx SPI Instance
2241 * @retval State of bit (1 or 0)
2242 */
LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef * SPIx)2243 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef *SPIx)
2244 {
2245 return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
2246 }
2247
2248 /**
2249 * @brief Check if Underrun IT is enabled
2250 * @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR
2251 * @param SPIx SPI Instance
2252 * @retval State of bit (1 or 0)
2253 */
LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef * SPIx)2254 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef *SPIx)
2255 {
2256 return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
2257 }
2258
2259 /**
2260 * @brief Check if Overrun IT is enabled
2261 * @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR
2262 * @param SPIx SPI Instance
2263 * @retval State of bit (1 or 0)
2264 */
LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef * SPIx)2265 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef *SPIx)
2266 {
2267 return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
2268 }
2269
2270 /**
2271 * @brief Check if CRC Error IT is enabled
2272 * @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR
2273 * @param SPIx SPI Instance
2274 * @retval State of bit (1 or 0)
2275 */
LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef * SPIx)2276 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef *SPIx)
2277 {
2278 return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
2279 }
2280
2281 /**
2282 * @brief Check if TI Frame Format Error IT is enabled
2283 * @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE
2284 * @param SPIx SPI Instance
2285 * @retval State of bit (1 or 0)
2286 */
LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef * SPIx)2287 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef *SPIx)
2288 {
2289 return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
2290 }
2291
2292 /**
2293 * @brief Check if MODF IT is enabled
2294 * @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF
2295 * @param SPIx SPI Instance
2296 * @retval State of bit (1 or 0)
2297 */
LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef * SPIx)2298 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef *SPIx)
2299 {
2300 return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
2301 }
2302
2303 /**
2304 * @}
2305 */
2306
2307 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
2308 * @{
2309 */
2310
2311 /**
2312 * @brief Enable DMA Rx
2313 * @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX
2314 * @param SPIx SPI Instance
2315 * @retval None
2316 */
LL_SPI_EnableDMAReq_RX(SPI_TypeDef * SPIx)2317 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
2318 {
2319 SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2320 }
2321
2322 /**
2323 * @brief Disable DMA Rx
2324 * @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX
2325 * @param SPIx SPI Instance
2326 * @retval None
2327 */
LL_SPI_DisableDMAReq_RX(SPI_TypeDef * SPIx)2328 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
2329 {
2330 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2331 }
2332
2333 /**
2334 * @brief Check if DMA Rx is enabled
2335 * @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
2336 * @param SPIx SPI Instance
2337 * @retval State of bit (1 or 0)
2338 */
LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef * SPIx)2339 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
2340 {
2341 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
2342 }
2343
2344 /**
2345 * @brief Enable DMA Tx
2346 * @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX
2347 * @param SPIx SPI Instance
2348 * @retval None
2349 */
LL_SPI_EnableDMAReq_TX(SPI_TypeDef * SPIx)2350 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
2351 {
2352 SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2353 }
2354
2355 /**
2356 * @brief Disable DMA Tx
2357 * @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX
2358 * @param SPIx SPI Instance
2359 * @retval None
2360 */
LL_SPI_DisableDMAReq_TX(SPI_TypeDef * SPIx)2361 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
2362 {
2363 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2364 }
2365
2366 /**
2367 * @brief Check if DMA Tx is enabled
2368 * @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
2369 * @param SPIx SPI Instance
2370 * @retval State of bit (1 or 0)
2371 */
LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef * SPIx)2372 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
2373 {
2374 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
2375 }
2376 /**
2377 * @brief Get the data register address used for DMA transfer
2378 * @rmtoll TXDR TXDR LL_SPI_DMA_GetTxRegAddr
2379 * @param SPIx SPI Instance
2380 * @retval Address of data register
2381 */
LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef * SPIx)2382 __STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef *SPIx)
2383 {
2384 return (uint32_t) &(SPIx->TXDR);
2385 }
2386
2387 /**
2388 * @brief Get the data register address used for DMA transfer
2389 * @rmtoll RXDR RXDR LL_SPI_DMA_GetRxRegAddr
2390 * @param SPIx SPI Instance
2391 * @retval Address of data register
2392 */
LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef * SPIx)2393 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef *SPIx)
2394 {
2395 return (uint32_t) &(SPIx->RXDR);
2396 }
2397 /**
2398 * @}
2399 */
2400
2401 /** @defgroup SPI_LL_EF_DATA_Management DATA_Management
2402 * @{
2403 */
2404
2405 /**
2406 * @brief Read Data Register
2407 * @rmtoll RXDR . LL_SPI_ReceiveData8
2408 * @param SPIx SPI Instance
2409 * @retval 0..0xFF
2410 */
LL_SPI_ReceiveData8(SPI_TypeDef * SPIx)2411 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
2412 {
2413 return (*((__IO uint8_t *)&SPIx->RXDR));
2414 }
2415
2416 /**
2417 * @brief Read Data Register
2418 * @rmtoll RXDR . LL_SPI_ReceiveData16
2419 * @param SPIx SPI Instance
2420 * @retval 0..0xFFFF
2421 */
LL_SPI_ReceiveData16(SPI_TypeDef * SPIx)2422 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
2423 {
2424 #if defined (__GNUC__)
2425 __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR));
2426 return (*spirxdr);
2427 #else
2428 return (*((__IO uint16_t *)&SPIx->RXDR));
2429 #endif /* __GNUC__ */
2430 }
2431
2432 /**
2433 * @brief Read Data Register
2434 * @rmtoll RXDR . LL_SPI_ReceiveData32
2435 * @param SPIx SPI Instance
2436 * @retval 0..0xFFFFFFFF
2437 */
LL_SPI_ReceiveData32(SPI_TypeDef * SPIx)2438 __STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
2439 {
2440 return (*((__IO uint32_t *)&SPIx->RXDR));
2441 }
2442
2443 /**
2444 * @brief Write Data Register
2445 * @rmtoll TXDR . LL_SPI_TransmitData8
2446 * @param SPIx SPI Instance
2447 * @param TxData 0..0xFF
2448 * @retval None
2449 */
LL_SPI_TransmitData8(SPI_TypeDef * SPIx,uint8_t TxData)2450 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
2451 {
2452 *((__IO uint8_t *)&SPIx->TXDR) = TxData;
2453 }
2454
2455 /**
2456 * @brief Write Data Register
2457 * @rmtoll TXDR . LL_SPI_TransmitData16
2458 * @param SPIx SPI Instance
2459 * @param TxData 0..0xFFFF
2460 * @retval None
2461 */
LL_SPI_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)2462 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
2463 {
2464 #if defined (__GNUC__)
2465 __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR);
2466 *spitxdr = TxData;
2467 #else
2468 *((__IO uint16_t *)&SPIx->TXDR) = TxData;
2469 #endif /* __GNUC__ */
2470 }
2471
2472 /**
2473 * @brief Write Data Register
2474 * @rmtoll TXDR . LL_SPI_TransmitData32
2475 * @param SPIx SPI Instance
2476 * @param TxData 0..0xFFFFFFFF
2477 * @retval None
2478 */
LL_SPI_TransmitData32(SPI_TypeDef * SPIx,uint32_t TxData)2479 __STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
2480 {
2481 *((__IO uint32_t *)&SPIx->TXDR) = TxData;
2482 }
2483
2484 /**
2485 * @brief Set polynomial for CRC calcul
2486 * @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial
2487 * @param SPIx SPI Instance
2488 * @param CRCPoly 0..0xFFFFFFFF
2489 * @retval None
2490 */
LL_SPI_SetCRCPolynomial(SPI_TypeDef * SPIx,uint32_t CRCPoly)2491 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
2492 {
2493 WRITE_REG(SPIx->CRCPOLY, CRCPoly);
2494 }
2495
2496 /**
2497 * @brief Get polynomial for CRC calcul
2498 * @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial
2499 * @param SPIx SPI Instance
2500 * @retval 0..0xFFFFFFFF
2501 */
LL_SPI_GetCRCPolynomial(const SPI_TypeDef * SPIx)2502 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
2503 {
2504 return (uint32_t)(READ_REG(SPIx->CRCPOLY));
2505 }
2506
2507 /**
2508 * @brief Set the underrun pattern
2509 * @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern
2510 * @param SPIx SPI Instance
2511 * @param Pattern 0..0xFFFFFFFF
2512 * @retval None
2513 */
LL_SPI_SetUDRPattern(SPI_TypeDef * SPIx,uint32_t Pattern)2514 __STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
2515 {
2516 WRITE_REG(SPIx->UDRDR, Pattern);
2517 }
2518
2519 /**
2520 * @brief Get the underrun pattern
2521 * @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern
2522 * @param SPIx SPI Instance
2523 * @retval 0..0xFFFFFFFF
2524 */
LL_SPI_GetUDRPattern(const SPI_TypeDef * SPIx)2525 __STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(const SPI_TypeDef *SPIx)
2526 {
2527 return (uint32_t)(READ_REG(SPIx->UDRDR));
2528 }
2529
2530 /**
2531 * @brief Get Rx CRC
2532 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
2533 * @param SPIx SPI Instance
2534 * @retval 0..0xFFFFFFFF
2535 */
LL_SPI_GetRxCRC(const SPI_TypeDef * SPIx)2536 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
2537 {
2538 return (uint32_t)(READ_REG(SPIx->RXCRC));
2539 }
2540
2541 /**
2542 * @brief Get Tx CRC
2543 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
2544 * @param SPIx SPI Instance
2545 * @retval 0..0xFFFFFFFF
2546 */
LL_SPI_GetTxCRC(const SPI_TypeDef * SPIx)2547 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
2548 {
2549 return (uint32_t)(READ_REG(SPIx->TXCRC));
2550 }
2551
2552 /**
2553 * @}
2554 */
2555
2556 /** @defgroup SPI_LL_AutonomousMode Configuration functions related to Autonomous mode feature
2557 * @{
2558 */
2559
2560 /**
2561 * @brief Enable Selected Trigger
2562 * @rmtoll AUTOCR TRIGEN LL_SPI_Enable_SelectedTrigger
2563 * @param SPIx SPI Instance.
2564 * @retval None
2565 */
LL_SPI_Enable_SelectedTrigger(SPI_TypeDef * SPIx)2566 __STATIC_INLINE void LL_SPI_Enable_SelectedTrigger(SPI_TypeDef *SPIx)
2567 {
2568 SET_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN);
2569 }
2570
2571 /**
2572 * @brief Disable Selected Trigger
2573 * @rmtoll AUTOCR TRIGEN LL_SPI_Disable_SelectedTrigger
2574 * @param SPIx SPI Instance.
2575 * @retval None
2576 */
LL_SPI_Disable_SelectedTrigger(SPI_TypeDef * SPIx)2577 __STATIC_INLINE void LL_SPI_Disable_SelectedTrigger(SPI_TypeDef *SPIx)
2578 {
2579 CLEAR_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN);
2580 }
2581
2582 /**
2583 * @brief Indicate if selected Trigger is disabled or enabled
2584 * @rmtoll AUTOCR TRIGEN LL_SPI_IsEnabled_SelectedTrigger
2585 * @param SPIx SPI Instance.
2586 * @retval State of bit (1 or 0).
2587 */
LL_SPI_IsEnabled_SelectedTrigger(const SPI_TypeDef * SPIx)2588 __STATIC_INLINE uint32_t LL_SPI_IsEnabled_SelectedTrigger(const SPI_TypeDef *SPIx)
2589 {
2590 return ((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN) == (SPI_AUTOCR_TRIGEN)) ? 1UL : 0UL);
2591 }
2592
2593 /**
2594 * @brief Set the trigger polarity
2595 * @rmtoll AUTOCR TRIGPOL LL_SPI_SetTriggerPolarity
2596 * @param SPIx SPI Instance.
2597 * @param Polarity This parameter can be one of the following values:
2598 * @arg @ref LL_SPI_TRIG_POLARITY_RISING
2599 * @arg @ref LL_SPI_TRIG_POLARITY_FALLING
2600 * @retval None
2601 */
LL_SPI_SetTriggerPolarity(SPI_TypeDef * SPIx,uint32_t Polarity)2602 __STATIC_INLINE void LL_SPI_SetTriggerPolarity(SPI_TypeDef *SPIx, uint32_t Polarity)
2603 {
2604 MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL, Polarity);
2605 }
2606
2607 /**
2608 * @brief Get the trigger polarity
2609 * @rmtoll AUTOCR TRIGPOL LL_SPI_GetTriggerPolarity
2610 * @param SPIx SPI Instance.
2611 * @retval Returned value can be one of the following values:
2612 * @arg @ref LL_SPI_TRIG_POLARITY_RISING
2613 * @arg @ref LL_SPI_TRIG_POLARITY_FALLING
2614 */
LL_SPI_GetTriggerPolarity(const SPI_TypeDef * SPIx)2615 __STATIC_INLINE uint32_t LL_SPI_GetTriggerPolarity(const SPI_TypeDef *SPIx)
2616 {
2617 return (uint32_t)(READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL));
2618 }
2619
2620 /**
2621 * @brief Set the selected trigger
2622 * @rmtoll AUTOCR TRIGSEL LL_SPI_SetSelectedTrigger
2623 * @param SPIx SPI Instance.
2624 * @param Trigger This parameter can be one of the following values:
2625 * @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG
2626 * @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG
2627 * @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG
2628 * @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG
2629 * @arg @ref LL_SPI_GRP1_EXTI4_TRG
2630 * @arg @ref LL_SPI_GRP1_EXTI9_TRG
2631 * @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG
2632 * @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG
2633 * @arg @ref LL_SPI_GRP1_COMP1_TRG
2634 * @arg @ref LL_SPI_GRP1_COMP2_TRG
2635 * @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG
2636 * @arg @ref LL_SPI_GRP1_RTC_WUT_TRG
2637 * @arg @ref LL_SPI_GRP2_GPDMA_CH0_TCF_TRG
2638 * @arg @ref LL_SPI_GRP2_GPDMA_CH1_TCF_TRG
2639 * @arg @ref LL_SPI_GRP2_GPDMA_CH2_TCF_TRG
2640 * @arg @ref LL_SPI_GRP2_GPDMA_CH3_TCF_TRG
2641 * @arg @ref LL_SPI_GRP2_EXTI4_TRG
2642 * @arg @ref LL_SPI_GRP2_EXTI8_TRG
2643 * @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG
2644 * @arg @ref LL_SPI_GRP2_COMP1_TRG
2645 * @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG
2646 * @arg @ref LL_SPI_GRP2_RTC_WUT_TRG
2647 * @retval None
2648 */
LL_SPI_SetSelectedTrigger(SPI_TypeDef * SPIx,uint32_t Trigger)2649 __STATIC_INLINE void LL_SPI_SetSelectedTrigger(SPI_TypeDef *SPIx, uint32_t Trigger)
2650 {
2651 MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL, (Trigger & SPI_AUTOCR_TRIGSEL_Msk));
2652 }
2653
2654 /**
2655 * @brief Get the selected trigger
2656 * @rmtoll AUTOCR TRIGSEL LL_SPI_GetSelectedTrigger
2657 * @param SPIx SPI Instance.
2658 * @retval Returned value can be one of the following values:
2659 * @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG
2660 * @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG
2661 * @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG
2662 * @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG
2663 * @arg @ref LL_SPI_GRP1_EXTI4_TRG
2664 * @arg @ref LL_SPI_GRP1_EXTI9_TRG
2665 * @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG
2666 * @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG
2667 * @arg @ref LL_SPI_GRP1_COMP1_TRG
2668 * @arg @ref LL_SPI_GRP1_COMP2_TRG
2669 * @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG
2670 * @arg @ref LL_SPI_GRP1_RTC_WUT_TRG
2671 * @arg @ref LL_SPI_GRP2_GPDMA_CH0_TCF_TRG
2672 * @arg @ref LL_SPI_GRP2_GPDMA_CH1_TCF_TRG
2673 * @arg @ref LL_SPI_GRP2_GPDMA_CH2_TCF_TRG
2674 * @arg @ref LL_SPI_GRP2_GPDMA_CH3_TCF_TRG
2675 * @arg @ref LL_SPI_GRP2_EXTI4_TRG
2676 * @arg @ref LL_SPI_GRP2_EXTI8_TRG
2677 * @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG
2678 * @arg @ref LL_SPI_GRP2_COMP1_TRG
2679 * @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG
2680 * @arg @ref LL_SPI_GRP2_RTC_WUT_TRG
2681 */
LL_SPI_GetSelectedTrigger(const SPI_TypeDef * SPIx)2682 __STATIC_INLINE uint32_t LL_SPI_GetSelectedTrigger(const SPI_TypeDef *SPIx)
2683 {
2684 #if defined(LL_SPI_TRIG_GRP1)
2685 if (IS_LL_SPI_GRP2_INSTANCE(SPIx))
2686 {
2687 return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP2));
2688 }
2689 else
2690 {
2691 return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP1));
2692 }
2693 #else
2694 return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP2));
2695 #endif /* LL_SPI_TRIG_GRP1 */
2696 }
2697
2698 /**
2699 * @}
2700 */
2701
2702 #if defined(USE_FULL_LL_DRIVER)
2703 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
2704 * @{
2705 */
2706
2707 ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
2708 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
2709 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
2710
2711 /**
2712 * @}
2713 */
2714 #endif /* USE_FULL_LL_DRIVER */
2715 /**
2716 * @}
2717 */
2718 /**
2719 * @}
2720 */
2721
2722
2723 #endif /* defined(SPI1) || defined(SPI3) */
2724
2725 /**
2726 * @}
2727 */
2728
2729 #ifdef __cplusplus
2730 }
2731 #endif
2732
2733 #endif /* STM32WBAxx_LL_SPI_H */
2734
