1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBAxx_LL_PWR_H
21 #define STM32WBAxx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif /* __cplusplus */
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined (PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /* Exported types ------------------------------------------------------------*/
45 /* Exported constants --------------------------------------------------------*/
46
47 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
48 * @{
49 */
50
51 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
52 * @brief Flags defines which can be used with LL_PWR_WriteReg function
53 * @{
54 */
55 #define LL_PWR_SR_CSSF PWR_SR_CSSF /*!< Clear Stop and Standby flags */
56 #define LL_PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1 /*!< Clear Wakeup flag 1 */
57 #define LL_PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2 /*!< Clear Wakeup flag 2 */
58 #define LL_PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3 /*!< Clear Wakeup flag 3 */
59 #define LL_PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4 /*!< Clear Wakeup flag 4 */
60 #define LL_PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5 /*!< Clear Wakeup flag 5 */
61 #define LL_PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6 /*!< Clear Wakeup flag 6 */
62 #define LL_PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7 /*!< Clear Wakeup flag 7 */
63 #define LL_PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8 /*!< Clear Wakeup flag 8 */
64 #define LL_PWR_WUSCR_CWUF_ALL PWR_WUSCR_CWUF /*!< Clear all Wakeup flags */
65 /**
66 * @}
67 */
68
69 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
70 * @brief Flags defines which can be used with LL_PWR_ReadReg function
71 * @{
72 */
73 #define LL_PWR_FLAG_VOSRDY PWR_VOSR_VOSRDY /*!< Voltage scaling ready flag */
74 #define LL_PWR_FLAG_STOPF PWR_SR_STOPF /*!< Stop flag */
75 #define LL_PWR_FLAG_SBF PWR_SR_SBF /*!< Standby flag */
76 #define LL_PWR_FLAG_ACTVOSRDY PWR_SVMSR_ACTVOSRDY /*!< Currently applied VOS ready flag */
77 #define LL_PWR_FLAG_PVDO PWR_SVMSR_PVDO /*!< VDD voltage detector output flag */
78 #define LL_PWR_FLAG_REGS PWR_SVMSR_REGS /*!< Regulator selection flag */
79
80 #define LL_PWR_WAKEUP_FLAG1 PWR_WUSR_WUF1 /*!< Wakeup flag 1 */
81 #define LL_PWR_WAKEUP_FLAG2 PWR_WUSR_WUF2 /*!< Wakeup flag 2 */
82 #define LL_PWR_WAKEUP_FLAG3 PWR_WUSR_WUF3 /*!< Wakeup flag 3 */
83 #define LL_PWR_WAKEUP_FLAG4 PWR_WUSR_WUF4 /*!< Wakeup flag 4 */
84 #define LL_PWR_WAKEUP_FLAG5 PWR_WUSR_WUF5 /*!< Wakeup flag 5 */
85 #define LL_PWR_WAKEUP_FLAG6 PWR_WUSR_WUF6 /*!< Wakeup flag 6 */
86 #define LL_PWR_WAKEUP_FLAG7 PWR_WUSR_WUF7 /*!< Wakeup flag 7 */
87 #define LL_PWR_WAKEUP_FLAG8 PWR_WUSR_WUF8 /*!< Wakeup flag 8 */
88 /**
89 * @}
90 */
91
92 /** @defgroup PWR_LL_EC_LOW_POWER_MODE_SELECTION Low Power Mode Selection
93 * @{
94 */
95 #define LL_PWR_MODE_STOP0 0U /*!< Stop 0 mode */
96 #define LL_PWR_MODE_STOP1 PWR_CR1_LPMS_0 /*!< Stop 1 mode */
97 #define LL_PWR_MODE_STANDBY PWR_CR1_LPMS_2 /*!< Standby mode */
98 /**
99 * @}
100 */
101
102 /** @defgroup PWR_LL_EC_SRAM1_SB_CONTENTS_RETENTION PWR SRAM1 Content Retention in Standby Mode
103 * @{
104 */
105 #define LL_PWR_SRAM1_SB_NO_RETENTION 0U /*!< SRAM1 no retention in Standby mode */
106 #define LL_PWR_SRAM1_SB_FULL_RETENTION PWR_CR1_R1RSB1 /*!< SRAM1 all pages retention in Standby mode */
107 /**
108 * @}
109 */
110
111 /** @defgroup PWR_LL_EC_SRAM2_SB_CONTENTS_RETENTION PWR SRAM2 Content Retention in Standby Mode
112 * @{
113 */
114 #define LL_PWR_SRAM2_SB_NO_RETENTION 0U /*!< SRAM2 no retention in Standby mode */
115 #define LL_PWR_SRAM2_SB_FULL_RETENTION PWR_CR1_R2RSB1 /*!< SRAM2 all pages retention in Standby mode */
116 /**
117 * @}
118 */
119
120 /** @defgroup PWR_LL_EC_RADIO_SB_CONTENTS_RETENTION PWR RADIO SRAMs and Sleep Clock Retention in Standby Mode
121 * @{
122 */
123 #define LL_PWR_RADIO_SB_NO_RETENTION 0U /*!< 2.4 GHz RADIO SRAMs and sleep timer content not retained in Standby mode */
124 #define LL_PWR_RADIO_SB_FULL_RETENTION PWR_CR1_RADIORSB /*!< 2.4 GHz RADIO SRAMs and sleep timer content retained in Standby mode */
125 /**
126 * @}
127 */
128
129 /** @defgroup PWR_LL_EC_SRAM1_STOP_CONTENTS_RETENTION PWR SRAM1 Content Retention in Stop Mode
130 * @{
131 */
132 #define LL_PWR_SRAM1_STOP_NO_RETENTION 0U /*!< SRAM1 no retention in Stop mode (Stop 0, 1) */
133 #define LL_PWR_SRAM1_STOP_FULL_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 all pages retention in Stop mode (Stop 0, 1) */
134 /**
135 * @}
136 */
137
138 /** @defgroup PWR_LL_EC_SRAM2_STOP_CONTENTS_RETENTION PWR SRAM2 Content Retention in Stop Mode
139 * @{
140 */
141 #define LL_PWR_SRAM2_STOP_NO_RETENTION 0U /*!< SRAM2 no retention in Stop mode (Stop 0, 1) */
142 #define LL_PWR_SRAM2_STOP_FULL_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 all pages retention in Stop mode (Stop 0, 1) */
143 /**
144 * @}
145 */
146
147 /** @defgroup PWR_LL_EC_ICACHERAM_STOP_CONTENTS_RETENTION PWR ICACHE SRAM Content Retention in Stop Mode
148 * @{
149 */
150 #define LL_PWR_ICACHERAM_STOP_NO_RETENTION 0U /*!< ICACHE SRAM no retention in Stop mode (Stop 0, 1) */
151 #define LL_PWR_ICACHERAM_STOP_FULL_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM all pages retention in Stop mode (Stop 0, 1) */
152 /**
153 * @}
154 */
155
156 /** @defgroup PWR_LL_EC_SMPS_PWM_MODE PWR SMPS PWM mode
157 * @{
158 */
159 #define LL_PWR_SMPS_NO_PWM_MODE 0U /*!< SMPS PWM mode disabled (high-efficiency mode) */
160 #define LL_PWR_SMPS_PWM_MODE PWR_CR2_FPWM /*!< SMPS PWM mode enabled (harmonic reduction) */
161 /**
162 * @}
163 */
164
165 /** @defgroup PWR_LL_EC_REGULATOR_SUPPLY_SELECTION PWR Regulator Supply Selection
166 * @{
167 */
168 #define LL_PWR_LDO_SUPPLY 0U /*!< LDO regulator supply */
169 #define LL_PWR_SMPS_SUPPLY PWR_CR3_REGSEL /*!< SMPS regulator supply */
170 /**
171 * @}
172 */
173
174 /** @defgroup PWR_LL_EC_REGULATOR_VDDHPA_SUPPLY_SELECTION PWR Regulator REG_VDDHPA input supply selection
175 * @{
176 */
177 #define LL_PWR_REG_VDDHPA_VDDRFPA_PIN 0U /*!< VDDRFPA pin selected as regulator REG_VDDHPA input supply */
178 #define LL_PWR_REG_VDDHPA_VDDRFPA_VDD11 PWR_RADIOSCR_REGPASEL /*!< Regulator REG_VDDHPA input supply selection between VDDRFPA and VDD11 dependent on requested regulated output voltage */
179 /**
180 * @}
181 */
182
183 /** @defgroup PWR_LL_EC_RADIO_PHY_MODE PWR 2.4 GHz RADIO PHY operating mode
184 * @{
185 */
186 #define LL_PWR_RADIO_PHY_SLEEP_MODE 0U /*!< 2.4 GHz RADIO Sleep mode */
187 #define LL_PWR_RADIO_PHY_STANDBY_MODE PWR_RADIOSCR_PHYMODE /*!< 2.4 GHz RADIO Standby mode */
188 /**
189 * @}
190 */
191
192 /** @defgroup PWR_LL_EC_RADIO_OPERATING_MODE PWR 2.4 GHz RADIO operating mode
193 * @{
194 */
195 #define LL_PWR_RADIO_DEEP_SLEEP_MODE 0U /*!< 2.4 GHz RADIO Deep Sleep mode */
196 #define LL_PWR_RADIO_SLEEP_MODE PWR_RADIOSCR_MODE_0 /*!< 2.4 GHz RADIO Sleep mode */
197 #define LL_PWR_RADIO_ACTIVE_MODE PWR_RADIOSCR_MODE_1 /*!< 2.4 GHz RADIO Active mode */
198 /**
199 * @}
200 */
201
202 /** @defgroup PWR_LL_EC_VOLTAGE_SCALING_RANGE_SELECTION PWR Voltage scaling range selection
203 * @{
204 */
205 #define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSR_VOS /*!< Voltage scaling range 1 (highest frequency) */
206 #define LL_PWR_REGU_VOLTAGE_SCALE2 0U /*!< Voltage scaling range 2 (lowest power) */
207 /**
208 * @}
209 */
210
211 /** @defgroup PWR_LL_EC_PVD_LEVEL_SELECTION PWR Power Voltage Detector Level Selection
212 * @{
213 */
214 #define LL_PWR_PVDLEVEL_0 0U /*!< Voltage threshold detected by PVD 2.0 V */
215 #define LL_PWR_PVDLEVEL_1 PWR_SVMCR_PVDLS_0 /*!< Voltage threshold detected by PVD 2.2 V */
216 #define LL_PWR_PVDLEVEL_2 PWR_SVMCR_PVDLS_1 /*!< Voltage threshold detected by PVD 2.4 V */
217 #define LL_PWR_PVDLEVEL_3 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_1) /*!< Voltage threshold detected by PVD 2.5 V */
218 #define LL_PWR_PVDLEVEL_4 PWR_SVMCR_PVDLS_2 /*!< Voltage threshold detected by PVD 2.6 V */
219 #define LL_PWR_PVDLEVEL_5 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.8 V */
220 #define LL_PWR_PVDLEVEL_6 (PWR_SVMCR_PVDLS_1 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.9 V */
221 #define LL_PWR_PVDLEVEL_7 PWR_SVMCR_PVDLS /*!< External input analog voltage on PVD_IN
222 pin, compared to internal VREFINT level */
223 /**
224 * @}
225 */
226
227 /** @defgroup PWR_LL_EC_WAKEUP_PIN PWR Wake Up Pin
228 * @{
229 */
230 #define LL_PWR_WAKEUP_PIN1 PWR_WUCR1_WUPEN1 /*!< Wakeup pin 1 enable */
231 #define LL_PWR_WAKEUP_PIN2 PWR_WUCR1_WUPEN2 /*!< Wakeup pin 2 enable */
232 #define LL_PWR_WAKEUP_PIN3 PWR_WUCR1_WUPEN3 /*!< Wakeup pin 3 enable */
233 #define LL_PWR_WAKEUP_PIN4 PWR_WUCR1_WUPEN4 /*!< Wakeup pin 4 enable */
234 #define LL_PWR_WAKEUP_PIN5 PWR_WUCR1_WUPEN5 /*!< Wakeup pin 5 enable */
235 #define LL_PWR_WAKEUP_PIN6 PWR_WUCR1_WUPEN6 /*!< Wakeup pin 6 enable */
236 #define LL_PWR_WAKEUP_PIN7 PWR_WUCR1_WUPEN7 /*!< Wakeup pin 7 enable */
237 #define LL_PWR_WAKEUP_PIN8 PWR_WUCR1_WUPEN8 /*!< Wakeup pin 8 enable */
238 /**
239 * @}
240 */
241
242 /** @defgroup PWR_LL_EC_WAKEUP_PIN_SELECTION PWR Wakeup Pin Selection
243 * @{
244 */
245 #define LL_PWR_WAKEUP_PIN_SELECTION_0 0UL /*!< Wakeup pin selection 0 */
246 #define LL_PWR_WAKEUP_PIN_SELECTION_1 PWR_WUCR3_WUSEL1_0 /*!< Wakeup pin selection 1 */
247 #define LL_PWR_WAKEUP_PIN_SELECTION_2 PWR_WUCR3_WUSEL1_1 /*!< Wakeup pin selection 2 */
248 #define LL_PWR_WAKEUP_PIN_SELECTION_3 PWR_WUCR3_WUSEL1 /*!< Wakeup pin selection 3 */
249 /**
250 * @}
251 */
252
253 /** @defgroup PWR_LL_EC_GPIO_STATE_RETENTION_ENABLE_SELECTION PWR GPIO State Retention Enable Port Selection
254 * @{
255 */
256 #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA (uint32_t)(&(PWR->IORETENRA)) /*!< GPIO port A */
257 #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB (uint32_t)(&(PWR->IORETENRB)) /*!< GPIO port B */
258 #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC (uint32_t)(&(PWR->IORETENRC)) /*!< GPIO port C */
259 #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH (uint32_t)(&(PWR->IORETENRH)) /*!< GPIO port H */
260 /**
261 * @}
262 */
263
264 /** @defgroup PWR_LL_EC_GPIO_STATE_RETENTION_STATUS_SELECTION PWR GPIO State Retention Status Port Selection
265 * @{
266 */
267 #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTA (uint32_t)(&(PWR->IORETRA)) /*!< GPIO port A */
268 #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTB (uint32_t)(&(PWR->IORETRB)) /*!< GPIO port B */
269 #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTC (uint32_t)(&(PWR->IORETRC)) /*!< GPIO port C */
270 #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTH (uint32_t)(&(PWR->IORETRH)) /*!< GPIO port H */
271 /**
272 * @}
273 */
274
275 /** @defgroup PWR_LL_EC_GPIO_PIN_MASK PWR GPIO Pin Mask
276 * @{
277 */
278 #define LL_PWR_GPIO_PIN_0 (0x0001U) /*!< GPIO port I/O pin 0 */
279 #define LL_PWR_GPIO_PIN_1 (0x0002U) /*!< GPIO port I/O pin 1 */
280 #define LL_PWR_GPIO_PIN_2 (0x0004U) /*!< GPIO port I/O pin 2 */
281 #define LL_PWR_GPIO_PIN_3 (0x0008U) /*!< GPIO port I/O pin 3 */
282 #define LL_PWR_GPIO_PIN_4 (0x0010U) /*!< GPIO port I/O pin 4 */
283 #define LL_PWR_GPIO_PIN_5 (0x0020U) /*!< GPIO port I/O pin 5 */
284 #define LL_PWR_GPIO_PIN_6 (0x0040U) /*!< GPIO port I/O pin 6 */
285 #define LL_PWR_GPIO_PIN_7 (0x0080U) /*!< GPIO port I/O pin 7 */
286 #define LL_PWR_GPIO_PIN_8 (0x0100U) /*!< GPIO port I/O pin 8 */
287 #define LL_PWR_GPIO_PIN_9 (0x0200U) /*!< GPIO port I/O pin 9 */
288 #define LL_PWR_GPIO_PIN_10 (0x0400U) /*!< GPIO port I/O pin 10 */
289 #define LL_PWR_GPIO_PIN_11 (0x0800U) /*!< GPIO port I/O pin 11 */
290 #define LL_PWR_GPIO_PIN_12 (0x1000U) /*!< GPIO port I/O pin 12 */
291 #define LL_PWR_GPIO_PIN_13 (0x2000U) /*!< GPIO port I/O pin 13 */
292 #define LL_PWR_GPIO_PIN_14 (0x4000U) /*!< GPIO port I/O pin 14 */
293 #define LL_PWR_GPIO_PIN_15 (0x8000U) /*!< GPIO port I/O pin 15 */
294 /**
295 * @}
296 */
297
298 /** @defgroup PWR_LL_EC_ITEMS_SECURE_ATTRIBUTE PWR Items Secure Attribute
299 * @{
300 */
301 #define LL_PWR_WAKEUP_PIN1_NSEC 0U /*!< Wake up pin 1 nsecure mode */
302 #define LL_PWR_WAKEUP_PIN1_SEC PWR_SECCFGR_WUP1SEC /*!< Wake up pin 1 secure mode */
303 #define LL_PWR_WAKEUP_PIN2_NSEC 0U /*!< Wake up pin 2 nsecure mode */
304 #define LL_PWR_WAKEUP_PIN2_SEC PWR_SECCFGR_WUP2SEC /*!< Wake up pin 2 secure mode */
305 #define LL_PWR_WAKEUP_PIN3_NSEC 0U /*!< Wake up pin 3 nsecure mode */
306 #define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WUP3SEC /*!< Wake up pin 3 secure mode */
307 #define LL_PWR_WAKEUP_PIN4_NSEC 0U /*!< Wake up pin 4 nsecure mode */
308 #define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WUP4SEC /*!< Wake up pin 4 secure mode */
309 #define LL_PWR_WAKEUP_PIN5_NSEC 0U /*!< Wake up pin 5 nsecure mode */
310 #define LL_PWR_WAKEUP_PIN5_SEC PWR_SECCFGR_WUP5SEC /*!< Wake up pin 5 secure mode */
311 #define LL_PWR_WAKEUP_PIN6_NSEC 0U /*!< Wake up pin 6 nsecure mode */
312 #define LL_PWR_WAKEUP_PIN6_SEC PWR_SECCFGR_WUP6SEC /*!< Wake up pin 6 secure mode */
313 #define LL_PWR_WAKEUP_PIN7_NSEC 0U /*!< Wake up pin 7 nsecure mode */
314 #define LL_PWR_WAKEUP_PIN7_SEC PWR_SECCFGR_WUP7SEC /*!< Wake up pin 7 secure mode */
315 #define LL_PWR_WAKEUP_PIN8_NSEC 0U /*!< Wake up pin 8 nsecure mode */
316 #define LL_PWR_WAKEUP_PIN8_SEC PWR_SECCFGR_WUP8SEC /*!< Wake up pin 8 secure mode */
317
318 #define LL_PWR_LPM_NSEC 0U /*!< Low-power modes nsecure mode */
319 #define LL_PWR_LPM_SEC PWR_SECCFGR_LPMSEC /*!< Low-power modes secure mode */
320 #define LL_PWR_VDM_NSEC 0U /*!< Voltage detection and monitoring nsecure mode */
321 #define LL_PWR_VDM_SEC PWR_SECCFGR_VDMSEC /*!< Voltage detection and monitoring secure mode */
322 #define LL_PWR_VB_NSEC 0U /*!< Backup domain nsecure mode */
323 #define LL_PWR_VB_SEC PWR_SECCFGR_VBSEC /*!< Backup domain secure mode */
324 /**
325 * @}
326 */
327
328 /**
329 * @}
330 */
331
332 /* Exported macro ------------------------------------------------------------*/
333
334 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
335 * @{
336 */
337
338 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and Read Registers Macros
339 * @{
340 */
341
342 /**
343 * @brief Write a value in PWR register.
344 * @param __REG__ Register to be written.
345 * @param __VALUE__ Value to be written in the register.
346 * @retval None.
347 */
348 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
349
350 /**
351 * @brief Read a value in PWR register.
352 * @param __REG__ Register to be read.
353 * @retval Register value.
354 */
355 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
356 /**
357 * @}
358 */
359
360 /**
361 * @}
362 */
363
364 /* Exported functions --------------------------------------------------------*/
365
366 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
367 * @{
368 */
369
370 /** @defgroup PWR_LL_EF_CONFIGURATION PWR Configuration
371 * @{
372 */
373
374 /**
375 * @brief Set system power mode.
376 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
377 * @param Mode This parameter can be one of the following values:
378 * @arg @ref LL_PWR_MODE_STOP0
379 * @arg @ref LL_PWR_MODE_STOP1
380 * @arg @ref LL_PWR_MODE_STANDBY
381 * @retval None
382 */
LL_PWR_SetPowerMode(uint32_t Mode)383 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t Mode)
384 {
385 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, Mode);
386 }
387
388 /**
389 * @brief Get system power mode.
390 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
391 * @retval Returned value can be one of the following values:
392 * @arg @ref LL_PWR_MODE_STOP0
393 * @arg @ref LL_PWR_MODE_STOP1
394 * @arg @ref LL_PWR_MODE_STANDBY
395 */
LL_PWR_GetPowerMode(void)396 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
397 {
398 return (READ_BIT(PWR->CR1, PWR_CR1_LPMS));
399 }
400
401 /**
402 * @brief Set the SRAM2 page(s) retention in Standby mode.
403 * @rmtoll CR1 R2RSB1 LL_PWR_SetSRAM2SBRetention
404 * @param SRAM2PageRetention This parameter can be one of the following values:
405 * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION
406 * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION
407 * @retval None
408 */
LL_PWR_SetSRAM2SBRetention(uint32_t SRAM2PageRetention)409 __STATIC_INLINE void LL_PWR_SetSRAM2SBRetention(uint32_t SRAM2PageRetention)
410 {
411 MODIFY_REG(PWR->CR1, PWR_CR1_R2RSB1, SRAM2PageRetention);
412 }
413
414 /**
415 * @brief Get the SRAM2 page(s) retention in Standby mode.
416 * @rmtoll CR1 R2RSB1 LL_PWR_GetSRAM2SBRetention
417 * @retval Returned value can be one of the following values:
418 * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION
419 * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION
420 */
LL_PWR_GetSRAM2SBRetention(void)421 __STATIC_INLINE uint32_t LL_PWR_GetSRAM2SBRetention(void)
422 {
423 return (READ_BIT(PWR->CR1, PWR_CR1_R2RSB1));
424 }
425
426 /**
427 * @brief Set the SRAM1 page(s) retention in Standby mode.
428 * @rmtoll CR1 R1RSB1 LL_PWR_SetSRAM1SBRetention
429 * @param SRAM1PageRetention This parameter can be one of the following values:
430 * @arg @ref LL_PWR_SRAM1_SB_NO_RETENTION
431 * @arg @ref LL_PWR_SRAM1_SB_FULL_RETENTION
432 * @retval None
433 */
LL_PWR_SetSRAM1SBRetention(uint32_t SRAM1PageRetention)434 __STATIC_INLINE void LL_PWR_SetSRAM1SBRetention(uint32_t SRAM1PageRetention)
435 {
436 MODIFY_REG(PWR->CR1, PWR_CR1_R1RSB1, SRAM1PageRetention);
437 }
438
439 /**
440 * @brief Get the SRAM1 page(s) retention in Standby mode.
441 * @rmtoll CR1 R1RSB1 LL_PWR_GetSRAM1SBRetention
442 * @retval Returned value can be one of the following values:
443 * @arg @ref LL_PWR_SRAM1_SB_NO_RETENTION
444 * @arg @ref LL_PWR_SRAM1_SB_FULL_RETENTION
445 */
LL_PWR_GetSRAM1SBRetention(void)446 __STATIC_INLINE uint32_t LL_PWR_GetSRAM1SBRetention(void)
447 {
448 return (READ_BIT(PWR->CR1, PWR_CR1_R1RSB1));
449 }
450
451 /**
452 * @brief Set the Radio retention in Standby mode.
453 * @rmtoll CR1 RADIORSB LL_PWR_SetRadioSBRetention
454 * @param RadioRetention This parameter can be one of the following values:
455 * @arg @ref LL_PWR_RADIO_SB_NO_RETENTION
456 * @arg @ref LL_PWR_RADIO_SB_FULL_RETENTION
457 * @retval None
458 */
LL_PWR_SetRadioSBRetention(uint32_t RadioRetention)459 __STATIC_INLINE void LL_PWR_SetRadioSBRetention(uint32_t RadioRetention)
460 {
461 MODIFY_REG(PWR->CR1, PWR_CR1_RADIORSB, RadioRetention);
462 }
463
464 /**
465 * @brief Get the Radio retention in Standby mode.
466 * @rmtoll CR1 RADIORSB LL_PWR_GetRadioSBRetention
467 * @retval Returned value can be one of the following values:
468 * @arg @ref LL_PWR_RADIO_SB_NO_RETENTION
469 * @arg @ref LL_PWR_RADIO_SB_FULL_RETENTION
470 */
LL_PWR_GetRadioSBRetention(void)471 __STATIC_INLINE uint32_t LL_PWR_GetRadioSBRetention(void)
472 {
473 return (READ_BIT(PWR->CR1, PWR_CR1_RADIORSB));
474 }
475
476 /**
477 * @brief Enable BOR ultra low power mode.
478 * @rmtoll CR1 UPLMEN LL_PWR_EnableUltraLowPowerMode
479 * @retval None
480 */
LL_PWR_EnableUltraLowPowerMode(void)481 __STATIC_INLINE void LL_PWR_EnableUltraLowPowerMode(void)
482 {
483 SET_BIT(PWR->CR1, PWR_CR1_ULPMEN);
484 }
485
486 /**
487 * @brief Disable BOR ultra low-power mode.
488 * @rmtoll CR1 UPLMEN LL_PWR_DisableUltraLowPowerMode
489 * @retval None
490 */
LL_PWR_DisableUltraLowPowerMode(void)491 __STATIC_INLINE void LL_PWR_DisableUltraLowPowerMode(void)
492 {
493 CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN);
494 }
495
496 /**
497 * @brief Check if BOR ultra low power mode is enabled.
498 * @rmtoll CR1 UPLMEN LL_PWR_IsEnabledUltraLowPowerMode
499 * @retval State of bit (1 or 0).
500 */
LL_PWR_IsEnabledUltraLowPowerMode(void)501 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPowerMode(void)
502 {
503 return ((READ_BIT(PWR->CR1, PWR_CR1_ULPMEN) == (PWR_CR1_ULPMEN)) ? 1UL : 0UL);
504 }
505
506
507 /**
508 * @brief Set the SRAM1 page(s) retention in Stop mode.
509 * @rmtoll CR2 SRAM1PDS1 LL_PWR_SetSRAM1StopRetention
510 * @param SRAM1PageRetention This parameter can be one of the following values:
511 * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
512 * @arg @ref LL_PWR_SRAM1_STOP_FULL_RETENTION
513 * @retval None
514 */
LL_PWR_SetSRAM1StopRetention(uint32_t SRAM1PageRetention)515 __STATIC_INLINE void LL_PWR_SetSRAM1StopRetention(uint32_t SRAM1PageRetention)
516 {
517 MODIFY_REG(PWR->CR2, PWR_CR2_SRAM1PDS1, ((~SRAM1PageRetention) & PWR_CR2_SRAM1PDS1));
518 }
519
520 /**
521 * @brief Get the SRAM1 page(s) retention in Stop mode.
522 * @rmtoll CR2 SRAM1PDS1 LL_PWR_GetSRAM1StopRetention
523 * @retval Returned value can be one of the following values:
524 * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
525 * @arg @ref LL_PWR_SRAM1_STOP_FULL_RETENTION
526 */
LL_PWR_GetSRAM1StopRetention(void)527 __STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention(void)
528 {
529 return ((~(READ_BIT(PWR->CR2, PWR_CR2_SRAM1PDS1))) & PWR_CR2_SRAM1PDS1);
530 }
531
532 /**
533 * @brief Set the SRAM2 page(s) retention in Stop mode.
534 * @rmtoll CR2 SRAM2PDS1 LL_PWR_SetSRAM2StopRetention
535 * @param SRAM2PageRetention This parameter can be one of the following values:
536 * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION
537 * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION
538 * @retval None
539 */
LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention)540 __STATIC_INLINE void LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention)
541 {
542 MODIFY_REG(PWR->CR2, PWR_CR2_SRAM2PDS1, ((~SRAM2PageRetention) & PWR_CR2_SRAM2PDS1));
543 }
544
545 /**
546 * @brief Get the SRAM2 page(s) retention in Stop mode.
547 * @rmtoll CR2 SRAM2PDS1 LL_PWR_GetSRAM2StopRetention
548 * @retval Returned value can be one of the following values:
549 * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION
550 * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION
551 */
LL_PWR_GetSRAM2StopRetention(void)552 __STATIC_INLINE uint32_t LL_PWR_GetSRAM2StopRetention(void)
553 {
554 return ((~(READ_BIT(PWR->CR2, PWR_CR2_SRAM2PDS1))) & PWR_CR2_SRAM2PDS1);
555 }
556
557 /**
558 * @brief Set the ICACHE SRAM page(s) retention in Stop mode.
559 * @rmtoll CR2 ICRAMPDS LL_PWR_SetICacheRAMStopRetention
560 * @note On Silicon Cut 1.0, it is mandatory to disable the ICACHE before going into
561 * stop modes otherwise an hard fault may occur when waking up from stop modes.
562 * @param ICRAMPageRetention This parameter can be one of the following values:
563 * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION
564 * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION
565 * @retval None
566 */
LL_PWR_SetICacheRAMStopRetention(uint32_t ICRAMPageRetention)567 __STATIC_INLINE void LL_PWR_SetICacheRAMStopRetention(uint32_t ICRAMPageRetention)
568 {
569 MODIFY_REG(PWR->CR2, PWR_CR2_ICRAMPDS,
570 ((~ICRAMPageRetention) & PWR_CR2_ICRAMPDS));
571 }
572
573 /**
574 * @brief Get the ICACHE SRAM page(s) retention in Stop mode.
575 * @rmtoll CR2 ICRAMPDS LL_PWR_GetICacheRAMStopRetention
576 * @retval Returned value can be one of the following values:
577 * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION
578 * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION
579 */
LL_PWR_GetICacheRAMStopRetention(void)580 __STATIC_INLINE uint32_t LL_PWR_GetICacheRAMStopRetention(void)
581 {
582 return ((~(READ_BIT(PWR->CR2, PWR_CR2_ICRAMPDS))) & PWR_CR2_ICRAMPDS);
583 }
584
585 /**
586 * @brief Enable the flash memory fast wakeup from Stop mode (Stop 0, 1).
587 * @rmtoll CR2 FLASHFWU LL_PWR_EnableFlashFastWakeUp
588 * @retval None
589 */
LL_PWR_EnableFlashFastWakeUp(void)590 __STATIC_INLINE void LL_PWR_EnableFlashFastWakeUp(void)
591 {
592 SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
593 }
594
595 /**
596 * @brief Disable the flash memory fast wakeup from Stop mode (Stop 0, 1).
597 * @rmtoll CR2 FLASHFWU LL_PWR_DisableFlashFastWakeUp
598 * @retval None
599 */
LL_PWR_DisableFlashFastWakeUp(void)600 __STATIC_INLINE void LL_PWR_DisableFlashFastWakeUp(void)
601 {
602 CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
603 }
604
605 /**
606 * @brief Check if the flash memory fast wakeup from Stop mode (Stop 0, 1)
607 * is enabled.
608 * @rmtoll CR2 FLASHFWU LL_PWR_IsEnabledFlashFastWakeUp
609 * @retval State of bit (1 or 0).
610 */
LL_PWR_IsEnabledFlashFastWakeUp(void)611 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashFastWakeUp(void)
612 {
613 return ((READ_BIT(PWR->CR2, PWR_CR2_FLASHFWU) == (PWR_CR2_FLASHFWU)) ? 1UL : 0UL);
614 }
615
616 #if defined(PWR_CR3_REGSEL)
617 /**
618 * @brief Set the VCore regulator supply.
619 * @rmtoll CR3 REGSEL LL_PWR_SetRegulatorSupply
620 * @param RegulatorSupply This parameter can be one of the following values:
621 * @arg @ref LL_PWR_LDO_SUPPLY
622 * @arg @ref LL_PWR_SMPS_SUPPLY
623 * @retval None
624 */
LL_PWR_SetRegulatorSupply(uint32_t RegulatorSupply)625 __STATIC_INLINE void LL_PWR_SetRegulatorSupply(uint32_t RegulatorSupply)
626 {
627 MODIFY_REG(PWR->CR3, PWR_CR3_REGSEL, RegulatorSupply);
628 }
629
630 /**
631 * @brief Get the VCore regulator supply.
632 * @rmtoll CR3 REGSEL LL_PWR_GetRegulatorSupply
633 * @retval Returned value can be one of the following values:
634 * @arg @ref LL_PWR_LDO_SUPPLY
635 * @arg @ref LL_PWR_SMPS_SUPPLY
636 */
LL_PWR_GetRegulatorSupply(void)637 __STATIC_INLINE uint32_t LL_PWR_GetRegulatorSupply(void)
638 {
639 return (READ_BIT(PWR->CR3, PWR_CR3_REGSEL));
640 }
641 #endif /* PWR_CR3_REGSEL */
642
643 #if defined(PWR_CR2_FPWM)
644 /**
645 * @brief Enable the SMPS PWM mode.
646 * @rmtoll CR2 FPWM LL_PWR_EnableSMPSPWMMode
647 * @retval None
648 */
LL_PWR_EnableSMPSPWMMode(void)649 __STATIC_INLINE void LL_PWR_EnableSMPSPWMMode(void)
650 {
651 SET_BIT(PWR->CR2, PWR_CR2_FPWM);
652 }
653
654 /**
655 * @brief Disable the SMPS PWM mode.
656 * @rmtoll CR2 FPWM LL_PWR_DisableSMPSPWMMode
657 * @retval None
658 */
LL_PWR_DisableSMPSPWMMode(void)659 __STATIC_INLINE void LL_PWR_DisableSMPSPWMMode(void)
660 {
661 CLEAR_BIT(PWR->CR2, PWR_CR2_FPWM);
662 }
663
664 /**
665 * @brief Check if the SMPS PWM mode is enabled.
666 * @rmtoll CR2 FPWM LL_PWR_IsEnabledSMPSPWMMode
667 * @retval State of bit (1 or 0).
668 */
LL_PWR_IsEnabledSMPSPWMMode(void)669 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSMPSPWMMode(void)
670 {
671 return ((READ_BIT(PWR->CR2, PWR_CR2_FPWM) == (PWR_CR2_FPWM)) ? 1UL : 0UL);
672 }
673 #endif /* PWR_CR2_FPWM */
674
675 /**
676 * @brief Enable the fast soft start for selected regulator.
677 * @rmtoll CR3 FSTEN LL_PWR_EnableFastSoftStart
678 * @retval None
679 */
LL_PWR_EnableFastSoftStart(void)680 __STATIC_INLINE void LL_PWR_EnableFastSoftStart(void)
681 {
682 SET_BIT(PWR->CR3, PWR_CR3_FSTEN);
683 }
684
685 /**
686 * @brief Disable the fast soft start for selected regulator.
687 * @rmtoll CR3 FSTEN LL_PWR_DisableFastSoftStart
688 * @retval None
689 */
LL_PWR_DisableFastSoftStart(void)690 __STATIC_INLINE void LL_PWR_DisableFastSoftStart(void)
691 {
692 CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN);
693 }
694
695 /**
696 * @brief Check if the fast soft start for selected regulator is enabled.
697 * @rmtoll CR3 FSTEN LL_PWR_IsEnabledFastSoftStart
698 * @retval State of bit (1 or 0).
699 */
LL_PWR_IsEnabledFastSoftStart(void)700 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFastSoftStart(void)
701 {
702 return ((READ_BIT(PWR->CR3, PWR_CR3_FSTEN) == (PWR_CR3_FSTEN)) ? 1UL : 0UL);
703 }
704
705 /**
706 * @brief Set the regulator supply output voltage.
707 * @rmtoll VOSR VOS LL_PWR_SetRegulVoltageScaling
708 * @param VoltageScaling This parameter can be one of the following values:
709 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
710 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
711 * @retval None
712 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)713 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
714 {
715 MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, VoltageScaling);
716 }
717
718 /**
719 * @brief Get the regulator supply output voltage.
720 * @rmtoll VOSR VOS LL_PWR_GetRegulVoltageScaling
721 * @retval Returned value can be one of the following values:
722 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
723 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
724 */
LL_PWR_GetRegulVoltageScaling(void)725 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
726 {
727 return (uint32_t)(READ_BIT(PWR->VOSR, PWR_VOSR_VOS));
728 }
729
730 /**
731 * @brief Set the Power voltage detector level.
732 * @rmtoll SVMCR PVDLS LL_PWR_SetPVDLevel
733 * @param PVDLevel This parameter can be one of the following values:
734 * @arg @ref LL_PWR_PVDLEVEL_0
735 * @arg @ref LL_PWR_PVDLEVEL_1
736 * @arg @ref LL_PWR_PVDLEVEL_2
737 * @arg @ref LL_PWR_PVDLEVEL_3
738 * @arg @ref LL_PWR_PVDLEVEL_4
739 * @arg @ref LL_PWR_PVDLEVEL_5
740 * @arg @ref LL_PWR_PVDLEVEL_6
741 * @arg @ref LL_PWR_PVDLEVEL_7
742 * @retval None
743 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)744 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
745 {
746 MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, PVDLevel);
747 }
748
749 /**
750 * @brief Get the Power voltage detector level.
751 * @rmtoll SVMCR PVDLS LL_PWR_GetPVDLevel
752 * @retval Returned value can be one of the following values:
753 * @arg @ref LL_PWR_PVDLEVEL_0
754 * @arg @ref LL_PWR_PVDLEVEL_1
755 * @arg @ref LL_PWR_PVDLEVEL_2
756 * @arg @ref LL_PWR_PVDLEVEL_3
757 * @arg @ref LL_PWR_PVDLEVEL_4
758 * @arg @ref LL_PWR_PVDLEVEL_5
759 * @arg @ref LL_PWR_PVDLEVEL_6
760 * @arg @ref LL_PWR_PVDLEVEL_7
761 */
LL_PWR_GetPVDLevel(void)762 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
763 {
764 return (READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDLS));
765 }
766
767 /**
768 * @brief Enable the power voltage detector.
769 * @rmtoll SVMCR PVDE LL_PWR_EnablePVD
770 * @retval None
771 */
LL_PWR_EnablePVD(void)772 __STATIC_INLINE void LL_PWR_EnablePVD(void)
773 {
774 SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
775 }
776
777 /**
778 * @brief Disable the power voltage detector.
779 * @rmtoll SVMCR PVDE LL_PWR_DisablePVD
780 * @retval None
781 */
LL_PWR_DisablePVD(void)782 __STATIC_INLINE void LL_PWR_DisablePVD(void)
783 {
784 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
785 }
786
787 /**
788 * @brief Check if the power voltage detector is enabled.
789 * @rmtoll SVMCR PVDE LL_PWR_IsEnabledPVD
790 * @retval State of bit (1 or 0).
791 */
LL_PWR_IsEnabledPVD(void)792 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
793 {
794 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDE) == (PWR_SVMCR_PVDE)) ? 1UL : 0UL);
795 }
796
797 /**
798 * @brief Enable the wake up pin_x.
799 * @rmtoll WUCR1 WUPENx LL_PWR_EnableWakeUpPin
800 * @param WakeUpPin This parameter can be a combination of the following values:
801 * @arg @ref LL_PWR_WAKEUP_PIN1
802 * @arg @ref LL_PWR_WAKEUP_PIN2
803 * @arg @ref LL_PWR_WAKEUP_PIN3
804 * @arg @ref LL_PWR_WAKEUP_PIN4
805 * @arg @ref LL_PWR_WAKEUP_PIN5
806 * @arg @ref LL_PWR_WAKEUP_PIN6
807 * @arg @ref LL_PWR_WAKEUP_PIN7
808 * @arg @ref LL_PWR_WAKEUP_PIN8
809 * @retval None
810 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)811 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
812 {
813 SET_BIT(PWR->WUCR1, WakeUpPin);
814 }
815
816 /**
817 * @brief Disable the wake up pin_x.
818 * @rmtoll WUCR1 WUPENx LL_PWR_DisableWakeUpPin
819 * @param WakeUpPin This parameter can be a combination of the following values:
820 * @arg @ref LL_PWR_WAKEUP_PIN1
821 * @arg @ref LL_PWR_WAKEUP_PIN2
822 * @arg @ref LL_PWR_WAKEUP_PIN3
823 * @arg @ref LL_PWR_WAKEUP_PIN4
824 * @arg @ref LL_PWR_WAKEUP_PIN5
825 * @arg @ref LL_PWR_WAKEUP_PIN6
826 * @arg @ref LL_PWR_WAKEUP_PIN7
827 * @arg @ref LL_PWR_WAKEUP_PIN8
828 * @retval None
829 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)830 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
831 {
832 CLEAR_BIT(PWR->WUCR1, WakeUpPin);
833 }
834
835 /**
836 * @brief Check if the wake up pin_x is enabled.
837 * @rmtoll WUCR1 WUPENx LL_PWR_IsEnabledWakeUpPin
838 * @param WakeUpPin This parameter can be one of the following values:
839 * @arg @ref LL_PWR_WAKEUP_PIN1
840 * @arg @ref LL_PWR_WAKEUP_PIN2
841 * @arg @ref LL_PWR_WAKEUP_PIN3
842 * @arg @ref LL_PWR_WAKEUP_PIN4
843 * @arg @ref LL_PWR_WAKEUP_PIN5
844 * @arg @ref LL_PWR_WAKEUP_PIN6
845 * @arg @ref LL_PWR_WAKEUP_PIN7
846 * @arg @ref LL_PWR_WAKEUP_PIN8
847 * @retval State of bit (1 or 0).
848 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)849 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
850 {
851 return ((READ_BIT(PWR->WUCR1, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
852 }
853
854 /**
855 * @brief Set the wake up pin polarity low for the event detection.
856 * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityLow
857 * @param WakeUpPin This parameter can be a combination of the following values:
858 * @arg @ref LL_PWR_WAKEUP_PIN1
859 * @arg @ref LL_PWR_WAKEUP_PIN2
860 * @arg @ref LL_PWR_WAKEUP_PIN3
861 * @arg @ref LL_PWR_WAKEUP_PIN4
862 * @arg @ref LL_PWR_WAKEUP_PIN5
863 * @arg @ref LL_PWR_WAKEUP_PIN6
864 * @arg @ref LL_PWR_WAKEUP_PIN7
865 * @arg @ref LL_PWR_WAKEUP_PIN8
866 * @retval None
867 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)868 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
869 {
870 SET_BIT(PWR->WUCR2, WakeUpPin);
871 }
872
873 /**
874 * @brief Set the wake up pin polarity high for the event detection.
875 * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityHigh
876 * @param WakeUpPin This parameter can be a combination of the following values:
877 * @arg @ref LL_PWR_WAKEUP_PIN1
878 * @arg @ref LL_PWR_WAKEUP_PIN2
879 * @arg @ref LL_PWR_WAKEUP_PIN3
880 * @arg @ref LL_PWR_WAKEUP_PIN4
881 * @arg @ref LL_PWR_WAKEUP_PIN5
882 * @arg @ref LL_PWR_WAKEUP_PIN6
883 * @arg @ref LL_PWR_WAKEUP_PIN7
884 * @arg @ref LL_PWR_WAKEUP_PIN8
885 * @retval None
886 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)887 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
888 {
889 CLEAR_BIT(PWR->WUCR2, WakeUpPin);
890 }
891
892 /**
893 * @brief Get the wake up pin polarity for the event detection.
894 * @rmtoll WUCR2 WUPPx LL_PWR_GetWakeUpPinPolarity
895 * @param WakeUpPin This parameter can be one of the following values:
896 * @arg @ref LL_PWR_WAKEUP_PIN1
897 * @arg @ref LL_PWR_WAKEUP_PIN2
898 * @arg @ref LL_PWR_WAKEUP_PIN3
899 * @arg @ref LL_PWR_WAKEUP_PIN4
900 * @arg @ref LL_PWR_WAKEUP_PIN5
901 * @arg @ref LL_PWR_WAKEUP_PIN6
902 * @arg @ref LL_PWR_WAKEUP_PIN7
903 * @arg @ref LL_PWR_WAKEUP_PIN8
904 * @retval State of bit (1 : polarity or 0 : polarity high).
905 */
LL_PWR_GetWakeUpPinPolarity(uint32_t WakeUpPin)906 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPolarity(uint32_t WakeUpPin)
907 {
908 return ((READ_BIT(PWR->WUCR2, WakeUpPin) == WakeUpPin) ? 1UL : 0UL);
909 }
910
911 /**
912 * @brief Set the wakeup pin_x selection 0.
913 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal0Selection
914 * @param WakeUpPin This parameter can be one of the following values:
915 * @arg @ref LL_PWR_WAKEUP_PIN1
916 * @arg @ref LL_PWR_WAKEUP_PIN2
917 * @arg @ref LL_PWR_WAKEUP_PIN3
918 * @arg @ref LL_PWR_WAKEUP_PIN4
919 * @arg @ref LL_PWR_WAKEUP_PIN5
920 * @arg @ref LL_PWR_WAKEUP_PIN6
921 * @arg @ref LL_PWR_WAKEUP_PIN7
922 * @arg @ref LL_PWR_WAKEUP_PIN8
923 * @retval None
924 */
LL_PWR_SetWakeUpPinSignal0Selection(uint32_t WakeUpPin)925 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal0Selection(uint32_t WakeUpPin)
926 {
927 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
928 (LL_PWR_WAKEUP_PIN_SELECTION_0 << (POSITION_VAL(WakeUpPin) * 2U)));
929 }
930
931 /**
932 * @brief Set the wakeup pin_x selection 1.
933 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal1Selection
934 * @param WakeUpPin This parameter can be one of the following values:
935 * @arg @ref LL_PWR_WAKEUP_PIN1
936 * @arg @ref LL_PWR_WAKEUP_PIN2
937 * @arg @ref LL_PWR_WAKEUP_PIN3
938 * @arg @ref LL_PWR_WAKEUP_PIN4
939 * @arg @ref LL_PWR_WAKEUP_PIN5
940 * @arg @ref LL_PWR_WAKEUP_PIN6
941 * @arg @ref LL_PWR_WAKEUP_PIN7
942 * @arg @ref LL_PWR_WAKEUP_PIN8
943 * @retval None
944 */
LL_PWR_SetWakeUpPinSignal1Selection(uint32_t WakeUpPin)945 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal1Selection(uint32_t WakeUpPin)
946 {
947 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
948 (LL_PWR_WAKEUP_PIN_SELECTION_1 << (POSITION_VAL(WakeUpPin) * 2U)));
949 }
950
951 /**
952 * @brief Set the wakeup pin_x selection 2.
953 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal2Selection
954 * @param WakeUpPin This parameter can be one of the following values:
955 * @arg @ref LL_PWR_WAKEUP_PIN1
956 * @arg @ref LL_PWR_WAKEUP_PIN2
957 * @arg @ref LL_PWR_WAKEUP_PIN3
958 * @arg @ref LL_PWR_WAKEUP_PIN4
959 * @arg @ref LL_PWR_WAKEUP_PIN5
960 * @arg @ref LL_PWR_WAKEUP_PIN6
961 * @arg @ref LL_PWR_WAKEUP_PIN7
962 * @arg @ref LL_PWR_WAKEUP_PIN8
963 * @retval None
964 */
LL_PWR_SetWakeUpPinSignal2Selection(uint32_t WakeUpPin)965 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal2Selection(uint32_t WakeUpPin)
966 {
967 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
968 (LL_PWR_WAKEUP_PIN_SELECTION_2 << (POSITION_VAL(WakeUpPin) * 2U)));
969 }
970
971 /**
972 * @brief Set the wakeup pin_x selection 3.
973 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal3Selection
974 * @param WakeUpPin This parameter can be one of the following values:
975 * @arg @ref LL_PWR_WAKEUP_PIN1
976 * @arg @ref LL_PWR_WAKEUP_PIN2
977 * @arg @ref LL_PWR_WAKEUP_PIN3
978 * @arg @ref LL_PWR_WAKEUP_PIN4
979 * @arg @ref LL_PWR_WAKEUP_PIN5
980 * @arg @ref LL_PWR_WAKEUP_PIN6
981 * @arg @ref LL_PWR_WAKEUP_PIN7
982 * @arg @ref LL_PWR_WAKEUP_PIN8
983 * @retval None
984 */
LL_PWR_SetWakeUpPinSignal3Selection(uint32_t WakeUpPin)985 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal3Selection(uint32_t WakeUpPin)
986 {
987 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
988 (LL_PWR_WAKEUP_PIN_SELECTION_3 << (POSITION_VAL(WakeUpPin) * 2U)));
989 }
990
991 /**
992 * @brief Get the wakeup pin_x selection.
993 * @rmtoll WUCR3 WUSELx LL_PWR_GetWakeUpPinSignalSelection
994 * @param WakeUpPin This parameter can be one of the following values:
995 * @arg @ref LL_PWR_WAKEUP_PIN1
996 * @arg @ref LL_PWR_WAKEUP_PIN2
997 * @arg @ref LL_PWR_WAKEUP_PIN3
998 * @arg @ref LL_PWR_WAKEUP_PIN4
999 * @arg @ref LL_PWR_WAKEUP_PIN5
1000 * @arg @ref LL_PWR_WAKEUP_PIN6
1001 * @arg @ref LL_PWR_WAKEUP_PIN7
1002 * @arg @ref LL_PWR_WAKEUP_PIN8
1003 */
LL_PWR_GetWakeUpPinSignalSelection(uint32_t WakeUpPin)1004 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinSignalSelection(uint32_t WakeUpPin)
1005 {
1006 return (READ_BIT(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U))));
1007 }
1008
1009
1010
1011
1012 /**
1013 * @brief Enable access to the backup domain.
1014 * @rmtoll DBPR DBP LL_PWR_EnableBkUpAccess
1015 * @retval None
1016 */
LL_PWR_EnableBkUpAccess(void)1017 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
1018 {
1019 SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
1020 }
1021
1022 /**
1023 * @brief Disable access to the backup domain.
1024 * @rmtoll DBPR DBP LL_PWR_DisableBkUpAccess
1025 * @retval None
1026 */
LL_PWR_DisableBkUpAccess(void)1027 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
1028 {
1029 CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP);
1030 }
1031
1032 /**
1033 * @brief Check if the access to backup domain is enabled.
1034 * @rmtoll DBPR DBP LL_PWR_IsEnabledBkUpAccess
1035 * @retval State of bit (1 or 0).
1036 */
LL_PWR_IsEnabledBkUpAccess(void)1037 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
1038 {
1039 return ((READ_BIT(PWR->DBPR, PWR_DBPR_DBP) == (PWR_DBPR_DBP)) ? 1UL : 0UL);
1040 }
1041
1042
1043
1044
1045 /**
1046 * @brief Enable GPIO retention in Standby mode
1047 * @rmtoll IORETENRx ENx LL_PWR_EnableGPIOStandbyRetention
1048 * @param GPIOPort This parameter can be one of the following values:
1049 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA
1050 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB
1051 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC
1052 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH
1053 * @param GPIOPin This parameter can be a combination of the following values:
1054 * @arg @ref LL_PWR_GPIO_PIN_0
1055 * @arg @ref LL_PWR_GPIO_PIN_1
1056 * @arg @ref LL_PWR_GPIO_PIN_2
1057 * @arg @ref LL_PWR_GPIO_PIN_3
1058 * @arg @ref LL_PWR_GPIO_PIN_4
1059 * @arg @ref LL_PWR_GPIO_PIN_5
1060 * @arg @ref LL_PWR_GPIO_PIN_6
1061 * @arg @ref LL_PWR_GPIO_PIN_7
1062 * @arg @ref LL_PWR_GPIO_PIN_8
1063 * @arg @ref LL_PWR_GPIO_PIN_9
1064 * @arg @ref LL_PWR_GPIO_PIN_10
1065 * @arg @ref LL_PWR_GPIO_PIN_11
1066 * @arg @ref LL_PWR_GPIO_PIN_12
1067 * @arg @ref LL_PWR_GPIO_PIN_13
1068 * @arg @ref LL_PWR_GPIO_PIN_14
1069 * @arg @ref LL_PWR_GPIO_PIN_15
1070 * @retval None.
1071 */
LL_PWR_EnableGPIOStandbyRetention(uint32_t GPIOPort,uint32_t GPIOPin)1072 __STATIC_INLINE void LL_PWR_EnableGPIOStandbyRetention(uint32_t GPIOPort, uint32_t GPIOPin)
1073 {
1074 SET_BIT(*((__IO uint32_t *)GPIOPort), GPIOPin);
1075 }
1076
1077
1078 /**
1079 * @brief Disable GPIO retention in Standby mode
1080 * @rmtoll IORETENRx ENx LL_PWR_DisableGPIOStandbyRetention
1081 * @param GPIOPort This parameter can be one of the following values:
1082 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA
1083 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB
1084 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC
1085 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH
1086 * @param GPIOPin This parameter can be a combinat+ion of the following values:
1087 * @arg @ref LL_PWR_GPIO_PIN_0
1088 * @arg @ref LL_PWR_GPIO_PIN_1
1089 * @arg @ref LL_PWR_GPIO_PIN_2
1090 * @arg @ref LL_PWR_GPIO_PIN_3
1091 * @arg @ref LL_PWR_GPIO_PIN_4
1092 * @arg @ref LL_PWR_GPIO_PIN_5
1093 * @arg @ref LL_PWR_GPIO_PIN_6
1094 * @arg @ref LL_PWR_GPIO_PIN_7
1095 * @arg @ref LL_PWR_GPIO_PIN_8
1096 * @arg @ref LL_PWR_GPIO_PIN_9
1097 * @arg @ref LL_PWR_GPIO_PIN_10
1098 * @arg @ref LL_PWR_GPIO_PIN_11
1099 * @arg @ref LL_PWR_GPIO_PIN_12
1100 * @arg @ref LL_PWR_GPIO_PIN_13
1101 * @arg @ref LL_PWR_GPIO_PIN_14
1102 * @arg @ref LL_PWR_GPIO_PIN_15
1103 * @retval None.
1104 */
LL_PWR_DisableGPIOStandbyRetention(uint32_t GPIOPort,uint32_t GPIOPin)1105 __STATIC_INLINE void LL_PWR_DisableGPIOStandbyRetention(uint32_t GPIOPort, uint32_t GPIOPin)
1106 {
1107 CLEAR_BIT(*((__IO uint32_t *)GPIOPort), GPIOPin);
1108 }
1109
1110
1111
1112 /**
1113 * @brief Check if GPIO retention is enabled in Standby mode
1114 * @rmtoll IORETENRx ENx LL_PWR_IsEnabledGPIOStandbyRetention
1115 * @param GPIOPort This parameter can be one of the following values:
1116 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA
1117 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB
1118 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC
1119 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH
1120 * @param GPIOPin This parameter can be one of the following values:
1121 * @arg @ref LL_PWR_GPIO_PIN_0
1122 * @arg @ref LL_PWR_GPIO_PIN_1
1123 * @arg @ref LL_PWR_GPIO_PIN_2
1124 * @arg @ref LL_PWR_GPIO_PIN_3
1125 * @arg @ref LL_PWR_GPIO_PIN_4
1126 * @arg @ref LL_PWR_GPIO_PIN_5
1127 * @arg @ref LL_PWR_GPIO_PIN_6
1128 * @arg @ref LL_PWR_GPIO_PIN_7
1129 * @arg @ref LL_PWR_GPIO_PIN_8
1130 * @arg @ref LL_PWR_GPIO_PIN_9
1131 * @arg @ref LL_PWR_GPIO_PIN_10
1132 * @arg @ref LL_PWR_GPIO_PIN_11
1133 * @arg @ref LL_PWR_GPIO_PIN_12
1134 * @arg @ref LL_PWR_GPIO_PIN_13
1135 * @arg @ref LL_PWR_GPIO_PIN_14
1136 * @arg @ref LL_PWR_GPIO_PIN_15
1137 * @retval State of bit (1 or 0).
1138 */
LL_PWR_IsEnabledGPIOStandbyRetention(uint32_t GPIOPort,uint32_t GPIOPin)1139 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOStandbyRetention(uint32_t GPIOPort, uint32_t GPIOPin)
1140 {
1141 return ((READ_BIT(*((__IO uint32_t *)(GPIOPort)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
1142 }
1143
1144 /**
1145 * @brief Check if GPIO state was retained after Standby mode entry
1146 * @rmtoll IORETRx RETx LL_PWR_IsGPIOStandbyStateRetained
1147 * @param GPIOPort This parameter can be one of the following values:
1148 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTA
1149 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTB
1150 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTC
1151 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTH
1152 * @param GPIOPin This parameter can be one of the following values:
1153 * @arg @ref LL_PWR_GPIO_PIN_0
1154 * @arg @ref LL_PWR_GPIO_PIN_1
1155 * @arg @ref LL_PWR_GPIO_PIN_2
1156 * @arg @ref LL_PWR_GPIO_PIN_3
1157 * @arg @ref LL_PWR_GPIO_PIN_4
1158 * @arg @ref LL_PWR_GPIO_PIN_5
1159 * @arg @ref LL_PWR_GPIO_PIN_6
1160 * @arg @ref LL_PWR_GPIO_PIN_7
1161 * @arg @ref LL_PWR_GPIO_PIN_8
1162 * @arg @ref LL_PWR_GPIO_PIN_9
1163 * @arg @ref LL_PWR_GPIO_PIN_10
1164 * @arg @ref LL_PWR_GPIO_PIN_11
1165 * @arg @ref LL_PWR_GPIO_PIN_12
1166 * @arg @ref LL_PWR_GPIO_PIN_13
1167 * @arg @ref LL_PWR_GPIO_PIN_14
1168 * @arg @ref LL_PWR_GPIO_PIN_15
1169 * @retval State of bit (1 or 0).
1170 */
LL_PWR_IsGPIOStandbyStateRetained(uint32_t GPIOPort,uint32_t GPIOPin)1171 __STATIC_INLINE uint32_t LL_PWR_IsGPIOStandbyStateRetained(uint32_t GPIOPort, uint32_t GPIOPin)
1172 {
1173 return ((READ_BIT(*((__IO uint32_t *)(GPIOPort)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
1174 }
1175
1176 /**
1177 * @brief Clear GPIO state retention status after Standby mode entry
1178 * @rmtoll IORETRx RETx LL_PWR_ClearGPIOStandbyRetentionStatus
1179 * @param GPIOPort This parameter can be one of the following values:
1180 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTA
1181 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTB
1182 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTC
1183 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTH
1184 * @param GPIOPin This parameter can be one of the following values:
1185 * @arg @ref LL_PWR_GPIO_PIN_0
1186 * @arg @ref LL_PWR_GPIO_PIN_1
1187 * @arg @ref LL_PWR_GPIO_PIN_2
1188 * @arg @ref LL_PWR_GPIO_PIN_3
1189 * @arg @ref LL_PWR_GPIO_PIN_4
1190 * @arg @ref LL_PWR_GPIO_PIN_5
1191 * @arg @ref LL_PWR_GPIO_PIN_6
1192 * @arg @ref LL_PWR_GPIO_PIN_7
1193 * @arg @ref LL_PWR_GPIO_PIN_8
1194 * @arg @ref LL_PWR_GPIO_PIN_9
1195 * @arg @ref LL_PWR_GPIO_PIN_10
1196 * @arg @ref LL_PWR_GPIO_PIN_11
1197 * @arg @ref LL_PWR_GPIO_PIN_12
1198 * @arg @ref LL_PWR_GPIO_PIN_13
1199 * @arg @ref LL_PWR_GPIO_PIN_14
1200 * @arg @ref LL_PWR_GPIO_PIN_15
1201 * @retval None.
1202 */
LL_PWR_ClearGPIOStandbyRetentionStatus(uint32_t GPIOPort,uint32_t GPIOPin)1203 __STATIC_INLINE void LL_PWR_ClearGPIOStandbyRetentionStatus(uint32_t GPIOPort, uint32_t GPIOPin)
1204 {
1205 CLEAR_BIT(*((__IO uint32_t *)GPIOPort), GPIOPin);
1206 }
1207
1208 /**
1209 * @brief Get currently voltage scaling applied to VCORE.
1210 * @rmtoll SVMSR ACTVOS LL_PWR_GetRegulCurrentVOS
1211 * @retval Returned value can be one of the following values:
1212 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
1213 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
1214 */
LL_PWR_GetRegulCurrentVOS(void)1215 __STATIC_INLINE uint32_t LL_PWR_GetRegulCurrentVOS(void)
1216 {
1217 return (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS));
1218 }
1219 /**
1220 * @}
1221 */
1222
1223
1224 /** @defgroup PWR_LL_EF_RADIO_MANAGEMENT PWR RADIO Management
1225 * @{
1226 */
1227
1228 #if defined(PWR_RADIOSCR_REGPABYPEN)
1229 /**
1230 * @brief Enable regulator REG_VDDHPA bypass.
1231 * @rmtoll RADIOSCR REGPABYPEN LL_PWR_EnableREGVDDHPABypass
1232 * @note This bit shall only be written when the VDDHPA regulator is not used (When REGPASEL = 0)
1233 * @retval None
1234 */
LL_PWR_EnableREGVDDHPABypass(void)1235 __STATIC_INLINE void LL_PWR_EnableREGVDDHPABypass(void)
1236 {
1237 SET_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN);
1238 }
1239
1240 /**
1241 * @brief Disable regulator REG_VDDHPA bypass.
1242 * @rmtoll RADIOSCR REGPABYPEN LL_PWR_DisableREGVDDHPABypass
1243 * @retval None
1244 */
LL_PWR_DisableREGVDDHPABypass(void)1245 __STATIC_INLINE void LL_PWR_DisableREGVDDHPABypass(void)
1246 {
1247 CLEAR_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN);
1248 }
1249
1250 /**
1251 * @brief Check if regulator REG_VDDHPA bypass is enabled.
1252 * @rmtoll RADIOSCR REGPABYPEN LL_PWR_IsEnabledREGVDDHPABypass
1253 * @retval State of bit (1 or 0).
1254 */
LL_PWR_IsEnabledREGVDDHPABypass(void)1255 __STATIC_INLINE uint32_t LL_PWR_IsEnabledREGVDDHPABypass(void)
1256 {
1257 return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN) == (PWR_RADIOSCR_REGPABYPEN)) ? 1UL : 0UL);
1258 }
1259 #endif /* PWR_RADIOSCR_REGPABYPEN */
1260
1261 #if defined(PWR_RADIOSCR_REGPASEL)
1262 /**
1263 * @brief Set regulator REG_VDDHPA input supply.
1264 * @rmtoll RADIOSCR REGPASEL LL_PWR_SetREGVDDHPAInputSupply
1265 * @note This bit shall only be written when the VDDHPA regulator is not used (When REGPASEL = 0)
1266 * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_PIN
1267 * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_VDD11
1268 * @retval None
1269 */
LL_PWR_SetREGVDDHPAInputSupply(uint32_t InputSupply)1270 __STATIC_INLINE void LL_PWR_SetREGVDDHPAInputSupply(uint32_t InputSupply)
1271 {
1272 MODIFY_REG(PWR->RADIOSCR, PWR_RADIOSCR_REGPASEL, InputSupply);
1273 }
1274
1275 /**
1276 * @brief Get regulator REG_VDDHPA input supply.
1277 * @rmtoll RADIOSCR REGPASEL LL_PWR_GetREGVDDHPAInputSupply
1278 * @retval Returned value can be one of the following values:
1279 * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_PIN
1280 * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_VDD11
1281 */
LL_PWR_GetREGVDDHPAInputSupply(void)1282 __STATIC_INLINE uint32_t LL_PWR_GetREGVDDHPAInputSupply(void)
1283 {
1284 return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPASEL));
1285 }
1286 #endif /* PWR_RADIOSCR_REGPASEL */
1287
1288 /**
1289 * @brief Indicate whether the VDDHPA voltage output is ready when selecting VDDRFPA input.
1290 * @rmtoll RADIOSCR REGPARDYVDDRFPA LL_PWR_IsActiveFlag_REGPARDYVDDRFPA
1291 * @retval State of bit (1 or 0).
1292 */
LL_PWR_IsActiveFlag_REGPARDYVDDRFPA(void)1293 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGPARDYVDDRFPA(void)
1294 {
1295 return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYVDDRFPA) == (PWR_RADIOSCR_REGPARDYVDDRFPA)) ? 1UL : 0UL);
1296 }
1297
1298 #if defined(PWR_RADIOSCR_REGPARDYV11)
1299 /**
1300 * @brief Indicate whether the VDDHPA voltage output is ready when selecting VDD11 input.
1301 * @rmtoll RADIOSCR REGPARDYV11 LL_PWR_IsActiveFlag_REGPARDYV11
1302 * @retval State of bit (1 or 0).
1303 */
LL_PWR_IsActiveFlag_REGPARDYV11(void)1304 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGPARDYV11(void)
1305 {
1306 return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYV11) == (PWR_RADIOSCR_REGPARDYV11)) ? 1UL : 0UL);
1307 }
1308 #endif /* PWR_RADIOSCR_REGPARDYV11 */
1309
1310 /**
1311 * @brief Get 2.4 GHz RADIO VDDHPA control word.
1312 * @rmtoll RADIOSCR RFVDDHPA LL_PWR_GetRadioVDDHPAControlWord
1313 * @retval 4-bit control word.
1314 */
LL_PWR_GetRadioVDDHPAControlWord(void)1315 __STATIC_INLINE uint32_t LL_PWR_GetRadioVDDHPAControlWord(void)
1316 {
1317 return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_RFVDDHPA));
1318 }
1319
1320 /**
1321 * @brief Indicate whether the 2.4 GHz RADIO encryption function is enabled
1322 * @rmtoll RADIOSCR ENCMODE LL_PWR_IsEnabledRadioEncryption
1323 * @retval State of bit (1 or 0).
1324 */
LL_PWR_IsEnabledRadioEncryption(void)1325 __STATIC_INLINE uint32_t LL_PWR_IsEnabledRadioEncryption(void)
1326 {
1327 return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_ENCMODE) == (PWR_RADIOSCR_ENCMODE)) ? 1UL : 0UL);
1328 }
1329
1330 /**
1331 * @brief Get 2.4 GHz RADIO PHY operating mode.
1332 * @rmtoll RADIOSCR PHYMODE LL_PWR_GetRadioPhyMode
1333 * @retval Returned value can be one of the following values:
1334 * @arg @ref LL_PWR_RADIO_PHY_SLEEP_MODE
1335 * @arg @ref LL_PWR_RADIO_PHY_STANDBY_MODE
1336 */
LL_PWR_GetRadioPhyMode(void)1337 __STATIC_INLINE uint32_t LL_PWR_GetRadioPhyMode(void)
1338 {
1339 return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_PHYMODE));
1340 }
1341
1342 /**
1343 * @brief Get 2.4 GHz RADIO operating mode.
1344 * @rmtoll RADIOSCR MODE LL_PWR_GetRadioMode
1345 * @retval Returned value can be one of the following values:
1346 * @arg @ref LL_PWR_RADIO_DEEP_SLEEP_MODE
1347 * @arg @ref LL_PWR_RADIO_SLEEP_MODE
1348 * @arg @ref LL_PWR_RADIO_ACTIVE_MODE
1349 */
LL_PWR_GetRadioMode(void)1350 __STATIC_INLINE uint32_t LL_PWR_GetRadioMode(void)
1351 {
1352 if (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_MODE_1) != 0UL)
1353 {
1354 return LL_PWR_RADIO_ACTIVE_MODE;
1355 }
1356 else
1357 {
1358 return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_MODE_0));
1359 }
1360 }
1361
1362 /**
1363 * @}
1364 */
1365
1366 /** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management
1367 * @{
1368 */
1369 /**
1370 * @brief Indicate whether the regulator voltage output is above voltage
1371 * scaling range or not.
1372 * @rmtoll VOSR VOSRDY LL_PWR_IsActiveFlag_VOS
1373 * @retval State of bit (1 or 0).
1374 */
LL_PWR_IsActiveFlag_VOS(void)1375 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
1376 {
1377 return ((READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == (PWR_VOSR_VOSRDY)) ? 1UL : 0UL);
1378 }
1379
1380 /**
1381 * @brief Indicate whether the system was in standby mode or not.
1382 * @rmtoll SR SBF LL_PWR_IsActiveFlag_SB
1383 * @retval State of bit (1 or 0).
1384 */
LL_PWR_IsActiveFlag_SB(void)1385 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1386 {
1387 return ((READ_BIT(PWR->SR, PWR_SR_SBF) == (PWR_SR_SBF)) ? 1UL : 0UL);
1388 }
1389
1390 /**
1391 * @brief Indicate whether the system was in stop mode or not.
1392 * @rmtoll SR STOPF LL_PWR_IsActiveFlag_STOP
1393 * @retval State of bit (1 or 0).
1394 */
LL_PWR_IsActiveFlag_STOP(void)1395 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void)
1396 {
1397 return ((READ_BIT(PWR->SR, PWR_SR_STOPF) == (PWR_SR_STOPF)) ? 1UL : 0UL);
1398 }
1399
1400 #if defined(PWR_SVMSR_REGS)
1401 /**
1402 * @brief Indicate whether the regulator supply is LDO or SMPS.
1403 * @rmtoll SVMSR REGS LL_PWR_IsActiveFlag_REGULATOR
1404 * @retval State of bit (1 or 0).
1405 */
LL_PWR_IsActiveFlag_REGULATOR(void)1406 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGULATOR(void)
1407 {
1408 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == (PWR_SVMSR_REGS)) ? 1UL : 0UL);
1409 }
1410 #endif /* PWR_SVMSR_REGS */
1411
1412 /**
1413 * @brief Indicate whether the VDD voltage is below the threshold or not.
1414 * @rmtoll SVMSR PVDO LL_PWR_IsActiveFlag_PVDO
1415 * @retval State of bit (1 or 0).
1416 */
LL_PWR_IsActiveFlag_PVDO(void)1417 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1418 {
1419 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == (PWR_SVMSR_PVDO)) ? 1UL : 0UL);
1420 }
1421
1422 /**
1423 * @brief Indicate whether the regulator voltage output is equal to current
1424 * used voltage scaling range or not.
1425 * @rmtoll SVMSR ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS
1426 * @retval State of bit (1 or 0).
1427 */
LL_PWR_IsActiveFlag_ACTVOS(void)1428 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
1429 {
1430 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == (PWR_SVMSR_ACTVOSRDY)) ? 1UL : 0UL);
1431 }
1432
1433
1434
1435 /**
1436 * @brief Indicate whether a wakeup event is detected on wake up pin 1.
1437 * @rmtoll WUSR WUF1 LL_PWR_IsActiveFlag_WU1
1438 * @retval State of bit (1 or 0).
1439 */
LL_PWR_IsActiveFlag_WU1(void)1440 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1441 {
1442 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL);
1443 }
1444
1445 #if defined(PWR_WUSR_WUF2)
1446 /**
1447 * @brief Indicate whether a wakeup event is detected on wake up pin 2.
1448 * @rmtoll WUSR WUF2 LL_PWR_IsActiveFlag_WU2
1449 * @retval State of bit (1 or 0).
1450 */
LL_PWR_IsActiveFlag_WU2(void)1451 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1452 {
1453 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL);
1454 }
1455 #endif /* PWR_WUSR_WUF2 */
1456
1457 /**
1458 * @brief Indicate whether a wakeup event is detected on wake up pin 3.
1459 * @rmtoll WUSR WUF3 LL_PWR_IsActiveFlag_WU3
1460 * @retval State of bit (1 or 0).
1461 */
LL_PWR_IsActiveFlag_WU3(void)1462 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1463 {
1464 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL);
1465 }
1466
1467 /**
1468 * @brief Indicate whether a wakeup event is detected on wake up pin 4.
1469 * @rmtoll WUSR WUF4 LL_PWR_IsActiveFlag_WU4
1470 * @retval State of bit (1 or 0).
1471 */
LL_PWR_IsActiveFlag_WU4(void)1472 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1473 {
1474 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL);
1475 }
1476
1477 #if defined(PWR_WUSR_WUF5)
1478 /**
1479 * @brief Indicate whether a wakeup event is detected on wake up pin 5.
1480 * @rmtoll WUSR WUF5 LL_PWR_IsActiveFlag_WU5
1481 * @retval State of bit (1 or 0).
1482 */
LL_PWR_IsActiveFlag_WU5(void)1483 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1484 {
1485 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL);
1486 }
1487 #endif /* PWR_WUSR_WUF5 */
1488
1489 /**
1490 * @brief Indicate whether a wakeup event is detected on wake up pin 6.
1491 * @rmtoll WUSR WUF6 LL_PWR_IsActiveFlag_WU6
1492 * @retval State of bit (1 or 0).
1493 */
LL_PWR_IsActiveFlag_WU6(void)1494 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
1495 {
1496 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL);
1497 }
1498
1499 /**
1500 * @brief Indicate whether a wakeup event is detected on wake up pin 7.
1501 * @rmtoll WUSR WUF7 LL_PWR_IsActiveFlag_WU7
1502 * @retval State of bit (1 or 0).
1503 */
LL_PWR_IsActiveFlag_WU7(void)1504 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void)
1505 {
1506 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL);
1507 }
1508
1509 /**
1510 * @brief Indicate whether a wakeup event is detected on wake up pin 8.
1511 * @rmtoll WUSR WUF8 LL_PWR_IsActiveFlag_WU8
1512 * @retval State of bit (1 or 0).
1513 */
LL_PWR_IsActiveFlag_WU8(void)1514 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void)
1515 {
1516 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL);
1517 }
1518
1519 /**
1520 * @brief Clear stop flag.
1521 * @rmtoll SR CSSF LL_PWR_ClearFlag_STOP
1522 * @retval None
1523 */
LL_PWR_ClearFlag_STOP(void)1524 __STATIC_INLINE void LL_PWR_ClearFlag_STOP(void)
1525 {
1526 WRITE_REG(PWR->SR, PWR_SR_CSSF);
1527 }
1528
1529 /**
1530 * @brief Clear standby flag.
1531 * @rmtoll SR CSSF LL_PWR_ClearFlag_SB
1532 * @retval None
1533 */
LL_PWR_ClearFlag_SB(void)1534 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
1535 {
1536 WRITE_REG(PWR->SR, PWR_SR_CSSF);
1537 }
1538
1539 /**
1540 * @brief Clear wake up flag 1.
1541 * @rmtoll WUSCR CWUF1 LL_PWR_ClearFlag_WU1
1542 * @retval None
1543 */
LL_PWR_ClearFlag_WU1(void)1544 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1545 {
1546 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1);
1547 }
1548
1549 #if defined(PWR_WUSCR_CWUF2)
1550 /**
1551 * @brief Clear wake up flag 2.
1552 * @rmtoll WUSCR CWUF2 LL_PWR_ClearFlag_WU2
1553 * @retval None
1554 */
LL_PWR_ClearFlag_WU2(void)1555 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1556 {
1557 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2);
1558 }
1559 #endif /* PWR_WUSCR_CWUF2 */
1560
1561 /**
1562 * @brief Clear wake up flag 3.
1563 * @rmtoll WUSCR CWUF3 LL_PWR_ClearFlag_WU3
1564 * @retval None
1565 */
LL_PWR_ClearFlag_WU3(void)1566 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1567 {
1568 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3);
1569 }
1570
1571 /**
1572 * @brief Clear wake up flag 4.
1573 * @rmtoll WUSCR CWUF4 LL_PWR_ClearFlag_WU4
1574 * @retval None
1575 */
LL_PWR_ClearFlag_WU4(void)1576 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1577 {
1578 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4);
1579 }
1580
1581 #if defined(PWR_WUSCR_CWUF5)
1582 /**
1583 * @brief Clear wake up flag 5.
1584 * @rmtoll WUSCR CWUF5 LL_PWR_ClearFlag_WU5
1585 * @retval None
1586 */
LL_PWR_ClearFlag_WU5(void)1587 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1588 {
1589 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5);
1590 }
1591 #endif /* PWR_WUSCR_CWUF5 */
1592
1593 /**
1594 * @brief Clear wake up flag 6.
1595 * @rmtoll WUSCR CWUF6 LL_PWR_ClearFlag_WU6
1596 * @retval None
1597 */
LL_PWR_ClearFlag_WU6(void)1598 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
1599 {
1600 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6);
1601 }
1602
1603 /**
1604 * @brief Clear wake up flag 7.
1605 * @rmtoll WUSCR CWUF7 LL_PWR_ClearFlag_WU7
1606 * @retval None
1607 */
LL_PWR_ClearFlag_WU7(void)1608 __STATIC_INLINE void LL_PWR_ClearFlag_WU7(void)
1609 {
1610 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7);
1611 }
1612
1613 /**
1614 * @brief Clear wake up flag 8.
1615 * @rmtoll WUSCR CWUF8 LL_PWR_ClearFlag_WU8
1616 * @retval None
1617 */
LL_PWR_ClearFlag_WU8(void)1618 __STATIC_INLINE void LL_PWR_ClearFlag_WU8(void)
1619 {
1620 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF8);
1621 }
1622
1623 /**
1624 * @brief Clear all wake up flags.
1625 * @rmtoll WUSCR CWUF LL_PWR_ClearFlag_WU
1626 * @retval None
1627 */
LL_PWR_ClearFlag_WU(void)1628 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1629 {
1630 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF);
1631 }
1632 /**
1633 * @}
1634 */
1635
1636 /** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management
1637 * @{
1638 */
1639
1640 #if defined(PWR_PRIVCFGR_NSPRIV)
1641 /**
1642 * @brief Enable privileged mode for nsecure items.
1643 * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege
1644 * @retval None
1645 */
LL_PWR_EnableNSecurePrivilege(void)1646 __STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void)
1647 {
1648 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
1649 }
1650
1651 /**
1652 * @brief Disable privileged mode for nsecure items.
1653 * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege
1654 * @retval None
1655 */
LL_PWR_DisableNSecurePrivilege(void)1656 __STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void)
1657 {
1658 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
1659 }
1660
1661 /**
1662 * @brief Check if privileged mode for nsecure items is enabled.
1663 * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege
1664 * @retval State of bit (1 or 0).
1665 */
LL_PWR_IsEnabledNSecurePrivilege(void)1666 __STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void)
1667 {
1668 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV) == PWR_PRIVCFGR_NSPRIV) ? 1UL : 0UL);
1669 }
1670 #endif /* PWR_PRIVCFGR_NSPRIV */
1671
1672 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1673 /**
1674 * @brief Enable privileged mode for secure items.
1675 * @rmtoll PRIVCFGR SPRIV LL_PWR_EnableSecurePrivilege
1676 * @retval None
1677 */
LL_PWR_EnableSecurePrivilege(void)1678 __STATIC_INLINE void LL_PWR_EnableSecurePrivilege(void)
1679 {
1680 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
1681 }
1682
1683 /**
1684 * @brief Disable privileged mode for secure items.
1685 * @rmtoll PRIVCFGR SPRIV LL_PWR_DisableSecurePrivilege
1686 * @retval None
1687 */
LL_PWR_DisableSecurePrivilege(void)1688 __STATIC_INLINE void LL_PWR_DisableSecurePrivilege(void)
1689 {
1690 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
1691 }
1692 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1693
1694 #if defined(PWR_PRIVCFGR_NSPRIV)
1695 /**
1696 * @brief Check if privileged mode for secure items is enabled.
1697 * @rmtoll PRIVCFGR SPRIV LL_PWR_IsEnabledSecurePrivilege
1698 * @retval State of bit (1 or 0).
1699 */
LL_PWR_IsEnabledSecurePrivilege(void)1700 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSecurePrivilege(void)
1701 {
1702 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV) == PWR_PRIVCFGR_SPRIV) ? 1UL : 0UL);
1703 }
1704 #endif /* PWR_PRIVCFGR_NSPRIV */
1705
1706 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1707 /**
1708 * @brief Configure secure attribute mode.
1709 * @note This API can be executed only by CPU in secure mode.
1710 * @rmtoll SECCFGR WUP1SEC LL_PWR_ConfigSecure\n
1711 * SECCFGR WUP2SEC LL_PWR_ConfigSecure\n
1712 * SECCFGR WUP3SEC LL_PWR_ConfigSecure\n
1713 * SECCFGR WUP4SEC LL_PWR_ConfigSecure\n
1714 * SECCFGR WUP5SEC LL_PWR_ConfigSecure\n
1715 * SECCFGR WUP6SEC LL_PWR_ConfigSecure\n
1716 * SECCFGR WUP7SEC LL_PWR_ConfigSecure\n
1717 * SECCFGR WUP8SEC LL_PWR_ConfigSecure\n
1718 * SECCFGR LPMSEC LL_PWR_ConfigSecure\n
1719 * SECCFGR VDMSEC LL_PWR_ConfigSecure\n
1720 * SECCFGR VBSEC LL_PWR_ConfigSecure
1721 * @param SecureConfig This parameter can be the full combination
1722 * of the following values:
1723 * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
1724 * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
1725 * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
1726 * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
1727 * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
1728 * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
1729 * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
1730 * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
1731 * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
1732 * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
1733 * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
1734 * @retval None.
1735 */
LL_PWR_ConfigSecure(uint32_t SecureConfig)1736 __STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig)
1737 {
1738 WRITE_REG(PWR->SECCFGR, SecureConfig);
1739 }
1740
1741 /**
1742 * @brief Get secure attribute configuration.
1743 * @note This API can be executed only by CPU in secure mode.
1744 * @rmtoll SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n
1745 * SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n
1746 * SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n
1747 * SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n
1748 * SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n
1749 * SECCFGR WUP6SEC LL_PWR_GetConfigSecure\n
1750 * SECCFGR WUP7SEC LL_PWR_GetConfigSecure\n
1751 * SECCFGR WUP8SEC LL_PWR_GetConfigSecure\n
1752 * SECCFGR LPMSEC LL_PWR_GetConfigSecure\n
1753 * SECCFGR VDMSEC LL_PWR_GetConfigSecure\n
1754 * SECCFGR VBSEC LL_PWR_GetConfigSecure
1755 * @retval Returned value is the combination of the following values:
1756 * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
1757 * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
1758 * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
1759 * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
1760 * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
1761 * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
1762 * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
1763 * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
1764 * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
1765 * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
1766 * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
1767 */
LL_PWR_GetConfigSecure(void)1768 __STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void)
1769 {
1770 return (READ_REG(PWR->SECCFGR));
1771 }
1772 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1773 /**
1774 * @}
1775 */
1776
1777 #if defined (USE_FULL_LL_DRIVER)
1778 /** @defgroup PWR_LL_EF_Init De-initialization function
1779 * @{
1780 */
1781 ErrorStatus LL_PWR_DeInit(void);
1782 /**
1783 * @}
1784 */
1785 #endif /* defined (USE_FULL_LL_DRIVER) */
1786
1787
1788 /**
1789 * @}
1790 */
1791
1792 /**
1793 * @}
1794 */
1795
1796 #endif /* defined (PWR) */
1797
1798 /**
1799 * @}
1800 */
1801
1802 #ifdef __cplusplus
1803 }
1804 #endif /* __cplusplus */
1805
1806 #endif /* STM32WBAxx_LL_PWR_H */
1807
1808
