1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_lpuart.h
4 * @author MCD Application Team
5 * @brief Header file of LPUART LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBAxx_LL_LPUART_H
21 #define STM32WBAxx_LL_LPUART_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPUART1)
35
36 /** @defgroup LPUART_LL LPUART
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
43 * @{
44 */
45 /* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
46 static const uint16_t LPUART_PRESCALER_TAB[] =
47 {
48 (uint16_t)1,
49 (uint16_t)2,
50 (uint16_t)4,
51 (uint16_t)6,
52 (uint16_t)8,
53 (uint16_t)10,
54 (uint16_t)12,
55 (uint16_t)16,
56 (uint16_t)32,
57 (uint16_t)64,
58 (uint16_t)128,
59 (uint16_t)256
60 };
61 /**
62 * @}
63 */
64
65 /* Private constants ---------------------------------------------------------*/
66 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
67 * @{
68 */
69 /* Defines used in Baud Rate related macros and corresponding register setting computation */
70 #define LPUART_LPUARTDIV_FREQ_MUL 256U
71 #define LPUART_BRR_MASK 0x000FFFFFU
72 #define LPUART_BRR_MIN_VALUE 0x00000300U
73 /**
74 * @}
75 */
76
77
78 /* Private macros ------------------------------------------------------------*/
79 #if defined(USE_FULL_LL_DRIVER)
80 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
81 * @{
82 */
83 /**
84 * @}
85 */
86 #endif /*USE_FULL_LL_DRIVER*/
87
88 /* Exported types ------------------------------------------------------------*/
89 #if defined(USE_FULL_LL_DRIVER)
90 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
91 * @{
92 */
93
94 /**
95 * @brief LL LPUART Init Structure definition
96 */
97 typedef struct
98 {
99 uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
100 This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
101
102 This feature can be modified afterwards using unitary
103 function @ref LL_LPUART_SetPrescaler().*/
104
105 uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
106
107 This feature can be modified afterwards using unitary
108 function @ref LL_LPUART_SetBaudRate().*/
109
110 uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
111 This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
112
113 This feature can be modified afterwards using unitary
114 function @ref LL_LPUART_SetDataWidth().*/
115
116 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
117 This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
118
119 This feature can be modified afterwards using unitary
120 function @ref LL_LPUART_SetStopBitsLength().*/
121
122 uint32_t Parity; /*!< Specifies the parity mode.
123 This parameter can be a value of @ref LPUART_LL_EC_PARITY.
124
125 This feature can be modified afterwards using unitary
126 function @ref LL_LPUART_SetParity().*/
127
128 uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
129 This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
130
131 This feature can be modified afterwards using unitary
132 function @ref LL_LPUART_SetTransferDirection().*/
133
134 uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
135 This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
136
137 This feature can be modified afterwards using unitary
138 function @ref LL_LPUART_SetHWFlowCtrl().*/
139
140 } LL_LPUART_InitTypeDef;
141
142 /**
143 * @}
144 */
145 #endif /* USE_FULL_LL_DRIVER */
146
147 /* Exported constants --------------------------------------------------------*/
148 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
149 * @{
150 */
151
152 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
153 * @brief Flags defines which can be used with LL_LPUART_WriteReg function
154 * @{
155 */
156 #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
157 #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
158 #define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */
159 #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
160 #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
161 #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
162 #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
163 #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
164 /**
165 * @}
166 */
167
168 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
169 * @brief Flags defines which can be used with LL_LPUART_ReadReg function
170 * @{
171 */
172 #define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
173 #define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
174 #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
175 #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
176 #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
177 #define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
178 #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
179 #define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
180 #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
181 #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
182 #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
183 #define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
184 #define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
185 #define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
186 #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
187 #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
188 #define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
189 #define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
190 #define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
191 #define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
192 /**
193 * @}
194 */
195
196 /** @defgroup LPUART_LL_EC_IT IT Defines
197 * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
198 * @{
199 */
200 #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
201 #define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
202 interrupt enable */
203 #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
204 #define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO
205 not full interrupt enable */
206 #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
207 #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
208 #define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
209 #define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
210 #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
211 #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
212 #define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
213 #define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
214 /**
215 * @}
216 */
217
218 /** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
219 * @{
220 */
221 #define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
222 #define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
223 #define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
224 #define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
225 #define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
226 #define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
227 /**
228 * @}
229 */
230
231 /** @defgroup LPUART_LL_EC_DIRECTION Direction
232 * @{
233 */
234 #define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
235 #define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
236 #define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
237 #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
238 /**
239 * @}
240 */
241
242 /** @defgroup LPUART_LL_EC_PARITY Parity Control
243 * @{
244 */
245 #define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
246 #define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
247 #define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
248 /**
249 * @}
250 */
251
252 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
253 * @{
254 */
255 #define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
256 #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
257 /**
258 * @}
259 */
260
261 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
262 * @{
263 */
264 #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
265 #define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
266 #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
267 /**
268 * @}
269 */
270
271 /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
272 * @{
273 */
274 #define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
275 #define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
276 #define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
277 #define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\
278 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
279 #define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
280 #define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\
281 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
282 #define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\
283 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
284 #define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\
285 USART_PRESC_PRESCALER_1 |\
286 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
287 #define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
288 #define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\
289 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
290 #define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
291 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
292 #define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
293 USART_PRESC_PRESCALER_1 |\
294 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
295 /**
296 * @}
297 */
298
299 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
300 * @{
301 */
302 #define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
303 #define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
304 /**
305 * @}
306 */
307
308 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
309 * @{
310 */
311 #define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
312 #define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
313 /**
314 * @}
315 */
316
317 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
318 * @{
319 */
320 #define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
321 #define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
322 /**
323 * @}
324 */
325
326 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
327 * @{
328 */
329 #define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
330 #define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
331 /**
332 * @}
333 */
334
335 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
336 * @{
337 */
338 #define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received
339 in positive/direct logic. (1=H, 0=L) */
340 #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
341 in negative/inverse logic. (1=L, 0=H).
342 The parity bit is also inverted. */
343 /**
344 * @}
345 */
346
347 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
348 * @{
349 */
350 #define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first,
351 following the start bit */
352 #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
353 following the start bit */
354 /**
355 * @}
356 */
357
358 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
359 * @{
360 */
361 #define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
362 #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
363 /**
364 * @}
365 */
366
367 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
368 * @{
369 */
370 #define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
371 #define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested
372 when there is space in the receive buffer */
373 #define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted
374 when the nCTS input is asserted (tied to 0)*/
375 #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
376 /**
377 * @}
378 */
379
380 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
381 * @{
382 */
383 #define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
384 #define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
385 /**
386 * @}
387 */
388
389 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
390 * @{
391 */
392 #define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
393 #define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
394 /**
395 * @}
396 */
397
398 /** @defgroup LPUART_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection
399 * @brief LPUART Autonomous Trigger selection
400 * @{
401 */
402 #define LL_LPUART_GPDMA1_CH0_TCF_TRG 0U /*!< LPUART GPDMA1 channel0 Internal Trigger */
403 #define LL_LPUART_GPDMA1_CH1_TCF_TRG 1U /*!< LPUART GPDMA1 channel1 Internal Trigger */
404 #define LL_LPUART_GPDMA1_CH2_TCF_TRG 2U /*!< LPUART GPDMA1 channel2 Internal Trigger */
405 #define LL_LPUART_GPDMA1_CH3_TCF_TRG 3U /*!< LPUART GPDMA1 channel3 Internal Trigger */
406 #define LL_LPUART_EXTI_LINE6_TRG 4U /*!< LPUART EXTI line 6 Internal Trigger */
407 #define LL_LPUART_EXTI_LINE8_TRG 5U /*!< LPUART EXTI line 8 Internal Trigger */
408 #define LL_LPUART_LPTIM1_OUT_TRG 6U /*!< LPUART LPTIM1 out Internal Trigger */
409 #if defined(COMP12_COMMON)
410 #define LL_LPUART_COMP1_OUT_TRG 8U /*!< LPUART COMP1 out Internal Trigger */
411 #define LL_LPUART_COMP2_OUT_TRG 9U /*!< LPUART COMP2 out Internal Trigger */
412 #endif /* COMP12_COMMON */
413 #define LL_LPUART_RTC_ALRA_TRG 10U /*!< LPUART RTC alarm Internal Trigger */
414 #define LL_LPUART_RTC_WUT_TRG 11U /*!< LPUART RTC wakeup Internal Trigger */
415 /**
416 * @}
417 */
418
419 /** @defgroup LPUART_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity
420 * @brief LPUART Autonomous Trigger Polarity
421 * @{
422 */
423 #define LL_LPUART_TRIG_POLARITY_RISING 0x00000000U /*!< LPUART triggered on rising edge */
424 #define LL_LPUART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< LPUART triggered on falling edge */
425 /**
426 * @}
427 */
428 /**
429 * @}
430 */
431
432 /* Exported macro ------------------------------------------------------------*/
433 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
434 * @{
435 */
436
437 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
438 * @{
439 */
440
441 /**
442 * @brief Write a value in LPUART register
443 * @param __INSTANCE__ LPUART Instance
444 * @param __REG__ Register to be written
445 * @param __VALUE__ Value to be written in the register
446 * @retval None
447 */
448 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
449
450 /**
451 * @brief Read a value in LPUART register
452 * @param __INSTANCE__ LPUART Instance
453 * @param __REG__ Register to be read
454 * @retval Register value
455 */
456 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
457 /**
458 * @}
459 */
460
461 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
462 * @{
463 */
464
465 /**
466 * @brief Compute LPUARTDIV value according to Peripheral Clock and
467 * expected Baud Rate (20-bit value of LPUARTDIV is returned)
468 * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
469 * @param __PRESCALER__ This parameter can be one of the following values:
470 * @arg @ref LL_LPUART_PRESCALER_DIV1
471 * @arg @ref LL_LPUART_PRESCALER_DIV2
472 * @arg @ref LL_LPUART_PRESCALER_DIV4
473 * @arg @ref LL_LPUART_PRESCALER_DIV6
474 * @arg @ref LL_LPUART_PRESCALER_DIV8
475 * @arg @ref LL_LPUART_PRESCALER_DIV10
476 * @arg @ref LL_LPUART_PRESCALER_DIV12
477 * @arg @ref LL_LPUART_PRESCALER_DIV16
478 * @arg @ref LL_LPUART_PRESCALER_DIV32
479 * @arg @ref LL_LPUART_PRESCALER_DIV64
480 * @arg @ref LL_LPUART_PRESCALER_DIV128
481 * @arg @ref LL_LPUART_PRESCALER_DIV256
482 * @param __BAUDRATE__ Baud Rate value to achieve
483 * @retval LPUARTDIV value to be used for BRR register filling
484 */
485 #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
486 ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
487 * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
488
489 /**
490 * @}
491 */
492
493 /**
494 * @}
495 */
496
497 /* Exported functions --------------------------------------------------------*/
498 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
499 * @{
500 */
501
502 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
503 * @{
504 */
505
506 /**
507 * @brief LPUART Enable
508 * @rmtoll CR1 UE LL_LPUART_Enable
509 * @param LPUARTx LPUART Instance
510 * @retval None
511 */
LL_LPUART_Enable(USART_TypeDef * LPUARTx)512 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
513 {
514 SET_BIT(LPUARTx->CR1, USART_CR1_UE);
515 }
516
517 /**
518 * @brief LPUART Disable
519 * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
520 * and current operations are discarded. The configuration of the LPUART is kept, but all the status
521 * flags, in the LPUARTx_ISR are set to their default values.
522 * @note In order to go into low-power mode without generating errors on the line,
523 * the TE bit must be reset before and the software must wait
524 * for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
525 * The DMA requests are also reset when UE = 0 so the DMA channel must
526 * be disabled before resetting the UE bit.
527 * @rmtoll CR1 UE LL_LPUART_Disable
528 * @param LPUARTx LPUART Instance
529 * @retval None
530 */
LL_LPUART_Disable(USART_TypeDef * LPUARTx)531 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
532 {
533 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
534 }
535
536 /**
537 * @brief Indicate if LPUART is enabled
538 * @rmtoll CR1 UE LL_LPUART_IsEnabled
539 * @param LPUARTx LPUART Instance
540 * @retval State of bit (1 or 0).
541 */
LL_LPUART_IsEnabled(const USART_TypeDef * LPUARTx)542 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx)
543 {
544 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
545 }
546
547 /**
548 * @brief FIFO Mode Enable
549 * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
550 * @param LPUARTx LPUART Instance
551 * @retval None
552 */
LL_LPUART_EnableFIFO(USART_TypeDef * LPUARTx)553 __STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
554 {
555 SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
556 }
557
558 /**
559 * @brief FIFO Mode Disable
560 * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
561 * @param LPUARTx LPUART Instance
562 * @retval None
563 */
LL_LPUART_DisableFIFO(USART_TypeDef * LPUARTx)564 __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
565 {
566 CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
567 }
568
569 /**
570 * @brief Indicate if FIFO Mode is enabled
571 * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
572 * @param LPUARTx LPUART Instance
573 * @retval State of bit (1 or 0).
574 */
LL_LPUART_IsEnabledFIFO(const USART_TypeDef * LPUARTx)575 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx)
576 {
577 return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
578 }
579
580 /**
581 * @brief Configure TX FIFO Threshold
582 * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
583 * @param LPUARTx LPUART Instance
584 * @param Threshold This parameter can be one of the following values:
585 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
586 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
587 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
588 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
589 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
590 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
591 * @retval None
592 */
LL_LPUART_SetTXFIFOThreshold(USART_TypeDef * LPUARTx,uint32_t Threshold)593 __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
594 {
595 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
596 }
597
598 /**
599 * @brief Return TX FIFO Threshold Configuration
600 * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
601 * @param LPUARTx LPUART Instance
602 * @retval Returned value can be one of the following values:
603 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
604 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
605 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
606 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
607 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
608 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
609 */
LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef * LPUARTx)610 __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx)
611 {
612 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
613 }
614
615 /**
616 * @brief Configure RX FIFO Threshold
617 * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
618 * @param LPUARTx LPUART Instance
619 * @param Threshold This parameter can be one of the following values:
620 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
621 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
622 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
623 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
624 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
625 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
626 * @retval None
627 */
LL_LPUART_SetRXFIFOThreshold(USART_TypeDef * LPUARTx,uint32_t Threshold)628 __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
629 {
630 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
631 }
632
633 /**
634 * @brief Return RX FIFO Threshold Configuration
635 * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
636 * @param LPUARTx LPUART Instance
637 * @retval Returned value can be one of the following values:
638 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
639 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
640 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
641 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
642 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
643 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
644 */
LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef * LPUARTx)645 __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx)
646 {
647 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
648 }
649
650 /**
651 * @brief Configure TX and RX FIFOs Threshold
652 * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
653 * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
654 * @param LPUARTx LPUART Instance
655 * @param TXThreshold This parameter can be one of the following values:
656 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
657 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
658 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
659 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
660 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
661 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
662 * @param RXThreshold This parameter can be one of the following values:
663 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
664 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
665 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
666 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
667 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
668 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
669 * @retval None
670 */
LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef * LPUARTx,uint32_t TXThreshold,uint32_t RXThreshold)671 __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
672 {
673 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
674 (RXThreshold << USART_CR3_RXFTCFG_Pos));
675 }
676
677 /**
678 * @brief LPUART enabled in STOP Mode
679 * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
680 * LPUART clock selection is HSI or LSE in RCC.
681 * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
682 * @param LPUARTx LPUART Instance
683 * @retval None
684 */
LL_LPUART_EnableInStopMode(USART_TypeDef * LPUARTx)685 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
686 {
687 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
688 }
689
690 /**
691 * @brief LPUART disabled in STOP Mode
692 * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
693 * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
694 * @param LPUARTx LPUART Instance
695 * @retval None
696 */
LL_LPUART_DisableInStopMode(USART_TypeDef * LPUARTx)697 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
698 {
699 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
700 }
701
702 /**
703 * @brief Indicate if LPUART is enabled in STOP Mode
704 * (able to wake up MCU from Stop mode or not)
705 * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
706 * @param LPUARTx LPUART Instance
707 * @retval State of bit (1 or 0).
708 */
LL_LPUART_IsEnabledInStopMode(const USART_TypeDef * LPUARTx)709 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx)
710 {
711 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
712 }
713
714 /**
715 * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
716 * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
717 * @param LPUARTx LPUART Instance
718 * @retval None
719 */
LL_LPUART_EnableDirectionRx(USART_TypeDef * LPUARTx)720 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
721 {
722 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
723 }
724
725 /**
726 * @brief Receiver Disable
727 * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
728 * @param LPUARTx LPUART Instance
729 * @retval None
730 */
LL_LPUART_DisableDirectionRx(USART_TypeDef * LPUARTx)731 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
732 {
733 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
734 }
735
736 /**
737 * @brief Transmitter Enable
738 * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
739 * @param LPUARTx LPUART Instance
740 * @retval None
741 */
LL_LPUART_EnableDirectionTx(USART_TypeDef * LPUARTx)742 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
743 {
744 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
745 }
746
747 /**
748 * @brief Transmitter Disable
749 * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
750 * @param LPUARTx LPUART Instance
751 * @retval None
752 */
LL_LPUART_DisableDirectionTx(USART_TypeDef * LPUARTx)753 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
754 {
755 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
756 }
757
758 /**
759 * @brief Configure simultaneously enabled/disabled states
760 * of Transmitter and Receiver
761 * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
762 * CR1 TE LL_LPUART_SetTransferDirection
763 * @param LPUARTx LPUART Instance
764 * @param TransferDirection This parameter can be one of the following values:
765 * @arg @ref LL_LPUART_DIRECTION_NONE
766 * @arg @ref LL_LPUART_DIRECTION_RX
767 * @arg @ref LL_LPUART_DIRECTION_TX
768 * @arg @ref LL_LPUART_DIRECTION_TX_RX
769 * @retval None
770 */
LL_LPUART_SetTransferDirection(USART_TypeDef * LPUARTx,uint32_t TransferDirection)771 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
772 {
773 ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
774 }
775
776 /**
777 * @brief Return enabled/disabled states of Transmitter and Receiver
778 * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
779 * CR1 TE LL_LPUART_GetTransferDirection
780 * @param LPUARTx LPUART Instance
781 * @retval Returned value can be one of the following values:
782 * @arg @ref LL_LPUART_DIRECTION_NONE
783 * @arg @ref LL_LPUART_DIRECTION_RX
784 * @arg @ref LL_LPUART_DIRECTION_TX
785 * @arg @ref LL_LPUART_DIRECTION_TX_RX
786 */
LL_LPUART_GetTransferDirection(const USART_TypeDef * LPUARTx)787 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx)
788 {
789 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
790 }
791
792 /**
793 * @brief Configure Parity (enabled/disabled and parity mode if enabled)
794 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
795 * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
796 * (depending on data width) and parity is checked on the received data.
797 * @rmtoll CR1 PS LL_LPUART_SetParity\n
798 * CR1 PCE LL_LPUART_SetParity
799 * @param LPUARTx LPUART Instance
800 * @param Parity This parameter can be one of the following values:
801 * @arg @ref LL_LPUART_PARITY_NONE
802 * @arg @ref LL_LPUART_PARITY_EVEN
803 * @arg @ref LL_LPUART_PARITY_ODD
804 * @retval None
805 */
LL_LPUART_SetParity(USART_TypeDef * LPUARTx,uint32_t Parity)806 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
807 {
808 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
809 }
810
811 /**
812 * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
813 * @rmtoll CR1 PS LL_LPUART_GetParity\n
814 * CR1 PCE LL_LPUART_GetParity
815 * @param LPUARTx LPUART Instance
816 * @retval Returned value can be one of the following values:
817 * @arg @ref LL_LPUART_PARITY_NONE
818 * @arg @ref LL_LPUART_PARITY_EVEN
819 * @arg @ref LL_LPUART_PARITY_ODD
820 */
LL_LPUART_GetParity(const USART_TypeDef * LPUARTx)821 __STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx)
822 {
823 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
824 }
825
826 /**
827 * @brief Set Receiver Wake Up method from Mute mode.
828 * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
829 * @param LPUARTx LPUART Instance
830 * @param Method This parameter can be one of the following values:
831 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
832 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
833 * @retval None
834 */
LL_LPUART_SetWakeUpMethod(USART_TypeDef * LPUARTx,uint32_t Method)835 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
836 {
837 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
838 }
839
840 /**
841 * @brief Return Receiver Wake Up method from Mute mode
842 * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
843 * @param LPUARTx LPUART Instance
844 * @retval Returned value can be one of the following values:
845 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
846 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
847 */
LL_LPUART_GetWakeUpMethod(const USART_TypeDef * LPUARTx)848 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx)
849 {
850 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
851 }
852
853 /**
854 * @brief Set Word length (nb of data bits, excluding start and stop bits)
855 * @rmtoll CR1 M LL_LPUART_SetDataWidth
856 * @param LPUARTx LPUART Instance
857 * @param DataWidth This parameter can be one of the following values:
858 * @arg @ref LL_LPUART_DATAWIDTH_7B
859 * @arg @ref LL_LPUART_DATAWIDTH_8B
860 * @arg @ref LL_LPUART_DATAWIDTH_9B
861 * @retval None
862 */
LL_LPUART_SetDataWidth(USART_TypeDef * LPUARTx,uint32_t DataWidth)863 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
864 {
865 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
866 }
867
868 /**
869 * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
870 * @rmtoll CR1 M LL_LPUART_GetDataWidth
871 * @param LPUARTx LPUART Instance
872 * @retval Returned value can be one of the following values:
873 * @arg @ref LL_LPUART_DATAWIDTH_7B
874 * @arg @ref LL_LPUART_DATAWIDTH_8B
875 * @arg @ref LL_LPUART_DATAWIDTH_9B
876 */
LL_LPUART_GetDataWidth(const USART_TypeDef * LPUARTx)877 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx)
878 {
879 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
880 }
881
882 /**
883 * @brief Allow switch between Mute Mode and Active mode
884 * @rmtoll CR1 MME LL_LPUART_EnableMuteMode
885 * @param LPUARTx LPUART Instance
886 * @retval None
887 */
LL_LPUART_EnableMuteMode(USART_TypeDef * LPUARTx)888 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
889 {
890 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
891 }
892
893 /**
894 * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
895 * @rmtoll CR1 MME LL_LPUART_DisableMuteMode
896 * @param LPUARTx LPUART Instance
897 * @retval None
898 */
LL_LPUART_DisableMuteMode(USART_TypeDef * LPUARTx)899 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
900 {
901 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
902 }
903
904 /**
905 * @brief Indicate if switch between Mute Mode and Active mode is allowed
906 * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
907 * @param LPUARTx LPUART Instance
908 * @retval State of bit (1 or 0).
909 */
LL_LPUART_IsEnabledMuteMode(const USART_TypeDef * LPUARTx)910 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx)
911 {
912 return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
913 }
914
915 /**
916 * @brief Configure Clock source prescaler for baudrate generator and oversampling
917 * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
918 * @param LPUARTx LPUART Instance
919 * @param PrescalerValue This parameter can be one of the following values:
920 * @arg @ref LL_LPUART_PRESCALER_DIV1
921 * @arg @ref LL_LPUART_PRESCALER_DIV2
922 * @arg @ref LL_LPUART_PRESCALER_DIV4
923 * @arg @ref LL_LPUART_PRESCALER_DIV6
924 * @arg @ref LL_LPUART_PRESCALER_DIV8
925 * @arg @ref LL_LPUART_PRESCALER_DIV10
926 * @arg @ref LL_LPUART_PRESCALER_DIV12
927 * @arg @ref LL_LPUART_PRESCALER_DIV16
928 * @arg @ref LL_LPUART_PRESCALER_DIV32
929 * @arg @ref LL_LPUART_PRESCALER_DIV64
930 * @arg @ref LL_LPUART_PRESCALER_DIV128
931 * @arg @ref LL_LPUART_PRESCALER_DIV256
932 * @retval None
933 */
LL_LPUART_SetPrescaler(USART_TypeDef * LPUARTx,uint32_t PrescalerValue)934 __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
935 {
936 MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
937 }
938
939 /**
940 * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
941 * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
942 * @param LPUARTx LPUART Instance
943 * @retval Returned value can be one of the following values:
944 * @arg @ref LL_LPUART_PRESCALER_DIV1
945 * @arg @ref LL_LPUART_PRESCALER_DIV2
946 * @arg @ref LL_LPUART_PRESCALER_DIV4
947 * @arg @ref LL_LPUART_PRESCALER_DIV6
948 * @arg @ref LL_LPUART_PRESCALER_DIV8
949 * @arg @ref LL_LPUART_PRESCALER_DIV10
950 * @arg @ref LL_LPUART_PRESCALER_DIV12
951 * @arg @ref LL_LPUART_PRESCALER_DIV16
952 * @arg @ref LL_LPUART_PRESCALER_DIV32
953 * @arg @ref LL_LPUART_PRESCALER_DIV64
954 * @arg @ref LL_LPUART_PRESCALER_DIV128
955 * @arg @ref LL_LPUART_PRESCALER_DIV256
956 */
LL_LPUART_GetPrescaler(const USART_TypeDef * LPUARTx)957 __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx)
958 {
959 return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
960 }
961
962 /**
963 * @brief Set the length of the stop bits
964 * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
965 * @param LPUARTx LPUART Instance
966 * @param StopBits This parameter can be one of the following values:
967 * @arg @ref LL_LPUART_STOPBITS_1
968 * @arg @ref LL_LPUART_STOPBITS_2
969 * @retval None
970 */
LL_LPUART_SetStopBitsLength(USART_TypeDef * LPUARTx,uint32_t StopBits)971 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
972 {
973 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
974 }
975
976 /**
977 * @brief Retrieve the length of the stop bits
978 * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
979 * @param LPUARTx LPUART Instance
980 * @retval Returned value can be one of the following values:
981 * @arg @ref LL_LPUART_STOPBITS_1
982 * @arg @ref LL_LPUART_STOPBITS_2
983 */
LL_LPUART_GetStopBitsLength(const USART_TypeDef * LPUARTx)984 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx)
985 {
986 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
987 }
988
989 /**
990 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
991 * @note Call of this function is equivalent to following function call sequence :
992 * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
993 * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
994 * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
995 * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
996 * CR1 PCE LL_LPUART_ConfigCharacter\n
997 * CR1 M LL_LPUART_ConfigCharacter\n
998 * CR2 STOP LL_LPUART_ConfigCharacter
999 * @param LPUARTx LPUART Instance
1000 * @param DataWidth This parameter can be one of the following values:
1001 * @arg @ref LL_LPUART_DATAWIDTH_7B
1002 * @arg @ref LL_LPUART_DATAWIDTH_8B
1003 * @arg @ref LL_LPUART_DATAWIDTH_9B
1004 * @param Parity This parameter can be one of the following values:
1005 * @arg @ref LL_LPUART_PARITY_NONE
1006 * @arg @ref LL_LPUART_PARITY_EVEN
1007 * @arg @ref LL_LPUART_PARITY_ODD
1008 * @param StopBits This parameter can be one of the following values:
1009 * @arg @ref LL_LPUART_STOPBITS_1
1010 * @arg @ref LL_LPUART_STOPBITS_2
1011 * @retval None
1012 */
LL_LPUART_ConfigCharacter(USART_TypeDef * LPUARTx,uint32_t DataWidth,uint32_t Parity,uint32_t StopBits)1013 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
1014 uint32_t StopBits)
1015 {
1016 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
1017 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
1018 }
1019
1020 /**
1021 * @brief Configure TX/RX pins swapping setting.
1022 * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
1023 * @param LPUARTx LPUART Instance
1024 * @param SwapConfig This parameter can be one of the following values:
1025 * @arg @ref LL_LPUART_TXRX_STANDARD
1026 * @arg @ref LL_LPUART_TXRX_SWAPPED
1027 * @retval None
1028 */
LL_LPUART_SetTXRXSwap(USART_TypeDef * LPUARTx,uint32_t SwapConfig)1029 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
1030 {
1031 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
1032 }
1033
1034 /**
1035 * @brief Retrieve TX/RX pins swapping configuration.
1036 * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
1037 * @param LPUARTx LPUART Instance
1038 * @retval Returned value can be one of the following values:
1039 * @arg @ref LL_LPUART_TXRX_STANDARD
1040 * @arg @ref LL_LPUART_TXRX_SWAPPED
1041 */
LL_LPUART_GetTXRXSwap(const USART_TypeDef * LPUARTx)1042 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx)
1043 {
1044 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
1045 }
1046
1047 /**
1048 * @brief Configure RX pin active level logic
1049 * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
1050 * @param LPUARTx LPUART Instance
1051 * @param PinInvMethod This parameter can be one of the following values:
1052 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1053 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1054 * @retval None
1055 */
LL_LPUART_SetRXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)1056 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1057 {
1058 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
1059 }
1060
1061 /**
1062 * @brief Retrieve RX pin active level logic configuration
1063 * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
1064 * @param LPUARTx LPUART Instance
1065 * @retval Returned value can be one of the following values:
1066 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1067 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1068 */
LL_LPUART_GetRXPinLevel(const USART_TypeDef * LPUARTx)1069 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx)
1070 {
1071 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
1072 }
1073
1074 /**
1075 * @brief Configure TX pin active level logic
1076 * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
1077 * @param LPUARTx LPUART Instance
1078 * @param PinInvMethod This parameter can be one of the following values:
1079 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1080 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1081 * @retval None
1082 */
LL_LPUART_SetTXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)1083 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1084 {
1085 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
1086 }
1087
1088 /**
1089 * @brief Retrieve TX pin active level logic configuration
1090 * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
1091 * @param LPUARTx LPUART Instance
1092 * @retval Returned value can be one of the following values:
1093 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1094 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1095 */
LL_LPUART_GetTXPinLevel(const USART_TypeDef * LPUARTx)1096 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx)
1097 {
1098 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
1099 }
1100
1101 /**
1102 * @brief Configure Binary data logic.
1103 *
1104 * @note Allow to define how Logical data from the data register are send/received :
1105 * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
1106 * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
1107 * @param LPUARTx LPUART Instance
1108 * @param DataLogic This parameter can be one of the following values:
1109 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1110 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1111 * @retval None
1112 */
LL_LPUART_SetBinaryDataLogic(USART_TypeDef * LPUARTx,uint32_t DataLogic)1113 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
1114 {
1115 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
1116 }
1117
1118 /**
1119 * @brief Retrieve Binary data configuration
1120 * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
1121 * @param LPUARTx LPUART Instance
1122 * @retval Returned value can be one of the following values:
1123 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1124 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1125 */
LL_LPUART_GetBinaryDataLogic(const USART_TypeDef * LPUARTx)1126 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx)
1127 {
1128 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
1129 }
1130
1131 /**
1132 * @brief Configure transfer bit order (either Less or Most Significant Bit First)
1133 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1134 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1135 * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
1136 * @param LPUARTx LPUART Instance
1137 * @param BitOrder This parameter can be one of the following values:
1138 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1139 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1140 * @retval None
1141 */
LL_LPUART_SetTransferBitOrder(USART_TypeDef * LPUARTx,uint32_t BitOrder)1142 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
1143 {
1144 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
1145 }
1146
1147 /**
1148 * @brief Return transfer bit order (either Less or Most Significant Bit First)
1149 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1150 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1151 * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
1152 * @param LPUARTx LPUART Instance
1153 * @retval Returned value can be one of the following values:
1154 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1155 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1156 */
LL_LPUART_GetTransferBitOrder(const USART_TypeDef * LPUARTx)1157 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx)
1158 {
1159 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
1160 }
1161
1162 /**
1163 * @brief Set Address of the LPUART node.
1164 * @note This is used in multiprocessor communication during Mute mode or Stop mode,
1165 * for wake up with address mark detection.
1166 * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
1167 * (b7-b4 should be set to 0)
1168 * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
1169 * (This is used in multiprocessor communication during Mute mode or Stop mode,
1170 * for wake up with 7-bit address mark detection.
1171 * The MSB of the character sent by the transmitter should be equal to 1.
1172 * It may also be used for character detection during normal reception,
1173 * Mute mode inactive (for example, end of block detection in ModBus protocol).
1174 * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
1175 * value and CMF flag is set on match)
1176 * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
1177 * CR2 ADDM7 LL_LPUART_ConfigNodeAddress
1178 * @param LPUARTx LPUART Instance
1179 * @param AddressLen This parameter can be one of the following values:
1180 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1181 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1182 * @param NodeAddress 4 or 7 bit Address of the LPUART node.
1183 * @retval None
1184 */
LL_LPUART_ConfigNodeAddress(USART_TypeDef * LPUARTx,uint32_t AddressLen,uint32_t NodeAddress)1185 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
1186 {
1187 MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
1188 (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
1189 }
1190
1191 /**
1192 * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
1193 * @note If 4-bit Address Detection is selected in ADDM7,
1194 * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
1195 * If 7-bit Address Detection is selected in ADDM7,
1196 * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
1197 * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
1198 * @param LPUARTx LPUART Instance
1199 * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
1200 */
LL_LPUART_GetNodeAddress(const USART_TypeDef * LPUARTx)1201 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx)
1202 {
1203 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
1204 }
1205
1206 /**
1207 * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
1208 * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
1209 * @param LPUARTx LPUART Instance
1210 * @retval Returned value can be one of the following values:
1211 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1212 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1213 */
LL_LPUART_GetNodeAddressLen(const USART_TypeDef * LPUARTx)1214 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx)
1215 {
1216 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
1217 }
1218
1219 /**
1220 * @brief Enable RTS HW Flow Control
1221 * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
1222 * @param LPUARTx LPUART Instance
1223 * @retval None
1224 */
LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)1225 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1226 {
1227 SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1228 }
1229
1230 /**
1231 * @brief Disable RTS HW Flow Control
1232 * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
1233 * @param LPUARTx LPUART Instance
1234 * @retval None
1235 */
LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)1236 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1237 {
1238 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1239 }
1240
1241 /**
1242 * @brief Enable CTS HW Flow Control
1243 * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
1244 * @param LPUARTx LPUART Instance
1245 * @retval None
1246 */
LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)1247 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1248 {
1249 SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1250 }
1251
1252 /**
1253 * @brief Disable CTS HW Flow Control
1254 * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
1255 * @param LPUARTx LPUART Instance
1256 * @retval None
1257 */
LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)1258 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1259 {
1260 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1261 }
1262
1263 /**
1264 * @brief Configure HW Flow Control mode (both CTS and RTS)
1265 * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
1266 * CR3 CTSE LL_LPUART_SetHWFlowCtrl
1267 * @param LPUARTx LPUART Instance
1268 * @param HardwareFlowControl This parameter can be one of the following values:
1269 * @arg @ref LL_LPUART_HWCONTROL_NONE
1270 * @arg @ref LL_LPUART_HWCONTROL_RTS
1271 * @arg @ref LL_LPUART_HWCONTROL_CTS
1272 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1273 * @retval None
1274 */
LL_LPUART_SetHWFlowCtrl(USART_TypeDef * LPUARTx,uint32_t HardwareFlowControl)1275 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
1276 {
1277 MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
1278 }
1279
1280 /**
1281 * @brief Return HW Flow Control configuration (both CTS and RTS)
1282 * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
1283 * CR3 CTSE LL_LPUART_GetHWFlowCtrl
1284 * @param LPUARTx LPUART Instance
1285 * @retval Returned value can be one of the following values:
1286 * @arg @ref LL_LPUART_HWCONTROL_NONE
1287 * @arg @ref LL_LPUART_HWCONTROL_RTS
1288 * @arg @ref LL_LPUART_HWCONTROL_CTS
1289 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1290 */
LL_LPUART_GetHWFlowCtrl(const USART_TypeDef * LPUARTx)1291 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx)
1292 {
1293 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
1294 }
1295
1296 /**
1297 * @brief Enable Overrun detection
1298 * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
1299 * @param LPUARTx LPUART Instance
1300 * @retval None
1301 */
LL_LPUART_EnableOverrunDetect(USART_TypeDef * LPUARTx)1302 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
1303 {
1304 CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1305 }
1306
1307 /**
1308 * @brief Disable Overrun detection
1309 * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
1310 * @param LPUARTx LPUART Instance
1311 * @retval None
1312 */
LL_LPUART_DisableOverrunDetect(USART_TypeDef * LPUARTx)1313 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
1314 {
1315 SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1316 }
1317
1318 /**
1319 * @brief Indicate if Overrun detection is enabled
1320 * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
1321 * @param LPUARTx LPUART Instance
1322 * @retval State of bit (1 or 0).
1323 */
LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef * LPUARTx)1324 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx)
1325 {
1326 return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
1327 }
1328
1329 /**
1330 * @brief Configure LPUART BRR register for achieving expected Baud Rate value.
1331 *
1332 * @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
1333 * according to used Peripheral Clock and expected Baud Rate values
1334 * @note Peripheral clock and Baud Rate values provided as function parameters should be valid
1335 * (Baud rate value != 0).
1336 * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
1337 * a care should be taken when generating high baud rates using high PeriphClk
1338 * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
1339 * @rmtoll BRR BRR LL_LPUART_SetBaudRate
1340 * @param LPUARTx LPUART Instance
1341 * @param PeriphClk Peripheral Clock
1342 * @param PrescalerValue This parameter can be one of the following values:
1343 * @arg @ref LL_LPUART_PRESCALER_DIV1
1344 * @arg @ref LL_LPUART_PRESCALER_DIV2
1345 * @arg @ref LL_LPUART_PRESCALER_DIV4
1346 * @arg @ref LL_LPUART_PRESCALER_DIV6
1347 * @arg @ref LL_LPUART_PRESCALER_DIV8
1348 * @arg @ref LL_LPUART_PRESCALER_DIV10
1349 * @arg @ref LL_LPUART_PRESCALER_DIV12
1350 * @arg @ref LL_LPUART_PRESCALER_DIV16
1351 * @arg @ref LL_LPUART_PRESCALER_DIV32
1352 * @arg @ref LL_LPUART_PRESCALER_DIV64
1353 * @arg @ref LL_LPUART_PRESCALER_DIV128
1354 * @arg @ref LL_LPUART_PRESCALER_DIV256
1355 * @param BaudRate Baud Rate
1356 * @retval None
1357 */
LL_LPUART_SetBaudRate(USART_TypeDef * LPUARTx,uint32_t PeriphClk,uint32_t PrescalerValue,uint32_t BaudRate)1358 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
1359 uint32_t BaudRate)
1360 {
1361 if (BaudRate != 0U)
1362 {
1363 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
1364 }
1365 }
1366
1367 /**
1368 * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
1369 * (full BRR content), and to used Peripheral Clock values
1370 * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
1371 * @rmtoll BRR BRR LL_LPUART_GetBaudRate
1372 * @param LPUARTx LPUART Instance
1373 * @param PeriphClk Peripheral Clock
1374 * @param PrescalerValue This parameter can be one of the following values:
1375 * @arg @ref LL_LPUART_PRESCALER_DIV1
1376 * @arg @ref LL_LPUART_PRESCALER_DIV2
1377 * @arg @ref LL_LPUART_PRESCALER_DIV4
1378 * @arg @ref LL_LPUART_PRESCALER_DIV6
1379 * @arg @ref LL_LPUART_PRESCALER_DIV8
1380 * @arg @ref LL_LPUART_PRESCALER_DIV10
1381 * @arg @ref LL_LPUART_PRESCALER_DIV12
1382 * @arg @ref LL_LPUART_PRESCALER_DIV16
1383 * @arg @ref LL_LPUART_PRESCALER_DIV32
1384 * @arg @ref LL_LPUART_PRESCALER_DIV64
1385 * @arg @ref LL_LPUART_PRESCALER_DIV128
1386 * @arg @ref LL_LPUART_PRESCALER_DIV256
1387 * @retval Baud Rate
1388 */
LL_LPUART_GetBaudRate(const USART_TypeDef * LPUARTx,uint32_t PeriphClk,uint32_t PrescalerValue)1389 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
1390 uint32_t PrescalerValue)
1391 {
1392 uint32_t lpuartdiv;
1393 uint32_t brrresult;
1394 uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
1395
1396 lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
1397
1398 if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
1399 {
1400 brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
1401 }
1402 else
1403 {
1404 brrresult = 0x0UL;
1405 }
1406
1407 return (brrresult);
1408 }
1409
1410 /**
1411 * @}
1412 */
1413
1414 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
1415 * @{
1416 */
1417
1418 /**
1419 * @brief Enable Single Wire Half-Duplex mode
1420 * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
1421 * @param LPUARTx LPUART Instance
1422 * @retval None
1423 */
LL_LPUART_EnableHalfDuplex(USART_TypeDef * LPUARTx)1424 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
1425 {
1426 SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1427 }
1428
1429 /**
1430 * @brief Disable Single Wire Half-Duplex mode
1431 * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
1432 * @param LPUARTx LPUART Instance
1433 * @retval None
1434 */
LL_LPUART_DisableHalfDuplex(USART_TypeDef * LPUARTx)1435 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
1436 {
1437 CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1438 }
1439
1440 /**
1441 * @brief Indicate if Single Wire Half-Duplex mode is enabled
1442 * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
1443 * @param LPUARTx LPUART Instance
1444 * @retval State of bit (1 or 0).
1445 */
LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef * LPUARTx)1446 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx)
1447 {
1448 return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
1449 }
1450
1451 /**
1452 * @}
1453 */
1454
1455 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
1456 * @{
1457 */
1458
1459 /**
1460 * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1461 * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
1462 * @param LPUARTx LPUART Instance
1463 * @param Time Value between Min_Data=0 and Max_Data=31
1464 * @retval None
1465 */
LL_LPUART_SetDEDeassertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1466 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1467 {
1468 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
1469 }
1470
1471 /**
1472 * @brief Return DEDT (Driver Enable De-Assertion Time)
1473 * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
1474 * @param LPUARTx LPUART Instance
1475 * @retval Time value expressed on 5 bits ([4:0] bits) : c
1476 */
LL_LPUART_GetDEDeassertionTime(const USART_TypeDef * LPUARTx)1477 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx)
1478 {
1479 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
1480 }
1481
1482 /**
1483 * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1484 * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
1485 * @param LPUARTx LPUART Instance
1486 * @param Time Value between Min_Data=0 and Max_Data=31
1487 * @retval None
1488 */
LL_LPUART_SetDEAssertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1489 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1490 {
1491 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
1492 }
1493
1494 /**
1495 * @brief Return DEAT (Driver Enable Assertion Time)
1496 * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
1497 * @param LPUARTx LPUART Instance
1498 * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
1499 */
LL_LPUART_GetDEAssertionTime(const USART_TypeDef * LPUARTx)1500 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx)
1501 {
1502 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
1503 }
1504
1505 /**
1506 * @brief Enable Driver Enable (DE) Mode
1507 * @rmtoll CR3 DEM LL_LPUART_EnableDEMode
1508 * @param LPUARTx LPUART Instance
1509 * @retval None
1510 */
LL_LPUART_EnableDEMode(USART_TypeDef * LPUARTx)1511 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
1512 {
1513 SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
1514 }
1515
1516 /**
1517 * @brief Disable Driver Enable (DE) Mode
1518 * @rmtoll CR3 DEM LL_LPUART_DisableDEMode
1519 * @param LPUARTx LPUART Instance
1520 * @retval None
1521 */
LL_LPUART_DisableDEMode(USART_TypeDef * LPUARTx)1522 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
1523 {
1524 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
1525 }
1526
1527 /**
1528 * @brief Indicate if Driver Enable (DE) Mode is enabled
1529 * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
1530 * @param LPUARTx LPUART Instance
1531 * @retval State of bit (1 or 0).
1532 */
LL_LPUART_IsEnabledDEMode(const USART_TypeDef * LPUARTx)1533 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx)
1534 {
1535 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
1536 }
1537
1538 /**
1539 * @brief Select Driver Enable Polarity
1540 * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
1541 * @param LPUARTx LPUART Instance
1542 * @param Polarity This parameter can be one of the following values:
1543 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1544 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1545 * @retval None
1546 */
LL_LPUART_SetDESignalPolarity(USART_TypeDef * LPUARTx,uint32_t Polarity)1547 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
1548 {
1549 MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
1550 }
1551
1552 /**
1553 * @brief Return Driver Enable Polarity
1554 * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
1555 * @param LPUARTx LPUART Instance
1556 * @retval Returned value can be one of the following values:
1557 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1558 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1559 */
LL_LPUART_GetDESignalPolarity(const USART_TypeDef * LPUARTx)1560 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx)
1561 {
1562 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
1563 }
1564
1565 /**
1566 * @}
1567 */
1568
1569 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
1570 * @{
1571 */
1572
1573 /**
1574 * @brief Check if the LPUART Parity Error Flag is set or not
1575 * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
1576 * @param LPUARTx LPUART Instance
1577 * @retval State of bit (1 or 0).
1578 */
LL_LPUART_IsActiveFlag_PE(const USART_TypeDef * LPUARTx)1579 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx)
1580 {
1581 return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
1582 }
1583
1584 /**
1585 * @brief Check if the LPUART Framing Error Flag is set or not
1586 * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
1587 * @param LPUARTx LPUART Instance
1588 * @retval State of bit (1 or 0).
1589 */
LL_LPUART_IsActiveFlag_FE(const USART_TypeDef * LPUARTx)1590 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx)
1591 {
1592 return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
1593 }
1594
1595 /**
1596 * @brief Check if the LPUART Noise error detected Flag is set or not
1597 * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
1598 * @param LPUARTx LPUART Instance
1599 * @retval State of bit (1 or 0).
1600 */
LL_LPUART_IsActiveFlag_NE(const USART_TypeDef * LPUARTx)1601 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx)
1602 {
1603 return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
1604 }
1605
1606 /**
1607 * @brief Check if the LPUART OverRun Error Flag is set or not
1608 * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
1609 * @param LPUARTx LPUART Instance
1610 * @retval State of bit (1 or 0).
1611 */
LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef * LPUARTx)1612 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx)
1613 {
1614 return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
1615 }
1616
1617 /**
1618 * @brief Check if the LPUART IDLE line detected Flag is set or not
1619 * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
1620 * @param LPUARTx LPUART Instance
1621 * @retval State of bit (1 or 0).
1622 */
LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef * LPUARTx)1623 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx)
1624 {
1625 return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
1626 }
1627
1628 #define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
1629
1630 /**
1631 * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
1632 * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
1633 * @param LPUARTx LPUART Instance
1634 * @retval State of bit (1 or 0).
1635 */
LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef * LPUARTx)1636 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
1637 {
1638 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
1639 }
1640
1641 /**
1642 * @brief Check if the LPUART Transmission Complete Flag is set or not
1643 * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
1644 * @param LPUARTx LPUART Instance
1645 * @retval State of bit (1 or 0).
1646 */
LL_LPUART_IsActiveFlag_TC(const USART_TypeDef * LPUARTx)1647 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
1648 {
1649 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
1650 }
1651
1652 #define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
1653
1654 /**
1655 * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
1656 * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
1657 * @param LPUARTx LPUART Instance
1658 * @retval State of bit (1 or 0).
1659 */
LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef * LPUARTx)1660 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx)
1661 {
1662 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
1663 }
1664
1665 /**
1666 * @brief Check if the LPUART CTS interrupt Flag is set or not
1667 * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
1668 * @param LPUARTx LPUART Instance
1669 * @retval State of bit (1 or 0).
1670 */
LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef * LPUARTx)1671 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx)
1672 {
1673 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
1674 }
1675
1676 /**
1677 * @brief Check if the LPUART CTS Flag is set or not
1678 * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
1679 * @param LPUARTx LPUART Instance
1680 * @retval State of bit (1 or 0).
1681 */
LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef * LPUARTx)1682 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx)
1683 {
1684 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
1685 }
1686
1687 /**
1688 * @brief Check if the LPUART Busy Flag is set or not
1689 * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
1690 * @param LPUARTx LPUART Instance
1691 * @retval State of bit (1 or 0).
1692 */
LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef * LPUARTx)1693 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx)
1694 {
1695 return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
1696 }
1697
1698 /**
1699 * @brief Check if the LPUART Character Match Flag is set or not
1700 * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
1701 * @param LPUARTx LPUART Instance
1702 * @retval State of bit (1 or 0).
1703 */
LL_LPUART_IsActiveFlag_CM(const USART_TypeDef * LPUARTx)1704 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx)
1705 {
1706 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
1707 }
1708
1709 /**
1710 * @brief Check if the LPUART Send Break Flag is set or not
1711 * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
1712 * @param LPUARTx LPUART Instance
1713 * @retval State of bit (1 or 0).
1714 */
LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef * LPUARTx)1715 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx)
1716 {
1717 return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
1718 }
1719
1720 /**
1721 * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
1722 * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
1723 * @param LPUARTx LPUART Instance
1724 * @retval State of bit (1 or 0).
1725 */
LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef * LPUARTx)1726 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx)
1727 {
1728 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
1729 }
1730
1731 /**
1732 * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
1733 * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
1734 * @param LPUARTx LPUART Instance
1735 * @retval State of bit (1 or 0).
1736 */
LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef * LPUARTx)1737 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx)
1738 {
1739 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
1740 }
1741
1742 /**
1743 * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
1744 * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
1745 * @param LPUARTx LPUART Instance
1746 * @retval State of bit (1 or 0).
1747 */
LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef * LPUARTx)1748 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx)
1749 {
1750 return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
1751 }
1752
1753 /**
1754 * @brief Check if the LPUART TX FIFO Empty Flag is set or not
1755 * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
1756 * @param LPUARTx LPUART Instance
1757 * @retval State of bit (1 or 0).
1758 */
LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef * LPUARTx)1759 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx)
1760 {
1761 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
1762 }
1763
1764 /**
1765 * @brief Check if the LPUART RX FIFO Full Flag is set or not
1766 * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
1767 * @param LPUARTx LPUART Instance
1768 * @retval State of bit (1 or 0).
1769 */
LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef * LPUARTx)1770 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx)
1771 {
1772 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
1773 }
1774
1775 /**
1776 * @brief Check if the LPUART TX FIFO Threshold Flag is set or not
1777 * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
1778 * @param LPUARTx LPUART Instance
1779 * @retval State of bit (1 or 0).
1780 */
LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef * LPUARTx)1781 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx)
1782 {
1783 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
1784 }
1785
1786 /**
1787 * @brief Check if the LPUART RX FIFO Threshold Flag is set or not
1788 * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
1789 * @param LPUARTx LPUART Instance
1790 * @retval State of bit (1 or 0).
1791 */
LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef * LPUARTx)1792 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx)
1793 {
1794 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
1795 }
1796
1797 /**
1798 * @brief Clear Parity Error Flag
1799 * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
1800 * @param LPUARTx LPUART Instance
1801 * @retval None
1802 */
LL_LPUART_ClearFlag_PE(USART_TypeDef * LPUARTx)1803 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
1804 {
1805 WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
1806 }
1807
1808 /**
1809 * @brief Clear Framing Error Flag
1810 * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
1811 * @param LPUARTx LPUART Instance
1812 * @retval None
1813 */
LL_LPUART_ClearFlag_FE(USART_TypeDef * LPUARTx)1814 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
1815 {
1816 WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
1817 }
1818
1819 /**
1820 * @brief Clear Noise detected Flag
1821 * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
1822 * @param LPUARTx LPUART Instance
1823 * @retval None
1824 */
LL_LPUART_ClearFlag_NE(USART_TypeDef * LPUARTx)1825 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
1826 {
1827 WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
1828 }
1829
1830 /**
1831 * @brief Clear OverRun Error Flag
1832 * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
1833 * @param LPUARTx LPUART Instance
1834 * @retval None
1835 */
LL_LPUART_ClearFlag_ORE(USART_TypeDef * LPUARTx)1836 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
1837 {
1838 WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
1839 }
1840
1841 /**
1842 * @brief Clear IDLE line detected Flag
1843 * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
1844 * @param LPUARTx LPUART Instance
1845 * @retval None
1846 */
LL_LPUART_ClearFlag_IDLE(USART_TypeDef * LPUARTx)1847 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
1848 {
1849 WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
1850 }
1851
1852 /**
1853 * @brief Clear Transmission Complete Flag
1854 * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
1855 * @param LPUARTx LPUART Instance
1856 * @retval None
1857 */
LL_LPUART_ClearFlag_TC(USART_TypeDef * LPUARTx)1858 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
1859 {
1860 WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
1861 }
1862
1863 /**
1864 * @brief Clear CTS Interrupt Flag
1865 * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
1866 * @param LPUARTx LPUART Instance
1867 * @retval None
1868 */
LL_LPUART_ClearFlag_nCTS(USART_TypeDef * LPUARTx)1869 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
1870 {
1871 WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
1872 }
1873
1874 /**
1875 * @brief Clear Character Match Flag
1876 * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
1877 * @param LPUARTx LPUART Instance
1878 * @retval None
1879 */
LL_LPUART_ClearFlag_CM(USART_TypeDef * LPUARTx)1880 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
1881 {
1882 WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
1883 }
1884
1885 /**
1886 * @}
1887 */
1888
1889 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
1890 * @{
1891 */
1892
1893 /**
1894 * @brief Enable IDLE Interrupt
1895 * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
1896 * @param LPUARTx LPUART Instance
1897 * @retval None
1898 */
LL_LPUART_EnableIT_IDLE(USART_TypeDef * LPUARTx)1899 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
1900 {
1901 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
1902 }
1903
1904 #define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
1905
1906 /**
1907 * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
1908 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
1909 * @param LPUARTx LPUART Instance
1910 * @retval None
1911 */
LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef * LPUARTx)1912 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
1913 {
1914 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
1915 }
1916
1917 /**
1918 * @brief Enable Transmission Complete Interrupt
1919 * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
1920 * @param LPUARTx LPUART Instance
1921 * @retval None
1922 */
LL_LPUART_EnableIT_TC(USART_TypeDef * LPUARTx)1923 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
1924 {
1925 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
1926 }
1927
1928 #define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
1929
1930 /**
1931 * @brief Enable TX Empty and TX FIFO Not Full Interrupt
1932 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
1933 * @param LPUARTx LPUART Instance
1934 * @retval None
1935 */
LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef * LPUARTx)1936 __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
1937 {
1938 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
1939 }
1940
1941 /**
1942 * @brief Enable Parity Error Interrupt
1943 * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
1944 * @param LPUARTx LPUART Instance
1945 * @retval None
1946 */
LL_LPUART_EnableIT_PE(USART_TypeDef * LPUARTx)1947 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
1948 {
1949 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
1950 }
1951
1952 /**
1953 * @brief Enable Character Match Interrupt
1954 * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
1955 * @param LPUARTx LPUART Instance
1956 * @retval None
1957 */
LL_LPUART_EnableIT_CM(USART_TypeDef * LPUARTx)1958 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
1959 {
1960 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
1961 }
1962
1963 /**
1964 * @brief Enable TX FIFO Empty Interrupt
1965 * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
1966 * @param LPUARTx LPUART Instance
1967 * @retval None
1968 */
LL_LPUART_EnableIT_TXFE(USART_TypeDef * LPUARTx)1969 __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
1970 {
1971 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
1972 }
1973
1974 /**
1975 * @brief Enable RX FIFO Full Interrupt
1976 * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
1977 * @param LPUARTx LPUART Instance
1978 * @retval None
1979 */
LL_LPUART_EnableIT_RXFF(USART_TypeDef * LPUARTx)1980 __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
1981 {
1982 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
1983 }
1984
1985 /**
1986 * @brief Enable Error Interrupt
1987 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
1988 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
1989 * - 0: Interrupt is inhibited
1990 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
1991 * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
1992 * @param LPUARTx LPUART Instance
1993 * @retval None
1994 */
LL_LPUART_EnableIT_ERROR(USART_TypeDef * LPUARTx)1995 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
1996 {
1997 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
1998 }
1999
2000 /**
2001 * @brief Enable CTS Interrupt
2002 * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
2003 * @param LPUARTx LPUART Instance
2004 * @retval None
2005 */
LL_LPUART_EnableIT_CTS(USART_TypeDef * LPUARTx)2006 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
2007 {
2008 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2009 }
2010
2011 /**
2012 * @brief Enable TX FIFO Threshold Interrupt
2013 * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
2014 * @param LPUARTx LPUART Instance
2015 * @retval None
2016 */
LL_LPUART_EnableIT_TXFT(USART_TypeDef * LPUARTx)2017 __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
2018 {
2019 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2020 }
2021
2022 /**
2023 * @brief Enable RX FIFO Threshold Interrupt
2024 * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
2025 * @param LPUARTx LPUART Instance
2026 * @retval None
2027 */
LL_LPUART_EnableIT_RXFT(USART_TypeDef * LPUARTx)2028 __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
2029 {
2030 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2031 }
2032
2033 /**
2034 * @brief Disable IDLE Interrupt
2035 * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
2036 * @param LPUARTx LPUART Instance
2037 * @retval None
2038 */
LL_LPUART_DisableIT_IDLE(USART_TypeDef * LPUARTx)2039 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
2040 {
2041 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
2042 }
2043
2044 #define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
2045
2046 /**
2047 * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
2048 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
2049 * @param LPUARTx LPUART Instance
2050 * @retval None
2051 */
LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef * LPUARTx)2052 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2053 {
2054 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
2055 }
2056
2057 /**
2058 * @brief Disable Transmission Complete Interrupt
2059 * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
2060 * @param LPUARTx LPUART Instance
2061 * @retval None
2062 */
LL_LPUART_DisableIT_TC(USART_TypeDef * LPUARTx)2063 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
2064 {
2065 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
2066 }
2067
2068 #define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
2069
2070 /**
2071 * @brief Disable TX Empty and TX FIFO Not Full Interrupt
2072 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
2073 * @param LPUARTx LPUART Instance
2074 * @retval None
2075 */
LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef * LPUARTx)2076 __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2077 {
2078 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
2079 }
2080
2081 /**
2082 * @brief Disable Parity Error Interrupt
2083 * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
2084 * @param LPUARTx LPUART Instance
2085 * @retval None
2086 */
LL_LPUART_DisableIT_PE(USART_TypeDef * LPUARTx)2087 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
2088 {
2089 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
2090 }
2091
2092 /**
2093 * @brief Disable Character Match Interrupt
2094 * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
2095 * @param LPUARTx LPUART Instance
2096 * @retval None
2097 */
LL_LPUART_DisableIT_CM(USART_TypeDef * LPUARTx)2098 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
2099 {
2100 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
2101 }
2102
2103 /**
2104 * @brief Disable TX FIFO Empty Interrupt
2105 * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
2106 * @param LPUARTx LPUART Instance
2107 * @retval None
2108 */
LL_LPUART_DisableIT_TXFE(USART_TypeDef * LPUARTx)2109 __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
2110 {
2111 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2112 }
2113
2114 /**
2115 * @brief Disable RX FIFO Full Interrupt
2116 * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
2117 * @param LPUARTx LPUART Instance
2118 * @retval None
2119 */
LL_LPUART_DisableIT_RXFF(USART_TypeDef * LPUARTx)2120 __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
2121 {
2122 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2123 }
2124
2125 /**
2126 * @brief Disable Error Interrupt
2127 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2128 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2129 * - 0: Interrupt is inhibited
2130 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2131 * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
2132 * @param LPUARTx LPUART Instance
2133 * @retval None
2134 */
LL_LPUART_DisableIT_ERROR(USART_TypeDef * LPUARTx)2135 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
2136 {
2137 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
2138 }
2139
2140 /**
2141 * @brief Disable CTS Interrupt
2142 * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
2143 * @param LPUARTx LPUART Instance
2144 * @retval None
2145 */
LL_LPUART_DisableIT_CTS(USART_TypeDef * LPUARTx)2146 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
2147 {
2148 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2149 }
2150
2151 /**
2152 * @brief Disable TX FIFO Threshold Interrupt
2153 * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
2154 * @param LPUARTx LPUART Instance
2155 * @retval None
2156 */
LL_LPUART_DisableIT_TXFT(USART_TypeDef * LPUARTx)2157 __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
2158 {
2159 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2160 }
2161
2162 /**
2163 * @brief Disable RX FIFO Threshold Interrupt
2164 * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
2165 * @param LPUARTx LPUART Instance
2166 * @retval None
2167 */
LL_LPUART_DisableIT_RXFT(USART_TypeDef * LPUARTx)2168 __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
2169 {
2170 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2171 }
2172
2173 /**
2174 * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
2175 * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
2176 * @param LPUARTx LPUART Instance
2177 * @retval State of bit (1 or 0).
2178 */
LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef * LPUARTx)2179 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx)
2180 {
2181 return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
2182 }
2183
2184 #define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
2185
2186 /**
2187 * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
2188 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
2189 * @param LPUARTx LPUART Instance
2190 * @retval State of bit (1 or 0).
2191 */
LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef * LPUARTx)2192 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
2193 {
2194 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
2195 }
2196
2197 /**
2198 * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
2199 * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
2200 * @param LPUARTx LPUART Instance
2201 * @retval State of bit (1 or 0).
2202 */
LL_LPUART_IsEnabledIT_TC(const USART_TypeDef * LPUARTx)2203 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
2204 {
2205 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
2206 }
2207
2208 #define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
2209
2210 /**
2211 * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
2212 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
2213 * @param LPUARTx LPUART Instance
2214 * @retval State of bit (1 or 0).
2215 */
LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef * LPUARTx)2216 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx)
2217 {
2218 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
2219 }
2220
2221 /**
2222 * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
2223 * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
2224 * @param LPUARTx LPUART Instance
2225 * @retval State of bit (1 or 0).
2226 */
LL_LPUART_IsEnabledIT_PE(const USART_TypeDef * LPUARTx)2227 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx)
2228 {
2229 return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
2230 }
2231
2232 /**
2233 * @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
2234 * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
2235 * @param LPUARTx LPUART Instance
2236 * @retval State of bit (1 or 0).
2237 */
LL_LPUART_IsEnabledIT_CM(const USART_TypeDef * LPUARTx)2238 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx)
2239 {
2240 return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
2241 }
2242
2243 /**
2244 * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
2245 * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
2246 * @param LPUARTx LPUART Instance
2247 * @retval State of bit (1 or 0).
2248 */
LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef * LPUARTx)2249 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx)
2250 {
2251 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
2252 }
2253
2254 /**
2255 * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
2256 * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
2257 * @param LPUARTx LPUART Instance
2258 * @retval State of bit (1 or 0).
2259 */
LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef * LPUARTx)2260 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx)
2261 {
2262 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
2263 }
2264
2265 /**
2266 * @brief Check if the LPUART Error Interrupt is enabled or disabled.
2267 * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
2268 * @param LPUARTx LPUART Instance
2269 * @retval State of bit (1 or 0).
2270 */
LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef * LPUARTx)2271 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx)
2272 {
2273 return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
2274 }
2275
2276 /**
2277 * @brief Check if the LPUART CTS Interrupt is enabled or disabled.
2278 * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
2279 * @param LPUARTx LPUART Instance
2280 * @retval State of bit (1 or 0).
2281 */
LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef * LPUARTx)2282 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx)
2283 {
2284 return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
2285 }
2286
2287 /**
2288 * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
2289 * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
2290 * @param LPUARTx LPUART Instance
2291 * @retval State of bit (1 or 0).
2292 */
LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef * LPUARTx)2293 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx)
2294 {
2295 return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
2296 }
2297
2298 /**
2299 * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
2300 * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
2301 * @param LPUARTx LPUART Instance
2302 * @retval State of bit (1 or 0).
2303 */
LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef * LPUARTx)2304 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx)
2305 {
2306 return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
2307 }
2308
2309 /**
2310 * @}
2311 */
2312
2313 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
2314 * @{
2315 */
2316
2317 /**
2318 * @brief Enable DMA Mode for reception
2319 * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
2320 * @param LPUARTx LPUART Instance
2321 * @retval None
2322 */
LL_LPUART_EnableDMAReq_RX(USART_TypeDef * LPUARTx)2323 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
2324 {
2325 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2326 }
2327
2328 /**
2329 * @brief Disable DMA Mode for reception
2330 * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
2331 * @param LPUARTx LPUART Instance
2332 * @retval None
2333 */
LL_LPUART_DisableDMAReq_RX(USART_TypeDef * LPUARTx)2334 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
2335 {
2336 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2337 }
2338
2339 /**
2340 * @brief Check if DMA Mode is enabled for reception
2341 * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
2342 * @param LPUARTx LPUART Instance
2343 * @retval State of bit (1 or 0).
2344 */
LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef * LPUARTx)2345 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx)
2346 {
2347 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
2348 }
2349
2350 /**
2351 * @brief Enable DMA Mode for transmission
2352 * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
2353 * @param LPUARTx LPUART Instance
2354 * @retval None
2355 */
LL_LPUART_EnableDMAReq_TX(USART_TypeDef * LPUARTx)2356 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
2357 {
2358 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2359 }
2360
2361 /**
2362 * @brief Disable DMA Mode for transmission
2363 * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
2364 * @param LPUARTx LPUART Instance
2365 * @retval None
2366 */
LL_LPUART_DisableDMAReq_TX(USART_TypeDef * LPUARTx)2367 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
2368 {
2369 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2370 }
2371
2372 /**
2373 * @brief Check if DMA Mode is enabled for transmission
2374 * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
2375 * @param LPUARTx LPUART Instance
2376 * @retval State of bit (1 or 0).
2377 */
LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef * LPUARTx)2378 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx)
2379 {
2380 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
2381 }
2382
2383 /**
2384 * @brief Enable DMA Disabling on Reception Error
2385 * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
2386 * @param LPUARTx LPUART Instance
2387 * @retval None
2388 */
LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2389 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2390 {
2391 SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2392 }
2393
2394 /**
2395 * @brief Disable DMA Disabling on Reception Error
2396 * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
2397 * @param LPUARTx LPUART Instance
2398 * @retval None
2399 */
LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2400 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2401 {
2402 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2403 }
2404
2405 /**
2406 * @brief Indicate if DMA Disabling on Reception Error is disabled
2407 * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
2408 * @param LPUARTx LPUART Instance
2409 * @retval State of bit (1 or 0).
2410 */
LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef * LPUARTx)2411 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx)
2412 {
2413 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
2414 }
2415
2416 /**
2417 * @brief Get the LPUART data register address used for DMA transfer
2418 * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
2419 * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
2420 * @param LPUARTx LPUART Instance
2421 * @param Direction This parameter can be one of the following values:
2422 * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
2423 * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
2424 * @retval Address of data register
2425 */
LL_LPUART_DMA_GetRegAddr(const USART_TypeDef * LPUARTx,uint32_t Direction)2426 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction)
2427 {
2428 uint32_t data_reg_addr;
2429
2430 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
2431 {
2432 /* return address of TDR register */
2433 data_reg_addr = (uint32_t) &(LPUARTx->TDR);
2434 }
2435 else
2436 {
2437 /* return address of RDR register */
2438 data_reg_addr = (uint32_t) &(LPUARTx->RDR);
2439 }
2440
2441 return data_reg_addr;
2442 }
2443
2444 /**
2445 * @}
2446 */
2447
2448 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
2449 * @{
2450 */
2451
2452 /**
2453 * @brief Read Receiver Data register (Receive Data value, 8 bits)
2454 * @rmtoll RDR RDR LL_LPUART_ReceiveData8
2455 * @param LPUARTx LPUART Instance
2456 * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
2457 */
LL_LPUART_ReceiveData8(const USART_TypeDef * LPUARTx)2458 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx)
2459 {
2460 return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
2461 }
2462
2463 /**
2464 * @brief Read Receiver Data register (Receive Data value, 9 bits)
2465 * @rmtoll RDR RDR LL_LPUART_ReceiveData9
2466 * @param LPUARTx LPUART Instance
2467 * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
2468 */
LL_LPUART_ReceiveData9(const USART_TypeDef * LPUARTx)2469 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx)
2470 {
2471 return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
2472 }
2473
2474 /**
2475 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
2476 * @rmtoll TDR TDR LL_LPUART_TransmitData8
2477 * @param LPUARTx LPUART Instance
2478 * @param Value between Min_Data=0x00 and Max_Data=0xFF
2479 * @retval None
2480 */
LL_LPUART_TransmitData8(USART_TypeDef * LPUARTx,uint8_t Value)2481 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
2482 {
2483 LPUARTx->TDR = Value;
2484 }
2485
2486 /**
2487 * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
2488 * @rmtoll TDR TDR LL_LPUART_TransmitData9
2489 * @param LPUARTx LPUART Instance
2490 * @param Value between Min_Data=0x00 and Max_Data=0x1FF
2491 * @retval None
2492 */
LL_LPUART_TransmitData9(USART_TypeDef * LPUARTx,uint16_t Value)2493 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
2494 {
2495 LPUARTx->TDR = Value & 0x1FFUL;
2496 }
2497
2498 /**
2499 * @}
2500 */
2501
2502 /** @defgroup LPUART_LL_EF_Execution Execution
2503 * @{
2504 */
2505
2506 /**
2507 * @brief Request Break sending
2508 * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
2509 * @param LPUARTx LPUART Instance
2510 * @retval None
2511 */
LL_LPUART_RequestBreakSending(USART_TypeDef * LPUARTx)2512 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
2513 {
2514 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
2515 }
2516
2517 /**
2518 * @brief Put LPUART in mute mode and set the RWU flag
2519 * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
2520 * @param LPUARTx LPUART Instance
2521 * @retval None
2522 */
LL_LPUART_RequestEnterMuteMode(USART_TypeDef * LPUARTx)2523 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
2524 {
2525 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
2526 }
2527
2528 /**
2529 * @brief Request a Receive Data and FIFO flush
2530 * @note Allows to discard the received data without reading them, and avoid an overrun
2531 * condition.
2532 * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
2533 * @param LPUARTx LPUART Instance
2534 * @retval None
2535 */
LL_LPUART_RequestRxDataFlush(USART_TypeDef * LPUARTx)2536 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
2537 {
2538 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
2539 }
2540
2541 /**
2542 * @}
2543 */
2544
2545 /** @defgroup LPUART_LL_EF_AutonomousMode Configuration functions related to Autonomous mode feature
2546 * @{
2547 */
2548
2549 /**
2550 * @brief Enable Selected Trigger
2551 * @rmtoll AUTOCR TRIGEN LL_LPUART_Enable_SelectedTrigger
2552 * @param LPUARTx LPUART Instance
2553 * @retval None
2554 */
LL_LPUART_Enable_SelectedTrigger(USART_TypeDef * LPUARTx)2555 __STATIC_INLINE void LL_LPUART_Enable_SelectedTrigger(USART_TypeDef *LPUARTx)
2556 {
2557 SET_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN);
2558 }
2559
2560 /**
2561 * @brief Disable Selected Trigger
2562 * @rmtoll AUTOCR TRIGEN LL_LPUART_Disable_SelectedTrigger
2563 * @param LPUARTx LPUART Instance
2564 * @retval None
2565 */
LL_LPUART_Disable_SelectedTrigger(USART_TypeDef * LPUARTx)2566 __STATIC_INLINE void LL_LPUART_Disable_SelectedTrigger(USART_TypeDef *LPUARTx)
2567 {
2568 CLEAR_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN);
2569 }
2570
2571 /**
2572 * @brief Indicate if selected Trigger is disabled or enabled
2573 * @rmtoll AUTOCR TRIGEN LL_LPUART_IsEnabled_SelectedTrigger
2574 * @param LPUARTx LPUART Instance
2575 * @retval State of bit (1 or 0).
2576 */
LL_LPUART_IsEnabled_SelectedTrigger(const USART_TypeDef * LPUARTx)2577 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled_SelectedTrigger(const USART_TypeDef *LPUARTx)
2578 {
2579 return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN) == (USART_AUTOCR_TRIGEN)) ? 1UL : 0UL);
2580 }
2581
2582 /**
2583 * @brief Enable Autonomous Send Idle Frame feature
2584 * @rmtoll AUTOCR IDLEDIS LL_LPUART_Enable_AutonomousSendIdleFrame
2585 * @param LPUARTx LPUART Instance
2586 * @retval None
2587 */
LL_LPUART_Enable_AutonomousSendIdleFrame(USART_TypeDef * LPUARTx)2588 __STATIC_INLINE void LL_LPUART_Enable_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx)
2589 {
2590 CLEAR_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS);
2591 }
2592
2593 /**
2594 * @brief Disable Autonomous Send Idle Frame feature
2595 * @rmtoll AUTOCR IDLEDIS LL_LPUART_Disable_AutonomousSendIdleFrame
2596 * @param LPUARTx LPUART Instance
2597 * @retval None
2598 */
LL_LPUART_Disable_AutonomousSendIdleFrame(USART_TypeDef * LPUARTx)2599 __STATIC_INLINE void LL_LPUART_Disable_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx)
2600 {
2601 SET_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS);
2602 }
2603
2604 /**
2605 * @brief Indicate if Autonomous send Idle Frame feature is disabled or enabled
2606 * @rmtoll AUTOCR IDLEDIS LL_LPUART_IsEnabled_AutonomousSendIdleFrame
2607 * @param LPUARTx LPUART Instance
2608 * @retval State of bit (1 or 0).
2609 */
LL_LPUART_IsEnabled_AutonomousSendIdleFrame(const USART_TypeDef * LPUARTx)2610 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled_AutonomousSendIdleFrame(const USART_TypeDef *LPUARTx)
2611 {
2612 return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS) == (USART_AUTOCR_IDLEDIS)) ? 0UL : 1UL);
2613 }
2614
2615 /**
2616 * @brief Configure the Number of transferred data in bytes
2617 * @rmtoll AUTOCR TDN LL_LPUART_SetNbTxData
2618 * @param LPUARTx LPUART Instance
2619 * @param Nbdata This parameter can be a value between 0 and 0xFFFF
2620 * @retval None
2621 */
LL_LPUART_SetNbTxData(USART_TypeDef * LPUARTx,uint32_t Nbdata)2622 __STATIC_INLINE void LL_LPUART_SetNbTxData(USART_TypeDef *LPUARTx, uint32_t Nbdata)
2623 {
2624 MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TDN, (uint16_t)Nbdata);
2625 }
2626
2627 /**
2628 * @brief Retrieve the Number of transferred data in bytes
2629 * @rmtoll AUTOCR TDN LL_LPUART_GetNbTxData
2630 * @param LPUARTx LPUART Instance
2631 * @retval Returned value can be a value between 0 and 0xFFFF
2632 */
LL_LPUART_GetNbTxData(const USART_TypeDef * LPUARTx)2633 __STATIC_INLINE uint32_t LL_LPUART_GetNbTxData(const USART_TypeDef *LPUARTx)
2634 {
2635 return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TDN));
2636 }
2637
2638 /**
2639 * @brief Set the trigger polarity
2640 * @rmtoll AUTOCR TRIGPOL LL_LPUART_SetTriggerPolarity
2641 * @param LPUARTx LPUART Instance
2642 * @param Polarity This parameter can be one of the following values:
2643 * @arg @ref LL_LPUART_TRIG_POLARITY_RISING
2644 * @arg @ref LL_LPUART_TRIG_POLARITY_FALLING
2645 * @retval None
2646 */
LL_LPUART_SetTriggerPolarity(USART_TypeDef * LPUARTx,uint32_t Polarity)2647 __STATIC_INLINE void LL_LPUART_SetTriggerPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
2648 {
2649 MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TRIGPOL, Polarity);
2650 }
2651
2652 /**
2653 * @brief Get the trigger polarity
2654 * @rmtoll AUTOCR TRIGPOL LL_LPUART_GetTriggerPolarity
2655 * @param LPUARTx LPUART Instance
2656 * @retval Returned value can be one of the following values:
2657 * @arg @ref LL_LPUART_TRIG_POLARITY_RISING
2658 * @arg @ref LL_LPUART_TRIG_POLARITY_FALLING
2659 */
LL_LPUART_GetTriggerPolarity(const USART_TypeDef * LPUARTx)2660 __STATIC_INLINE uint32_t LL_LPUART_GetTriggerPolarity(const USART_TypeDef *LPUARTx)
2661 {
2662 return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGPOL));
2663 }
2664
2665 /**
2666 * @brief Set the selected trigger
2667 * @rmtoll AUTOCR TRIGSEL LL_LPUART_SetSelectedTrigger
2668 * @param LPUARTx LPUART Instance
2669 * @param Trigger This parameter can be one of the following values:
2670 * @arg @ref LL_LPUART_GPDMA1_CH0_TCF_TRG
2671 * @arg @ref LL_LPUART_GPDMA1_CH1_TCF_TRG
2672 * @arg @ref LL_LPUART_GPDMA1_CH2_TCF_TRG
2673 * @arg @ref LL_LPUART_GPDMA1_CH3_TCF_TRG
2674 * @arg @ref LL_LPUART_EXTI_LINE6_TRG
2675 * @arg @ref LL_LPUART_EXTI_LINE8_TRG
2676 * @arg @ref LL_LPUART_LPTIM1_OUT_TRG
2677 * @arg @ref LL_LPUART_COMP1_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx)
2678 * @arg @ref LL_LPUART_COMP2_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx)
2679 * @arg @ref LL_LPUART_RTC_ALRA_TRG
2680 * @arg @ref LL_LPUART_RTC_WUT_TRG
2681 * @retval None
2682 */
LL_LPUART_SetSelectedTrigger(USART_TypeDef * LPUARTx,uint32_t Trigger)2683 __STATIC_INLINE void LL_LPUART_SetSelectedTrigger(USART_TypeDef *LPUARTx, uint32_t Trigger)
2684 {
2685 MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TRIGSEL, (Trigger << USART_AUTOCR_TRIGSEL_Pos));
2686 }
2687
2688 /**
2689 * @brief Get the selected trigger
2690 * @rmtoll AUTOCR TRIGSEL LL_LPUART_GetSelectedTrigger
2691 * @param LPUARTx LPUART Instance
2692 * @retval Returned value can be one of the following values:
2693 * @arg @ref LL_LPUART_GPDMA1_CH0_TCF_TRG
2694 * @arg @ref LL_LPUART_GPDMA1_CH1_TCF_TRG
2695 * @arg @ref LL_LPUART_GPDMA1_CH2_TCF_TRG
2696 * @arg @ref LL_LPUART_GPDMA1_CH3_TCF_TRG
2697 * @arg @ref LL_LPUART_EXTI_LINE6_TRG
2698 * @arg @ref LL_LPUART_EXTI_LINE8_TRG
2699 * @arg @ref LL_LPUART_LPTIM1_OUT_TRG
2700 * @arg @ref LL_LPUART_COMP1_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx)
2701 * @arg @ref LL_LPUART_COMP2_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx)
2702 * @arg @ref LL_LPUART_RTC_ALRA_TRG
2703 * @arg @ref LL_LPUART_RTC_WUT_TRG
2704 */
LL_LPUART_GetSelectedTrigger(const USART_TypeDef * LPUARTx)2705 __STATIC_INLINE uint32_t LL_LPUART_GetSelectedTrigger(const USART_TypeDef *LPUARTx)
2706 {
2707 return (uint32_t)((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos));
2708 }
2709
2710 /**
2711 * @}
2712 */
2713
2714 #if defined(USE_FULL_LL_DRIVER)
2715 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
2716 * @{
2717 */
2718 ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
2719 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct);
2720 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
2721 /**
2722 * @}
2723 */
2724 #endif /* USE_FULL_LL_DRIVER */
2725
2726 /**
2727 * @}
2728 */
2729
2730 /**
2731 * @}
2732 */
2733
2734 #endif /* LPUART1 */
2735
2736 /**
2737 * @}
2738 */
2739
2740 #ifdef __cplusplus
2741 }
2742 #endif
2743
2744 #endif /* STM32WBAxx_LL_LPUART_H */
2745
2746
