1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBAxx_LL_LPTIM_H
21 #define STM32WBAxx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPTIM1) || defined (LPTIM2)
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup LPTIM_LL_Private_variables LPTIM Private variables
43 * @{
44 */
45
46 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxP[] =
47 {
48 0U, /* CC1P */
49 16U /* CC2P */
50 };
51
52 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxF[] =
53 {
54 0U, /* IC1F */
55 16U /* IC2F */
56 };
57
58 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxPSC[] =
59 {
60 0U, /* IC1PSC */
61 16U /* IC2PSC */
62 };
63
64 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] =
65 {
66 0U, /* CC1SEL */
67 16U /* CC2SEL */
68 };
69
70 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] =
71 {
72 LPTIM_CCMR1_CC1E_Pos, /* CC1E */
73 LPTIM_CCMR1_CC2E_Pos /* CC2E */
74 };
75
76 static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] =
77 {
78 {2, 7, 9, 13},
79 {3, 5, 6, 8},
80 {2, 3, 4, 5},
81 {2, 2, 3, 3},
82 {2, 2, 2, 2},
83 {2, 2, 2, 2},
84 {2, 2, 2, 2},
85 {2, 2, 2, 2}
86
87 };
88
89 /**
90 * @}
91 */
92
93 /* Private constants ---------------------------------------------------------*/
94
95 /* Private macros ------------------------------------------------------------*/
96 #if defined(USE_FULL_LL_DRIVER)
97 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
98 * @{
99 */
100 /**
101 * @}
102 */
103 #endif /*USE_FULL_LL_DRIVER*/
104
105 /* Exported types ------------------------------------------------------------*/
106 #if defined(USE_FULL_LL_DRIVER)
107 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
108 * @{
109 */
110
111 /**
112 * @brief LPTIM Init structure definition
113 */
114 typedef struct
115 {
116 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
117 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
118
119 This feature can be modified afterwards using unitary
120 function @ref LL_LPTIM_SetClockSource().*/
121
122 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
123 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
124
125 This feature can be modified afterwards using using unitary
126 function @ref LL_LPTIM_SetPrescaler().*/
127
128 uint32_t Waveform; /*!< Specifies the waveform shape.
129 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
130
131 This feature can be modified afterwards using unitary
132 function @ref LL_LPTIM_SetWaveform().*/
133 } LL_LPTIM_InitTypeDef;
134
135 /**
136 * @}
137 */
138 #endif /* USE_FULL_LL_DRIVER */
139
140 /* Exported constants --------------------------------------------------------*/
141 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
142 * @{
143 */
144
145 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
146 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
147 * @{
148 */
149 #define LL_LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK /*!< Compare register 1 update OK */
150 #define LL_LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK /*!< Compare register 2 update OK */
151 #define LL_LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF /*!< Capture/Compare 1 interrupt flag */
152 #define LL_LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF /*!< Capture/Compare 2 interrupt flag */
153 #define LL_LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF /*!< Capture/Compare 1 over-capture flag */
154 #define LL_LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF /*!< Capture/Compare 2 over-capture flag */
155 #define LL_LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK /*!< Interrupt enable register update OK */
156 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
157 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
158 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
159 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
160 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
161 #define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */
162 #define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */
163 /**
164 * @}
165 */
166
167 /** @defgroup LPTIM_LL_EC_IT IT Defines
168 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
169 * @{
170 */
171 #define LL_LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE /*!< Compare register 1 update OK */
172 #define LL_LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE /*!< Compare register 2 update OK */
173 #define LL_LPTIM_DIER_CC1IFIE LPTIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt flag */
174 #define LL_LPTIM_DIER_CC2IFIE LPTIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt flag */
175 #define LL_LPTIM_DIER_CC1OFIE LPTIM_DIER_CC1OIE /*!< Capture/Compare 1 over-capture flag */
176 #define LL_LPTIM_DIER_CC2OFIE LPTIM_DIER_CC2OIE /*!< Capture/Compare 2 over-capture flag */
177 #define LL_LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE /*!< Autoreload match */
178 #define LL_LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE /*!< External trigger edge event */
179 #define LL_LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE /*!< Autoreload register update OK */
180 #define LL_LPTIM_DIER_UPIE LPTIM_DIER_UPIE /*!< Counter direction change down to up */
181 #define LL_LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE /*!< Counter direction change up to down */
182 #define LL_LPTIM_DIER_UEIE LPTIM_DIER_UEIE /*!< Update event */
183 #define LL_LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE /*!< Repetition register update OK */
184 /**
185 * @}
186 */
187
188 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
189 * @{
190 */
191 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
192 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
193 /**
194 * @}
195 */
196
197 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
198 * @{
199 */
200 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
201 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
202 /**
203 * @}
204 */
205
206 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
207 * @{
208 */
209 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
210 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
211 /**
212 * @}
213 */
214
215 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
216 * @{
217 */
218 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
219 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
220 /**
221 * @}
222 */
223
224 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
225 * @{
226 */
227 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CCRx registers*/
228 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CCMR1_CC1P_0 /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CCx registers*/
229 /**
230 * @}
231 */
232
233 /** @defgroup TIM_LL_EC_CHANNEL Channel
234 * @{
235 */
236 #define LL_LPTIM_CHANNEL_CH1 0x00000000U /*!< LPTIM input/output channel 1 */
237 #define LL_LPTIM_CHANNEL_CH2 0x00000001U /*!< LPTIM input/output channel 2 */
238 /**
239 * @}
240 */
241
242 /** @defgroup LPTIM_LL_EC_LPTIM_IC_PRESCALER Input Capture Prescaler
243 * @{
244 */
245 #define LL_LPTIM_ICPSC_DIV1 0x00000000UL /*!< Capture performed each time an edge is detected on the capture input */
246 #define LL_LPTIM_ICPSC_DIV2 LPTIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
247 #define LL_LPTIM_ICPSC_DIV4 LPTIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
248 #define LL_LPTIM_ICPSC_DIV8 (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 8 events */
249 /**
250 * @}
251 */
252
253 /** @defgroup LPTIM_LL_EC_LPTIM_IC_FILTER Input Capture Filter
254 * @{
255 */
256 #define LL_LPTIM_ICFLT_CLOCK_DIV1 0x00000000UL /*!< any external input capture signal level change is considered as a valid transition */
257 #define LL_LPTIM_ICFLT_CLOCK_DIV2 LPTIM_CCMR1_IC1F_0 /*!< external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition */
258 #define LL_LPTIM_ICFLT_CLOCK_DIV4 LPTIM_CCMR1_IC1F_1 /*!< external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition */
259 #define LL_LPTIM_ICFLT_CLOCK_DIV8 (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1) /*!< external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition */
260 /**
261 * @}
262 */
263
264 /** @defgroup LPTIM_LL_EC_LPTIM_IC_POLARITY Input Capture Polarity
265 * @{
266 */
267 #define LL_LPTIM_ICPOLARITY_RISING 0x00000000UL /*!< Capture/Compare input rising polarity */
268 #define LL_LPTIM_ICPOLARITY_FALLING LPTIM_CCMR1_CC1P_0 /*!< Capture/Compare input falling polarity */
269 #define LL_LPTIM_ICPOLARITY_RISING_FALLING (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1) /*!< Capture/Compare input rising and falling polarities */
270 /**
271 * @}
272 */
273 /** @defgroup LPTIM_LL_EC_LPTIM_IC_Selection Input Capture selection
274 * @{
275 */
276 #define LL_LPTIM_CCMODE_OUTPUT_PWM 0x00000000UL /*!< Select PWM mode */
277 #define LL_LPTIM_CCMODE_INPUTCAPTURE LPTIM_CCMR1_CC1SEL /*!< Select Input Capture mode*/
278 /**
279 * @}
280 */
281
282 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
283 * @{
284 */
285 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
286 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
287 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
288 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
289 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
290 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
291 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
292 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
293 /**
294 * @}
295 */
296
297 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
298 * @{
299 */
300 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
301 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
302 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
303 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
304 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
305 #if defined(COMP1)
306 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
307 #endif /* COMP1 */
308 #if defined(COMP2)
309 #define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
310 #endif /* COMP2 */
311 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to GPDMA CH0 transfer complete */
312 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to GPDMA CH4 transfer complete */
313 /**
314 * @}
315 */
316
317 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
318 * @{
319 */
320 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
321 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
322 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
323 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
324 /**
325 * @}
326 */
327
328 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
329 * @{
330 */
331 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
332 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
333 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
334 /**
335 * @}
336 */
337
338 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
339 * @{
340 */
341 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
342 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
343 /**
344 * @}
345 */
346
347 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
348 * @{
349 */
350 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
351 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
352 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
353 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
354 /**
355 * @}
356 */
357
358 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
359 * @{
360 */
361 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
362 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
363 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
364 /**
365 * @}
366 */
367
368 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
369 * @{
370 */
371 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
372 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
373 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
374 /**
375 * @}
376 */
377
378 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
379 * @{
380 */
381 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000UL /*!< For LPTIM1 and LPTIM2 */
382 #if defined(COMP1)
383 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1 and LPTIM2 */
384 #endif /* COMP1 */
385 /**
386 * @}
387 */
388
389 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
390 * @{
391 */
392 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000UL /*!< For LPTIM1 and LPTIM2 */
393 #if defined(COMP2)
394 #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0 /*!< For LPTIM1 and LPTIM2 */
395 #endif /* COMP2 */
396 /**
397 * @}
398 */
399
400 /** @defgroup LPTIM_EC_LPTIM1_IC1_RMP LPTIM1 Input Ch1 Remap
401 * @{
402 */
403 #define LL_LPTIM_LPTIM1_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
404 #if defined(COMP1) && defined(COMP2)
405 #define LL_LPTIM_LPTIM1_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
406 #define LL_LPTIM_LPTIM1_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
407 #endif /* COMP1 && COMP2 */
408 /**
409 * @}
410 */
411
412 /** @defgroup LPTIM_EC_LPTIM1_IC2_RMP LPTIM1 Input Ch2 Remap
413 * @{
414 */
415 #define LL_LPTIM_LPTIM1_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
416 #define LL_LPTIM_LPTIM1_IC2_RMP_LSI LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to LSI */
417 #define LL_LPTIM_LPTIM1_IC2_RMP_LSE LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to LSE */
418 /**
419 * @}
420 */
421
422 /** @defgroup LPTIM_EC_LPTIM2_IC1_RMP LPTIM2 Input Ch1 Remap
423 * @{
424 */
425 #define LL_LPTIM_LPTIM2_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
426 #if defined(COMP1) && defined(COMP2)
427 #define LL_LPTIM_LPTIM2_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
428 #define LL_LPTIM_LPTIM2_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
429 #endif /* COMP1 && COMP2 */
430 /**
431 * @}
432 */
433
434 /** @defgroup LPTIM_EC_LPTIM2_IC2_RMP LPTIM2 Input Ch2 Remap
435 * @{
436 */
437 #define LL_LPTIM_LPTIM2_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
438 #define LL_LPTIM_LPTIM2_IC2_RMP_HSI_256 LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to HSI/256 */
439 /**
440 * @}
441 */
442
443
444 /**
445 * @}
446 */
447
448 /* Exported macro ------------------------------------------------------------*/
449 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
450 * @{
451 */
452
453 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
454 * @{
455 */
456
457 /**
458 * @brief Write a value in LPTIM register
459 * @param __INSTANCE__ LPTIM Instance
460 * @param __REG__ Register to be written
461 * @param __VALUE__ Value to be written in the register
462 * @retval None
463 */
464 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
465
466 /**
467 * @brief Read a value in LPTIM register
468 * @param __INSTANCE__ LPTIM Instance
469 * @param __REG__ Register to be read
470 * @retval Register value
471 */
472 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
473
474 /**
475 * @brief LPTimer Input Capture Get Offset(in counter step unit)
476 * @note The real capture value corresponding to the input capture trigger can be calculated using
477 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
478 * The Offset value is depending on the glitch filter value for the channel
479 * and the value of the prescaler for the kernel clock.
480 * Please check Errata Sheet V1_8 for more details under "variable latency
481 * on input capture channel" section.
482 * @param __PSC__ This parameter can be one of the following values:
483 * @arg @ref LL_LPTIM_PRESCALER_DIV1
484 * @arg @ref LL_LPTIM_PRESCALER_DIV2
485 * @arg @ref LL_LPTIM_PRESCALER_DIV4
486 * @arg @ref LL_LPTIM_PRESCALER_DIV8
487 * @arg @ref LL_LPTIM_PRESCALER_DIV16
488 * @arg @ref LL_LPTIM_PRESCALER_DIV32
489 * @arg @ref LL_LPTIM_PRESCALER_DIV64
490 * @arg @ref LL_LPTIM_PRESCALER_DIV128
491 * @param __FLT__ This parameter can be one of the following values:
492 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
493 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
494 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
495 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
496 * @retval offset value
497 */
498 #define LL_LPTIM_IC_GET_OFFSET(__PSC__, __FLT__) LL_LPTIM_OFFSET_TAB_ICx\
499 [((__PSC__) & LPTIM_CFGR_PRESC_Msk) >> LPTIM_CFGR_PRESC_Pos]\
500 [((__FLT__) & LPTIM_CCMR1_IC1F_Msk) >> LPTIM_CCMR1_IC1F_Pos]
501 /**
502 * @}
503 */
504
505 /**
506 * @}
507 */
508
509 /* Exported functions --------------------------------------------------------*/
510 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
511 * @{
512 */
513
514 /** Legacy definitions for compatibility purpose
515 @cond 0
516 */
517 #define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
518 #define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
519 #define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
520 #define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
521 #define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
522 #define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
523 /**
524 @endcond
525 */
526
527 #if defined(USE_FULL_LL_DRIVER)
528 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
529 * @{
530 */
531
532 ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
533 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
534 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
535 /**
536 * @}
537 */
538 #endif /* USE_FULL_LL_DRIVER */
539
540 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
541 * @{
542 */
543
544 /**
545 * @brief Enable the LPTIM instance
546 * @note After setting the ENABLE bit, a delay of two counter clock is needed
547 * before the LPTIM instance is actually enabled.
548 * @rmtoll CR ENABLE LL_LPTIM_Enable
549 * @param LPTIMx Low-Power Timer instance
550 * @retval None
551 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)552 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
553 {
554 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
555 }
556
557 /**
558 * @brief Disable the LPTIM instance
559 * @rmtoll CR ENABLE LL_LPTIM_Disable
560 * @param LPTIMx Low-Power Timer instance
561 * @retval None
562 */
LL_LPTIM_Disable(LPTIM_TypeDef * LPTIMx)563 __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
564 {
565 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
566 }
567
568 /**
569 * @brief Indicates whether the LPTIM instance is enabled.
570 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
571 * @param LPTIMx Low-Power Timer instance
572 * @retval State of bit (1 or 0).
573 */
LL_LPTIM_IsEnabled(const LPTIM_TypeDef * LPTIMx)574 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
575 {
576 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
577 }
578
579 /**
580 * @brief Starts the LPTIM counter in the desired mode.
581 * @note LPTIM instance must be enabled before starting the counter.
582 * @note It is possible to change on the fly from One Shot mode to
583 * Continuous mode.
584 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
585 * CR SNGSTRT LL_LPTIM_StartCounter
586 * @param LPTIMx Low-Power Timer instance
587 * @param OperatingMode This parameter can be one of the following values:
588 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
589 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
590 * @retval None
591 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)592 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
593 {
594 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
595 }
596
597 /**
598 * @brief Enable reset after read.
599 * @note After calling this function any read access to LPTIM_CNT
600 * register will asynchronously reset the LPTIM_CNT register content.
601 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
602 * @param LPTIMx Low-Power Timer instance
603 * @retval None
604 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)605 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
606 {
607 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
608 }
609
610 /**
611 * @brief Disable reset after read.
612 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
613 * @param LPTIMx Low-Power Timer instance
614 * @retval None
615 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)616 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
617 {
618 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
619 }
620
621 /**
622 * @brief Indicate whether the reset after read feature is enabled.
623 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
624 * @param LPTIMx Low-Power Timer instance
625 * @retval State of bit (1 or 0).
626 */
LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef * LPTIMx)627 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
628 {
629 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
630 }
631
632 /**
633 * @brief Reset of the LPTIM_CNT counter register (synchronous).
634 * @note Due to the synchronous nature of this reset, it only takes
635 * place after a synchronization delay of 3 LPTIM core clock cycles
636 * (LPTIM core clock may be different from APB clock).
637 * @note COUNTRST is automatically cleared by hardware
638 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
639 * @param LPTIMx Low-Power Timer instance
640 * @retval None
641 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)642 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
643 {
644 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
645 }
646
647 /**
648 * @brief Set the LPTIM registers update mode (enable/disable register preload)
649 * @note This function must be called when the LPTIM instance is disabled.
650 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
651 * @param LPTIMx Low-Power Timer instance
652 * @param UpdateMode This parameter can be one of the following values:
653 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
654 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
655 * @retval None
656 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)657 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
658 {
659 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
660 }
661
662 /**
663 * @brief Get the LPTIM registers update mode
664 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
665 * @param LPTIMx Low-Power Timer instance
666 * @retval Returned value can be one of the following values:
667 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
668 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
669 */
LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef * LPTIMx)670 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
671 {
672 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
673 }
674
675 /**
676 * @brief Set the auto reload value
677 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
678 * @note After a write to the LPTIMx_ARR register a new write operation to the
679 * same register can only be performed when the previous write operation
680 * is completed. Any successive write before the ARROK flag is set, will
681 * lead to unpredictable results.
682 * @note autoreload value be strictly greater than the compare value.
683 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
684 * @param LPTIMx Low-Power Timer instance
685 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
686 * @retval None
687 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)688 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
689 {
690 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
691 }
692
693 /**
694 * @brief Get actual auto reload value
695 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
696 * @param LPTIMx Low-Power Timer instance
697 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
698 */
LL_LPTIM_GetAutoReload(const LPTIM_TypeDef * LPTIMx)699 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
700 {
701 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
702 }
703
704 /**
705 * @brief Set the repetition value
706 * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
707 * @rmtoll RCR REP LL_LPTIM_SetRepetition
708 * @param LPTIMx Low-Power Timer instance
709 * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF
710 * @retval None
711 */
LL_LPTIM_SetRepetition(LPTIM_TypeDef * LPTIMx,uint32_t Repetition)712 __STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
713 {
714 MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
715 }
716
717 /**
718 * @brief Get the repetition value
719 * @rmtoll RCR REP LL_LPTIM_GetRepetition
720 * @param LPTIMx Low-Power Timer instance
721 * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
722 */
LL_LPTIM_GetRepetition(const LPTIM_TypeDef * LPTIMx)723 __STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx)
724 {
725 return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
726 }
727
728 /**
729 * @brief Enable capture/compare channel.
730 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_EnableChannel\n
731 * CCMR1 CC2E LL_LPTIM_CC_EnableChannel
732 * @param LPTIMx LPTimer instance
733 * @param Channel This parameter can be one of the following values:
734 * @arg @ref LL_LPTIM_CHANNEL_CH1
735 * @arg @ref LL_LPTIM_CHANNEL_CH2
736 * @retval None
737 */
LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)738 __STATIC_INLINE void LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
739 {
740 SET_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
741 }
742
743 /**
744 * @brief Disable capture/compare channel.
745 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_DisableChannel\n
746 * CCMR1 CC2E LL_LPTIM_CC_DisableChannel
747 * @param LPTIMx LPTimer instance
748 * @param Channel This parameter can be one of the following values:
749 * @arg @ref LL_LPTIM_CHANNEL_CH1
750 * @arg @ref LL_LPTIM_CHANNEL_CH2
751 * @retval None
752 */
LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)753 __STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
754 {
755 CLEAR_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
756 }
757
758 /**
759 * @brief Indicate whether channel is enabled.
760 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_IsEnabledChannel\n
761 * CCMR1 CC2E LL_LPTIM_CC_IsEnabledChannel
762 * @param LPTIMx LPTimer instance
763 * @param Channel This parameter can be one of the following values:
764 * @arg @ref LL_LPTIM_CHANNEL_CH1
765 * @arg @ref LL_LPTIM_CHANNEL_CH2
766 * @retval State of bit (1 or 0).
767 */
LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)768 __STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
769 {
770 return ((READ_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]) == \
771 (0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel])) ? 1UL : 0UL);
772
773 }
774
775 /**
776 * @brief Set the compare value
777 * @note After a write to the LPTIMx_CCR1 register a new write operation to the
778 * same register can only be performed when the previous write operation
779 * is completed. Any successive write before the CMP1OK flag is set, will
780 * lead to unpredictable results.
781 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_SetCompareCH1
782 * @param LPTIMx Low-Power Timer instance
783 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
784 * @retval None
785 */
LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)786 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
787 {
788 MODIFY_REG(LPTIMx->CCR1, LPTIM_CCR1_CCR1, CompareValue);
789 }
790
791 /**
792 * @brief Get actual compare value
793 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_GetCompareCH1
794 * @param LPTIMx Low-Power Timer instance
795 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
796 */
LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef * LPTIMx)797 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef *LPTIMx)
798 {
799 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
800 }
801
802 /**
803 * @brief Set the compare value
804 * @note After a write to the LPTIMx_CCR2 register a new write operation to the
805 * same register can only be performed when the previous write operation
806 * is completed. Any successive write before the CMP2OK flag is set, will
807 * lead to unpredictable results.
808 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_SetCompareCH2
809 * @param LPTIMx Low-Power Timer instance
810 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
811 * @retval None
812 */
LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)813 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
814 {
815 MODIFY_REG(LPTIMx->CCR2, LPTIM_CCR2_CCR2, CompareValue);
816 }
817
818 /**
819 * @brief Get actual compare value
820 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_GetCompareCH2
821 * @param LPTIMx Low-Power Timer instance
822 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
823 */
LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef * LPTIMx)824 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef *LPTIMx)
825 {
826 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
827 }
828
829 /**
830 * @brief Get actual counter value
831 * @note When the LPTIM instance is running with an asynchronous clock, reading
832 * the LPTIMx_CNT register may return unreliable values. So in this case
833 * it is necessary to perform two consecutive read accesses and verify
834 * that the two returned values are identical.
835 * @rmtoll CNT CNT LL_LPTIM_GetCounter
836 * @param LPTIMx Low-Power Timer instance
837 * @retval Counter value
838 */
LL_LPTIM_GetCounter(const LPTIM_TypeDef * LPTIMx)839 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
840 {
841 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
842 }
843
844 /**
845 * @brief Set the counter mode (selection of the LPTIM counter clock source).
846 * @note The counter mode can be set only when the LPTIM instance is disabled.
847 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
848 * @param LPTIMx Low-Power Timer instance
849 * @param CounterMode This parameter can be one of the following values:
850 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
851 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
852 * @retval None
853 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)854 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
855 {
856 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
857 }
858
859 /**
860 * @brief Get the counter mode
861 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
862 * @param LPTIMx Low-Power Timer instance
863 * @retval Returned value can be one of the following values:
864 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
865 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
866 */
LL_LPTIM_GetCounterMode(const LPTIM_TypeDef * LPTIMx)867 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
868 {
869 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
870 }
871
872 /**
873 * @brief Set waveform shape
874 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
875 * @param LPTIMx Low-Power Timer instance
876 * @param Waveform This parameter can be one of the following values:
877 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
878 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
879 * @retval None
880 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)881 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
882 {
883 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
884 }
885
886 /**
887 * @brief Get actual waveform shape
888 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
889 * @param LPTIMx Low-Power Timer instance
890 * @retval Returned value can be one of the following values:
891 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
892 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
893 */
LL_LPTIM_GetWaveform(const LPTIM_TypeDef * LPTIMx)894 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
895 {
896 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
897 }
898
899 /**
900 * @brief Set the polarity of an output channel.
901 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_SetPolarity\n
902 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_SetPolarity\n
903 * @param LPTIMx Low-Power Timer instance
904 * @param Channel This parameter can be one of the following values:
905 * @arg @ref LL_LPTIM_CHANNEL_CH1
906 * @arg @ref LL_LPTIM_CHANNEL_CH2
907 * @param Polarity This parameter can be one of the following values:
908 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
909 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
910 * @retval None
911 */
LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)912 __STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
913 {
914 MODIFY_REG(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]),
915 (Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]));
916 }
917
918 /**
919 * @brief Get the polarity of an output channel.
920 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_GetPolarity\n
921 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_GetPolarity\n
922 * @param LPTIMx Low-Power Timer instance
923 * @param Channel This parameter can be one of the following values:
924 * @arg @ref LL_LPTIM_CHANNEL_CH1
925 * @arg @ref LL_LPTIM_CHANNEL_CH2
926 * @retval Returned value can be one of the following values:
927 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
928 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
929 */
LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)930 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
931 {
932 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]))) >> \
933 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
934 }
935
936 /**
937 * @brief Set actual prescaler division ratio.
938 * @note This function must be called when the LPTIM instance is disabled.
939 * @note When the LPTIM is configured to be clocked by an internal clock source
940 * and the LPTIM counter is configured to be updated by active edges
941 * detected on the LPTIM external Input1, the internal clock provided to
942 * the LPTIM must be not be prescaled.
943 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
944 * @param LPTIMx Low-Power Timer instance
945 * @param Prescaler This parameter can be one of the following values:
946 * @arg @ref LL_LPTIM_PRESCALER_DIV1
947 * @arg @ref LL_LPTIM_PRESCALER_DIV2
948 * @arg @ref LL_LPTIM_PRESCALER_DIV4
949 * @arg @ref LL_LPTIM_PRESCALER_DIV8
950 * @arg @ref LL_LPTIM_PRESCALER_DIV16
951 * @arg @ref LL_LPTIM_PRESCALER_DIV32
952 * @arg @ref LL_LPTIM_PRESCALER_DIV64
953 * @arg @ref LL_LPTIM_PRESCALER_DIV128
954 * @retval None
955 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)956 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
957 {
958 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
959 }
960
961 /**
962 * @brief Get actual prescaler division ratio.
963 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
964 * @param LPTIMx Low-Power Timer instance
965 * @retval Returned value can be one of the following values:
966 * @arg @ref LL_LPTIM_PRESCALER_DIV1
967 * @arg @ref LL_LPTIM_PRESCALER_DIV2
968 * @arg @ref LL_LPTIM_PRESCALER_DIV4
969 * @arg @ref LL_LPTIM_PRESCALER_DIV8
970 * @arg @ref LL_LPTIM_PRESCALER_DIV16
971 * @arg @ref LL_LPTIM_PRESCALER_DIV32
972 * @arg @ref LL_LPTIM_PRESCALER_DIV64
973 * @arg @ref LL_LPTIM_PRESCALER_DIV128
974 */
LL_LPTIM_GetPrescaler(const LPTIM_TypeDef * LPTIMx)975 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
976 {
977 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
978 }
979
980 /**
981 * @brief Set LPTIM input 1 source (default GPIO).
982 * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src
983 * @param LPTIMx Low-Power Timer instance
984 * @param Src This parameter can be one of the following values:
985 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
986 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1 (*)
987 * (*) Value not defined for all devices
988 * @retval None
989 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)990 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
991 {
992 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
993 }
994
995 /**
996 * @brief Set LPTIM input 2 source (default GPIO).
997 * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src
998 * @param LPTIMx Low-Power Timer instance
999 * @param Src This parameter can be one of the following values:
1000 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
1001 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2 (*)
1002 * (*) Value not defined for all devices
1003 * @retval None
1004 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1005 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1006 {
1007 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
1008 }
1009
1010 /**
1011 * @brief Set LPTIM input source (default GPIO).
1012 * @rmtoll CFGR2 IC1SEL LL_LPTIM_SetRemap
1013 * @rmtoll CFGR2 IC2SEL LL_LPTIM_SetRemap
1014 * @param LPTIMx Low-Power Timer instance
1015 * @param Src This parameter can be one of the following values:
1016 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO
1017 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP1 (*)
1018 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP2 (*)
1019 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO
1020 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI
1021 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE
1022 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO
1023 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP1 (*)
1024 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP2 (*)
1025 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_GPIO
1026 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI_256
1027 *
1028 * (*) Value not defined in all devices. \n
1029 *
1030 * @retval None
1031 */
LL_LPTIM_SetRemap(LPTIM_TypeDef * LPTIMx,uint32_t Src)1032 __STATIC_INLINE void LL_LPTIM_SetRemap(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1033 {
1034 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL, Src);
1035 }
1036
1037 /**
1038 * @brief Set the polarity of IC channel 1.
1039 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_SetPolarity\n
1040 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_SetPolarity\n
1041 * @param LPTIMx Low-Power Timer instance
1042 * @param Channel This parameter can be one of the following values:
1043 * @arg @ref LL_LPTIM_CHANNEL_CH1
1044 * @arg @ref LL_LPTIM_CHANNEL_CH2
1045 * @param Polarity This parameter can be one of the following values:
1046 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1047 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1048 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1049 * @retval None
1050 */
LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)1051 __STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
1052 {
1053 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel],
1054 Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1055 }
1056
1057 /**
1058 * @brief Get the polarity of IC channels.
1059 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_GetPolarity\n
1060 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_GetPolarity\n
1061 * @param LPTIMx Low-Power Timer instance
1062 * @param Channel This parameter can be one of the following values:
1063 * @arg @ref LL_LPTIM_CHANNEL_CH1
1064 * @arg @ref LL_LPTIM_CHANNEL_CH2
1065 * @retval Returned value can be one of the following values:
1066 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1067 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1068 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1069 */
LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1070 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1071 {
1072 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >> \
1073 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1074
1075 }
1076
1077 /**
1078 * @brief Set the filter of IC channels.
1079 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_SetFilter\n
1080 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_SetFilter\n
1081 * @param LPTIMx Low-Power Timer instance
1082 * @param Channel This parameter can be one of the following values:
1083 * @arg @ref LL_LPTIM_CHANNEL_CH1
1084 * @arg @ref LL_LPTIM_CHANNEL_CH2
1085 * @param Filter This parameter can be one of the following values:
1086 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1087 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1088 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1089 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1090 * @retval None
1091 */
LL_LPTIM_IC_SetFilter(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Filter)1092 __STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Filter)
1093 {
1094 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel],
1095 Filter << LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1096 }
1097
1098 /**
1099 * @brief Get the filter of IC channels.
1100 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_GetFilter\n
1101 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_GetFilter\n
1102 * @param LPTIMx Low-Power Timer instance
1103 * @param Channel This parameter can be one of the following values:
1104 * @arg @ref LL_LPTIM_CHANNEL_CH1
1105 * @arg @ref LL_LPTIM_CHANNEL_CH2
1106 * @retval Returned value can be one of the following values:
1107 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1108 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1109 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1110 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1111 */
LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1112 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1113 {
1114 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel])) >> \
1115 LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1116 }
1117
1118 /**
1119 * @brief Set the prescaler of IC channels.
1120 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_SetPrescaler\n
1121 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_SetPrescaler\n
1122 * @param LPTIMx Low-Power Timer instance
1123 * @param Channel This parameter can be one of the following values:
1124 * @arg @ref LL_LPTIM_CHANNEL_CH1
1125 * @arg @ref LL_LPTIM_CHANNEL_CH2
1126 * @param Prescaler This parameter can be one of the following values:
1127 * @arg @ref LL_LPTIM_ICPSC_DIV1
1128 * @arg @ref LL_LPTIM_ICPSC_DIV2
1129 * @arg @ref LL_LPTIM_ICPSC_DIV4
1130 * @arg @ref LL_LPTIM_ICPSC_DIV8
1131 * @retval None
1132 */
LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Prescaler)1133 __STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Prescaler)
1134 {
1135 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel],
1136 Prescaler << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1137 }
1138
1139 /**
1140 * @brief Get the prescaler of IC channels.
1141 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_GetPrescaler\n
1142 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_GetPrescaler\n
1143 * @param LPTIMx Low-Power Timer instance
1144 * @param Channel This parameter can be one of the following values:
1145 * @arg @ref LL_LPTIM_CHANNEL_CH1
1146 * @arg @ref LL_LPTIM_CHANNEL_CH2
1147 * @retval Returned value can be one of the following values:
1148 * @arg @ref LL_LPTIM_ICPSC_DIV1
1149 * @arg @ref LL_LPTIM_ICPSC_DIV2
1150 * @arg @ref LL_LPTIM_ICPSC_DIV4
1151 * @arg @ref LL_LPTIM_ICPSC_DIV8
1152 */
LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1153 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1154 {
1155 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel])) >> \
1156 LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1157 }
1158
1159 /**
1160 * @brief Set the Channel Mode.
1161 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_SetChannelMode\n
1162 * CCMR1 CC2SEL LL_LPTIM_CC_SetChannelMode
1163 * @param LPTIMx Low-Power Timer instance
1164 * @param Channel This parameter can be one of the following values:
1165 * @arg @ref LL_LPTIM_CHANNEL_CH1
1166 * @arg @ref LL_LPTIM_CHANNEL_CH2
1167 * @param CCMode This parameter can be one of the following values:
1168 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1169 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1170 * @retval None
1171 */
LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t CCMode)1172 __STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode)
1173 {
1174 SET_BIT(LPTIMx->CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1175 }
1176
1177 /**
1178 * @brief Get the Channel Mode.
1179 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_GetChannelMode\n
1180 * CCMR1 CC2SEL LL_LPTIM_CC_GetChannelMode
1181 * @param LPTIMx Low-Power Timer instance
1182 * @param Channel This parameter can be one of the following values:
1183 * @arg @ref LL_LPTIM_CHANNEL_CH1
1184 * @arg @ref LL_LPTIM_CHANNEL_CH2
1185 * @retval Returned value can be one of the following values:
1186 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1187 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1188 */
LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1189 __STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1190 {
1191 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel])) >> \
1192 LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1193 }
1194
1195 /**
1196 * @brief Get captured value for input channel 1.
1197 * @rmtoll CCR1 CCR1 LL_LPTIM_IC_GetCaptureCH1
1198 * @note The real capture value corresponding to the input capture trigger can be calculated using
1199 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1200 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1201 * @param LPTIMx Low-Power Timer instance
1202 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1203 */
LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef * LPTIMx)1204 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef *LPTIMx)
1205 {
1206 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
1207 }
1208
1209 /**
1210 * @brief Get captured value for input channel 2.
1211 * @rmtoll CCR2 CCR2 LL_LPTIM_IC_GetCaptureCH2
1212 * @note The real capture value corresponding to the input capture trigger can be calculated using
1213 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1214 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1215 * @param LPTIMx Low-Power Timer instance
1216 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1217 */
LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef * LPTIMx)1218 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef *LPTIMx)
1219 {
1220 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
1221 }
1222
1223 /**
1224 * @}
1225 */
1226
1227 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
1228 * @{
1229 */
1230
1231 /**
1232 * @brief Enable the timeout function
1233 * @note This function must be called when the LPTIM instance is disabled.
1234 * @note The first trigger event will start the timer, any successive trigger
1235 * event will reset the counter and the timer will restart.
1236 * @note The timeout value corresponds to the compare value; if no trigger
1237 * occurs within the expected time frame, the MCU is waked-up by the
1238 * compare match event.
1239 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
1240 * @param LPTIMx Low-Power Timer instance
1241 * @retval None
1242 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)1243 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
1244 {
1245 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1246 }
1247
1248 /**
1249 * @brief Disable the timeout function
1250 * @note This function must be called when the LPTIM instance is disabled.
1251 * @note A trigger event arriving when the timer is already started will be
1252 * ignored.
1253 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
1254 * @param LPTIMx Low-Power Timer instance
1255 * @retval None
1256 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)1257 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
1258 {
1259 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1260 }
1261
1262 /**
1263 * @brief Indicate whether the timeout function is enabled.
1264 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
1265 * @param LPTIMx Low-Power Timer instance
1266 * @retval State of bit (1 or 0).
1267 */
LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef * LPTIMx)1268 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
1269 {
1270 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
1271 }
1272
1273 /**
1274 * @brief Start the LPTIM counter
1275 * @note This function must be called when the LPTIM instance is disabled.
1276 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
1277 * @param LPTIMx Low-Power Timer instance
1278 * @retval None
1279 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)1280 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
1281 {
1282 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
1283 }
1284
1285 /**
1286 * @brief Configure the external trigger used as a trigger event for the LPTIM.
1287 * @note This function must be called when the LPTIM instance is disabled.
1288 * @note An internal clock source must be present when a digital filter is
1289 * required for the trigger.
1290 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
1291 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
1292 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
1293 * @param LPTIMx Low-Power Timer instance
1294 * @param Source This parameter can be one of the following values:
1295 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1296 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1297 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1298 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1299 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1300 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 (*)
1301 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 (*)
1302 *
1303 * (*) Value not defined in all devices. \n
1304 *
1305 * @param Filter This parameter can be one of the following values:
1306 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1307 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1308 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1309 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1310 * @param Polarity This parameter can be one of the following values:
1311 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1312 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1313 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1314 * @retval None
1315 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)1316 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
1317 {
1318 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
1319 }
1320
1321 /**
1322 * @brief Get actual external trigger source.
1323 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
1324 * @param LPTIMx Low-Power Timer instance
1325 * @retval Returned value can be one of the following values:
1326 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1327 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1328 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1329 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1330 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1331 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 (*)
1332 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 (*)
1333 *
1334 * (*) Value not defined in all devices. \n
1335 *
1336 */
LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef * LPTIMx)1337 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
1338 {
1339 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
1340 }
1341
1342 /**
1343 * @brief Get actual external trigger filter.
1344 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
1345 * @param LPTIMx Low-Power Timer instance
1346 * @retval Returned value can be one of the following values:
1347 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1348 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1349 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1350 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1351 */
LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef * LPTIMx)1352 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
1353 {
1354 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
1355 }
1356
1357 /**
1358 * @brief Get actual external trigger polarity.
1359 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
1360 * @param LPTIMx Low-Power Timer instance
1361 * @retval Returned value can be one of the following values:
1362 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1363 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1364 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1365 */
LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef * LPTIMx)1366 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
1367 {
1368 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
1369 }
1370
1371 /**
1372 * @}
1373 */
1374
1375 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
1376 * @{
1377 */
1378
1379 /**
1380 * @brief Set the source of the clock used by the LPTIM instance.
1381 * @note This function must be called when the LPTIM instance is disabled.
1382 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
1383 * @param LPTIMx Low-Power Timer instance
1384 * @param ClockSource This parameter can be one of the following values:
1385 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1386 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1387 * @retval None
1388 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)1389 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
1390 {
1391 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
1392 }
1393
1394 /**
1395 * @brief Get actual LPTIM instance clock source.
1396 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
1397 * @param LPTIMx Low-Power Timer instance
1398 * @retval Returned value can be one of the following values:
1399 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1400 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1401 */
LL_LPTIM_GetClockSource(const LPTIM_TypeDef * LPTIMx)1402 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
1403 {
1404 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
1405 }
1406
1407 /**
1408 * @brief Configure the active edge or edges used by the counter when
1409 the LPTIM is clocked by an external clock source.
1410 * @note This function must be called when the LPTIM instance is disabled.
1411 * @note When both external clock signal edges are considered active ones,
1412 * the LPTIM must also be clocked by an internal clock source with a
1413 * frequency equal to at least four times the external clock frequency.
1414 * @note An internal clock source must be present when a digital filter is
1415 * required for external clock.
1416 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
1417 * CFGR CKPOL LL_LPTIM_ConfigClock
1418 * @param LPTIMx Low-Power Timer instance
1419 * @param ClockFilter This parameter can be one of the following values:
1420 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1421 * @arg @ref LL_LPTIM_CLK_FILTER_2
1422 * @arg @ref LL_LPTIM_CLK_FILTER_4
1423 * @arg @ref LL_LPTIM_CLK_FILTER_8
1424 * @param ClockPolarity This parameter can be one of the following values:
1425 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1426 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1427 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1428 * @retval None
1429 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)1430 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
1431 {
1432 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
1433 }
1434
1435 /**
1436 * @brief Get actual clock polarity
1437 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
1438 * @param LPTIMx Low-Power Timer instance
1439 * @retval Returned value can be one of the following values:
1440 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1441 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1442 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1443 */
LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef * LPTIMx)1444 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
1445 {
1446 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1447 }
1448
1449 /**
1450 * @brief Get actual clock digital filter
1451 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
1452 * @param LPTIMx Low-Power Timer instance
1453 * @retval Returned value can be one of the following values:
1454 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1455 * @arg @ref LL_LPTIM_CLK_FILTER_2
1456 * @arg @ref LL_LPTIM_CLK_FILTER_4
1457 * @arg @ref LL_LPTIM_CLK_FILTER_8
1458 */
LL_LPTIM_GetClockFilter(const LPTIM_TypeDef * LPTIMx)1459 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
1460 {
1461 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
1462 }
1463
1464 /**
1465 * @}
1466 */
1467
1468 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
1469 * @{
1470 */
1471
1472 /**
1473 * @brief Configure the encoder mode.
1474 * @note This function must be called when the LPTIM instance is disabled.
1475 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1476 * @param LPTIMx Low-Power Timer instance
1477 * @param EncoderMode This parameter can be one of the following values:
1478 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1479 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1480 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1481 * @retval None
1482 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1483 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1484 {
1485 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1486 }
1487
1488 /**
1489 * @brief Get actual encoder mode.
1490 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1491 * @param LPTIMx Low-Power Timer instance
1492 * @retval Returned value can be one of the following values:
1493 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1494 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1495 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1496 */
LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef * LPTIMx)1497 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
1498 {
1499 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1500 }
1501
1502 /**
1503 * @brief Enable the encoder mode
1504 * @note This function must be called when the LPTIM instance is disabled.
1505 * @note In this mode the LPTIM instance must be clocked by an internal clock
1506 * source. Also, the prescaler division ratio must be equal to 1.
1507 * @note LPTIM instance must be configured in continuous mode prior enabling
1508 * the encoder mode.
1509 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1510 * @param LPTIMx Low-Power Timer instance
1511 * @retval None
1512 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1513 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1514 {
1515 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1516 }
1517
1518 /**
1519 * @brief Disable the encoder mode
1520 * @note This function must be called when the LPTIM instance is disabled.
1521 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1522 * @param LPTIMx Low-Power Timer instance
1523 * @retval None
1524 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1525 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1526 {
1527 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1528 }
1529
1530 /**
1531 * @brief Indicates whether the LPTIM operates in encoder mode.
1532 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1533 * @param LPTIMx Low-Power Timer instance
1534 * @retval State of bit (1 or 0).
1535 */
LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef * LPTIMx)1536 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
1537 {
1538 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1539 }
1540
1541 /**
1542 * @}
1543 */
1544
1545 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1546 * @{
1547 */
1548
1549 /**
1550 * @brief Clear the compare match flag for channel 1 (CC1CF)
1551 * @rmtoll ICR CC1CF LL_LPTIM_ClearFlag_CC1
1552 * @param LPTIMx Low-Power Timer instance
1553 * @retval None
1554 */
LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef * LPTIMx)1555 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef *LPTIMx)
1556 {
1557 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1CF);
1558 }
1559
1560 /**
1561 * @brief Inform application whether a capture/compare interrupt has occurred for channel 1.
1562 * @rmtoll ISR CC1IF LL_LPTIM_IsActiveFlag_CC1
1563 * @param LPTIMx Low-Power Timer instance
1564 * @retval State of bit (1 or 0).
1565 */
LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef * LPTIMx)1566 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef *LPTIMx)
1567 {
1568 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL));
1569 }
1570
1571 /**
1572 * @brief Clear the compare match flag for channel 2 (CC2CF)
1573 * @rmtoll ICR CC2CF LL_LPTIM_ClearFlag_CC2
1574 * @param LPTIMx Low-Power Timer instance
1575 * @retval None
1576 */
LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef * LPTIMx)1577 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef *LPTIMx)
1578 {
1579 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2CF);
1580 }
1581
1582 /**
1583 * @brief Inform application whether a capture/compare interrupt has occurred for channel 2.
1584 * @rmtoll ISR CC2IF LL_LPTIM_IsActiveFlag_CC2
1585 * @param LPTIMx Low-Power Timer instance
1586 * @retval State of bit (1 or 0).
1587 */
LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef * LPTIMx)1588 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef *LPTIMx)
1589 {
1590 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL));
1591 }
1592
1593 /**
1594 * @brief Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF)
1595 * @rmtoll ICR CC1OCF LL_LPTIM_ClearFlag_CC1O
1596 * @param LPTIMx Low-Power Timer instance
1597 * @retval None
1598 */
LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef * LPTIMx)1599 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef *LPTIMx)
1600 {
1601 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1OCF);
1602 }
1603
1604 /**
1605 * @brief Inform application whether a Capture/Compare 1 over-capture has occurred for channel 1.
1606 * @rmtoll ISR CC1OF LL_LPTIM_IsActiveFlag_CC1O
1607 * @param LPTIMx Low-Power Timer instance
1608 * @retval State of bit (1 or 0).
1609 */
LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef * LPTIMx)1610 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef *LPTIMx)
1611 {
1612 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL));
1613 }
1614
1615 /**
1616 * @brief Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF)
1617 * @rmtoll ICR CC2OCF LL_LPTIM_ClearFlag_CC2O
1618 * @param LPTIMx Low-Power Timer instance
1619 * @retval None
1620 */
LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef * LPTIMx)1621 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef *LPTIMx)
1622 {
1623 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2OCF);
1624 }
1625
1626 /**
1627 * @brief Inform application whether a Capture/Compare 2 over-capture has occurred for channel 2.
1628 * @rmtoll ISR CC2OF LL_LPTIM_IsActiveFlag_CC2O
1629 * @param LPTIMx Low-Power Timer instance
1630 * @retval State of bit (1 or 0).
1631 */
LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef * LPTIMx)1632 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx)
1633 {
1634 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL));
1635 }
1636 /**
1637 * @brief Clear the autoreload match flag (ARRMCF)
1638 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
1639 * @param LPTIMx Low-Power Timer instance
1640 * @retval None
1641 */
LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef * LPTIMx)1642 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1643 {
1644 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1645 }
1646
1647 /**
1648 * @brief Inform application whether a autoreload match interrupt has occurred.
1649 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1650 * @param LPTIMx Low-Power Timer instance
1651 * @retval State of bit (1 or 0).
1652 */
LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef * LPTIMx)1653 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
1654 {
1655 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1656 }
1657
1658 /**
1659 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1660 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1661 * @param LPTIMx Low-Power Timer instance
1662 * @retval None
1663 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1664 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1665 {
1666 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1667 }
1668
1669 /**
1670 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1671 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1672 * @param LPTIMx Low-Power Timer instance
1673 * @retval State of bit (1 or 0).
1674 */
LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1675 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1676 {
1677 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1678 }
1679
1680 /**
1681 * @brief Clear the compare register update interrupt flag (CMP1OKCF).
1682 * @rmtoll ICR CMP1OKCF LL_LPTIM_ClearFlag_CMP1OK
1683 * @param LPTIMx Low-Power Timer instance
1684 * @retval None
1685 */
LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef * LPTIMx)1686 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *LPTIMx)
1687 {
1688 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP1OKCF);
1689 }
1690
1691 /**
1692 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR1 register has been successfully
1693 completed. If so, a new one can be initiated.
1694 * @rmtoll ISR CMP1OK LL_LPTIM_IsActiveFlag_CMP1OK
1695 * @param LPTIMx Low-Power Timer instance
1696 * @retval State of bit (1 or 0).
1697 */
LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef * LPTIMx)1698 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef *LPTIMx)
1699 {
1700 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL));
1701 }
1702
1703 /**
1704 * @brief Clear the compare register update interrupt flag (CMP2OKCF).
1705 * @rmtoll ICR CMP2OKCF LL_LPTIM_ClearFlag_CMP2OK
1706 * @param LPTIMx Low-Power Timer instance
1707 * @retval None
1708 */
LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef * LPTIMx)1709 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *LPTIMx)
1710 {
1711 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP2OKCF);
1712 }
1713
1714 /**
1715 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR2 register has been successfully
1716 completed. If so, a new one can be initiated.
1717 * @rmtoll ISR CMP2OK LL_LPTIM_IsActiveFlag_CMP2OK
1718 * @param LPTIMx Low-Power Timer instance
1719 * @retval State of bit (1 or 0).
1720 */
LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef * LPTIMx)1721 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef *LPTIMx)
1722 {
1723 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL));
1724 }
1725
1726 /**
1727 * @brief Clear the interrupt register update interrupt flag (DIEROKCF).
1728 * @rmtoll ICR DIEROKCF LL_LPTIM_ClearFlag_DIEROK
1729 * @param LPTIMx Low-Power Timer instance
1730 * @retval None
1731 */
LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef * LPTIMx)1732 __STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *LPTIMx)
1733 {
1734 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DIEROKCF);
1735 }
1736
1737 /**
1738 * @brief Informs application whether the APB bus write operation to the LPTIMx_DIER register has been successfully
1739 completed. If so, a new one can be initiated.
1740 * @rmtoll ISR DIEROK LL_LPTIM_IsActiveFlag_DIEROK
1741 * @param LPTIMx Low-Power Timer instance
1742 * @retval State of bit (1 or 0).
1743 */
LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef * LPTIMx)1744 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef *LPTIMx)
1745 {
1746 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL);
1747 }
1748
1749 /**
1750 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1751 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1752 * @param LPTIMx Low-Power Timer instance
1753 * @retval None
1754 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1755 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1756 {
1757 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1758 }
1759
1760 /**
1761 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1762 completed. If so, a new one can be initiated.
1763 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1764 * @param LPTIMx Low-Power Timer instance
1765 * @retval State of bit (1 or 0).
1766 */
LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef * LPTIMx)1767 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
1768 {
1769 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1770 }
1771
1772 /**
1773 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1774 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1775 * @param LPTIMx Low-Power Timer instance
1776 * @retval None
1777 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1778 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1779 {
1780 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1781 }
1782
1783 /**
1784 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1785 operates in encoder mode).
1786 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1787 * @param LPTIMx Low-Power Timer instance
1788 * @retval State of bit (1 or 0).
1789 */
LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef * LPTIMx)1790 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
1791 {
1792 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1793 }
1794
1795 /**
1796 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1797 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1798 * @param LPTIMx Low-Power Timer instance
1799 * @retval None
1800 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1801 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1802 {
1803 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1804 }
1805
1806 /**
1807 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1808 operates in encoder mode).
1809 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1810 * @param LPTIMx Low-Power Timer instance
1811 * @retval State of bit (1 or 0).
1812 */
LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef * LPTIMx)1813 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
1814 {
1815 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1816 }
1817
1818 /**
1819 * @brief Clear the repetition register update interrupt flag (REPOKCF).
1820 * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK
1821 * @param LPTIMx Low-Power Timer instance
1822 * @retval None
1823 */
LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef * LPTIMx)1824 __STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
1825 {
1826 SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
1827 }
1828
1829 /**
1830 * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
1831 completed; If so, a new one can be initiated.
1832 * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
1833 * @param LPTIMx Low-Power Timer instance
1834 * @retval State of bit (1 or 0).
1835 */
LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef * LPTIMx)1836 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx)
1837 {
1838 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
1839 }
1840
1841 /**
1842 * @brief Clear the update event flag (UECF).
1843 * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE
1844 * @param LPTIMx Low-Power Timer instance
1845 * @retval None
1846 */
LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef * LPTIMx)1847 __STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
1848 {
1849 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
1850 }
1851
1852 /**
1853 * @brief Informs application whether the LPTIMx update event has occurred.
1854 * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE
1855 * @param LPTIMx Low-Power Timer instance
1856 * @retval State of bit (1 or 0).
1857 */
LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef * LPTIMx)1858 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx)
1859 {
1860 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
1861 }
1862
1863 /**
1864 * @}
1865 */
1866
1867 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1868 * @{
1869 */
1870 /**
1871 * @brief Enable capture/compare 1 interrupt (CC1IE).
1872 * @rmtoll DIER CC1IE LL_LPTIM_EnableIT_CC1
1873 * @param LPTIMx Low-Power Timer instance
1874 * @retval None
1875 */
LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef * LPTIMx)1876 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef *LPTIMx)
1877 {
1878 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1879 }
1880
1881 /**
1882 * @brief Disable capture/compare 1 interrupt (CC1IE).
1883 * @rmtoll DIER CC1IE LL_LPTIM_DisableIT_CC1
1884 * @param LPTIMx Low-Power Timer instance
1885 * @retval None
1886 */
LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef * LPTIMx)1887 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *LPTIMx)
1888 {
1889 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1890 }
1891
1892 /**
1893 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
1894 * @rmtoll DIER CC1IE LL_LPTIM_IsEnabledIT_CC1
1895 * @param LPTIMx Low-Power Timer instance
1896 * @retval State of bit (1 or 0).
1897 */
LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef * LPTIMx)1898 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef *LPTIMx)
1899 {
1900 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL));
1901 }
1902
1903 /**
1904 * @brief Enable capture/compare 1 interrupt (CC2IE).
1905 * @rmtoll DIER CC2IE LL_LPTIM_EnableIT_CC2
1906 * @param LPTIMx Low-Power Timer instance
1907 * @retval None
1908 */
LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef * LPTIMx)1909 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef *LPTIMx)
1910 {
1911 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
1912 }
1913
1914 /**
1915 * @brief Disable capture/compare 2 interrupt (CC2IE).
1916 * @rmtoll DIER CC2IE LL_LPTIM_DisableIT_CC2
1917 * @param LPTIMx Low-Power Timer instance
1918 * @retval None
1919 */
LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef * LPTIMx)1920 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *LPTIMx)
1921 {
1922 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
1923 }
1924
1925 /**
1926 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
1927 * @rmtoll DIER CC2IE LL_LPTIM_IsEnabledIT_CC2
1928 * @param LPTIMx Low-Power Timer instance
1929 * @retval State of bit (1 or 0).
1930 */
LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef * LPTIMx)1931 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef *LPTIMx)
1932 {
1933 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL));
1934 }
1935
1936 /**
1937 * @brief Enable capture/compare 1 over-capture interrupt (CC1OIE).
1938 * @rmtoll DIER CC1OIE LL_LPTIM_EnableIT_CC1O
1939 * @param LPTIMx Low-Power Timer instance
1940 * @retval None
1941 */
LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef * LPTIMx)1942 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *LPTIMx)
1943 {
1944 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
1945 }
1946
1947 /**
1948 * @brief Disable capture/compare 1 over-capture interrupt (CC1OIE).
1949 * @rmtoll DIER CC1OIE LL_LPTIM_DisableIT_CC1O
1950 * @param LPTIMx Low-Power Timer instance
1951 * @retval None
1952 */
LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef * LPTIMx)1953 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *LPTIMx)
1954 {
1955 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
1956 }
1957
1958 /**
1959 * @brief Indicates whether the capture/compare 1 over-capture interrupt (CC1OIE) is enabled.
1960 * @rmtoll DIER CC1OIE LL_LPTIM_IsEnabledIT_CC1O
1961 * @param LPTIMx Low-Power Timer instance
1962 * @retval State of bit (1 or 0).
1963 */
LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef * LPTIMx)1964 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef *LPTIMx)
1965 {
1966 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL));
1967 }
1968
1969 /**
1970 * @brief Enable capture/compare 1 over-capture interrupt (CC2OIE).
1971 * @rmtoll DIER CC2OIE LL_LPTIM_EnableIT_CC2O
1972 * @param LPTIMx Low-Power Timer instance
1973 * @retval None
1974 */
LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef * LPTIMx)1975 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *LPTIMx)
1976 {
1977 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
1978 }
1979
1980 /**
1981 * @brief Disable capture/compare 1 over-capture interrupt (CC2OIE).
1982 * @rmtoll DIER CC2OIE LL_LPTIM_DisableIT_CC2O
1983 * @param LPTIMx Low-Power Timer instance
1984 * @retval None
1985 */
LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef * LPTIMx)1986 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *LPTIMx)
1987 {
1988 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
1989 }
1990
1991 /**
1992 * @brief Indicates whether the capture/compare 2 over-capture interrupt (CC2OIE) is enabled.
1993 * @rmtoll DIER CC2OIE LL_LPTIM_IsEnabledIT_CC2O
1994 * @param LPTIMx Low-Power Timer instance
1995 * @retval State of bit (1 or 0).
1996 */
LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef * LPTIMx)1997 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef *LPTIMx)
1998 {
1999 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL));
2000 }
2001
2002 /**
2003 * @brief Enable autoreload match interrupt (ARRMIE).
2004 * @rmtoll DIER ARRMIE LL_LPTIM_EnableIT_ARRM
2005 * @param LPTIMx Low-Power Timer instance
2006 * @retval None
2007 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)2008 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2009 {
2010 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2011 }
2012
2013 /**
2014 * @brief Disable autoreload match interrupt (ARRMIE).
2015 * @rmtoll DIER ARRMIE LL_LPTIM_DisableIT_ARRM
2016 * @param LPTIMx Low-Power Timer instance
2017 * @retval None
2018 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)2019 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2020 {
2021 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2022 }
2023
2024 /**
2025 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
2026 * @rmtoll DIER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
2027 * @param LPTIMx Low-Power Timer instance
2028 * @retval State of bit (1 or 0).
2029 */
LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef * LPTIMx)2030 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
2031 {
2032 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL));
2033 }
2034
2035 /**
2036 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
2037 * @rmtoll DIER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
2038 * @param LPTIMx Low-Power Timer instance
2039 * @retval None
2040 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2041 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2042 {
2043 SET_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2044 }
2045
2046 /**
2047 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
2048 * @rmtoll DIER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
2049 * @param LPTIMx Low-Power Timer instance
2050 * @retval None
2051 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2052 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2053 {
2054 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2055 }
2056
2057 /**
2058 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
2059 * @rmtoll DIER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
2060 * @param LPTIMx Low-Power Timer instance
2061 * @retval State of bit (1 or 0).
2062 */
LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef * LPTIMx)2063 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
2064 {
2065 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL));
2066 }
2067
2068 /**
2069 * @brief Enable compare register write completed interrupt (CMP1OKIE).
2070 * @rmtoll IER CMP1OKIE LL_LPTIM_EnableIT_CMP1OK
2071 * @param LPTIMx Low-Power Timer instance
2072 * @retval None
2073 */
LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2074 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2075 {
2076 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2077 }
2078
2079 /**
2080 * @brief Disable compare register write completed interrupt (CMP1OKIE).
2081 * @rmtoll IER CMPO1KIE LL_LPTIM_DisableIT_CMP1OK
2082 * @param LPTIMx Low-Power Timer instance
2083 * @retval None
2084 */
LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2085 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2086 {
2087 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2088 }
2089
2090 /**
2091 * @brief Indicates whether the compare register write completed interrupt (CMP1OKIE) is enabled.
2092 * @rmtoll IER CMP1OKIE LL_LPTIM_IsEnabledIT_CMP1OK
2093 * @param LPTIMx Low-Power Timer instance
2094 * @retval State of bit (1 or 0).
2095 */
LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef * LPTIMx)2096 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef *LPTIMx)
2097 {
2098 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL));
2099 }
2100
2101 /**
2102 * @brief Enable compare register write completed interrupt (CMP2OKIE).
2103 * @rmtoll IER CMP2OKIE LL_LPTIM_EnableIT_CMP2OK
2104 * @param LPTIMx Low-Power Timer instance
2105 * @retval None
2106 */
LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2107 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2108 {
2109 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2110 }
2111
2112 /**
2113 * @brief Disable compare register write completed interrupt (CMP2OKIE).
2114 * @rmtoll IER CMP2OKIE LL_LPTIM_DisableIT_CMP2OK
2115 * @param LPTIMx Low-Power Timer instance
2116 * @retval None
2117 */
LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2118 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2119 {
2120 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2121 }
2122
2123 /**
2124 * @brief Indicates whether the compare register write completed interrupt (CMP2OKIE) is enabled.
2125 * @rmtoll IER CMP2OKIE LL_LPTIM_IsEnabledIT_CMP2OK
2126 * @param LPTIMx Low-Power Timer instance
2127 * @retval State of bit (1 or 0).
2128 */
LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef * LPTIMx)2129 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef *LPTIMx)
2130 {
2131 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL));
2132 }
2133
2134 /**
2135 * @brief Enable autoreload register write completed interrupt (ARROKIE).
2136 * @rmtoll DIER ARROKIE LL_LPTIM_EnableIT_ARROK
2137 * @param LPTIMx Low-Power Timer instance
2138 * @retval None
2139 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)2140 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2141 {
2142 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2143 }
2144
2145 /**
2146 * @brief Disable autoreload register write completed interrupt (ARROKIE).
2147 * @rmtoll DIER ARROKIE LL_LPTIM_DisableIT_ARROK
2148 * @param LPTIMx Low-Power Timer instance
2149 * @retval None
2150 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)2151 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2152 {
2153 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2154 }
2155
2156 /**
2157 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
2158 * @rmtoll DIER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
2159 * @param LPTIMx Low-Power Timer instance
2160 * @retval State of bit(1 or 0).
2161 */
LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef * LPTIMx)2162 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
2163 {
2164 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL));
2165 }
2166
2167 /**
2168 * @brief Enable direction change to up interrupt (UPIE).
2169 * @rmtoll DIER UPIE LL_LPTIM_EnableIT_UP
2170 * @param LPTIMx Low-Power Timer instance
2171 * @retval None
2172 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)2173 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
2174 {
2175 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2176 }
2177
2178 /**
2179 * @brief Disable direction change to up interrupt (UPIE).
2180 * @rmtoll DIER UPIE LL_LPTIM_DisableIT_UP
2181 * @param LPTIMx Low-Power Timer instance
2182 * @retval None
2183 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)2184 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
2185 {
2186 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2187 }
2188
2189 /**
2190 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
2191 * @rmtoll DIER UPIE LL_LPTIM_IsEnabledIT_UP
2192 * @param LPTIMx Low-Power Timer instance
2193 * @retval State of bit(1 or 0).
2194 */
LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef * LPTIMx)2195 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
2196 {
2197 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL));
2198 }
2199
2200 /**
2201 * @brief Enable direction change to down interrupt (DOWNIE).
2202 * @rmtoll DIER DOWNIE LL_LPTIM_EnableIT_DOWN
2203 * @param LPTIMx Low-Power Timer instance
2204 * @retval None
2205 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)2206 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2207 {
2208 SET_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2209 }
2210
2211 /**
2212 * @brief Disable direction change to down interrupt (DOWNIE).
2213 * @rmtoll DIER DOWNIE LL_LPTIM_DisableIT_DOWN
2214 * @param LPTIMx Low-Power Timer instance
2215 * @retval None
2216 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)2217 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2218 {
2219 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2220 }
2221
2222 /**
2223 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
2224 * @rmtoll DIER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
2225 * @param LPTIMx Low-Power Timer instance
2226 * @retval State of bit(1 or 0).
2227 */
LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef * LPTIMx)2228 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
2229 {
2230 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL);
2231 }
2232
2233 /**
2234 * @brief Enable repetition register update successfully completed interrupt (REPOKIE).
2235 * @rmtoll DIER REPOKIE LL_LPTIM_EnableIT_REPOK
2236 * @param LPTIMx Low-Power Timer instance
2237 * @retval None
2238 */
LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef * LPTIMx)2239 __STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2240 {
2241 SET_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2242 }
2243
2244 /**
2245 * @brief Disable repetition register update successfully completed interrupt (REPOKIE).
2246 * @rmtoll DIER REPOKIE LL_LPTIM_DisableIT_REPOK
2247 * @param LPTIMx Low-Power Timer instance
2248 * @retval None
2249 */
LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef * LPTIMx)2250 __STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2251 {
2252 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2253 }
2254
2255 /**
2256 * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
2257 * @rmtoll DIER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
2258 * @param LPTIMx Low-Power Timer instance
2259 * @retval State of bit(1 or 0).
2260 */
LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef * LPTIMx)2261 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx)
2262 {
2263 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL);
2264 }
2265
2266 /**
2267 * @brief Enable update event interrupt (UEIE).
2268 * @rmtoll DIER UEIE LL_LPTIM_EnableIT_UE
2269 * @param LPTIMx Low-Power Timer instance
2270 * @retval None
2271 */
LL_LPTIM_EnableIT_UE(LPTIM_TypeDef * LPTIMx)2272 __STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
2273 {
2274 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2275 }
2276
2277 /**
2278 * @brief Disable update event interrupt (UEIE).
2279 * @rmtoll DIER UEIE LL_LPTIM_DisableIT_UE
2280 * @param LPTIMx Low-Power Timer instance
2281 * @retval None
2282 */
LL_LPTIM_DisableIT_UE(LPTIM_TypeDef * LPTIMx)2283 __STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
2284 {
2285 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2286 }
2287
2288 /**
2289 * @brief Indicates whether the update event interrupt (UEIE) is enabled.
2290 * @rmtoll DIER UEIE LL_LPTIM_IsEnabledIT_UE
2291 * @param LPTIMx Low-Power Timer instance
2292 *@ retval State of bit(1 or 0).
2293 */
LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef * LPTIMx)2294 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx)
2295 {
2296 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL);
2297 }
2298 /**
2299 * @}
2300 */
2301
2302
2303 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
2304 * @{
2305 */
2306 /**
2307 * @brief Enable update DMA request.
2308 * @rmtoll DIER UEDE LL_LPTIM_EnableDMAReq_UPDATE
2309 * @param LPTIMx Low-Power Timer instance
2310 * @retval None
2311 */
LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2312 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2313 {
2314 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2315 }
2316
2317 /**
2318 * @brief Disable update DMA request.
2319 * @rmtoll DIER UEDE LL_LPTIM_DisableDMAReq_UPDATE
2320 * @param LPTIMx Low-Power Timer instance
2321 * @retval None
2322 */
LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2323 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2324 {
2325 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2326 }
2327
2328 /**
2329 * @brief Indicates whether the update DMA request is enabled.
2330 * @rmtoll DIER UEDE LL_LPTIM_IsEnabledDMAReq_UPDATE
2331 * @param LPTIMx Low-Power Timer instance
2332 * @retval State of bit (1 or 0).
2333 */
LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef * LPTIMx)2334 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef *LPTIMx)
2335 {
2336 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL);
2337 }
2338
2339 /**
2340 * @brief Enable capture/compare 1 DMA request (CC1DE).
2341 * @rmtoll DIER CC1DE LL_LPTIM_EnableDMAReq_CC1
2342 * @param LPTIMx Low-Power Timer instance
2343 * @retval None
2344 */
LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2345 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2346 {
2347 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2348 }
2349
2350 /**
2351 * @brief Disable capture/compare 1 DMA request (CC1DE).
2352 * @rmtoll DIER CC1DE LL_LPTIM_DisableDMAReq_CC1
2353 * @param LPTIMx Low-Power Timer instance
2354 * @retval None
2355 */
LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2356 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2357 {
2358 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2359 }
2360
2361 /**
2362 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
2363 * @rmtoll DIER CC1DE LL_LPTIM_IsEnabledDMAReq_CC1
2364 * @param LPTIMx Low-Power Timer instance
2365 * @retval State of bit (1 or 0).
2366 */
LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef * LPTIMx)2367 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef *LPTIMx)
2368 {
2369 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL);
2370 }
2371
2372 /**
2373 * @brief Enable capture/compare 2 DMA request (CC2DE).
2374 * @rmtoll DIER CC2DE LL_LPTIM_EnableDMAReq_CC2
2375 * @param LPTIMx Low-Power Timer instance
2376 * @retval None
2377 */
LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2378 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2379 {
2380 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2381 }
2382
2383 /**
2384 * @brief Disable capture/compare 2 DMA request (CC2DE).
2385 * @rmtoll DIER CC2DE LL_LPTIM_DisableDMAReq_CC2
2386 * @param LPTIMx Low-Power Timer instance
2387 * @retval None
2388 */
LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2389 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2390 {
2391 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2392 }
2393
2394 /**
2395 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
2396 * @rmtoll DIER CC2DE LL_LPTIM_IsEnabledDMAReq_CC2
2397 * @param LPTIMx Low-Power Timer instance
2398 * @retval State of bit (1 or 0).
2399 */
LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef * LPTIMx)2400 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef *LPTIMx)
2401 {
2402 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL);
2403 }
2404
2405 /**
2406 * @}
2407 */
2408 /**
2409 * @}
2410 */
2411
2412 /**
2413 * @}
2414 */
2415
2416 #endif /* LPTIM1 || LPTIM2 */
2417
2418 /**
2419 * @}
2420 */
2421
2422 #ifdef __cplusplus
2423 }
2424 #endif
2425
2426 #endif /* STM32WBAxx_LL_LPTIM_H */
2427
