1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_i2c.h
4 * @author MCD Application Team
5 * @brief Header file of I2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBAxx_LL_I2C_H
21 #define STM32WBAxx_LL_I2C_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined (I2C1) || defined (I2C3)
35
36 /** @defgroup I2C_LL I2C
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
45 * @{
46 */
47 /**
48 * @}
49 */
50
51 /* Private macros ------------------------------------------------------------*/
52 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
53 * @{
54 */
55 #if defined(I2C_TRIG_GRP1)
56 #define IS_LL_I2C_GRP1_INSTANCE(__INSTANCE__) IS_I2C_GRP1_INSTANCE(__INSTANCE__)
57 #endif /* I2C_TRIG_GRP1 */
58
59 #define IS_LL_I2C_GRP2_INSTANCE(__INSTANCE__) IS_I2C_GRP2_INSTANCE(__INSTANCE__)
60 /**
61 * @}
62 */
63
64 /* Exported types ------------------------------------------------------------*/
65 #if defined(USE_FULL_LL_DRIVER)
66 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
67 * @{
68 */
69 typedef struct
70 {
71 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
72 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
73
74 This feature can be modified afterwards using unitary function
75 @ref LL_I2C_SetMode(). */
76
77 uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
78 This parameter must be set by referring to the STM32CubeMX Tool and
79 the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
80
81 This feature can be modified afterwards using unitary function
82 @ref LL_I2C_SetTiming(). */
83
84 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
85 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
86
87 This feature can be modified afterwards using unitary functions
88 @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
89
90 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
91 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
92
93 This feature can be modified afterwards using unitary function
94 @ref LL_I2C_SetDigitalFilter(). */
95
96 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
97 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
98
99 This feature can be modified afterwards using unitary function
100 @ref LL_I2C_SetOwnAddress1(). */
101
102 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
103 match code or next received byte.
104 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
105
106 This feature can be modified afterwards using unitary function
107 @ref LL_I2C_AcknowledgeNextData(). */
108
109 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
110 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
111
112 This feature can be modified afterwards using unitary function
113 @ref LL_I2C_SetOwnAddress1(). */
114 } LL_I2C_InitTypeDef;
115 /**
116 * @}
117 */
118 #endif /*USE_FULL_LL_DRIVER*/
119
120 /* Exported constants --------------------------------------------------------*/
121 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
122 * @{
123 */
124
125 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
126 * @brief Flags defines which can be used with LL_I2C_WriteReg function
127 * @{
128 */
129 #define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
130 #define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
131 #define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
132 #define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
133 #define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
134 #define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
135 #define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
136 #define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
137 #define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
138 /**
139 * @}
140 */
141
142 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
143 * @brief Flags defines which can be used with LL_I2C_ReadReg function
144 * @{
145 */
146 #define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
147 #define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
148 #define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
149 #define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
150 #define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
151 #define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
152 #define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
153 #define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
154 #define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
155 #define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
156 #define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
157 #define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
158 #define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
159 #define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
160 #define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
161 /**
162 * @}
163 */
164
165 /** @defgroup I2C_LL_EC_IT IT Defines
166 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
167 * @{
168 */
169 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
170 #define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
171 #define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
172 #define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
173 #define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
174 #define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
175 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
176 /**
177 * @}
178 */
179
180 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
181 * @{
182 */
183 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
184 #define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
185 #define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode
186 (Default address not acknowledge) */
187 #define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
188 /**
189 * @}
190 */
191
192 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
193 * @{
194 */
195 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
196 #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
197 /**
198 * @}
199 */
200
201 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
202 * @{
203 */
204 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
205 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
206 /**
207 * @}
208 */
209
210 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
211 * @{
212 */
213 #define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
214 #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
215 /**
216 * @}
217 */
218
219 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
220 * @{
221 */
222 #define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
223 #define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
224 #define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
225 #define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
226 #define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
227 #define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
228 #define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
229 #define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done.
230 All Address2 are acknowledged. */
231 /**
232 * @}
233 */
234
235 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
236 * @{
237 */
238 #define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
239 #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
240 /**
241 * @}
242 */
243
244 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
245 * @{
246 */
247 #define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
248 #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
249 /**
250 * @}
251 */
252
253 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
254 * @{
255 */
256 #define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
257 #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
258 /**
259 * @}
260 */
261
262 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
263 * @{
264 */
265 #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
266 #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode
267 with no HW PEC comparison. */
268 #define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode
269 with no HW PEC comparison. */
270 #define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode
271 with HW PEC comparison. */
272 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode
273 with HW PEC comparison. */
274 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode
275 with HW PEC comparison. */
276 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
277 /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
278 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
279 /*!< Enable SMBUS Software end mode with HW PEC comparison. */
280 /**
281 * @}
282 */
283
284 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
285 * @{
286 */
287 #define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
288 /*!< Don't Generate Stop and Start condition. */
289 #define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
290 /*!< Generate Stop condition (Size should be set to 0). */
291 #define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
292 /*!< Generate Start for read request. */
293 #define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
294 /*!< Generate Start for write request. */
295 #define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
296 /*!< Generate Restart for read request, slave 7Bit address. */
297 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
298 /*!< Generate Restart for write request, slave 7Bit address. */
299 #define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \
300 I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
301 /*!< Generate Restart for read request, slave 10Bit address. */
302 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
303 /*!< Generate Restart for write request, slave 10Bit address.*/
304 /**
305 * @}
306 */
307
308 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
309 * @{
310 */
311 #define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master,
312 slave enters receiver mode. */
313 #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master,
314 slave enters transmitter mode.*/
315 /**
316 * @}
317 */
318
319 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
320 * @{
321 */
322 #define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for
323 transmission */
324 #define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for
325 reception */
326 /**
327 * @}
328 */
329
330 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
331 * @{
332 */
333 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect
334 SCL low level timeout. */
335 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect
336 both SCL and SDA high level timeout.*/
337 /**
338 * @}
339 */
340
341 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
342 * @{
343 */
344 #define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
345 #define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock)
346 enable bit */
347 #define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
348 I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB
349 (extended clock) enable bits */
350 /**
351 * @}
352 */
353
354 /** @defgroup I2C_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection
355 * @brief I2C Autonomous Trigger selection
356 * @{
357 */
358 #if defined(I2C1)
359 #define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */
360 #endif /* I2C1 */
361 #define LL_I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */
362
363 #if defined(I2C_TRIG_GRP1)
364 #define LL_I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x00000000U))
365 /*!< HW Trigger signal is GPDMA_CH0_TRG */
366 #define LL_I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
367 /*!< HW Trigger signal is GPDMA_CH1_TRG */
368 #define LL_I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
369 /*!< HW Trigger signal is GPDMA_CH2_TRG */
370 #define LL_I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
371 /*!< HW Trigger signal is GPDMA_CH3_TRG */
372 #define LL_I2C_GRP1_EXTI5_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
373 /*!< HW Trigger signal is EXTI5_TRG */
374 #define LL_I2C_GRP1_EXTI9_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
375 /*!< HW Trigger signal is EXTI9_TRG */
376 #define LL_I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
377 /*!< HW Trigger signal is LPTIM1_CH1_TRG */
378 #define LL_I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
379 /*!< HW Trigger signal is LPTIM2_CH1_TRG */
380 #if defined(COMP1)
381 #define LL_I2C_GRP1_COMP1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
382 /*!< HW Trigger signal is COMP1_TRG */
383 #endif /* COMP1 */
384 #if defined(COMP2)
385 #define LL_I2C_GRP1_COMP2_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
386 /*!< HW Trigger signal is COMP2_TRG */
387 #endif /* COMP2 */
388 #define LL_I2C_GRP1_RTC_ALRA_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
389 /*!< HW Trigger signal is RTC_ALRA_TRG */
390 #define LL_I2C_GRP1_RTC_WUT_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
391 /*!< HW Trigger signal is RTC_WUT_TRG */
392 #endif /* I2C_TRIG_GRP1 */
393
394 #define LL_I2C_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x00000000U))
395 /*!< HW Trigger signal is GPDMA_CH0_TRG */
396 #define LL_I2C_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
397 /*!< HW Trigger signal is GPDMA_CH1_TRG */
398 #define LL_I2C_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
399 /*!< HW Trigger signal is GPDMA_CH2_TRG */
400 #define LL_I2C_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
401 /*!< HW Trigger signal is GPDMA_CH3_TRG */
402 #define LL_I2C_GRP2_EXTI5_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
403 /*!< HW Trigger signal is EXTI5_TRG */
404 #define LL_I2C_GRP2_EXTI8_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
405 /*!< HW Trigger signal is EXTI8_TRG */
406 #define LL_I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
407 /*!< HW Trigger signal is LPTIM1_CH1_TRG */
408 #if defined(COMP1)
409 #define LL_I2C_GRP2_COMP1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
410 /*!< HW Trigger signal is COMP1_TRG */
411 #endif /* COMP1 */
412 #if defined(COMP2)
413 #define LL_I2C_GRP2_COMP2_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
414 /*!< HW Trigger signal is COMP2_TRG */
415 #endif /* COMP2 */
416 #define LL_I2C_GRP2_RTC_ALRA_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
417 /*!< HW Trigger signal is RTC_ALRA_TRG */
418 #define LL_I2C_GRP2_RTC_WUT_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
419 /*!< HW Trigger signal is RTC_WUT_TRG */
420 /**
421 * @}
422 */
423
424 /** @defgroup I2C_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity
425 * @brief I2C Autonomous Trigger Polarity
426 * @{
427 */
428 #define LL_I2C_TRIG_POLARITY_RISING 0x00000000U /*!< I2C triggered on rising edge */
429 #define LL_I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /*!< I2C triggered on falling edge */
430 /**
431 * @}
432 */
433
434 /**
435 * @}
436 */
437
438 /* Exported macro ------------------------------------------------------------*/
439 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
440 * @{
441 */
442
443 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
444 * @{
445 */
446
447 /**
448 * @brief Write a value in I2C register
449 * @param __INSTANCE__ I2C Instance
450 * @param __REG__ Register to be written
451 * @param __VALUE__ Value to be written in the register
452 * @retval None
453 */
454 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
455
456 /**
457 * @brief Read a value in I2C register
458 * @param __INSTANCE__ I2C Instance
459 * @param __REG__ Register to be read
460 * @retval Register value
461 */
462 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
463 /**
464 * @}
465 */
466
467 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
468 * @{
469 */
470 /**
471 * @brief Configure the SDA setup, hold time and the SCL high, low period.
472 * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
473 * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
474 (tscldel = (SCLDEL+1)xtpresc)
475 * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
476 (tsdadel = SDADELxtpresc)
477 * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
478 (tsclh = (SCLH+1)xtpresc)
479 * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
480 (tscll = (SCLL+1)xtpresc)
481 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
482 */
483 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
484 ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
485 (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
486 (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
487 (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
488 (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
489 /**
490 * @}
491 */
492
493 /**
494 * @}
495 */
496
497 /* Exported functions --------------------------------------------------------*/
498 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
499 * @{
500 */
501
502 /** @defgroup I2C_LL_EF_Configuration Configuration
503 * @{
504 */
505
506 /**
507 * @brief Enable I2C peripheral (PE = 1).
508 * @rmtoll CR1 PE LL_I2C_Enable
509 * @param I2Cx I2C Instance.
510 * @retval None
511 */
LL_I2C_Enable(I2C_TypeDef * I2Cx)512 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
513 {
514 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
515 }
516
517 /**
518 * @brief Disable I2C peripheral (PE = 0).
519 * @note When PE = 0, the I2C SCL and SDA lines are released.
520 * Internal state machines and status bits are put back to their reset value.
521 * When cleared, PE must be kept low for at least 3 APB clock cycles.
522 * @rmtoll CR1 PE LL_I2C_Disable
523 * @param I2Cx I2C Instance.
524 * @retval None
525 */
LL_I2C_Disable(I2C_TypeDef * I2Cx)526 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
527 {
528 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
529 }
530
531 /**
532 * @brief Check if the I2C peripheral is enabled or disabled.
533 * @rmtoll CR1 PE LL_I2C_IsEnabled
534 * @param I2Cx I2C Instance.
535 * @retval State of bit (1 or 0).
536 */
LL_I2C_IsEnabled(const I2C_TypeDef * I2Cx)537 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
538 {
539 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
540 }
541
542 /**
543 * @brief Configure Noise Filters (Analog and Digital).
544 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
545 * The filters can only be programmed when the I2C is disabled (PE = 0).
546 * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
547 * CR1 DNF LL_I2C_ConfigFilters
548 * @param I2Cx I2C Instance.
549 * @param AnalogFilter This parameter can be one of the following values:
550 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
551 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
552 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
553 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
554 * This parameter is used to configure the digital noise filter on SDA and SCL input.
555 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
556 * @retval None
557 */
LL_I2C_ConfigFilters(I2C_TypeDef * I2Cx,uint32_t AnalogFilter,uint32_t DigitalFilter)558 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
559 {
560 MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
561 }
562
563 /**
564 * @brief Configure Digital Noise Filter.
565 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
566 * This filter can only be programmed when the I2C is disabled (PE = 0).
567 * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
568 * @param I2Cx I2C Instance.
569 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
570 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
571 * This parameter is used to configure the digital noise filter on SDA and SCL input.
572 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
573 * @retval None
574 */
LL_I2C_SetDigitalFilter(I2C_TypeDef * I2Cx,uint32_t DigitalFilter)575 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
576 {
577 MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
578 }
579
580 /**
581 * @brief Get the current Digital Noise Filter configuration.
582 * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
583 * @param I2Cx I2C Instance.
584 * @retval Value between Min_Data=0x0 and Max_Data=0xF
585 */
LL_I2C_GetDigitalFilter(const I2C_TypeDef * I2Cx)586 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
587 {
588 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
589 }
590
591 /**
592 * @brief Enable Analog Noise Filter.
593 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
594 * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
595 * @param I2Cx I2C Instance.
596 * @retval None
597 */
LL_I2C_EnableAnalogFilter(I2C_TypeDef * I2Cx)598 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
599 {
600 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
601 }
602
603 /**
604 * @brief Disable Analog Noise Filter.
605 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
606 * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
607 * @param I2Cx I2C Instance.
608 * @retval None
609 */
LL_I2C_DisableAnalogFilter(I2C_TypeDef * I2Cx)610 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
611 {
612 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
613 }
614
615 /**
616 * @brief Check if Analog Noise Filter is enabled or disabled.
617 * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
618 * @param I2Cx I2C Instance.
619 * @retval State of bit (1 or 0).
620 */
LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef * I2Cx)621 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
622 {
623 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
624 }
625
626 /**
627 * @brief Enable DMA transmission requests.
628 * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
629 * @param I2Cx I2C Instance.
630 * @retval None
631 */
LL_I2C_EnableDMAReq_TX(I2C_TypeDef * I2Cx)632 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
633 {
634 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
635 }
636
637 /**
638 * @brief Disable DMA transmission requests.
639 * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
640 * @param I2Cx I2C Instance.
641 * @retval None
642 */
LL_I2C_DisableDMAReq_TX(I2C_TypeDef * I2Cx)643 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
644 {
645 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
646 }
647
648 /**
649 * @brief Check if DMA transmission requests are enabled or disabled.
650 * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
651 * @param I2Cx I2C Instance.
652 * @retval State of bit (1 or 0).
653 */
LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef * I2Cx)654 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
655 {
656 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
657 }
658
659 /**
660 * @brief Enable DMA reception requests.
661 * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
662 * @param I2Cx I2C Instance.
663 * @retval None
664 */
LL_I2C_EnableDMAReq_RX(I2C_TypeDef * I2Cx)665 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
666 {
667 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
668 }
669
670 /**
671 * @brief Disable DMA reception requests.
672 * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
673 * @param I2Cx I2C Instance.
674 * @retval None
675 */
LL_I2C_DisableDMAReq_RX(I2C_TypeDef * I2Cx)676 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
677 {
678 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
679 }
680
681 /**
682 * @brief Check if DMA reception requests are enabled or disabled.
683 * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
684 * @param I2Cx I2C Instance.
685 * @retval State of bit (1 or 0).
686 */
LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef * I2Cx)687 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
688 {
689 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
690 }
691
692 /**
693 * @brief Get the data register address used for DMA transfer
694 * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
695 * RXDR RXDATA LL_I2C_DMA_GetRegAddr
696 * @param I2Cx I2C Instance
697 * @param Direction This parameter can be one of the following values:
698 * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
699 * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
700 * @retval Address of data register
701 */
LL_I2C_DMA_GetRegAddr(const I2C_TypeDef * I2Cx,uint32_t Direction)702 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
703 {
704 uint32_t data_reg_addr;
705
706 if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
707 {
708 /* return address of TXDR register */
709 data_reg_addr = (uint32_t) &(I2Cx->TXDR);
710 }
711 else
712 {
713 /* return address of RXDR register */
714 data_reg_addr = (uint32_t) &(I2Cx->RXDR);
715 }
716
717 return data_reg_addr;
718 }
719
720 /**
721 * @brief Enable Clock stretching.
722 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
723 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
724 * @param I2Cx I2C Instance.
725 * @retval None
726 */
LL_I2C_EnableClockStretching(I2C_TypeDef * I2Cx)727 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
728 {
729 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
730 }
731
732 /**
733 * @brief Disable Clock stretching.
734 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
735 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
736 * @param I2Cx I2C Instance.
737 * @retval None
738 */
LL_I2C_DisableClockStretching(I2C_TypeDef * I2Cx)739 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
740 {
741 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
742 }
743
744 /**
745 * @brief Check if Clock stretching is enabled or disabled.
746 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
747 * @param I2Cx I2C Instance.
748 * @retval State of bit (1 or 0).
749 */
LL_I2C_IsEnabledClockStretching(const I2C_TypeDef * I2Cx)750 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
751 {
752 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
753 }
754
755 /**
756 * @brief Enable hardware byte control in slave mode.
757 * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
758 * @param I2Cx I2C Instance.
759 * @retval None
760 */
LL_I2C_EnableSlaveByteControl(I2C_TypeDef * I2Cx)761 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
762 {
763 SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
764 }
765
766 /**
767 * @brief Disable hardware byte control in slave mode.
768 * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
769 * @param I2Cx I2C Instance.
770 * @retval None
771 */
LL_I2C_DisableSlaveByteControl(I2C_TypeDef * I2Cx)772 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
773 {
774 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
775 }
776
777 /**
778 * @brief Check if hardware byte control in slave mode is enabled or disabled.
779 * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
780 * @param I2Cx I2C Instance.
781 * @retval State of bit (1 or 0).
782 */
LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef * I2Cx)783 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
784 {
785 return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
786 }
787
788 /**
789 * @brief Enable Wakeup from STOP.
790 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
791 * WakeUpFromStop feature is supported by the I2Cx Instance.
792 * @note This bit can only be programmed when Digital Filter is disabled.
793 * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
794 * @param I2Cx I2C Instance.
795 * @retval None
796 */
LL_I2C_EnableWakeUpFromStop(I2C_TypeDef * I2Cx)797 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
798 {
799 SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
800 }
801
802 /**
803 * @brief Disable Wakeup from STOP.
804 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
805 * WakeUpFromStop feature is supported by the I2Cx Instance.
806 * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
807 * @param I2Cx I2C Instance.
808 * @retval None
809 */
LL_I2C_DisableWakeUpFromStop(I2C_TypeDef * I2Cx)810 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
811 {
812 CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
813 }
814
815 /**
816 * @brief Check if Wakeup from STOP is enabled or disabled.
817 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
818 * WakeUpFromStop feature is supported by the I2Cx Instance.
819 * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
820 * @param I2Cx I2C Instance.
821 * @retval State of bit (1 or 0).
822 */
LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef * I2Cx)823 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
824 {
825 return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
826 }
827
828 /**
829 * @brief Enable General Call.
830 * @note When enabled the Address 0x00 is ACKed.
831 * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
832 * @param I2Cx I2C Instance.
833 * @retval None
834 */
LL_I2C_EnableGeneralCall(I2C_TypeDef * I2Cx)835 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
836 {
837 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
838 }
839
840 /**
841 * @brief Disable General Call.
842 * @note When disabled the Address 0x00 is NACKed.
843 * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
844 * @param I2Cx I2C Instance.
845 * @retval None
846 */
LL_I2C_DisableGeneralCall(I2C_TypeDef * I2Cx)847 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
848 {
849 CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
850 }
851
852 /**
853 * @brief Check if General Call is enabled or disabled.
854 * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
855 * @param I2Cx I2C Instance.
856 * @retval State of bit (1 or 0).
857 */
LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef * I2Cx)858 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
859 {
860 return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
861 }
862
863 /**
864 * @brief Enable I2C Fast Mode Plus (FMP = 1).
865 * @note 20mA I/O drive enable
866 * @rmtoll CR1 FMP LL_I2C_EnableFastModePlus
867 * @param I2Cx I2C Instance.
868 * @retval None
869 */
LL_I2C_EnableFastModePlus(I2C_TypeDef * I2Cx)870 __STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx)
871 {
872 SET_BIT(I2Cx->CR1, I2C_CR1_FMP);
873 }
874
875 /**
876 * @brief Disable I2C Fast Mode Plus (FMP = 0).
877 * @note 20mA I/O drive disable
878 * @rmtoll CR1 FMP LL_I2C_DisableFastModePlus
879 * @param I2Cx I2C Instance.
880 * @retval None
881 */
LL_I2C_DisableFastModePlus(I2C_TypeDef * I2Cx)882 __STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx)
883 {
884 CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP);
885 }
886
887 /**
888 * @brief Check if the I2C Fast Mode Plus is enabled or disabled.
889 * @rmtoll CR1 FMP LL_I2C_IsEnabledFastModePlus
890 * @param I2Cx I2C Instance.
891 * @retval State of bit (1 or 0).
892 */
LL_I2C_IsEnabledFastModePlus(const I2C_TypeDef * I2Cx)893 __STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(const I2C_TypeDef *I2Cx)
894 {
895 return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL);
896 }
897
898 /**
899 * @brief Enable automatic clear of ADDR flag.
900 * @rmtoll CR1 ADDRACLR LL_I2C_EnableAutoClearFlag_ADDR
901 * @param I2Cx I2C Instance.
902 * @retval None
903 */
LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef * I2Cx)904 __STATIC_INLINE void LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx)
905 {
906 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR);
907 }
908
909 /**
910 * @brief Disable automatic clear of ADDR flag.
911 * @rmtoll CR1 ADDRACLR LL_I2C_DisableAutoClearFlag_ADDR
912 * @param I2Cx I2C Instance.
913 * @retval None
914 */
LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef * I2Cx)915 __STATIC_INLINE void LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx)
916 {
917 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR);
918 }
919
920 /**
921 * @brief Check if the automatic clear of ADDR flag is enabled or disabled.
922 * @rmtoll CR1 ADDRACLR LL_I2C_IsEnabledAutoClearFlag_ADDR
923 * @param I2Cx I2C Instance.
924 * @retval State of bit (1 or 0).
925 */
LL_I2C_IsEnabledAutoClearFlag_ADDR(const I2C_TypeDef * I2Cx)926 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_ADDR(const I2C_TypeDef *I2Cx)
927 {
928 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR) == (I2C_CR1_ADDRACLR)) ? 1UL : 0UL);
929 }
930
931 /**
932 * @brief Enable automatic clear of STOP flag.
933 * @rmtoll CR1 STOPFACLR LL_I2C_EnableAutoClearFlag_STOP
934 * @param I2Cx I2C Instance.
935 * @retval None
936 */
LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef * I2Cx)937 __STATIC_INLINE void LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef *I2Cx)
938 {
939 SET_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR);
940 }
941
942 /**
943 * @brief Disable automatic clear of STOP flag.
944 * @rmtoll CR1 STOPFACLR LL_I2C_DisableAutoClearFlag_STOP
945 * @param I2Cx I2C Instance.
946 * @retval None
947 */
LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef * I2Cx)948 __STATIC_INLINE void LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef *I2Cx)
949 {
950 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR);
951 }
952
953 /**
954 * @brief Check if the automatic clear of STOP flag is enabled or disabled.
955 * @rmtoll CR1 STOPFACLR LL_I2C_IsEnabledAutoClearFlag_STOP
956 * @param I2Cx I2C Instance.
957 * @retval State of bit (1 or 0).
958 */
LL_I2C_IsEnabledAutoClearFlag_STOP(const I2C_TypeDef * I2Cx)959 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_STOP(const I2C_TypeDef *I2Cx)
960 {
961 return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR) == (I2C_CR1_STOPFACLR)) ? 1UL : 0UL);
962 }
963
964 /**
965 * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
966 * @note Changing this bit is not allowed, when the START bit is set.
967 * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
968 * @param I2Cx I2C Instance.
969 * @param AddressingMode This parameter can be one of the following values:
970 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
971 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
972 * @retval None
973 */
LL_I2C_SetMasterAddressingMode(I2C_TypeDef * I2Cx,uint32_t AddressingMode)974 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
975 {
976 MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
977 }
978
979 /**
980 * @brief Get the Master addressing mode.
981 * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
982 * @param I2Cx I2C Instance.
983 * @retval Returned value can be one of the following values:
984 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
985 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
986 */
LL_I2C_GetMasterAddressingMode(const I2C_TypeDef * I2Cx)987 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
988 {
989 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
990 }
991
992 /**
993 * @brief Set the Own Address1.
994 * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
995 * OAR1 OA1MODE LL_I2C_SetOwnAddress1
996 * @param I2Cx I2C Instance.
997 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
998 * @param OwnAddrSize This parameter can be one of the following values:
999 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
1000 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
1001 * @retval None
1002 */
LL_I2C_SetOwnAddress1(I2C_TypeDef * I2Cx,uint32_t OwnAddress1,uint32_t OwnAddrSize)1003 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
1004 {
1005 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
1006 }
1007
1008 /**
1009 * @brief Enable acknowledge on Own Address1 match address.
1010 * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
1011 * @param I2Cx I2C Instance.
1012 * @retval None
1013 */
LL_I2C_EnableOwnAddress1(I2C_TypeDef * I2Cx)1014 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
1015 {
1016 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
1017 }
1018
1019 /**
1020 * @brief Disable acknowledge on Own Address1 match address.
1021 * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
1022 * @param I2Cx I2C Instance.
1023 * @retval None
1024 */
LL_I2C_DisableOwnAddress1(I2C_TypeDef * I2Cx)1025 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
1026 {
1027 CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
1028 }
1029
1030 /**
1031 * @brief Check if Own Address1 acknowledge is enabled or disabled.
1032 * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
1033 * @param I2Cx I2C Instance.
1034 * @retval State of bit (1 or 0).
1035 */
LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef * I2Cx)1036 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
1037 {
1038 return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
1039 }
1040
1041 /**
1042 * @brief Set the 7bits Own Address2.
1043 * @note This action has no effect if own address2 is enabled.
1044 * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
1045 * OAR2 OA2MSK LL_I2C_SetOwnAddress2
1046 * @param I2Cx I2C Instance.
1047 * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
1048 * @param OwnAddrMask This parameter can be one of the following values:
1049 * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
1050 * @arg @ref LL_I2C_OWNADDRESS2_MASK01
1051 * @arg @ref LL_I2C_OWNADDRESS2_MASK02
1052 * @arg @ref LL_I2C_OWNADDRESS2_MASK03
1053 * @arg @ref LL_I2C_OWNADDRESS2_MASK04
1054 * @arg @ref LL_I2C_OWNADDRESS2_MASK05
1055 * @arg @ref LL_I2C_OWNADDRESS2_MASK06
1056 * @arg @ref LL_I2C_OWNADDRESS2_MASK07
1057 * @retval None
1058 */
LL_I2C_SetOwnAddress2(I2C_TypeDef * I2Cx,uint32_t OwnAddress2,uint32_t OwnAddrMask)1059 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
1060 {
1061 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
1062 }
1063
1064 /**
1065 * @brief Enable acknowledge on Own Address2 match address.
1066 * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
1067 * @param I2Cx I2C Instance.
1068 * @retval None
1069 */
LL_I2C_EnableOwnAddress2(I2C_TypeDef * I2Cx)1070 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
1071 {
1072 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
1073 }
1074
1075 /**
1076 * @brief Disable acknowledge on Own Address2 match address.
1077 * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
1078 * @param I2Cx I2C Instance.
1079 * @retval None
1080 */
LL_I2C_DisableOwnAddress2(I2C_TypeDef * I2Cx)1081 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
1082 {
1083 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
1084 }
1085
1086 /**
1087 * @brief Check if Own Address1 acknowledge is enabled or disabled.
1088 * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
1089 * @param I2Cx I2C Instance.
1090 * @retval State of bit (1 or 0).
1091 */
LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef * I2Cx)1092 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
1093 {
1094 return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
1095 }
1096
1097 /**
1098 * @brief Configure the SDA setup, hold time and the SCL high, low period.
1099 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
1100 * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
1101 * @param I2Cx I2C Instance.
1102 * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
1103 * @note This parameter is computed with the STM32CubeMX Tool.
1104 * @retval None
1105 */
LL_I2C_SetTiming(I2C_TypeDef * I2Cx,uint32_t Timing)1106 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
1107 {
1108 WRITE_REG(I2Cx->TIMINGR, Timing);
1109 }
1110
1111 /**
1112 * @brief Get the Timing Prescaler setting.
1113 * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
1114 * @param I2Cx I2C Instance.
1115 * @retval Value between Min_Data=0x0 and Max_Data=0xF
1116 */
LL_I2C_GetTimingPrescaler(const I2C_TypeDef * I2Cx)1117 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
1118 {
1119 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
1120 }
1121
1122 /**
1123 * @brief Get the SCL low period setting.
1124 * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
1125 * @param I2Cx I2C Instance.
1126 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1127 */
LL_I2C_GetClockLowPeriod(const I2C_TypeDef * I2Cx)1128 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
1129 {
1130 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
1131 }
1132
1133 /**
1134 * @brief Get the SCL high period setting.
1135 * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
1136 * @param I2Cx I2C Instance.
1137 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1138 */
LL_I2C_GetClockHighPeriod(const I2C_TypeDef * I2Cx)1139 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
1140 {
1141 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
1142 }
1143
1144 /**
1145 * @brief Get the SDA hold time.
1146 * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
1147 * @param I2Cx I2C Instance.
1148 * @retval Value between Min_Data=0x0 and Max_Data=0xF
1149 */
LL_I2C_GetDataHoldTime(const I2C_TypeDef * I2Cx)1150 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
1151 {
1152 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
1153 }
1154
1155 /**
1156 * @brief Get the SDA setup time.
1157 * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
1158 * @param I2Cx I2C Instance.
1159 * @retval Value between Min_Data=0x0 and Max_Data=0xF
1160 */
LL_I2C_GetDataSetupTime(const I2C_TypeDef * I2Cx)1161 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
1162 {
1163 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
1164 }
1165
1166 /**
1167 * @brief Configure peripheral mode.
1168 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1169 * SMBus feature is supported by the I2Cx Instance.
1170 * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
1171 * CR1 SMBDEN LL_I2C_SetMode
1172 * @param I2Cx I2C Instance.
1173 * @param PeripheralMode This parameter can be one of the following values:
1174 * @arg @ref LL_I2C_MODE_I2C
1175 * @arg @ref LL_I2C_MODE_SMBUS_HOST
1176 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
1177 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
1178 * @retval None
1179 */
LL_I2C_SetMode(I2C_TypeDef * I2Cx,uint32_t PeripheralMode)1180 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
1181 {
1182 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
1183 }
1184
1185 /**
1186 * @brief Get peripheral mode.
1187 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1188 * SMBus feature is supported by the I2Cx Instance.
1189 * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
1190 * CR1 SMBDEN LL_I2C_GetMode
1191 * @param I2Cx I2C Instance.
1192 * @retval Returned value can be one of the following values:
1193 * @arg @ref LL_I2C_MODE_I2C
1194 * @arg @ref LL_I2C_MODE_SMBUS_HOST
1195 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
1196 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
1197 */
LL_I2C_GetMode(const I2C_TypeDef * I2Cx)1198 __STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
1199 {
1200 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
1201 }
1202
1203 /**
1204 * @brief Enable SMBus alert (Host or Device mode)
1205 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1206 * SMBus feature is supported by the I2Cx Instance.
1207 * @note SMBus Device mode:
1208 * - SMBus Alert pin is drived low and
1209 * Alert Response Address Header acknowledge is enabled.
1210 * SMBus Host mode:
1211 * - SMBus Alert pin management is supported.
1212 * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
1213 * @param I2Cx I2C Instance.
1214 * @retval None
1215 */
LL_I2C_EnableSMBusAlert(I2C_TypeDef * I2Cx)1216 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
1217 {
1218 SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1219 }
1220
1221 /**
1222 * @brief Disable SMBus alert (Host or Device mode)
1223 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1224 * SMBus feature is supported by the I2Cx Instance.
1225 * @note SMBus Device mode:
1226 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
1227 * Alert Response Address Header acknowledge is disabled.
1228 * SMBus Host mode:
1229 * - SMBus Alert pin management is not supported.
1230 * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
1231 * @param I2Cx I2C Instance.
1232 * @retval None
1233 */
LL_I2C_DisableSMBusAlert(I2C_TypeDef * I2Cx)1234 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
1235 {
1236 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1237 }
1238
1239 /**
1240 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
1241 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1242 * SMBus feature is supported by the I2Cx Instance.
1243 * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
1244 * @param I2Cx I2C Instance.
1245 * @retval State of bit (1 or 0).
1246 */
LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef * I2Cx)1247 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
1248 {
1249 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
1250 }
1251
1252 /**
1253 * @brief Enable SMBus Packet Error Calculation (PEC).
1254 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1255 * SMBus feature is supported by the I2Cx Instance.
1256 * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
1257 * @param I2Cx I2C Instance.
1258 * @retval None
1259 */
LL_I2C_EnableSMBusPEC(I2C_TypeDef * I2Cx)1260 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
1261 {
1262 SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1263 }
1264
1265 /**
1266 * @brief Disable SMBus Packet Error Calculation (PEC).
1267 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1268 * SMBus feature is supported by the I2Cx Instance.
1269 * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
1270 * @param I2Cx I2C Instance.
1271 * @retval None
1272 */
LL_I2C_DisableSMBusPEC(I2C_TypeDef * I2Cx)1273 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
1274 {
1275 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1276 }
1277
1278 /**
1279 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
1280 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1281 * SMBus feature is supported by the I2Cx Instance.
1282 * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
1283 * @param I2Cx I2C Instance.
1284 * @retval State of bit (1 or 0).
1285 */
LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef * I2Cx)1286 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
1287 {
1288 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
1289 }
1290
1291 /**
1292 * @brief Configure the SMBus Clock Timeout.
1293 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1294 * SMBus feature is supported by the I2Cx Instance.
1295 * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
1296 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
1297 * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
1298 * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
1299 * @param I2Cx I2C Instance.
1300 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1301 * @param TimeoutAMode This parameter can be one of the following values:
1302 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1303 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1304 * @param TimeoutB
1305 * @retval None
1306 */
LL_I2C_ConfigSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t TimeoutA,uint32_t TimeoutAMode,uint32_t TimeoutB)1307 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
1308 uint32_t TimeoutB)
1309 {
1310 MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
1311 TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
1312 }
1313
1314 /**
1315 * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
1316 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1317 * SMBus feature is supported by the I2Cx Instance.
1318 * @note These bits can only be programmed when TimeoutA is disabled.
1319 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
1320 * @param I2Cx I2C Instance.
1321 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1322 * @retval None
1323 */
LL_I2C_SetSMBusTimeoutA(I2C_TypeDef * I2Cx,uint32_t TimeoutA)1324 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
1325 {
1326 WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
1327 }
1328
1329 /**
1330 * @brief Get the SMBus Clock TimeoutA setting.
1331 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1332 * SMBus feature is supported by the I2Cx Instance.
1333 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
1334 * @param I2Cx I2C Instance.
1335 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1336 */
LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef * I2Cx)1337 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
1338 {
1339 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
1340 }
1341
1342 /**
1343 * @brief Set the SMBus Clock TimeoutA mode.
1344 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1345 * SMBus feature is supported by the I2Cx Instance.
1346 * @note This bit can only be programmed when TimeoutA is disabled.
1347 * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
1348 * @param I2Cx I2C Instance.
1349 * @param TimeoutAMode This parameter can be one of the following values:
1350 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1351 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1352 * @retval None
1353 */
LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef * I2Cx,uint32_t TimeoutAMode)1354 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
1355 {
1356 WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
1357 }
1358
1359 /**
1360 * @brief Get the SMBus Clock TimeoutA mode.
1361 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1362 * SMBus feature is supported by the I2Cx Instance.
1363 * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
1364 * @param I2Cx I2C Instance.
1365 * @retval Returned value can be one of the following values:
1366 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1367 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1368 */
LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef * I2Cx)1369 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
1370 {
1371 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
1372 }
1373
1374 /**
1375 * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
1376 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1377 * SMBus feature is supported by the I2Cx Instance.
1378 * @note These bits can only be programmed when TimeoutB is disabled.
1379 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
1380 * @param I2Cx I2C Instance.
1381 * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1382 * @retval None
1383 */
LL_I2C_SetSMBusTimeoutB(I2C_TypeDef * I2Cx,uint32_t TimeoutB)1384 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
1385 {
1386 WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
1387 }
1388
1389 /**
1390 * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
1391 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1392 * SMBus feature is supported by the I2Cx Instance.
1393 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
1394 * @param I2Cx I2C Instance.
1395 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1396 */
LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef * I2Cx)1397 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
1398 {
1399 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
1400 }
1401
1402 /**
1403 * @brief Enable the SMBus Clock Timeout.
1404 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1405 * SMBus feature is supported by the I2Cx Instance.
1406 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
1407 * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
1408 * @param I2Cx I2C Instance.
1409 * @param ClockTimeout This parameter can be one of the following values:
1410 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1411 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1412 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1413 * @retval None
1414 */
LL_I2C_EnableSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1415 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1416 {
1417 SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1418 }
1419
1420 /**
1421 * @brief Disable the SMBus Clock Timeout.
1422 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1423 * SMBus feature is supported by the I2Cx Instance.
1424 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
1425 * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
1426 * @param I2Cx I2C Instance.
1427 * @param ClockTimeout This parameter can be one of the following values:
1428 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1429 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1430 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1431 * @retval None
1432 */
LL_I2C_DisableSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1433 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1434 {
1435 CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1436 }
1437
1438 /**
1439 * @brief Check if the SMBus Clock Timeout is enabled or disabled.
1440 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1441 * SMBus feature is supported by the I2Cx Instance.
1442 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
1443 * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
1444 * @param I2Cx I2C Instance.
1445 * @param ClockTimeout This parameter can be one of the following values:
1446 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1447 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1448 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1449 * @retval State of bit (1 or 0).
1450 */
LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1451 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1452 {
1453 return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
1454 (ClockTimeout)) ? 1UL : 0UL);
1455 }
1456
1457 /**
1458 * @}
1459 */
1460
1461 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1462 * @{
1463 */
1464
1465 /**
1466 * @brief Enable TXIS interrupt.
1467 * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
1468 * @param I2Cx I2C Instance.
1469 * @retval None
1470 */
LL_I2C_EnableIT_TX(I2C_TypeDef * I2Cx)1471 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1472 {
1473 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1474 }
1475
1476 /**
1477 * @brief Disable TXIS interrupt.
1478 * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
1479 * @param I2Cx I2C Instance.
1480 * @retval None
1481 */
LL_I2C_DisableIT_TX(I2C_TypeDef * I2Cx)1482 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1483 {
1484 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1485 }
1486
1487 /**
1488 * @brief Check if the TXIS Interrupt is enabled or disabled.
1489 * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
1490 * @param I2Cx I2C Instance.
1491 * @retval State of bit (1 or 0).
1492 */
LL_I2C_IsEnabledIT_TX(const I2C_TypeDef * I2Cx)1493 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
1494 {
1495 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
1496 }
1497
1498 /**
1499 * @brief Enable RXNE interrupt.
1500 * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
1501 * @param I2Cx I2C Instance.
1502 * @retval None
1503 */
LL_I2C_EnableIT_RX(I2C_TypeDef * I2Cx)1504 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1505 {
1506 SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1507 }
1508
1509 /**
1510 * @brief Disable RXNE interrupt.
1511 * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
1512 * @param I2Cx I2C Instance.
1513 * @retval None
1514 */
LL_I2C_DisableIT_RX(I2C_TypeDef * I2Cx)1515 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1516 {
1517 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1518 }
1519
1520 /**
1521 * @brief Check if the RXNE Interrupt is enabled or disabled.
1522 * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
1523 * @param I2Cx I2C Instance.
1524 * @retval State of bit (1 or 0).
1525 */
LL_I2C_IsEnabledIT_RX(const I2C_TypeDef * I2Cx)1526 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
1527 {
1528 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
1529 }
1530
1531 /**
1532 * @brief Enable Address match interrupt (slave mode only).
1533 * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
1534 * @param I2Cx I2C Instance.
1535 * @retval None
1536 */
LL_I2C_EnableIT_ADDR(I2C_TypeDef * I2Cx)1537 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
1538 {
1539 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1540 }
1541
1542 /**
1543 * @brief Disable Address match interrupt (slave mode only).
1544 * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
1545 * @param I2Cx I2C Instance.
1546 * @retval None
1547 */
LL_I2C_DisableIT_ADDR(I2C_TypeDef * I2Cx)1548 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
1549 {
1550 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1551 }
1552
1553 /**
1554 * @brief Check if Address match interrupt is enabled or disabled.
1555 * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
1556 * @param I2Cx I2C Instance.
1557 * @retval State of bit (1 or 0).
1558 */
LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef * I2Cx)1559 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
1560 {
1561 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
1562 }
1563
1564 /**
1565 * @brief Enable Not acknowledge received interrupt.
1566 * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
1567 * @param I2Cx I2C Instance.
1568 * @retval None
1569 */
LL_I2C_EnableIT_NACK(I2C_TypeDef * I2Cx)1570 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
1571 {
1572 SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1573 }
1574
1575 /**
1576 * @brief Disable Not acknowledge received interrupt.
1577 * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
1578 * @param I2Cx I2C Instance.
1579 * @retval None
1580 */
LL_I2C_DisableIT_NACK(I2C_TypeDef * I2Cx)1581 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
1582 {
1583 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1584 }
1585
1586 /**
1587 * @brief Check if Not acknowledge received interrupt is enabled or disabled.
1588 * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
1589 * @param I2Cx I2C Instance.
1590 * @retval State of bit (1 or 0).
1591 */
LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef * I2Cx)1592 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
1593 {
1594 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
1595 }
1596
1597 /**
1598 * @brief Enable STOP detection interrupt.
1599 * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
1600 * @param I2Cx I2C Instance.
1601 * @retval None
1602 */
LL_I2C_EnableIT_STOP(I2C_TypeDef * I2Cx)1603 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
1604 {
1605 SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1606 }
1607
1608 /**
1609 * @brief Disable STOP detection interrupt.
1610 * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
1611 * @param I2Cx I2C Instance.
1612 * @retval None
1613 */
LL_I2C_DisableIT_STOP(I2C_TypeDef * I2Cx)1614 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
1615 {
1616 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1617 }
1618
1619 /**
1620 * @brief Check if STOP detection interrupt is enabled or disabled.
1621 * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
1622 * @param I2Cx I2C Instance.
1623 * @retval State of bit (1 or 0).
1624 */
LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef * I2Cx)1625 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
1626 {
1627 return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
1628 }
1629
1630 /**
1631 * @brief Enable Transfer Complete interrupt.
1632 * @note Any of these events will generate interrupt :
1633 * Transfer Complete (TC)
1634 * Transfer Complete Reload (TCR)
1635 * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
1636 * @param I2Cx I2C Instance.
1637 * @retval None
1638 */
LL_I2C_EnableIT_TC(I2C_TypeDef * I2Cx)1639 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
1640 {
1641 SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1642 }
1643
1644 /**
1645 * @brief Disable Transfer Complete interrupt.
1646 * @note Any of these events will generate interrupt :
1647 * Transfer Complete (TC)
1648 * Transfer Complete Reload (TCR)
1649 * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
1650 * @param I2Cx I2C Instance.
1651 * @retval None
1652 */
LL_I2C_DisableIT_TC(I2C_TypeDef * I2Cx)1653 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
1654 {
1655 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1656 }
1657
1658 /**
1659 * @brief Check if Transfer Complete interrupt is enabled or disabled.
1660 * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
1661 * @param I2Cx I2C Instance.
1662 * @retval State of bit (1 or 0).
1663 */
LL_I2C_IsEnabledIT_TC(const I2C_TypeDef * I2Cx)1664 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
1665 {
1666 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
1667 }
1668
1669 /**
1670 * @brief Enable Error interrupts.
1671 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1672 * SMBus feature is supported by the I2Cx Instance.
1673 * @note Any of these errors will generate interrupt :
1674 * Arbitration Loss (ARLO)
1675 * Bus Error detection (BERR)
1676 * Overrun/Underrun (OVR)
1677 * SMBus Timeout detection (TIMEOUT)
1678 * SMBus PEC error detection (PECERR)
1679 * SMBus Alert pin event detection (ALERT)
1680 * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
1681 * @param I2Cx I2C Instance.
1682 * @retval None
1683 */
LL_I2C_EnableIT_ERR(I2C_TypeDef * I2Cx)1684 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1685 {
1686 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1687 }
1688
1689 /**
1690 * @brief Disable Error interrupts.
1691 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1692 * SMBus feature is supported by the I2Cx Instance.
1693 * @note Any of these errors will generate interrupt :
1694 * Arbitration Loss (ARLO)
1695 * Bus Error detection (BERR)
1696 * Overrun/Underrun (OVR)
1697 * SMBus Timeout detection (TIMEOUT)
1698 * SMBus PEC error detection (PECERR)
1699 * SMBus Alert pin event detection (ALERT)
1700 * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
1701 * @param I2Cx I2C Instance.
1702 * @retval None
1703 */
LL_I2C_DisableIT_ERR(I2C_TypeDef * I2Cx)1704 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1705 {
1706 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1707 }
1708
1709 /**
1710 * @brief Check if Error interrupts are enabled or disabled.
1711 * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
1712 * @param I2Cx I2C Instance.
1713 * @retval State of bit (1 or 0).
1714 */
LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef * I2Cx)1715 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
1716 {
1717 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
1718 }
1719
1720 /**
1721 * @}
1722 */
1723
1724 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1725 * @{
1726 */
1727
1728 /**
1729 * @brief Indicate the status of Transmit data register empty flag.
1730 * @note RESET: When next data is written in Transmit data register.
1731 * SET: When Transmit data register is empty.
1732 * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
1733 * @param I2Cx I2C Instance.
1734 * @retval State of bit (1 or 0).
1735 */
LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef * I2Cx)1736 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
1737 {
1738 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
1739 }
1740
1741 /**
1742 * @brief Indicate the status of Transmit interrupt flag.
1743 * @note RESET: When next data is written in Transmit data register.
1744 * SET: When Transmit data register is empty.
1745 * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
1746 * @param I2Cx I2C Instance.
1747 * @retval State of bit (1 or 0).
1748 */
LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef * I2Cx)1749 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
1750 {
1751 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
1752 }
1753
1754 /**
1755 * @brief Indicate the status of Receive data register not empty flag.
1756 * @note RESET: When Receive data register is read.
1757 * SET: When the received data is copied in Receive data register.
1758 * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
1759 * @param I2Cx I2C Instance.
1760 * @retval State of bit (1 or 0).
1761 */
LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef * I2Cx)1762 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
1763 {
1764 return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
1765 }
1766
1767 /**
1768 * @brief Indicate the status of Address matched flag (slave mode).
1769 * @note RESET: Clear default value.
1770 * SET: When the received slave address matched with one of the enabled slave address.
1771 * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
1772 * @param I2Cx I2C Instance.
1773 * @retval State of bit (1 or 0).
1774 */
LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef * I2Cx)1775 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
1776 {
1777 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
1778 }
1779
1780 /**
1781 * @brief Indicate the status of Not Acknowledge received flag.
1782 * @note RESET: Clear default value.
1783 * SET: When a NACK is received after a byte transmission.
1784 * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
1785 * @param I2Cx I2C Instance.
1786 * @retval State of bit (1 or 0).
1787 */
LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef * I2Cx)1788 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
1789 {
1790 return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
1791 }
1792
1793 /**
1794 * @brief Indicate the status of Stop detection flag.
1795 * @note RESET: Clear default value.
1796 * SET: When a Stop condition is detected.
1797 * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
1798 * @param I2Cx I2C Instance.
1799 * @retval State of bit (1 or 0).
1800 */
LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef * I2Cx)1801 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
1802 {
1803 return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
1804 }
1805
1806 /**
1807 * @brief Indicate the status of Transfer complete flag (master mode).
1808 * @note RESET: Clear default value.
1809 * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
1810 * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
1811 * @param I2Cx I2C Instance.
1812 * @retval State of bit (1 or 0).
1813 */
LL_I2C_IsActiveFlag_TC(const I2C_TypeDef * I2Cx)1814 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
1815 {
1816 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
1817 }
1818
1819 /**
1820 * @brief Indicate the status of Transfer complete flag (master mode).
1821 * @note RESET: Clear default value.
1822 * SET: When RELOAD=1 and NBYTES date have been transferred.
1823 * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
1824 * @param I2Cx I2C Instance.
1825 * @retval State of bit (1 or 0).
1826 */
LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef * I2Cx)1827 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
1828 {
1829 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
1830 }
1831
1832 /**
1833 * @brief Indicate the status of Bus error flag.
1834 * @note RESET: Clear default value.
1835 * SET: When a misplaced Start or Stop condition is detected.
1836 * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
1837 * @param I2Cx I2C Instance.
1838 * @retval State of bit (1 or 0).
1839 */
LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef * I2Cx)1840 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
1841 {
1842 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
1843 }
1844
1845 /**
1846 * @brief Indicate the status of Arbitration lost flag.
1847 * @note RESET: Clear default value.
1848 * SET: When arbitration lost.
1849 * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
1850 * @param I2Cx I2C Instance.
1851 * @retval State of bit (1 or 0).
1852 */
LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef * I2Cx)1853 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
1854 {
1855 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
1856 }
1857
1858 /**
1859 * @brief Indicate the status of Overrun/Underrun flag (slave mode).
1860 * @note RESET: Clear default value.
1861 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1862 * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
1863 * @param I2Cx I2C Instance.
1864 * @retval State of bit (1 or 0).
1865 */
LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef * I2Cx)1866 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
1867 {
1868 return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
1869 }
1870
1871 /**
1872 * @brief Indicate the status of SMBus PEC error flag in reception.
1873 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1874 * SMBus feature is supported by the I2Cx Instance.
1875 * @note RESET: Clear default value.
1876 * SET: When the received PEC does not match with the PEC register content.
1877 * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
1878 * @param I2Cx I2C Instance.
1879 * @retval State of bit (1 or 0).
1880 */
LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef * I2Cx)1881 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
1882 {
1883 return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
1884 }
1885
1886 /**
1887 * @brief Indicate the status of SMBus Timeout detection flag.
1888 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1889 * SMBus feature is supported by the I2Cx Instance.
1890 * @note RESET: Clear default value.
1891 * SET: When a timeout or extended clock timeout occurs.
1892 * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
1893 * @param I2Cx I2C Instance.
1894 * @retval State of bit (1 or 0).
1895 */
LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef * I2Cx)1896 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
1897 {
1898 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
1899 }
1900
1901 /**
1902 * @brief Indicate the status of SMBus alert flag.
1903 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1904 * SMBus feature is supported by the I2Cx Instance.
1905 * @note RESET: Clear default value.
1906 * SET: When SMBus host configuration, SMBus alert enabled and
1907 * a falling edge event occurs on SMBA pin.
1908 * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
1909 * @param I2Cx I2C Instance.
1910 * @retval State of bit (1 or 0).
1911 */
LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef * I2Cx)1912 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
1913 {
1914 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
1915 }
1916
1917 /**
1918 * @brief Indicate the status of Bus Busy flag.
1919 * @note RESET: Clear default value.
1920 * SET: When a Start condition is detected.
1921 * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
1922 * @param I2Cx I2C Instance.
1923 * @retval State of bit (1 or 0).
1924 */
LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef * I2Cx)1925 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
1926 {
1927 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
1928 }
1929
1930 /**
1931 * @brief Clear Address Matched flag.
1932 * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
1933 * @param I2Cx I2C Instance.
1934 * @retval None
1935 */
LL_I2C_ClearFlag_ADDR(I2C_TypeDef * I2Cx)1936 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1937 {
1938 SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
1939 }
1940
1941 /**
1942 * @brief Clear Not Acknowledge flag.
1943 * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
1944 * @param I2Cx I2C Instance.
1945 * @retval None
1946 */
LL_I2C_ClearFlag_NACK(I2C_TypeDef * I2Cx)1947 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
1948 {
1949 SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
1950 }
1951
1952 /**
1953 * @brief Clear Stop detection flag.
1954 * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
1955 * @param I2Cx I2C Instance.
1956 * @retval None
1957 */
LL_I2C_ClearFlag_STOP(I2C_TypeDef * I2Cx)1958 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1959 {
1960 SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
1961 }
1962
1963 /**
1964 * @brief Clear Transmit data register empty flag (TXE).
1965 * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
1966 * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
1967 * @param I2Cx I2C Instance.
1968 * @retval None
1969 */
LL_I2C_ClearFlag_TXE(I2C_TypeDef * I2Cx)1970 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
1971 {
1972 WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
1973 }
1974
1975 /**
1976 * @brief Clear Bus error flag.
1977 * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
1978 * @param I2Cx I2C Instance.
1979 * @retval None
1980 */
LL_I2C_ClearFlag_BERR(I2C_TypeDef * I2Cx)1981 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1982 {
1983 SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
1984 }
1985
1986 /**
1987 * @brief Clear Arbitration lost flag.
1988 * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
1989 * @param I2Cx I2C Instance.
1990 * @retval None
1991 */
LL_I2C_ClearFlag_ARLO(I2C_TypeDef * I2Cx)1992 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1993 {
1994 SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
1995 }
1996
1997 /**
1998 * @brief Clear Overrun/Underrun flag.
1999 * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
2000 * @param I2Cx I2C Instance.
2001 * @retval None
2002 */
LL_I2C_ClearFlag_OVR(I2C_TypeDef * I2Cx)2003 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
2004 {
2005 SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
2006 }
2007
2008 /**
2009 * @brief Clear SMBus PEC error flag.
2010 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2011 * SMBus feature is supported by the I2Cx Instance.
2012 * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
2013 * @param I2Cx I2C Instance.
2014 * @retval None
2015 */
LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef * I2Cx)2016 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
2017 {
2018 SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
2019 }
2020
2021 /**
2022 * @brief Clear SMBus Timeout detection flag.
2023 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2024 * SMBus feature is supported by the I2Cx Instance.
2025 * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
2026 * @param I2Cx I2C Instance.
2027 * @retval None
2028 */
LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)2029 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
2030 {
2031 SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
2032 }
2033
2034 /**
2035 * @brief Clear SMBus Alert flag.
2036 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2037 * SMBus feature is supported by the I2Cx Instance.
2038 * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
2039 * @param I2Cx I2C Instance.
2040 * @retval None
2041 */
LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef * I2Cx)2042 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
2043 {
2044 SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
2045 }
2046
2047 /**
2048 * @}
2049 */
2050
2051 /** @defgroup I2C_LL_EF_Data_Management Data_Management
2052 * @{
2053 */
2054
2055 /**
2056 * @brief Enable automatic STOP condition generation (master mode).
2057 * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
2058 * This bit has no effect in slave mode or when RELOAD bit is set.
2059 * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
2060 * @param I2Cx I2C Instance.
2061 * @retval None
2062 */
LL_I2C_EnableAutoEndMode(I2C_TypeDef * I2Cx)2063 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
2064 {
2065 SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
2066 }
2067
2068 /**
2069 * @brief Disable automatic STOP condition generation (master mode).
2070 * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
2071 * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
2072 * @param I2Cx I2C Instance.
2073 * @retval None
2074 */
LL_I2C_DisableAutoEndMode(I2C_TypeDef * I2Cx)2075 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
2076 {
2077 CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
2078 }
2079
2080 /**
2081 * @brief Check if automatic STOP condition is enabled or disabled.
2082 * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
2083 * @param I2Cx I2C Instance.
2084 * @retval State of bit (1 or 0).
2085 */
LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef * I2Cx)2086 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
2087 {
2088 return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
2089 }
2090
2091 /**
2092 * @brief Enable reload mode (master mode).
2093 * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
2094 * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
2095 * @param I2Cx I2C Instance.
2096 * @retval None
2097 */
LL_I2C_EnableReloadMode(I2C_TypeDef * I2Cx)2098 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
2099 {
2100 SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
2101 }
2102
2103 /**
2104 * @brief Disable reload mode (master mode).
2105 * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
2106 * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
2107 * @param I2Cx I2C Instance.
2108 * @retval None
2109 */
LL_I2C_DisableReloadMode(I2C_TypeDef * I2Cx)2110 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
2111 {
2112 CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
2113 }
2114
2115 /**
2116 * @brief Check if reload mode is enabled or disabled.
2117 * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
2118 * @param I2Cx I2C Instance.
2119 * @retval State of bit (1 or 0).
2120 */
LL_I2C_IsEnabledReloadMode(const I2C_TypeDef * I2Cx)2121 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
2122 {
2123 return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
2124 }
2125
2126 /**
2127 * @brief Configure the number of bytes for transfer.
2128 * @note Changing these bits when START bit is set is not allowed.
2129 * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
2130 * @param I2Cx I2C Instance.
2131 * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
2132 * @retval None
2133 */
LL_I2C_SetTransferSize(I2C_TypeDef * I2Cx,uint32_t TransferSize)2134 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
2135 {
2136 MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
2137 }
2138
2139 /**
2140 * @brief Get the number of bytes configured for transfer.
2141 * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
2142 * @param I2Cx I2C Instance.
2143 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
2144 */
LL_I2C_GetTransferSize(const I2C_TypeDef * I2Cx)2145 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
2146 {
2147 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
2148 }
2149
2150 /**
2151 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
2152 or next received byte.
2153 * @note Usage in Slave mode only.
2154 * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
2155 * @param I2Cx I2C Instance.
2156 * @param TypeAcknowledge This parameter can be one of the following values:
2157 * @arg @ref LL_I2C_ACK
2158 * @arg @ref LL_I2C_NACK
2159 * @retval None
2160 */
LL_I2C_AcknowledgeNextData(I2C_TypeDef * I2Cx,uint32_t TypeAcknowledge)2161 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
2162 {
2163 MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
2164 }
2165
2166 /**
2167 * @brief Generate a START or RESTART condition
2168 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
2169 * This action has no effect when RELOAD is set.
2170 * @rmtoll CR2 START LL_I2C_GenerateStartCondition
2171 * @param I2Cx I2C Instance.
2172 * @retval None
2173 */
LL_I2C_GenerateStartCondition(I2C_TypeDef * I2Cx)2174 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
2175 {
2176 SET_BIT(I2Cx->CR2, I2C_CR2_START);
2177 }
2178
2179 /**
2180 * @brief Generate a STOP condition after the current byte transfer (master mode).
2181 * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
2182 * @param I2Cx I2C Instance.
2183 * @retval None
2184 */
LL_I2C_GenerateStopCondition(I2C_TypeDef * I2Cx)2185 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
2186 {
2187 SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
2188 }
2189
2190 /**
2191 * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
2192 * @note The master sends the complete 10bit slave address read sequence :
2193 * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
2194 in Read direction.
2195 * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
2196 * @param I2Cx I2C Instance.
2197 * @retval None
2198 */
LL_I2C_EnableAuto10BitRead(I2C_TypeDef * I2Cx)2199 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
2200 {
2201 CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
2202 }
2203
2204 /**
2205 * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
2206 * @note The master only sends the first 7 bits of 10bit address in Read direction.
2207 * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
2208 * @param I2Cx I2C Instance.
2209 * @retval None
2210 */
LL_I2C_DisableAuto10BitRead(I2C_TypeDef * I2Cx)2211 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
2212 {
2213 SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
2214 }
2215
2216 /**
2217 * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
2218 * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
2219 * @param I2Cx I2C Instance.
2220 * @retval State of bit (1 or 0).
2221 */
LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef * I2Cx)2222 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
2223 {
2224 return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
2225 }
2226
2227 /**
2228 * @brief Configure the transfer direction (master mode).
2229 * @note Changing these bits when START bit is set is not allowed.
2230 * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
2231 * @param I2Cx I2C Instance.
2232 * @param TransferRequest This parameter can be one of the following values:
2233 * @arg @ref LL_I2C_REQUEST_WRITE
2234 * @arg @ref LL_I2C_REQUEST_READ
2235 * @retval None
2236 */
LL_I2C_SetTransferRequest(I2C_TypeDef * I2Cx,uint32_t TransferRequest)2237 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
2238 {
2239 MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
2240 }
2241
2242 /**
2243 * @brief Get the transfer direction requested (master mode).
2244 * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
2245 * @param I2Cx I2C Instance.
2246 * @retval Returned value can be one of the following values:
2247 * @arg @ref LL_I2C_REQUEST_WRITE
2248 * @arg @ref LL_I2C_REQUEST_READ
2249 */
LL_I2C_GetTransferRequest(const I2C_TypeDef * I2Cx)2250 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
2251 {
2252 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
2253 }
2254
2255 /**
2256 * @brief Configure the slave address for transfer (master mode).
2257 * @note Changing these bits when START bit is set is not allowed.
2258 * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
2259 * @param I2Cx I2C Instance.
2260 * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
2261 * @retval None
2262 */
LL_I2C_SetSlaveAddr(I2C_TypeDef * I2Cx,uint32_t SlaveAddr)2263 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
2264 {
2265 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
2266 }
2267
2268 /**
2269 * @brief Get the slave address programmed for transfer.
2270 * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
2271 * @param I2Cx I2C Instance.
2272 * @retval Value between Min_Data=0x0 and Max_Data=0x3F
2273 */
LL_I2C_GetSlaveAddr(const I2C_TypeDef * I2Cx)2274 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
2275 {
2276 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
2277 }
2278
2279 /**
2280 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
2281 * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
2282 * CR2 ADD10 LL_I2C_HandleTransfer\n
2283 * CR2 RD_WRN LL_I2C_HandleTransfer\n
2284 * CR2 START LL_I2C_HandleTransfer\n
2285 * CR2 STOP LL_I2C_HandleTransfer\n
2286 * CR2 RELOAD LL_I2C_HandleTransfer\n
2287 * CR2 NBYTES LL_I2C_HandleTransfer\n
2288 * CR2 AUTOEND LL_I2C_HandleTransfer\n
2289 * CR2 HEAD10R LL_I2C_HandleTransfer
2290 * @param I2Cx I2C Instance.
2291 * @param SlaveAddr Specifies the slave address to be programmed.
2292 * @param SlaveAddrSize This parameter can be one of the following values:
2293 * @arg @ref LL_I2C_ADDRSLAVE_7BIT
2294 * @arg @ref LL_I2C_ADDRSLAVE_10BIT
2295 * @param TransferSize Specifies the number of bytes to be programmed.
2296 * This parameter must be a value between Min_Data=0 and Max_Data=255.
2297 * @param EndMode This parameter can be one of the following values:
2298 * @arg @ref LL_I2C_MODE_RELOAD
2299 * @arg @ref LL_I2C_MODE_AUTOEND
2300 * @arg @ref LL_I2C_MODE_SOFTEND
2301 * @arg @ref LL_I2C_MODE_SMBUS_RELOAD
2302 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
2303 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
2304 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
2305 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
2306 * @param Request This parameter can be one of the following values:
2307 * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
2308 * @arg @ref LL_I2C_GENERATE_STOP
2309 * @arg @ref LL_I2C_GENERATE_START_READ
2310 * @arg @ref LL_I2C_GENERATE_START_WRITE
2311 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
2312 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
2313 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
2314 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
2315 * @retval None
2316 */
LL_I2C_HandleTransfer(I2C_TypeDef * I2Cx,uint32_t SlaveAddr,uint32_t SlaveAddrSize,uint32_t TransferSize,uint32_t EndMode,uint32_t Request)2317 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
2318 uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
2319 {
2320 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
2321 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
2322 I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
2323 I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
2324 SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
2325 }
2326
2327 /**
2328 * @brief Indicate the value of transfer direction (slave mode).
2329 * @note RESET: Write transfer, Slave enters in receiver mode.
2330 * SET: Read transfer, Slave enters in transmitter mode.
2331 * @rmtoll ISR DIR LL_I2C_GetTransferDirection
2332 * @param I2Cx I2C Instance.
2333 * @retval Returned value can be one of the following values:
2334 * @arg @ref LL_I2C_DIRECTION_WRITE
2335 * @arg @ref LL_I2C_DIRECTION_READ
2336 */
LL_I2C_GetTransferDirection(const I2C_TypeDef * I2Cx)2337 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
2338 {
2339 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
2340 }
2341
2342 /**
2343 * @brief Return the slave matched address.
2344 * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
2345 * @param I2Cx I2C Instance.
2346 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
2347 */
LL_I2C_GetAddressMatchCode(const I2C_TypeDef * I2Cx)2348 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
2349 {
2350 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
2351 }
2352
2353 /**
2354 * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
2355 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2356 * SMBus feature is supported by the I2Cx Instance.
2357 * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
2358 or an Address Matched is received.
2359 * This bit has no effect when RELOAD bit is set.
2360 * This bit has no effect in device mode when SBC bit is not set.
2361 * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
2362 * @param I2Cx I2C Instance.
2363 * @retval None
2364 */
LL_I2C_EnableSMBusPECCompare(I2C_TypeDef * I2Cx)2365 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
2366 {
2367 SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
2368 }
2369
2370 /**
2371 * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
2372 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2373 * SMBus feature is supported by the I2Cx Instance.
2374 * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
2375 * @param I2Cx I2C Instance.
2376 * @retval State of bit (1 or 0).
2377 */
LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef * I2Cx)2378 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
2379 {
2380 return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
2381 }
2382
2383 /**
2384 * @brief Get the SMBus Packet Error byte calculated.
2385 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2386 * SMBus feature is supported by the I2Cx Instance.
2387 * @rmtoll PECR PEC LL_I2C_GetSMBusPEC
2388 * @param I2Cx I2C Instance.
2389 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2390 */
LL_I2C_GetSMBusPEC(const I2C_TypeDef * I2Cx)2391 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
2392 {
2393 return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
2394 }
2395
2396 /**
2397 * @brief Read Receive Data register.
2398 * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
2399 * @param I2Cx I2C Instance.
2400 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2401 */
LL_I2C_ReceiveData8(const I2C_TypeDef * I2Cx)2402 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
2403 {
2404 return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
2405 }
2406
2407 /**
2408 * @brief Write in Transmit Data Register .
2409 * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
2410 * @param I2Cx I2C Instance.
2411 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
2412 * @retval None
2413 */
LL_I2C_TransmitData8(I2C_TypeDef * I2Cx,uint8_t Data)2414 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
2415 {
2416 WRITE_REG(I2Cx->TXDR, Data);
2417 }
2418
2419 /**
2420 * @}
2421 */
2422
2423 /** @defgroup I2C_LL_EF_AutonomousMode Configuration functions related to Autonomous mode feature
2424 * @{
2425 */
2426
2427 /**
2428 * @brief Enable Selected Trigger
2429 * @rmtoll AUTOCR TRIGEN LL_I2C_Enable_SelectedTrigger
2430 * @param I2Cx I2C Instance.
2431 * @retval None
2432 */
LL_I2C_Enable_SelectedTrigger(I2C_TypeDef * I2Cx)2433 __STATIC_INLINE void LL_I2C_Enable_SelectedTrigger(I2C_TypeDef *I2Cx)
2434 {
2435 SET_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN);
2436 }
2437
2438 /**
2439 * @brief Disable Selected Trigger
2440 * @rmtoll AUTOCR TRIGEN LL_I2C_Disable_SelectedTrigger
2441 * @param I2Cx I2C Instance.
2442 * @retval None
2443 */
LL_I2C_Disable_SelectedTrigger(I2C_TypeDef * I2Cx)2444 __STATIC_INLINE void LL_I2C_Disable_SelectedTrigger(I2C_TypeDef *I2Cx)
2445 {
2446 CLEAR_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN);
2447 }
2448
2449 /**
2450 * @brief Indicate if selected Trigger is disabled or enabled
2451 * @rmtoll AUTOCR TRIGEN LL_I2C_IsEnabled_SelectedTrigger
2452 * @param I2Cx I2C Instance.
2453 * @retval State of bit (1 or 0).
2454 */
LL_I2C_IsEnabled_SelectedTrigger(const I2C_TypeDef * I2Cx)2455 __STATIC_INLINE uint32_t LL_I2C_IsEnabled_SelectedTrigger(const I2C_TypeDef *I2Cx)
2456 {
2457 return ((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN) == (I2C_AUTOCR_TRIGEN)) ? 1UL : 0UL);
2458 }
2459
2460 /**
2461 * @brief Set the trigger polarity
2462 * @rmtoll AUTOCR TRIGPOL LL_I2C_SetTriggerPolarity
2463 * @param I2Cx I2C Instance.
2464 * @param Polarity This parameter can be one of the following values:
2465 * @arg @ref LL_I2C_TRIG_POLARITY_RISING
2466 * @arg @ref LL_I2C_TRIG_POLARITY_FALLING
2467 * @retval None
2468 */
LL_I2C_SetTriggerPolarity(I2C_TypeDef * I2Cx,uint32_t Polarity)2469 __STATIC_INLINE void LL_I2C_SetTriggerPolarity(I2C_TypeDef *I2Cx, uint32_t Polarity)
2470 {
2471 MODIFY_REG(I2Cx->AUTOCR, I2C_AUTOCR_TRIGPOL, Polarity);
2472 }
2473
2474 /**
2475 * @brief Get the trigger polarity
2476 * @rmtoll AUTOCR TRIGPOL LL_I2C_GetTriggerPolarity
2477 * @param I2Cx I2C Instance.
2478 * @retval Returned value can be one of the following values:
2479 * @arg @ref LL_I2C_TRIG_POLARITY_RISING
2480 * @arg @ref LL_I2C_TRIG_POLARITY_FALLING
2481 */
LL_I2C_GetTriggerPolarity(const I2C_TypeDef * I2Cx)2482 __STATIC_INLINE uint32_t LL_I2C_GetTriggerPolarity(const I2C_TypeDef *I2Cx)
2483 {
2484 return (uint32_t)(READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGPOL));
2485 }
2486
2487 /**
2488 * @brief Set the selected trigger
2489 * @rmtoll AUTOCR TRIGSEL LL_I2C_SetSelectedTrigger
2490 * @param I2Cx I2C Instance.
2491 * @param Trigger This parameter can be one of the following values:
2492 * @arg @ref LL_I2C_GRP1_GPDMA_CH0_TCF_TRG
2493 * @arg @ref LL_I2C_GRP1_GPDMA_CH1_TCF_TRG
2494 * @arg @ref LL_I2C_GRP1_GPDMA_CH2_TCF_TRG
2495 * @arg @ref LL_I2C_GRP1_GPDMA_CH3_TCF_TRG
2496 * @arg @ref LL_I2C_GRP1_EXTI5_TRG
2497 * @arg @ref LL_I2C_GRP1_EXTI9_TRG
2498 * @arg @ref LL_I2C_GRP1_LPTIM1_CH1_TRG
2499 * @arg @ref LL_I2C_GRP1_LPTIM2_CH1_TRG
2500 * @arg @ref LL_I2C_GRP1_COMP1_TRG
2501 * @arg @ref LL_I2C_GRP1_COMP2_TRG
2502 * @arg @ref LL_I2C_GRP1_RTC_ALRA_TRG
2503 * @arg @ref LL_I2C_GRP1_RTC_WUT_TRG
2504 * @arg @ref LL_I2C_GRP2_GPDMA_CH0_TCF_TRG
2505 * @arg @ref LL_I2C_GRP2_GPDMA_CH1_TCF_TRG
2506 * @arg @ref LL_I2C_GRP2_GPDMA_CH2_TCF_TRG
2507 * @arg @ref LL_I2C_GRP2_GPDMA_CH3_TCF_TRG
2508 * @arg @ref LL_I2C_GRP2_EXTI5_TRG
2509 * @arg @ref LL_I2C_GRP2_EXTI8_TRG
2510 * @arg @ref LL_I2C_GRP2_LPTIM1_CH1_TRG
2511 * @arg @ref LL_I2C_GRP2_COMP1_TRG
2512 * @arg @ref LL_I2C_GRP2_COMP2_TRG
2513 * @arg @ref LL_I2C_GRP2_RTC_ALRA_TRG
2514 * @arg @ref LL_I2C_GRP2_RTC_WUT_TRG
2515 * @retval None
2516 */
LL_I2C_SetSelectedTrigger(I2C_TypeDef * I2Cx,uint32_t Trigger)2517 __STATIC_INLINE void LL_I2C_SetSelectedTrigger(I2C_TypeDef *I2Cx, uint32_t Trigger)
2518 {
2519 MODIFY_REG(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL, (Trigger & I2C_AUTOCR_TRIGSEL_Msk));
2520 }
2521
2522 /**
2523 * @brief Get the selected trigger
2524 * @rmtoll AUTOCR TRIGSEL LL_I2C_GetSelectedTrigger
2525 * @param I2Cx I2C Instance.
2526 * @retval Returned value can be one of the following values:
2527 * @arg @ref LL_I2C_GRP1_GPDMA_CH0_TCF_TRG
2528 * @arg @ref LL_I2C_GRP1_GPDMA_CH1_TCF_TRG
2529 * @arg @ref LL_I2C_GRP1_GPDMA_CH2_TCF_TRG
2530 * @arg @ref LL_I2C_GRP1_GPDMA_CH3_TCF_TRG
2531 * @arg @ref LL_I2C_GRP1_EXTI5_TRG
2532 * @arg @ref LL_I2C_GRP1_EXTI9_TRG
2533 * @arg @ref LL_I2C_GRP1_LPTIM1_CH1_TRG
2534 * @arg @ref LL_I2C_GRP1_LPTIM2_CH1_TRG
2535 * @arg @ref LL_I2C_GRP1_COMP1_TRG
2536 * @arg @ref LL_I2C_GRP1_COMP2_TRG
2537 * @arg @ref LL_I2C_GRP1_RTC_ALRA_TRG
2538 * @arg @ref LL_I2C_GRP1_RTC_WUT_TRG
2539 * @arg @ref LL_I2C_GRP2_GPDMA_CH0_TCF_TRG
2540 * @arg @ref LL_I2C_GRP2_GPDMA_CH1_TCF_TRG
2541 * @arg @ref LL_I2C_GRP2_GPDMA_CH2_TCF_TRG
2542 * @arg @ref LL_I2C_GRP2_GPDMA_CH3_TCF_TRG
2543 * @arg @ref LL_I2C_GRP2_EXTI5_TRG
2544 * @arg @ref LL_I2C_GRP2_EXTI8_TRG
2545 * @arg @ref LL_I2C_GRP2_LPTIM1_CH1_TRG
2546 * @arg @ref LL_I2C_GRP2_COMP1_TRG
2547 * @arg @ref LL_I2C_GRP2_COMP2_TRG
2548 * @arg @ref LL_I2C_GRP2_RTC_ALRA_TRG
2549 * @arg @ref LL_I2C_GRP2_RTC_WUT_TRG
2550 */
LL_I2C_GetSelectedTrigger(const I2C_TypeDef * I2Cx)2551 __STATIC_INLINE uint32_t LL_I2C_GetSelectedTrigger(const I2C_TypeDef *I2Cx)
2552 {
2553 #if defined(LL_I2C_TRIG_GRP1)
2554 if (IS_LL_I2C_GRP2_INSTANCE(I2Cx))
2555 {
2556 return (uint32_t)((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL) | LL_I2C_TRIG_GRP2));
2557 }
2558 else
2559 {
2560 return (uint32_t)((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL) | LL_I2C_TRIG_GRP1));
2561 }
2562 #else
2563 return (uint32_t)((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL) | LL_I2C_TRIG_GRP2));
2564 #endif /* LL_I2C_TRIG_GRP1 */
2565 }
2566
2567 /**
2568 * @}
2569 */
2570
2571 #if defined(USE_FULL_LL_DRIVER)
2572 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
2573 * @{
2574 */
2575
2576 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
2577 ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
2578 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
2579
2580
2581 /**
2582 * @}
2583 */
2584 #endif /* USE_FULL_LL_DRIVER */
2585
2586 /**
2587 * @}
2588 */
2589
2590 /**
2591 * @}
2592 */
2593
2594 #endif /* I2C1 || I2C3 */
2595
2596 /**
2597 * @}
2598 */
2599
2600 #ifdef __cplusplus
2601 }
2602 #endif
2603
2604 #endif /* STM32WBAxx_LL_I2C_H */
2605
