1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL CORTEX driver contains a set of generic APIs that can be
23 used by user:
24 (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
25 functions
26 (+) Low power mode configuration (SCB register of Cortex-MCU)
27 (+) API to access to MCU info (CPUID register)
28 (+) API to enable fault handler (SHCSR accesses)
29 (+) API to enable and disable the MPU secure and non-secure
30 (+) API to configure the region of MPU secure and non-secure
31 (+) API to configure the attributes region of MPU secure and non-secure
32
33 @endverbatim
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef STM32WBAxx_LL_CORTEX_H
38 #define STM32WBAxx_LL_CORTEX_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32wbaxx.h"
46
47 /** @addtogroup STM32WBAxx_LL_Driver
48 * @{
49 */
50
51 /** @defgroup CORTEX_LL CORTEX
52 * @{
53 */
54
55 /* Private types -------------------------------------------------------------*/
56 /* Private variables ---------------------------------------------------------*/
57 /* Private constants ---------------------------------------------------------*/
58 /** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes
59 * @{
60 */
61 /* Register MPU_RBAR (Cortex-M33) : bits [4:0] */
62 #define MPU_ACCESS_MSK (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk)
63 /**
64 * @}
65 */
66
67 /* Private macros ------------------------------------------------------------*/
68 /* Exported types ------------------------------------------------------------*/
69 /* Exported constants --------------------------------------------------------*/
70 /** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants
71 * @{
72 */
73
74 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
75 * @{
76 */
77 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick
78 clock source */
79 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick
80 clock source */
81 /**
82 * @}
83 */
84
85 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
86 * @{
87 */
88 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
89 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
90 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
91 #define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */
92 /**
93 * @}
94 */
95
96 /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control
97 * @{
98 */
99 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U
100 #define LL_MPU_CTRL_HARDFAULT_NMI 2U
101 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U
102 #define LL_MPU_CTRL_HFNMI_PRIVDEF 6U
103 /**
104 * @}
105 */
106
107 /** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes
108 * @{
109 */
110 #define LL_MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
111 #define LL_MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
112 #define LL_MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
113 #define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */
114
115 #define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */
116 #define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */
117 #define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */
118
119 #define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */
120 #define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */
121
122 #define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */
123 #define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */
124 #define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */
125 #define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */
126 /**
127 * @}
128 */
129
130 /** @defgroup CORTEX_LL_MPU_Region_Enable CORTEX LL MPU Region Enable
131 * @{
132 */
133 #define LL_MPU_REGION_ENABLE 1U
134 #define LL_MPU_REGION_DISABLE 0U
135 /**
136 * @}
137 */
138
139 /** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access
140 * @{
141 */
142 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos)
143 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos)
144 /**
145 * @}
146 */
147
148 /** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable
149 * @{
150 */
151 #define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos)
152 #define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos)
153 #define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos)
154 /**
155 * @}
156 */
157
158 /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes
159 * @{
160 */
161 #define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos)
162 #define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos)
163 #define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos)
164 #define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos)
165 /**
166 * @}
167 */
168
169 /** @defgroup CORTEX_LL_MPU_Region_Index CORTEX LL MPU Region Index
170 * @{
171 */
172 #define LL_MPU_REGION_NUMBER0 0U
173 #define LL_MPU_REGION_NUMBER1 1U
174 #define LL_MPU_REGION_NUMBER2 2U
175 #define LL_MPU_REGION_NUMBER3 3U
176 #define LL_MPU_REGION_NUMBER4 4U
177 #define LL_MPU_REGION_NUMBER5 5U
178 #define LL_MPU_REGION_NUMBER6 6U
179 #define LL_MPU_REGION_NUMBER7 7U
180 /**
181 * @}
182 */
183
184 /** @defgroup CORTEX_LL_MPU_Attributes_Index CORTEX LL MPU Memory Attributes Index
185 * @{
186 */
187 #define LL_MPU_ATTRIBUTES_NUMBER0 0U
188 #define LL_MPU_ATTRIBUTES_NUMBER1 1U
189 #define LL_MPU_ATTRIBUTES_NUMBER2 2U
190 #define LL_MPU_ATTRIBUTES_NUMBER3 3U
191 #define LL_MPU_ATTRIBUTES_NUMBER4 4U
192 #define LL_MPU_ATTRIBUTES_NUMBER5 5U
193 #define LL_MPU_ATTRIBUTES_NUMBER6 6U
194 #define LL_MPU_ATTRIBUTES_NUMBER7 7U
195 /**
196 * @}
197 */
198
199 /**
200 * @}
201 */
202
203 /* Exported macro ------------------------------------------------------------*/
204
205 /* Exported functions --------------------------------------------------------*/
206 /** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions
207 * @{
208 */
209
210 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
211 * @brief CORTEX SYSTICK LL module driver
212 * @{
213 */
214
215 /**
216 * @brief This function checks if the Systick counter flag is active or not.
217 * @note It can be used in timeout function on application side.
218 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
219 * @retval State of bit (1 or 0).
220 */
LL_SYSTICK_IsActiveCounterFlag(void)221 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
222 {
223 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
224 }
225
226 /**
227 * @brief Configures the SysTick clock source
228 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
229 * @param Source This parameter can be one of the following values:
230 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
231 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
232 * @retval None
233 */
LL_SYSTICK_SetClkSource(uint32_t Source)234 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
235 {
236 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
237 {
238 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
239 }
240 else
241 {
242 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
243 }
244 }
245
246 /**
247 * @brief Get the SysTick clock source
248 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
249 * @retval Returned value can be one of the following values:
250 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
251 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
252 */
LL_SYSTICK_GetClkSource(void)253 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
254 {
255 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
256 }
257
258 /**
259 * @brief Enable SysTick exception request
260 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
261 * @retval None
262 */
LL_SYSTICK_EnableIT(void)263 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
264 {
265 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
266 }
267
268 /**
269 * @brief Disable SysTick exception request
270 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
271 * @retval None
272 */
LL_SYSTICK_DisableIT(void)273 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
274 {
275 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
276 }
277
278 /**
279 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
280 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
281 * @retval State of bit (1 or 0).
282 */
LL_SYSTICK_IsEnabledIT(void)283 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
284 {
285 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
286 }
287
288 /**
289 * @}
290 */
291
292 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE
293 * @{
294 */
295
296 /**
297 * @brief Processor uses sleep as its low power mode
298 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
299 * @retval None
300 */
LL_LPM_EnableSleep(void)301 __STATIC_INLINE void LL_LPM_EnableSleep(void)
302 {
303 /* Clear SLEEPDEEP bit of Cortex System Control Register */
304 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
305 }
306
307 /**
308 * @brief Processor uses deep sleep as its low power mode
309 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
310 * @retval None
311 */
LL_LPM_EnableDeepSleep(void)312 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
313 {
314 /* Set SLEEPDEEP bit of Cortex System Control Register */
315 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
316 }
317
318 /**
319 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
320 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
321 * empty main application.
322 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
323 * @retval None
324 */
LL_LPM_EnableSleepOnExit(void)325 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
326 {
327 /* Set SLEEPONEXIT bit of Cortex System Control Register */
328 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
329 }
330
331 /**
332 * @brief Do not sleep when returning to Thread mode.
333 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
334 * @retval None
335 */
LL_LPM_DisableSleepOnExit(void)336 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
337 {
338 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
339 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
340 }
341
342 /**
343 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
344 * processor.
345 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
346 * @retval None
347 */
LL_LPM_EnableEventOnPend(void)348 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
349 {
350 /* Set SEVEONPEND bit of Cortex System Control Register */
351 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
352 }
353
354 /**
355 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
356 * excluded
357 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
358 * @retval None
359 */
LL_LPM_DisableEventOnPend(void)360 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
361 {
362 /* Clear SEVEONPEND bit of Cortex System Control Register */
363 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
364 }
365
366 /**
367 * @}
368 */
369
370 /** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER
371 * @{
372 */
373
374 /**
375 * @brief Enable a fault in System handler control register (SHCSR)
376 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n
377 * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n
378 * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n
379 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault
380 * @param Fault This parameter can be a combination of the following values:
381 * @arg @ref LL_HANDLER_FAULT_USG
382 * @arg @ref LL_HANDLER_FAULT_BUS
383 * @arg @ref LL_HANDLER_FAULT_MEM
384 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
385 *
386 * (*) value applicable in secure when the system implements the security.
387 * @retval None
388 */
LL_HANDLER_EnableFault(uint32_t Fault)389 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
390 {
391 /* Enable the system handler fault */
392 SET_BIT(SCB->SHCSR, Fault);
393 }
394
395 /**
396 * @brief Disable a fault in System handler control register (SHCSR)
397 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n
398 * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n
399 * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n
400 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault
401 * @param Fault This parameter can be a combination of the following values:
402 * @arg @ref LL_HANDLER_FAULT_USG
403 * @arg @ref LL_HANDLER_FAULT_BUS
404 * @arg @ref LL_HANDLER_FAULT_MEM
405 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
406 *
407 * (*) value applicable in secure when the system implements the security.
408 * @retval None
409 */
LL_HANDLER_DisableFault(uint32_t Fault)410 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
411 {
412 /* Disable the system handler fault */
413 CLEAR_BIT(SCB->SHCSR, Fault);
414 }
415
416 /**
417 * @}
418 */
419
420 /** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO
421 * @{
422 */
423
424 /**
425 * @brief Get Implementer code
426 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
427 * @retval Value should be equal to 0x41 for ARM
428 */
LL_CPUID_GetImplementer(void)429 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
430 {
431 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
432 }
433
434 /**
435 * @brief Get Variant number (The r value in the rnpn product revision identifier)
436 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
437 * @retval Value between 0 and 255 (0x0: revision 0)
438 */
LL_CPUID_GetVariant(void)439 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
440 {
441 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
442 }
443
444 /**
445 * @brief Get Architecture version
446 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
447 * @retval Value should be equal to 0xF for Cortex-M33 ("ARMv8-M with Main Extension")
448 */
LL_CPUID_GetArchitecture(void)449 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
450 {
451 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
452 }
453
454 /**
455 * @brief Get Part number
456 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
457 * @retval Value should be equal to 0xD21 for Cortex-M33
458 */
LL_CPUID_GetParNo(void)459 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
460 {
461 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
462 }
463
464 /**
465 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
466 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
467 * @retval Value between 0 and 255 (0x1: patch 1)
468 */
LL_CPUID_GetRevision(void)469 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
470 {
471 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
472 }
473
474 /**
475 * @}
476 */
477
478 /** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU
479 * @{
480 */
481
482 /**
483 * @brief Enable MPU with input options
484 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
485 * @param MPU_Control This parameter can be one of the following values:
486 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
487 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
488 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
489 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
490 * @retval None
491 */
LL_MPU_Enable(uint32_t MPU_Control)492 __STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
493 {
494 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
495
496 /* Enable the MPU*/
497 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
498
499 /* Follow ARM recommendation with */
500 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
501 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
502 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
503 }
504
505 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
506 /**
507 * @brief Enable non-secure MPU with input options
508 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
509 * @param MPU_Control This parameter can be one of the following values:
510 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
511 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
512 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
513 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
514 * @retval None
515 */
LL_MPU_Enable_NS(uint32_t MPU_Control)516 __STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
517 {
518 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
519
520 /* Enable the MPU*/
521 MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
522
523 /* Follow ARM recommendation with */
524 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
525 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
526 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
527 }
528 #endif /* __ARM_FEATURE_CMSE */
529
530 /**
531 * @brief Disable MPU
532 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
533 * @retval None
534 */
LL_MPU_Disable(void)535 __STATIC_INLINE void LL_MPU_Disable(void)
536 {
537 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
538
539 /* Disable MPU*/
540 WRITE_REG(MPU->CTRL, 0U);
541
542 /* Follow ARM recommendation with */
543 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
544 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
545 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
546 }
547
548 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
549 /**
550 * @brief Disable the non-secure MPU
551 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS
552 * @retval None
553 */
LL_MPU_Disable_NS(void)554 __STATIC_INLINE void LL_MPU_Disable_NS(void)
555 {
556 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
557
558 /* Disable MPU*/
559 WRITE_REG(MPU_NS->CTRL, 0U);
560
561 /* Follow ARM recommendation with */
562 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
563 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
564 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
565 }
566 #endif /* __ARM_FEATURE_CMSE */
567
568
569 /**
570 * @brief Check if MPU is enabled or not
571 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
572 * @retval State of bit (1 or 0).
573 */
LL_MPU_IsEnabled(void)574 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
575 {
576 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
577 }
578
579 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
580 /**
581 * @brief Check if non-secure MPU is enabled or not
582 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS
583 * @retval State of bit (1 or 0).
584 */
LL_MPU_IsEnabled_NS(void)585 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void)
586 {
587 return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
588 }
589 #endif /* __ARM_FEATURE_CMSE */
590
591 /**
592 * @brief Enable a MPU region
593 * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion
594 * @param Region This parameter can be one of the following values:
595 * @arg @ref LL_MPU_REGION_NUMBER0
596 * @arg @ref LL_MPU_REGION_NUMBER1
597 * @arg @ref LL_MPU_REGION_NUMBER2
598 * @arg @ref LL_MPU_REGION_NUMBER3
599 * @arg @ref LL_MPU_REGION_NUMBER4
600 * @arg @ref LL_MPU_REGION_NUMBER5
601 * @arg @ref LL_MPU_REGION_NUMBER6
602 * @arg @ref LL_MPU_REGION_NUMBER7
603 * @note cortex-M33 supports 8 secure and 8 non secure regions.
604 * @retval None
605 */
LL_MPU_EnableRegion(uint32_t Region)606 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
607 {
608 /* Set Region number */
609 WRITE_REG(MPU->RNR, Region);
610
611 /* Enable the MPU region */
612 SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
613 }
614
615 /**
616 * @brief Check if MPU region is enabled or not
617 * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region
618 * @param Region This parameter can be one of the following values:
619 * @arg @ref LL_MPU_REGION_NUMBER0
620 * @arg @ref LL_MPU_REGION_NUMBER1
621 * @arg @ref LL_MPU_REGION_NUMBER2
622 * @arg @ref LL_MPU_REGION_NUMBER3
623 * @arg @ref LL_MPU_REGION_NUMBER4
624 * @arg @ref LL_MPU_REGION_NUMBER5
625 * @arg @ref LL_MPU_REGION_NUMBER6
626 * @arg @ref LL_MPU_REGION_NUMBER7
627 * @note cortex-M33 supports 8 secure and 8 non secure regions.
628 * @retval State of bit (1 or 0).
629 */
LL_MPU_IsEnabled_Region(uint32_t Region)630 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region)
631 {
632 /* Set region index */
633 WRITE_REG(MPU->RNR, Region);
634
635 /* Return MPU region status */
636 return ((READ_BIT(MPU->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
637 }
638
639 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
640 /**
641 * @brief Enable a non-secure MPU region
642 * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion_NS
643 * @param Region This parameter can be one of the following values:
644 * @arg @ref LL_MPU_REGION_NUMBER0
645 * @arg @ref LL_MPU_REGION_NUMBER1
646 * @arg @ref LL_MPU_REGION_NUMBER2
647 * @arg @ref LL_MPU_REGION_NUMBER3
648 * @arg @ref LL_MPU_REGION_NUMBER4
649 * @arg @ref LL_MPU_REGION_NUMBER5
650 * @arg @ref LL_MPU_REGION_NUMBER6
651 * @arg @ref LL_MPU_REGION_NUMBER7
652 * @note cortex-M33 supports 8 secure and 8 non secure regions.
653 * @retval None
654 */
LL_MPU_EnableRegion_NS(uint32_t Region)655 __STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region)
656 {
657 /* Set Region number */
658 WRITE_REG(MPU_NS->RNR, Region);
659
660 /* Enable the MPU region */
661 SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
662 }
663
664 /**
665 * @brief Check if non-secure MPU region is enabled or not
666 * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region_NS
667 * @param Region This parameter can be one of the following values:
668 * @arg @ref LL_MPU_REGION_NUMBER0
669 * @arg @ref LL_MPU_REGION_NUMBER1
670 * @arg @ref LL_MPU_REGION_NUMBER2
671 * @arg @ref LL_MPU_REGION_NUMBER3
672 * @arg @ref LL_MPU_REGION_NUMBER4
673 * @arg @ref LL_MPU_REGION_NUMBER5
674 * @arg @ref LL_MPU_REGION_NUMBER6
675 * @arg @ref LL_MPU_REGION_NUMBER7
676 * @note cortex-M33 supports 8 secure and 8 non secure regions.
677 * @retval State of bit (1 or 0).
678 */
LL_MPU_IsEnabled_Region_NS(uint32_t Region)679 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region_NS(uint32_t Region)
680 {
681 /* Set region index */
682 WRITE_REG(MPU_NS->RNR, Region);
683
684 /* Return non-secure MPU region status */
685 return ((READ_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
686 }
687 #endif /* __ARM_FEATURE_CMSE */
688
689 /**
690 * @brief Disable a MPU region
691 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
692 * MPU_RLAR ENABLE LL_MPU_DisableRegion
693 * @param Region This parameter can be one of the following values:
694 * @arg @ref LL_MPU_REGION_NUMBER0
695 * @arg @ref LL_MPU_REGION_NUMBER1
696 * @arg @ref LL_MPU_REGION_NUMBER2
697 * @arg @ref LL_MPU_REGION_NUMBER3
698 * @arg @ref LL_MPU_REGION_NUMBER4
699 * @arg @ref LL_MPU_REGION_NUMBER5
700 * @arg @ref LL_MPU_REGION_NUMBER6
701 * @arg @ref LL_MPU_REGION_NUMBER7
702 * @note cortex-M33 supports 8 secure and 8 non secure regions.
703 * @retval None
704 */
LL_MPU_DisableRegion(uint32_t Region)705 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
706 {
707 /* Set Region number */
708 WRITE_REG(MPU->RNR, Region);
709
710 /* Disable the MPU region */
711 CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
712 }
713
714 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
715 /**
716 * @brief Disable a non-secure MPU region
717 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n
718 * MPU_RLAR ENABLE LL_MPU_DisableRegion_NS\n
719 * @param Region This parameter can be one of the following values:
720 * @arg @ref LL_MPU_REGION_NUMBER0
721 * @arg @ref LL_MPU_REGION_NUMBER1
722 * @arg @ref LL_MPU_REGION_NUMBER2
723 * @arg @ref LL_MPU_REGION_NUMBER3
724 * @arg @ref LL_MPU_REGION_NUMBER4
725 * @arg @ref LL_MPU_REGION_NUMBER5
726 * @arg @ref LL_MPU_REGION_NUMBER6
727 * @arg @ref LL_MPU_REGION_NUMBER7
728 * @note cortex-M33 supports 8 secure and 8 non secure regions.
729 * @retval None
730 */
LL_MPU_DisableRegion_NS(uint32_t Region)731 __STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region)
732 {
733 /* Set Region number */
734 WRITE_REG(MPU_NS->RNR, Region);
735
736 /* Disable the MPU region */
737 CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
738 }
739 #endif /* __ARM_FEATURE_CMSE */
740
741 /**
742 * @brief Configure and enable a MPU region
743 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
744 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
745 * MPU_RLAR ADDR LL_MPU_ConfigRegion\n
746 * MPU_RBAR XN LL_MPU_ConfigRegion\n
747 * MPU_RBAR AP LL_MPU_ConfigRegion\n
748 * MPU_RBAR SH LL_MPU_ConfigRegion\n
749 * MPU_RLAR EN LL_MPU_ConfigRegion\n
750 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion\n
751 * @param Region This parameter can be one of the following values:
752 * @arg @ref LL_MPU_REGION_NUMBER0
753 * @arg @ref LL_MPU_REGION_NUMBER1
754 * @arg @ref LL_MPU_REGION_NUMBER2
755 * @arg @ref LL_MPU_REGION_NUMBER3
756 * @arg @ref LL_MPU_REGION_NUMBER4
757 * @arg @ref LL_MPU_REGION_NUMBER5
758 * @arg @ref LL_MPU_REGION_NUMBER6
759 * @arg @ref LL_MPU_REGION_NUMBER7
760 * @param Attributes This parameter can be a combination of the following values:
761 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
762 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
763 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
764 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
765 * or @ref LL_MPU_REGION_ALL_RO
766 * @param AttrIndx This parameter can be one of the following values:
767 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
768 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
769 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
770 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
771 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
772 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
773 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
774 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
775 * @param BaseAddress Value of region base address
776 * @param LimitAddress Value of region limit address
777 * @note cortex-M33 supports 8 secure and 8 non secure regions.
778 * @retval None
779 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)780 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress,
781 uint32_t LimitAddress)
782 {
783 /* Set region index */
784 WRITE_REG(MPU->RNR, Region);
785
786 /* Set base address */
787 MPU->RBAR |= Attributes;
788
789 /* Set region base address and region access attributes */
790 WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
791
792 /* Set region limit address, memory attributes index and enable region */
793 WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
794 }
795
796 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
797 /**
798 * @brief Configure and enable a non-secure MPU region
799 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n
800 * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n
801 * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n
802 * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n
803 * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n
804 * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n
805 * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n
806 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS\n
807 * @param Region This parameter can be one of the following values:
808 * @arg @ref LL_MPU_REGION_NUMBER0
809 * @arg @ref LL_MPU_REGION_NUMBER1
810 * @arg @ref LL_MPU_REGION_NUMBER2
811 * @arg @ref LL_MPU_REGION_NUMBER3
812 * @arg @ref LL_MPU_REGION_NUMBER4
813 * @arg @ref LL_MPU_REGION_NUMBER5
814 * @arg @ref LL_MPU_REGION_NUMBER6
815 * @arg @ref LL_MPU_REGION_NUMBER7
816 * @param Attributes This parameter can be a combination of the following values:
817 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
818 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
819 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
820 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
821 * or @ref LL_MPU_REGION_ALL_RO
822 * @param AttrIndx This parameter can be one of the following values:
823 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
824 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
825 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
826 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
827 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
828 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
829 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
830 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
831 * @param BaseAddress Value of region base address
832 * @param LimitAddress Value of region limit address
833 * @note cortex-M33 supports 8 secure and 8 non secure regions.
834 * @retval None
835 */
LL_MPU_ConfigRegion_NS(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)836 __STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx,
837 uint32_t BaseAddress, uint32_t LimitAddress)
838 {
839 /* Set Region number */
840 WRITE_REG(MPU_NS->RNR, Region);
841
842 /* Set region base address and region access attributes */
843 WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
844
845 /* Set region limit address, memory attributes index and enable region */
846 WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
847 }
848 #endif /* __ARM_FEATURE_CMSE */
849
850 /**
851 * @brief Configure a MPU region address range
852 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n
853 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n
854 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n
855 * @param Region This parameter can be one of the following values:
856 * @arg @ref LL_MPU_REGION_NUMBER0
857 * @arg @ref LL_MPU_REGION_NUMBER1
858 * @arg @ref LL_MPU_REGION_NUMBER2
859 * @arg @ref LL_MPU_REGION_NUMBER3
860 * @arg @ref LL_MPU_REGION_NUMBER4
861 * @arg @ref LL_MPU_REGION_NUMBER5
862 * @arg @ref LL_MPU_REGION_NUMBER6
863 * @arg @ref LL_MPU_REGION_NUMBER7
864 * @param BaseAddress Value of region base address
865 * @param LimitAddress Value of region limit address
866 * @note cortex-M33 supports 8 secure and 8 non secure regions.
867 * @retval None
868 */
LL_MPU_ConfigRegionAddress(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)869 __STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
870 {
871 /* Set Region number */
872 WRITE_REG(MPU->RNR, Region);
873
874 /* Modify region base address */
875 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
876
877 /* Modify region limit address */
878 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
879 }
880
881 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
882 /**
883 * @brief Configure a non-secure MPU region address range
884 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n
885 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n
886 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n
887 * @param Region This parameter can be one of the following values:
888 * @arg @ref LL_MPU_REGION_NUMBER0
889 * @arg @ref LL_MPU_REGION_NUMBER1
890 * @arg @ref LL_MPU_REGION_NUMBER2
891 * @arg @ref LL_MPU_REGION_NUMBER3
892 * @arg @ref LL_MPU_REGION_NUMBER4
893 * @arg @ref LL_MPU_REGION_NUMBER5
894 * @arg @ref LL_MPU_REGION_NUMBER6
895 * @arg @ref LL_MPU_REGION_NUMBER7
896 * @param BaseAddress Value of region base address
897 * @param LimitAddress Value of region limit address
898 * @note cortex-M33 supports 8 secure and 8 non secure regions.
899 * @retval None
900 */
LL_MPU_ConfigRegionAddress_NS(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)901 __STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
902 {
903 /* Set Region number */
904 WRITE_REG(MPU_NS->RNR, Region);
905
906 /* Set base address */
907 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
908
909 /* Set limit address */
910 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
911 }
912 #endif /* __ARM_FEATURE_CMSE */
913
914 /**
915 * @brief Configure a MPU attributes index
916 * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes\n
917 * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes\n
918 * @param AttIndex This parameter can be one of the following values:
919 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
920 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
921 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
922 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
923 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
924 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
925 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
926 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
927 * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
928 * @retval None
929 */
LL_MPU_ConfigAttributes(uint32_t AttIndex,uint32_t Attributes)930 __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes)
931 {
932 /* When selected index is in range [0;3] */
933 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
934 {
935 /* Modify Attr<i> field of MPU_MAIR0 accordingly */
936 MODIFY_REG(MPU->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
937 }
938 /* When selected index is in range [4;7] */
939 else
940 {
941 /* Modify Attr<i> field of MPU_MAIR1 accordingly */
942 MODIFY_REG(MPU->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
943 }
944 }
945
946 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
947 /**
948 * @brief Configure a non-secure MPU attributes index
949 * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes_NS\n
950 * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes_NS\n
951 * @param AttIndex This parameter can be one of the following values:
952 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
953 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
954 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
955 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
956 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
957 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
958 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
959 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
960 * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
961 * @retval None
962 */
LL_MPU_ConfigAttributes_NS(uint32_t AttIndex,uint32_t Attributes)963 __STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes)
964 {
965 /* When selected index is in range [0;3] */
966 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
967 {
968 /* Modify Attr<i> field of MPU_MAIR0_NS accordingly */
969 MODIFY_REG(MPU_NS->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
970 }
971 /* When selected index is in range [4;7] */
972 else
973 {
974 /* Modify Attr<i> field of MPU_MAIR1_NS accordingly */
975 MODIFY_REG(MPU_NS->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
976 }
977 }
978 #endif /* __ARM_FEATURE_CMSE */
979
980 /**
981 * @brief Configure a MPU region limit address
982 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n
983 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress\n
984 * @param Region This parameter can be one of the following values:
985 * @arg @ref LL_MPU_REGION_NUMBER0
986 * @arg @ref LL_MPU_REGION_NUMBER1
987 * @arg @ref LL_MPU_REGION_NUMBER2
988 * @arg @ref LL_MPU_REGION_NUMBER3
989 * @arg @ref LL_MPU_REGION_NUMBER4
990 * @arg @ref LL_MPU_REGION_NUMBER5
991 * @arg @ref LL_MPU_REGION_NUMBER6
992 * @arg @ref LL_MPU_REGION_NUMBER7
993 * @param LimitAddress Value of region limit address
994 * @note cortex-M33 supports 8 secure and 8 non secure regions.
995 * @retval None
996 */
LL_MPU_SetRegionLimitAddress(uint32_t Region,uint32_t LimitAddress)997 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress)
998 {
999 /* Set Region number */
1000 WRITE_REG(MPU->RNR, Region);
1001
1002 /* Set limit address */
1003 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1004 }
1005
1006 /**
1007 * @brief Get a MPU region limit address
1008 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n
1009 * @param Region This parameter can be one of the following values:
1010 * @arg @ref LL_MPU_REGION_NUMBER0
1011 * @arg @ref LL_MPU_REGION_NUMBER1
1012 * @arg @ref LL_MPU_REGION_NUMBER2
1013 * @arg @ref LL_MPU_REGION_NUMBER3
1014 * @arg @ref LL_MPU_REGION_NUMBER4
1015 * @arg @ref LL_MPU_REGION_NUMBER5
1016 * @arg @ref LL_MPU_REGION_NUMBER6
1017 * @arg @ref LL_MPU_REGION_NUMBER7
1018 * @retval None
1019 */
LL_MPU_GetRegionLimitAddress(uint32_t Region)1020 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region)
1021 {
1022 /* Set Region number */
1023 WRITE_REG(MPU->RNR, Region);
1024
1025 return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk));
1026 }
1027
1028 /**
1029 * @brief Configure a MPU region base address
1030 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n
1031 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress\n
1032 * @param Region This parameter can be one of the following values:
1033 * @arg @ref LL_MPU_REGION_NUMBER0
1034 * @arg @ref LL_MPU_REGION_NUMBER1
1035 * @arg @ref LL_MPU_REGION_NUMBER2
1036 * @arg @ref LL_MPU_REGION_NUMBER3
1037 * @arg @ref LL_MPU_REGION_NUMBER4
1038 * @arg @ref LL_MPU_REGION_NUMBER5
1039 * @arg @ref LL_MPU_REGION_NUMBER6
1040 * @arg @ref LL_MPU_REGION_NUMBER7
1041 * @param BaseAddress Value of region base address
1042 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1043 * @retval None
1044 */
LL_MPU_SetRegionBaseAddress(uint32_t Region,uint32_t BaseAddress)1045 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress)
1046 {
1047 /* Set Region number */
1048 WRITE_REG(MPU->RNR, Region);
1049
1050 /* Set base address */
1051 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1052 }
1053
1054 /**
1055 * @brief Get a MPU region base address
1056 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n
1057 * @param Region This parameter can be one of the following values:
1058 * @arg @ref LL_MPU_REGION_NUMBER0
1059 * @arg @ref LL_MPU_REGION_NUMBER1
1060 * @arg @ref LL_MPU_REGION_NUMBER2
1061 * @arg @ref LL_MPU_REGION_NUMBER3
1062 * @arg @ref LL_MPU_REGION_NUMBER4
1063 * @arg @ref LL_MPU_REGION_NUMBER5
1064 * @arg @ref LL_MPU_REGION_NUMBER6
1065 * @arg @ref LL_MPU_REGION_NUMBER7
1066 * @retval None
1067 */
LL_MPU_GetRegionBaseAddress(uint32_t Region)1068 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region)
1069 {
1070 /* Set Region number */
1071 WRITE_REG(MPU->RNR, Region);
1072
1073 return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk));
1074 }
1075
1076 /**
1077 * @brief Configure a MPU region access attributes and enable a region
1078 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n
1079 * MPU_RBAR XN LL_MPU_SetRegionAccess\n
1080 * MPU_RBAR AP LL_MPU_SetRegionAccess\n
1081 * MPU_RBAR SH LL_MPU_SetRegionAccess\n
1082 * @param Region This parameter can be one of the following values:
1083 * @arg @ref LL_MPU_REGION_NUMBER0
1084 * @arg @ref LL_MPU_REGION_NUMBER1
1085 * @arg @ref LL_MPU_REGION_NUMBER2
1086 * @arg @ref LL_MPU_REGION_NUMBER3
1087 * @arg @ref LL_MPU_REGION_NUMBER4
1088 * @arg @ref LL_MPU_REGION_NUMBER5
1089 * @arg @ref LL_MPU_REGION_NUMBER6
1090 * @arg @ref LL_MPU_REGION_NUMBER7
1091 * @param Attributes This parameter can be a combination of the following values:
1092 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1093 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1094 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1095 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1096 * or @ref LL_MPU_REGION_ALL_RO
1097 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1098 * @retval None
1099 */
LL_MPU_SetRegionAccess(uint32_t Region,uint32_t Attributes)1100 __STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes)
1101 {
1102 /* Set Region number */
1103 WRITE_REG(MPU->RNR, Region);
1104
1105 /* Set base address */
1106 MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
1107 }
1108
1109 /**
1110 * @brief Get a MPU region access attributes
1111 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n
1112 * MPU_RBAR XN LL_MPU_GetRegionAccess\n
1113 * MPU_RBAR AP LL_MPU_GetRegionAccess\n
1114 * MPU_RBAR SH LL_MPU_GetRegionAccess\n
1115 * @param Region This parameter can be one of the following values:
1116 * @arg @ref LL_MPU_REGION_NUMBER0
1117 * @arg @ref LL_MPU_REGION_NUMBER1
1118 * @arg @ref LL_MPU_REGION_NUMBER2
1119 * @arg @ref LL_MPU_REGION_NUMBER3
1120 * @arg @ref LL_MPU_REGION_NUMBER4
1121 * @arg @ref LL_MPU_REGION_NUMBER5
1122 * @arg @ref LL_MPU_REGION_NUMBER6
1123 * @arg @ref LL_MPU_REGION_NUMBER7
1124 * @retval None
1125 */
LL_MPU_GetRegionAccess(uint32_t Region)1126 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region)
1127 {
1128 /* Set Region number */
1129 WRITE_REG(MPU->RNR, Region);
1130
1131 return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1132 }
1133
1134 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1135 /**
1136 * @brief Configure a non-secure MPU region limit address
1137 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n
1138 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS\n
1139 * @param Region This parameter can be one of the following values:
1140 * @arg @ref LL_MPU_REGION_NUMBER0
1141 * @arg @ref LL_MPU_REGION_NUMBER1
1142 * @arg @ref LL_MPU_REGION_NUMBER2
1143 * @arg @ref LL_MPU_REGION_NUMBER3
1144 * @arg @ref LL_MPU_REGION_NUMBER4
1145 * @arg @ref LL_MPU_REGION_NUMBER5
1146 * @arg @ref LL_MPU_REGION_NUMBER6
1147 * @arg @ref LL_MPU_REGION_NUMBER7
1148 * @param LimitAddress Value of region limit address
1149 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1150 * @retval None
1151 */
LL_MPU_SetRegionLimitAddress_NS(uint32_t Region,uint32_t LimitAddress)1152 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress)
1153 {
1154 /* Set Region number */
1155 WRITE_REG(MPU_NS->RNR, Region);
1156
1157 /* Set limit address */
1158 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1159 }
1160
1161 /**
1162 * @brief Get a non-secure MPU region limit address
1163 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n
1164 * @param Region This parameter can be one of the following values:
1165 * @arg @ref LL_MPU_REGION_NUMBER0
1166 * @arg @ref LL_MPU_REGION_NUMBER1
1167 * @arg @ref LL_MPU_REGION_NUMBER2
1168 * @arg @ref LL_MPU_REGION_NUMBER3
1169 * @arg @ref LL_MPU_REGION_NUMBER4
1170 * @arg @ref LL_MPU_REGION_NUMBER5
1171 * @arg @ref LL_MPU_REGION_NUMBER6
1172 * @arg @ref LL_MPU_REGION_NUMBER7
1173 * @retval None
1174 */
LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)1175 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)
1176 {
1177 /* Set Region number */
1178 WRITE_REG(MPU_NS->RNR, Region);
1179
1180 return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk));
1181 }
1182
1183 /**
1184 * @brief Configure a non-secure MPU region base address
1185 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n
1186 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS\n
1187 * @param Region This parameter can be one of the following values:
1188 * @arg @ref LL_MPU_REGION_NUMBER0
1189 * @arg @ref LL_MPU_REGION_NUMBER1
1190 * @arg @ref LL_MPU_REGION_NUMBER2
1191 * @arg @ref LL_MPU_REGION_NUMBER3
1192 * @arg @ref LL_MPU_REGION_NUMBER4
1193 * @arg @ref LL_MPU_REGION_NUMBER5
1194 * @arg @ref LL_MPU_REGION_NUMBER6
1195 * @arg @ref LL_MPU_REGION_NUMBER7
1196 * @param BaseAddress Value of region base address
1197 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1198 * @retval None
1199 */
LL_MPU_SetRegionBaseAddress_NS(uint32_t Region,uint32_t BaseAddress)1200 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress)
1201 {
1202 /* Set Region number */
1203 WRITE_REG(MPU_NS->RNR, Region);
1204
1205 /* Set base address */
1206 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1207 }
1208
1209 /**
1210 * @brief Get a non-secure MPU region base address
1211 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n
1212 * @param Region This parameter can be one of the following values:
1213 * @arg @ref LL_MPU_REGION_NUMBER0
1214 * @arg @ref LL_MPU_REGION_NUMBER1
1215 * @arg @ref LL_MPU_REGION_NUMBER2
1216 * @arg @ref LL_MPU_REGION_NUMBER3
1217 * @arg @ref LL_MPU_REGION_NUMBER4
1218 * @arg @ref LL_MPU_REGION_NUMBER5
1219 * @arg @ref LL_MPU_REGION_NUMBER6
1220 * @arg @ref LL_MPU_REGION_NUMBER7
1221 * @retval None
1222 */
LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)1223 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)
1224 {
1225 /* Set Region number */
1226 WRITE_REG(MPU_NS->RNR, Region);
1227
1228 return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk));
1229 }
1230
1231 /**
1232 * @brief Configure a non-secure MPU region access attributes and enable a region
1233 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n
1234 * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n
1235 * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n
1236 * MPU_RBAR SH LL_MPU_SetRegionAccess_NS\n
1237 * @param Region This parameter can be one of the following values:
1238 * @arg @ref LL_MPU_REGION_NUMBER0
1239 * @arg @ref LL_MPU_REGION_NUMBER1
1240 * @arg @ref LL_MPU_REGION_NUMBER2
1241 * @arg @ref LL_MPU_REGION_NUMBER3
1242 * @arg @ref LL_MPU_REGION_NUMBER4
1243 * @arg @ref LL_MPU_REGION_NUMBER5
1244 * @arg @ref LL_MPU_REGION_NUMBER6
1245 * @arg @ref LL_MPU_REGION_NUMBER7
1246 * @param Attributes This parameter can be a combination of the following values:
1247 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1248 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1249 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1250 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1251 * or @ref LL_MPU_REGION_ALL_RO
1252 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1253 * @retval None
1254 */
LL_MPU_SetRegionAccess_NS(uint32_t Region,uint32_t Attributes)1255 __STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes)
1256 {
1257 /* Set Region number */
1258 WRITE_REG(MPU_NS->RNR, Region);
1259
1260 /* Set base address Attributes */
1261 MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
1262 }
1263
1264 /**
1265 * @brief Get a non-secure MPU region access attributes
1266 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n
1267 * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n
1268 * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n
1269 * MPU_RBAR SH LL_MPU_GetRegionAccess_NS\n
1270 * @param Region This parameter can be one of the following values:
1271 * @arg @ref LL_MPU_REGION_NUMBER0
1272 * @arg @ref LL_MPU_REGION_NUMBER1
1273 * @arg @ref LL_MPU_REGION_NUMBER2
1274 * @arg @ref LL_MPU_REGION_NUMBER3
1275 * @arg @ref LL_MPU_REGION_NUMBER4
1276 * @arg @ref LL_MPU_REGION_NUMBER5
1277 * @arg @ref LL_MPU_REGION_NUMBER6
1278 * @arg @ref LL_MPU_REGION_NUMBER7
1279 * @retval None
1280 */
LL_MPU_GetRegionAccess_NS(uint32_t Region)1281 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region)
1282 {
1283 /* Set Region number */
1284 WRITE_REG(MPU_NS->RNR, Region);
1285
1286 return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1287 }
1288 #endif /* __ARM_FEATURE_CMSE */
1289
1290 /**
1291 * @}
1292 */
1293
1294 /**
1295 * @}
1296 */
1297
1298 /**
1299 * @}
1300 */
1301
1302 /**
1303 * @}
1304 */
1305
1306 #ifdef __cplusplus
1307 }
1308 #endif
1309
1310 #endif /* STM32WBAxx_LL_CORTEX_H */
1311
