1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBAxx_LL_ADC_H
21 #define STM32WBAxx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC4)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer rank bits position into the selected register */
51
52 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
53
54 /* Definition of ADC group regular sequencer bits information to be inserted */
55 /* into ADC group regular sequencer ranks literals definition. */
56 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */
57 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */
58 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */
59 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */
60 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */
61 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */
62 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */
63 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */
64
65
66
67 /* Internal mask for ADC group regular trigger: */
68 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
69 /* - regular trigger source */
70 /* - regular trigger edge */
71 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for
72 compatibility with some ADC on other STM32 series
73 having this setting set by HW default value) */
74
75 /* Mask containing trigger source masks for each of possible */
76 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
77 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
78 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
79 ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \
80 ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \
81 ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) )
82
83 /* Mask containing trigger edge masks for each of possible */
84 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
85 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
86 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
87 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
88 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
89 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
90
91 /* Definition of ADC group regular trigger bits information. */
92 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */
93 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */
94
95
96
97 /* Internal mask for ADC channel: */
98 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
99 /* - channel identifier defined by number */
100 /* - channel identifier defined by bitfield */
101 /* - channel differentiation between external channels (connected to */
102 /* GPIO pins) and internal channels (connected to internal paths) */
103 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)
104 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
105 #define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to
106 ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer,
107 if set to mode "fully configurable", can contain channels with a restricted channel number.
108 Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
109 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK"
110 position in register */
111 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \
112 ADC_CHANNEL_ID_INTERNAL_CH_MASK)
113 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
114 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
115 >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
116
117 /* Channel differentiation between external and internal channels */
118 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
119 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
120
121 /* Definition of channels ID number information to be inserted into */
122 /* channels literals definition. */
123 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
124 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0)
125 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1)
126 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
127 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2)
128 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
129 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
130 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
131 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3)
132 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
133 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
134 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
135 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
136 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
137 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
138 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \
139 ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
140 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4)
141 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
142 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
143
144 /* Definition of channels ID bitfield information to be inserted into */
145 /* channels literals definition. */
146 #define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
147 #define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
148 #define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
149 #define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
150 #define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
151 #define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
152 #define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
153 #define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
154 #define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
155 #define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
156 #define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
157 #define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
158 #define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
159 #define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
160 #define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
161 #define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
162 #define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
163 #define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
164
165 /* Internal mask for ADC channel sampling time: */
166 /* To select into literals LL_ADC_SAMPLINGTIME_x */
167 /* the relevant bits for: */
168 /* (concatenation of multiple bits used in register SMPR) */
169 /* - ADC channels sampling time: setting channel wise, to map each channel */
170 /* on one of the common sampling time available. */
171 /* - ADC channels common sampling time: set a sampling time into one of the */
172 /* common sampling time available. */
173 #define ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS)
174 #define ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)
175 #define ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)
176
177 /* Internal mask for ADC analog watchdog: */
178 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
179 /* (concatenation of multiple bits used in different analog watchdogs, */
180 /* (feature of several watchdogs not available on all STM32 series)). */
181 /* - analog watchdog 1: monitored channel defined by number, */
182 /* selection of ADC group (ADC group regular). */
183 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
184 /* selection on groups. */
185
186 /* Internal register offset for ADC analog watchdog channel configuration */
187 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
188 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
189 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
190
191 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
192 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
193 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
194 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
195
196 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
197 #define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)
198
199 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
200 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
201 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
202
203 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET
204 in ADC_AWD_CRX_REGOFFSET_MASK */
205
206 /* Internal register offset for ADC analog watchdog threshold configuration */
207 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
208 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
209 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS))
210 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
211 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET
212 in ADC_AWD_TRX_REGOFFSET_MASK */
213 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
214 threshold high: mask of bit */
215 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
216 threshold high: position of bit */
217 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
218 position to perform a shift of 4 ranks */
219 #define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
220
221
222
223 /* ADC registers bits positions */
224 #define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */
225 #define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */
226 #define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */
227 #define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */
228 #define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */
229 #define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */
230 #define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */
231 #define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */
232 #define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */
233 #define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */
234 #define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */
235 #define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */
236 #define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */
237 #define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */
238 #define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */
239 #define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */
240 #define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */
241 #define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */
242 #define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */
243 #define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */
244 #define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */
245 #define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */
246
247
248 /* ADC registers bits groups */
249 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \
250 | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with
251 HW property "rs": Software can read as well as set this bit.
252 Writing '0' has no effect on the bit value. */
253
254
255 /* ADC internal channels related definitions */
256 /* Internal voltage reference VrefInt */
257 #define VREFINT_CAL_ADDR ((uint16_t*) (0x0BF907A5UL)) /* Internal voltage reference, address of
258 parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
259 (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
260 #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value
261 with which VrefInt has been calibrated in production
262 (tolerance: +-10 mV) (unit: mV). */
263 /* Temperature sensor */
264 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x0BF90710UL)) /* Address of parameter TS_CAL1: On this series,
265 temperature sensor ADC raw data acquired at temperature 30 DegC
266 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
267 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x0BF90742UL)) /* Address of parameter TS_CAL2: On this series,
268 temperature sensor ADC raw data acquired at temperature 130 DegC
269 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
270 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Temperature at which temperature sensor
271 has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR
272 (tolerance: +-5 DegC) (unit: DegC). */
273 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Temperature at which temperature sensor
274 has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
275 (tolerance: +-5 DegC) (unit: DegC). */
276 #define TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) value
277 with which temperature sensor has been calibrated in production
278 (tolerance: +-10 mV) (unit: mV). */
279
280 /**
281 * @}
282 */
283
284
285 /* Private macros ------------------------------------------------------------*/
286 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
287 * @{
288 */
289
290 /**
291 * @brief Driver macro reserved for internal use: isolate bits with the
292 * selected mask and shift them to the register LSB
293 * (shift mask on register position bit 0).
294 * @param __BITS__ Bits in register 32 bits
295 * @param __MASK__ Mask in register 32 bits
296 * @retval Bits in register 32 bits
297 */
298 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
299 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
300
301 /**
302 * @brief Driver macro reserved for internal use: set a pointer to
303 * a register from a register basis from which an offset
304 * is applied.
305 * @param __REG__ Register basis from which the offset is applied.
306 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
307 * @retval Pointer to register address
308 */
309 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
310 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
311
312 /**
313 * @}
314 */
315
316
317 /* Exported types ------------------------------------------------------------*/
318 #if defined(USE_FULL_LL_DRIVER)
319 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
320 * @{
321 */
322
323 /**
324 * @brief Structure definition of some features of ADC common parameters
325 * and multimode
326 * (all ADC instances belonging to the same ADC common instance).
327 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
328 * is conditioned to ADC instances state (all ADC instances
329 * sharing the same ADC common instance):
330 * All ADC instances sharing the same ADC common instance must be
331 * disabled.
332 */
333 typedef struct
334 {
335 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
336 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
337 This feature can be modified afterwards using unitary function
338 @ref LL_ADC_SetCommonClock(). */
339
340 } LL_ADC_CommonInitTypeDef;
341
342 /**
343 * @brief Structure definition of some features of ADC instance.
344 * @note These parameters have an impact on ADC scope: ADC instance.
345 * Refer to corresponding unitary functions into
346 * @ref ADC_LL_EF_Configuration_ADC_Instance .
347 * @note The setting of these parameters by function @ref LL_ADC_Init()
348 * is conditioned to ADC state:
349 * ADC instance must be disabled.
350 * This condition is applied to all ADC features, for efficiency
351 * and compatibility over all STM32 series. However, the different
352 * features can be set under different ADC state conditions
353 * (setting possible with ADC enabled without conversion on going,
354 * ADC enabled with conversion on going, ...)
355 * Each feature can be updated afterwards with a unitary function
356 * and potentially with ADC in a different state than disabled,
357 * refer to description of each function for setting
358 * conditioned to ADC state.
359 */
360 typedef struct
361 {
362 uint32_t Resolution; /*!< Set ADC resolution.
363 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
364 This feature can be modified afterwards using unitary function
365 @ref LL_ADC_SetResolution(). */
366
367 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
368 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
369 This feature can be modified afterwards using unitary function
370 @ref LL_ADC_SetDataAlignment(). */
371
372
373 } LL_ADC_InitTypeDef;
374
375 /**
376 * @brief Structure definition of some features of ADC group regular.
377 * @note These parameters have an impact on ADC scope: ADC group regular.
378 * Refer to corresponding unitary functions into
379 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
380 * (functions with prefix "REG").
381 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
382 * is conditioned to ADC state:
383 * ADC instance must be disabled.
384 * This condition is applied to all ADC features, for efficiency
385 * and compatibility over all STM32 series. However, the different
386 * features can be set under different ADC state conditions
387 * (setting possible with ADC enabled without conversion on going,
388 * ADC enabled with conversion on going, ...)
389 * Each feature can be updated afterwards with a unitary function
390 * and potentially with ADC in a different state than disabled,
391 * refer to description of each function for setting
392 * conditioned to ADC state.
393 */
394 typedef struct
395 {
396 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or
397 from external peripheral (timer event, external interrupt line).
398 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
399 @note On this STM32 series, setting trigger source to external trigger also
400 set trigger polarity to rising edge(default setting for compatibility
401 with some ADC on other STM32 series having this setting set by HW
402 default value).
403 In case of need to modify trigger edge, use function
404 @ref LL_ADC_REG_SetTriggerEdge().
405 This feature can be modified afterwards using unitary function
406 @ref LL_ADC_REG_SetTriggerSource(). */
407
408 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
409 @note This parameter has an effect only if group regular sequencer is set
410 to mode "fully configurable". Refer to function
411 @ref LL_ADC_REG_SetSequencerConfigurable().
412 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
413 This feature can be modified afterwards using unitary function
414 @ref LL_ADC_REG_SetSequencerLength(). */
415
416 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
417 and scan conversions interrupted every selected number of ranks.
418 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
419 @note This parameter has an effect only if group regular sequencer is
420 enabled (depending on the sequencer mode: scan length of 2 ranks or
421 more, or several ADC channels enabled in group regular sequencer.
422 Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ).
423 This feature can be modified afterwards using unitary function
424 @ref LL_ADC_REG_SetSequencerDiscont(). */
425
426 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
427 conversions are performed in single mode (one conversion per trigger) or in
428 continuous mode (after the first trigger, following conversions launched
429 successively automatically).
430 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
431 Note: It is not possible to enable both ADC group regular continuous mode
432 and discontinuous mode.
433 This feature can be modified afterwards using unitary function
434 @ref LL_ADC_REG_SetContinuousMode(). */
435
436 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
437 by DMA, and DMA requests mode.
438 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
439 This feature can be modified afterwards using unitary function
440 @ref LL_ADC_REG_SetDMATransfer(). */
441
442 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
443 data preserved or overwritten.
444 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
445 This feature can be modified afterwards using unitary function
446 @ref LL_ADC_REG_SetOverrun(). */
447
448 } LL_ADC_REG_InitTypeDef;
449
450 /**
451 * @}
452 */
453 #endif /* USE_FULL_LL_DRIVER */
454
455 /* Exported constants --------------------------------------------------------*/
456 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
457 * @{
458 */
459
460 /** @defgroup ADC_LL_EC_FLAG ADC flags
461 * @brief Flags defines which can be used with LL_ADC_ReadReg function
462 * @{
463 */
464 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
465 #define LL_ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC flag ADC internal voltage regulator ready */
466 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary
467 conversion */
468 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence
469 conversions */
470 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
471 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
472 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
473 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
474 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
475 #define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */
476 /**
477 * @}
478 */
479
480 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
481 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
482 * @{
483 */
484 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
485 #define LL_ADC_IT_LDORDY ADC_IER_LDORDYIE /*!< ADC interruption internal voltage regulator ready */
486 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary
487 conversion */
488 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence
489 conversions */
490 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
491 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling
492 phase */
493 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
494 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
495 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
496 #define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */
497 /**
498 * @}
499 */
500
501 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
502 * @{
503 */
504 /* List of ADC registers intended to be used (most commonly) with */
505 /* DMA transfer. */
506 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
507 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
508 (corresponding to register DR) to be used with ADC configured in independent
509 mode. Without DMA transfer, register accessed by LL function
510 @ref LL_ADC_REG_ReadConversionData32() and other
511 functions @ref LL_ADC_REG_ReadConversionDatax() */
512 /**
513 * @}
514 */
515
516 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
517 * @{
518 */
519 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without
520 prescaler */
521 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
522 prescaler division by 2. Setting common to ADC instances of ADC common
523 group */
524 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
525 prescaler division by 4. Setting common to ADC instances of ADC common
526 group */
527 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
528 prescaler division by 6. Setting common to ADC instances of ADC common
529 group */
530 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with
531 prescaler division by 8. Setting common to ADC instances of ADC common
532 group */
533 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
534 prescaler division by 10. Setting common to ADC instances of ADC common
535 group */
536 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
537 prescaler division by 12. Setting common to ADC instances of ADC common
538 group */
539 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \
540 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
541 prescaler division by 16. Setting common to ADC instances of ADC common
542 group */
543 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with
544 prescaler division by 32. Setting common to ADC instances of ADC common
545 group */
546 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
547 prescaler division by 64. Setting common to ADC instances of ADC common
548 group */
549 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
550 prescaler division by 128. Setting common to ADC instances of ADC common
551 group */
552 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \
553 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
554 prescaler division by 256. Setting common to ADC instances of ADC common
555 group */
556 /**
557 * @}
558 */
559
560 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
561 * @{
562 */
563 /* Note: Other measurement paths to internal channels may be available */
564 /* (connections to other peripherals). */
565 /* If they are not listed below, they do not require any specific */
566 /* path enable. In this case, Access to measurement path is done */
567 /* only by selecting the corresponding ADC internal channel. */
568 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
569 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
570 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel
571 temperature sensor */
572 /**
573 * @}
574 */
575
576 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
577 * @{
578 */
579 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
580 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
581 #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */
582 #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */
583 /**
584 * @}
585 */
586
587 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
588 * @{
589 */
590 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned
591 (alignment on data register LSB bit 0)*/
592 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned
593 (alignment on data register MSB bit 15)*/
594 /**
595 * @}
596 */
597
598 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
599 * @{
600 */
601 #define LL_ADC_LP_AUTOWAIT_DISABLE (0x00000000UL) /*!< ADC low power mode auto delay disabled. */
602 #define LL_ADC_LP_AUTOWAIT_ENABLE (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay enabled: dynamic
603 low power mode, ADC conversions are performed only when necessary
604 (when previous ADC conversion data is read).
605 See description with function @ref LL_ADC_SetLPModeAutoWait(). */
606 /**
607 * @}
608 */
609 /* Definitions for backward compatibility with legacy STM32 series */
610 #define LL_ADC_LP_MODE_NONE LL_ADC_LP_AUTOWAIT_DISABLE
611 #define LL_ADC_LP_AUTOWAIT LL_ADC_LP_AUTOWAIT_ENABLE
612
613
614 /** @defgroup ADC_LL_EC_AUTOPOWEROFF_MODE ADC instance - Low power mode auto power-off
615 * @{
616 */
617 #define LL_ADC_LP_AUTOPOWEROFF_DISABLE (0x00000000UL) /*!< ADC low power mode auto power-off disabled */
618 #define LL_ADC_LP_AUTOPOWEROFF_ENABLE (ADC_PWRR_AUTOFF) /*!< ADC low power mode auto power-off enabled: the ADC
619 automatically powers-off after a ADC conversion and automatically wakes up
620 when a new ADC conversion is triggered (with startup time between trigger
621 and start of sampling). See description with function
622 @ref LL_ADC_SetLPModeAutoPowerOff().
623 It can be combined with mode low power mode auto wait. */
624 /**
625 * @}
626 */
627
628
629 /** @defgroup ADC_LL_EC_AUTONOMOUS_DEEP_POWER_DOWN_MODE ADC instance - Autonomous deep power down mode
630 * @{
631 */
632 #define LL_ADC_LP_AUTONOMOUS_DPD_DISABLE (0x00000000UL) /*!< ADC deep power down in autonomous mode disabled */
633 #define LL_ADC_LP_AUTONOMOUS_DPD_ENABLE (ADC_PWRR_DPD) /*!< ADC deep power down in autonomous mode enabled */
634 /**
635 * @}
636 */
637
638 /** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
639 * @{
640 */
641 #define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency.
642 Note: ADC trigger frequency mode must be set to low frequency when a duration
643 is exceeded before ADC conversion start trigger event (between ADC enable
644 and ADC conversion start trigger event or between two ADC conversion start
645 trigger event).
646 Duration value: Refer to device datasheet, parameter "tIdle". */
647 #define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency.
648 Note: ADC trigger frequency mode must be set to low frequency when a duration
649 is exceeded before ADC conversion start trigger event (between ADC enable
650 and ADC conversion start trigger event or between two ADC conversion start
651 trigger event).
652 Duration value: Refer to device datasheet, parameter "tIdle". */
653 /**
654 * @}
655 */
656
657 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
658 * @{
659 */
660 #define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group
661 of channels: sampling time nb 1 */
662 #define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS \
663 | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group
664 of channels: sampling time nb 2 */
665 /**
666 * @}
667 */
668
669 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
670 * @{
671 */
672 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
673 /**
674 * @}
675 */
676
677 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
678 * @{
679 */
680 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \
681 | ADC_CHANNEL_0_BITFIELD ) /*!< ADC channel ADCx_IN0 */
682 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \
683 | ADC_CHANNEL_1_BITFIELD ) /*!< ADC channel ADCx_IN1 */
684 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \
685 | ADC_CHANNEL_2_BITFIELD ) /*!< ADC channel ADCx_IN2 */
686 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \
687 | ADC_CHANNEL_3_BITFIELD ) /*!< ADC channel ADCx_IN3 */
688 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \
689 | ADC_CHANNEL_4_BITFIELD ) /*!< ADC channel ADCx_IN4 */
690 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \
691 | ADC_CHANNEL_5_BITFIELD ) /*!< ADC channel ADCx_IN5 */
692 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \
693 | ADC_CHANNEL_6_BITFIELD ) /*!< ADC channel ADCx_IN6 */
694 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \
695 | ADC_CHANNEL_7_BITFIELD ) /*!< ADC channel ADCx_IN7 */
696 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \
697 | ADC_CHANNEL_8_BITFIELD ) /*!< ADC channel ADCx_IN8 */
698 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \
699 | ADC_CHANNEL_9_BITFIELD ) /*!< ADC channel ADCx_IN9 */
700 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \
701 | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */
702 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \
703 | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */
704 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \
705 | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */
706 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \
707 | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */
708 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \
709 | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */
710 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \
711 | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */
712 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \
713 | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */
714 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \
715 | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */
716 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
717 connected to VrefInt: Internal voltage reference. */
718 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
719 connected to internal temperature sensor. */
720 #define LL_ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
721 connected to Vcore: internal power supply of MCU digital logic */
722 /**
723 * @}
724 */
725
726 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
727 * @{
728 */
729 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular
730 conversion trigger internal: SW start. */
731 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
732 conversion trigger from external peripheral: TIM1 TRGO.
733 Trigger edge set to rising edge (default setting). */
734 #define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
735 conversion trigger from external peripheral: TIM1 channel 4 event
736 (capture compare: input capture or output capture).
737 Trigger edge set to rising edge (default setting). */
738 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
739 conversion trigger from external peripheral: TIM2 TRGO.
740 Trigger edge set to rising edge (default setting). */
741 #define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \
742 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
743 conversion trigger from external peripheral: LPTIM1 channel 1 event
744 (capture compare: input capture or output capture).
745 Trigger edge set to rising edge (default setting). */
746 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE15 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
747 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
748 conversion trigger from external peripheral: external interrupt line 15.
749 Trigger edge set to rising edge (default setting). */
750 /**
751 * @}
752 */
753
754 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
755 * @{
756 */
757 #define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
758 trigger polarity set to rising edge */
759 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1) /*!< ADC group regular conversion
760 trigger polarity set to falling edge */
761 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
762 trigger polarity set to both rising and falling edges */
763 /**
764 * @}
765 */
766
767 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
768 * @{
769 */
770 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode:
771 one conversion per trigger */
772 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions performed in continuous mode:
773 after the first trigger, following conversions launched successively
774 automatically */
775 /**
776 * @}
777 */
778
779 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
780 * @{
781 */
782 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
783 #define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA,
784 in limited mode (one shot mode): DMA transfer requests are stopped when
785 number of DMA data transfers (number of ADC conversions) is reached.
786 This ADC mode is intended to be used with DMA mode non-circular. */
787 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are
788 transferred by DMA, in unlimited mode: DMA transfer requests are unlimited,
789 whatever number of DMA data transferred (number of ADC conversions).
790 This ADC mode is intended to be used with DMA mode circular. */
791 /**
792 * @}
793 */
794
795 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
796 * @{
797 */
798 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun:
799 data preserved */
800 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun:
801 data overwritten */
802 /**
803 * @}
804 */
805
806 /** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility
807 * @{
808 */
809 #define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable:
810 sequencer length and each rank affectation to a channel are fixed
811 by channel HW number. Refer to description of function
812 @ref LL_ADC_REG_SetSequencerChannels(). */
813 #define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable:
814 sequencer length and each rank affectation to a channel are configurable.
815 Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
816 /**
817 * @}
818 */
819
820 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
821 * @{
822 */
823 #define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable
824 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
825 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable
826 with 2 ranks in the sequence */
827 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable
828 with 3 ranks in the sequence */
829 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable
830 with 4 ranks in the sequence */
831 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable
832 with 5 ranks in the sequence */
833 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable
834 with 6 ranks in the sequence */
835 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable
836 with 7 ranks in the sequence */
837 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable
838 with 8 ranks in the sequence */
839 /**
840 * @}
841 */
842
843 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
844 * @{
845 */
846 #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only if
847 sequencer set to mode not fully configurable, refer to function
848 @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan
849 direction forward: from lowest channel number to highest channel number
850 (scan of all ranks, ADC conversion of ranks with channels enabled in
851 sequencer). On some other STM32 series, this setting is not available
852 and the default scan direction is forward. */
853 #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only if
854 sequencer set to mode not fully configurable, refer to function
855 @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan
856 direction backward: from highest channel number to lowest channel number
857 (scan of all ranks, ADC conversion of ranks with channels enabled in
858 sequencer) */
859 /**
860 * @}
861 */
862
863 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
864 * @{
865 */
866 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer
867 discontinuous mode disable */
868 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer
869 discontinuous mode enable with sequence interruption every rank */
870 /**
871 * @}
872 */
873
874 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
875 * @{
876 */
877 #define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 1 */
878 #define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 2 */
879 #define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 3 */
880 #define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 4 */
881 #define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 5 */
882 #define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 6 */
883 #define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 7 */
884 #define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 8 */
885 /**
886 * @}
887 */
888
889 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
890 * @{
891 */
892 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
893 #define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
894 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
895 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 \
896 | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
897 #define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */
898 #define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 \
899 | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
900 #define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 \
901 | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
902 #define LL_ADC_SAMPLINGTIME_814CYCLES_5 (ADC_SMPR_SMP1_2 \
903 | ADC_SMPR_SMP1_1 \
904 | ADC_SMPR_SMP1_0) /*!< Sampling time 814.5 ADC clock cycles */
905 /**
906 * @}
907 */
908
909 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
910 * @{
911 */
912 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \
913 | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
914 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \
915 | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
916 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \
917 | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
918 /**
919 * @}
920 */
921
922 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
923 * @{
924 */
925 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring
926 disabled */
927 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \
928 | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring
929 of all channels, converted by group regular only */
930 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
931 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
932 of ADC channel ADCx_IN0, converted by group regular only */
933 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
934 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
935 of ADC channel ADCx_IN1, converted by group regular only */
936 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
937 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
938 of ADC channel ADCx_IN2, converted by group regular only */
939 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
940 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
941 of ADC channel ADCx_IN3, converted by group regular only */
942 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
943 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
944 of ADC channel ADCx_IN4, converted by group regular only */
945 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
946 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
947 of ADC channel ADCx_IN5, converted by group regular only */
948 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
949 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
950 of ADC channel ADCx_IN6, converted by group regular only */
951 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
952 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
953 of ADC channel ADCx_IN7, converted by group regular only */
954 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
955 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
956 of ADC channel ADCx_IN8, converted by group regular only */
957 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
958 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
959 of ADC channel ADCx_IN9, converted by group regular only */
960 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
961 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
962 of ADC channel ADCx_IN10, converted by group regular only */
963 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
964 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
965 of ADC channel ADCx_IN11, converted by group regular only */
966 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
967 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
968 of ADC channel ADCx_IN12, converted by group regular only */
969 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
970 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
971 of ADC channel ADCx_IN13, converted by group regular only */
972 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
973 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
974 of ADC channel ADCx_IN14, converted by group regular only */
975 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
976 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
977 of ADC channel ADCx_IN15, converted by group regular only */
978 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
979 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
980 of ADC channel ADCx_IN16, converted by group regular only */
981 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
982 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
983 of ADC channel ADCx_IN17, converted by group regular only */
984 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
985 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
986 of ADC internal channel connected to VrefInt: Internal
987 voltage reference, converted by group regular only */
988 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
989 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
990 of ADC internal channel connected to internal temperature sensor,
991 converted by group regular only */
992 #define LL_ADC_AWD_CH_VCORE_REG ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_MASK) \
993 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
994 of ADC internal channel connected to Vcore,
995 converted by group regular only */
996 /**
997 * @}
998 */
999
1000 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1001 * @{
1002 */
1003 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1) /*!< ADC analog watchdog threshold high */
1004 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */
1005 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 \
1006 | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low
1007 concatenated into the same data */
1008 /**
1009 * @}
1010 */
1011
1012 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1013 * @{
1014 */
1015 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1016 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of
1017 ADC group regular. Literal suffix "continued" is kept for compatibility
1018 with other STM32 devices featuring ADC group injected, in this case other
1019 oversampling scope parameters are available. */
1020 /**
1021 * @}
1022 */
1023
1024 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1025 * @{
1026 */
1027 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode
1028 (all conversions of oversampling ratio are done from 1 trigger) */
1029 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous
1030 mode (each conversion of oversampling ratio needs a trigger) */
1031 /**
1032 * @}
1033 */
1034
1035 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1036 * @{
1037 */
1038 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2
1039 (sum of conversions data computed to result as oversampling conversion data
1040 (before potential shift) */
1041 #define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4
1042 (sum of conversions data computed to result as oversampling conversion data
1043 (before potential shift) */
1044 #define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8
1045 (sum of conversions data computed to result as oversampling conversion data
1046 (before potential shift) */
1047 #define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16
1048 (sum of conversions data computed to result as oversampling conversion data
1049 (before potential shift) */
1050 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32
1051 (sum of conversions data computed to result as oversampling conversion data
1052 (before potential shift) */
1053 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64
1054 (sum of conversions data computed to result as oversampling conversion data
1055 (before potential shift) */
1056 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128
1057 (sum of conversions data computed to result as oversampling conversion data
1058 (before potential shift) */
1059 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \
1060 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256
1061 (sum of conversions data computed to result as oversampling conversion data
1062 (before potential shift) */
1063 /**
1064 * @}
1065 */
1066
1067 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift
1068 * @{
1069 */
1070 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift
1071 (sum of the ADC conversions data is not divided to result as oversampling
1072 conversion data) */
1073 #define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1
1074 (sum of the ADC conversions data (after OVS ratio) is divided by 2
1075 to result as oversampling conversion data) */
1076 #define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2
1077 (sum of the ADC conversions data (after OVS ratio) is divided by 4
1078 to result as oversampling conversion data) */
1079 #define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
1080 (sum of the ADC conversions data (after OVS ratio) is divided by 8
1081 to result as oversampling conversion data) */
1082 #define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4
1083 (sum of the ADC conversions data (after OVS ratio) is divided by 16
1084 to result as oversampling conversion data) */
1085 #define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
1086 (sum of the ADC conversions data (after OVS ratio) is divided by 32
1087 to result as oversampling conversion data) */
1088 #define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
1089 (sum of the ADC conversions data (after OVS ratio) is divided by 64
1090 to result as oversampling conversion data) */
1091 #define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
1092 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7
1093 (sum of the ADC conversions data (after OVS ratio) is divided by 128
1094 to result as oversampling conversion data) */
1095 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8
1096 (sum of the ADC conversions data (after OVS ratio) is divided by 256
1097 to result as oversampling conversion data) */
1098 /**
1099 * @}
1100 */
1101
1102 /** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro
1103 * @{
1104 */
1105 #define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro
1106 @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
1107 calibration parameters. This value is coded on 16 bits
1108 (to fit on signed word or double word) and corresponds
1109 to an inconsistent temperature value. */
1110 /**
1111 * @}
1112 */
1113
1114 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1115 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1116 * not timeout values.
1117 * For details on delays values, refer to descriptions in source code
1118 * above each literal definition.
1119 * @{
1120 */
1121
1122 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1123 /* not timeout values. */
1124 /* Timeout values for ADC operations are dependent to device clock */
1125 /* configuration (system clock versus ADC clock), */
1126 /* and therefore must be defined in user application. */
1127 /* Indications for estimation of ADC timeout delays, for this */
1128 /* STM32 series: */
1129 /* - ADC calibration time: maximum delay is 82/fADC. */
1130 /* (refer to device datasheet, parameter "tCAL") */
1131 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1132 /* (refer to device datasheet, parameter "tSTAB") */
1133 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1134 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1135 /* cycles */
1136 /* - ADC conversion time: duration depending on ADC clock and ADC */
1137 /* configuration. */
1138 /* (refer to device reference manual, section "Timing") */
1139
1140 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1141 /* Delay set to maximum value (refer to device datasheet, */
1142 /* parameter "tADCVREG_STUP"). */
1143 /* Unit: us */
1144 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage
1145 regulator start-up time) */
1146
1147 /* Delay for internal voltage reference stabilization time. */
1148 /* Delay set to maximum value (refer to device datasheet, */
1149 /* parameter "tstart_vrefint"). */
1150 /* Unit: us */
1151 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization
1152 time */
1153
1154 /* Delay for temperature sensor stabilization time. */
1155 /* Literal set to maximum value (refer to device datasheet, */
1156 /* parameter "tSTART"). */
1157 /* Unit: us */
1158 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time
1159 (starting from temperature sensor enable, refer to
1160 @ref LL_ADC_SetCommonPathInternalCh()) */
1161 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization
1162 time (starting from ADC enable, refer to
1163 @ref LL_ADC_Enable()) */
1164
1165 /* Delay required between ADC end of calibration and ADC enable. */
1166 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
1167 /* are required between ADC end of calibration and ADC enable. */
1168 /* Wait time can be computed in user application by waiting for the */
1169 /* equivalent number of CPU cycles, by taking into account */
1170 /* ratio of CPU clock versus ADC clock prescalers. */
1171 /* Unit: ADC clock cycles. */
1172 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL) /*!< Delay required between ADC end of calibration
1173 and ADC enable */
1174
1175 /**
1176 * @}
1177 */
1178
1179 /**
1180 * @}
1181 */
1182
1183
1184 /* Exported macro ------------------------------------------------------------*/
1185 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1186 * @{
1187 */
1188
1189 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1190 * @{
1191 */
1192
1193 /**
1194 * @brief Write a value in ADC register
1195 * @param __INSTANCE__ ADC Instance
1196 * @param __REG__ Register to be written
1197 * @param __VALUE__ Value to be written in the register
1198 * @retval None
1199 */
1200 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1201
1202 /**
1203 * @brief Read a value in ADC register
1204 * @param __INSTANCE__ ADC Instance
1205 * @param __REG__ Register to be read
1206 * @retval Register value
1207 */
1208 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1209 /**
1210 * @}
1211 */
1212
1213 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1214 * @{
1215 */
1216
1217 /**
1218 * @brief Helper macro to get ADC channel number in decimal format
1219 * from literals LL_ADC_CHANNEL_x.
1220 * @note Example:
1221 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1222 * will return decimal number "4".
1223 * @note The input can be a value from functions where a channel
1224 * number is returned, either defined with number
1225 * or with bitfield (only one bit must be set).
1226 * @param __CHANNEL__ This parameter can be one of the following values:
1227 * @arg @ref LL_ADC_CHANNEL_0
1228 * @arg @ref LL_ADC_CHANNEL_1
1229 * @arg @ref LL_ADC_CHANNEL_2
1230 * @arg @ref LL_ADC_CHANNEL_3
1231 * @arg @ref LL_ADC_CHANNEL_4
1232 * @arg @ref LL_ADC_CHANNEL_5
1233 * @arg @ref LL_ADC_CHANNEL_6
1234 * @arg @ref LL_ADC_CHANNEL_7
1235 * @arg @ref LL_ADC_CHANNEL_8
1236 * @arg @ref LL_ADC_CHANNEL_9
1237 * @arg @ref LL_ADC_CHANNEL_10
1238 * @arg @ref LL_ADC_CHANNEL_11
1239 * @arg @ref LL_ADC_CHANNEL_12
1240 * @arg @ref LL_ADC_CHANNEL_13
1241 * @arg @ref LL_ADC_CHANNEL_VREFINT
1242 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1243 * @arg @ref LL_ADC_CHANNEL_VCORE
1244 * @retval Value between Min_Data=0 and Max_Data=18
1245 */
1246 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1247 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
1248 ( \
1249 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1250 ) \
1251 : \
1252 ( \
1253 (uint32_t)POSITION_VAL((__CHANNEL__)) \
1254 ) \
1255 )
1256
1257 /**
1258 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1259 * from number in decimal format.
1260 * @note Example:
1261 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1262 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1263 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1264 * @retval Returned value can be one of the following values:
1265 * @arg @ref LL_ADC_CHANNEL_0
1266 * @arg @ref LL_ADC_CHANNEL_1
1267 * @arg @ref LL_ADC_CHANNEL_2
1268 * @arg @ref LL_ADC_CHANNEL_3
1269 * @arg @ref LL_ADC_CHANNEL_4
1270 * @arg @ref LL_ADC_CHANNEL_5
1271 * @arg @ref LL_ADC_CHANNEL_6
1272 * @arg @ref LL_ADC_CHANNEL_7
1273 * @arg @ref LL_ADC_CHANNEL_8
1274 * @arg @ref LL_ADC_CHANNEL_9
1275 * @arg @ref LL_ADC_CHANNEL_10
1276 * @arg @ref LL_ADC_CHANNEL_11
1277 * @arg @ref LL_ADC_CHANNEL_12
1278 * @arg @ref LL_ADC_CHANNEL_13
1279 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1280 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1281 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
1282 *
1283 * (1) For ADC channel read back from ADC register,
1284 * comparison with internal channel parameter to be done
1285 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1286 */
1287 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1288 (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1289 (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)))
1290
1291 /**
1292 * @brief Helper macro to determine whether the selected channel
1293 * corresponds to literal definitions of driver.
1294 * @note The different literal definitions of ADC channels are:
1295 * - ADC internal channel:
1296 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1297 * - ADC external channel (channel connected to a GPIO pin):
1298 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1299 * @note The channel parameter must be a value defined from literal
1300 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1301 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1302 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1303 * must not be a value from functions where a channel number is
1304 * returned from ADC registers,
1305 * because internal and external channels share the same channel
1306 * number in ADC registers. The differentiation is made only with
1307 * parameters definitions of driver.
1308 * @param __CHANNEL__ This parameter can be one of the following values:
1309 * @arg @ref LL_ADC_CHANNEL_0
1310 * @arg @ref LL_ADC_CHANNEL_1
1311 * @arg @ref LL_ADC_CHANNEL_2
1312 * @arg @ref LL_ADC_CHANNEL_3
1313 * @arg @ref LL_ADC_CHANNEL_4
1314 * @arg @ref LL_ADC_CHANNEL_5
1315 * @arg @ref LL_ADC_CHANNEL_6
1316 * @arg @ref LL_ADC_CHANNEL_7
1317 * @arg @ref LL_ADC_CHANNEL_8
1318 * @arg @ref LL_ADC_CHANNEL_9
1319 * @arg @ref LL_ADC_CHANNEL_10
1320 * @arg @ref LL_ADC_CHANNEL_11
1321 * @arg @ref LL_ADC_CHANNEL_12
1322 * @arg @ref LL_ADC_CHANNEL_13
1323 * @arg @ref LL_ADC_CHANNEL_VREFINT
1324 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1325 * @arg @ref LL_ADC_CHANNEL_VCORE
1326 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
1327 connected to a GPIO pin).
1328 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1329 */
1330 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1331 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1332
1333 /**
1334 * @brief Helper macro to convert a channel defined from parameter
1335 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1336 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1337 * to its equivalent parameter definition of a ADC external channel
1338 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1339 * @note The channel parameter can be, additionally to a value
1340 * defined from parameter definition of a ADC internal channel
1341 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1342 * a value defined from parameter definition of
1343 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1344 * or a value from functions where a channel number is returned
1345 * from ADC registers.
1346 * @param __CHANNEL__ This parameter can be one of the following values:
1347 * @arg @ref LL_ADC_CHANNEL_0
1348 * @arg @ref LL_ADC_CHANNEL_1
1349 * @arg @ref LL_ADC_CHANNEL_2
1350 * @arg @ref LL_ADC_CHANNEL_3
1351 * @arg @ref LL_ADC_CHANNEL_4
1352 * @arg @ref LL_ADC_CHANNEL_5
1353 * @arg @ref LL_ADC_CHANNEL_6
1354 * @arg @ref LL_ADC_CHANNEL_7
1355 * @arg @ref LL_ADC_CHANNEL_8
1356 * @arg @ref LL_ADC_CHANNEL_9
1357 * @arg @ref LL_ADC_CHANNEL_10
1358 * @arg @ref LL_ADC_CHANNEL_11
1359 * @arg @ref LL_ADC_CHANNEL_12
1360 * @arg @ref LL_ADC_CHANNEL_13
1361 * @arg @ref LL_ADC_CHANNEL_VREFINT
1362 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1363 * @arg @ref LL_ADC_CHANNEL_VCORE
1364 * @retval Returned value can be one of the following values:
1365 * @arg @ref LL_ADC_CHANNEL_0
1366 * @arg @ref LL_ADC_CHANNEL_1
1367 * @arg @ref LL_ADC_CHANNEL_2
1368 * @arg @ref LL_ADC_CHANNEL_3
1369 * @arg @ref LL_ADC_CHANNEL_4
1370 * @arg @ref LL_ADC_CHANNEL_5
1371 * @arg @ref LL_ADC_CHANNEL_6
1372 * @arg @ref LL_ADC_CHANNEL_7
1373 * @arg @ref LL_ADC_CHANNEL_8
1374 * @arg @ref LL_ADC_CHANNEL_9
1375 * @arg @ref LL_ADC_CHANNEL_10
1376 * @arg @ref LL_ADC_CHANNEL_11
1377 * @arg @ref LL_ADC_CHANNEL_12
1378 * @arg @ref LL_ADC_CHANNEL_13
1379 */
1380 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1381 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1382
1383 /**
1384 * @brief Helper macro to determine whether the internal channel
1385 * selected is available on the ADC instance selected.
1386 * @note The channel parameter must be a value defined from parameter
1387 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1388 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1389 * must not be a value defined from parameter definition of
1390 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1391 * or a value from functions where a channel number is
1392 * returned from ADC registers,
1393 * because internal and external channels share the same channel
1394 * number in ADC registers. The differentiation is made only with
1395 * parameters definitions of driver.
1396 * @param __ADC_INSTANCE__ ADC instance
1397 * @param __CHANNEL__ This parameter can be one of the following values:
1398 * @arg @ref LL_ADC_CHANNEL_VREFINT
1399 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1400 * @arg @ref LL_ADC_CHANNEL_VCORE
1401 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1402 * Value "1" if the internal channel selected is available on the ADC instance selected.
1403 */
1404 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1405 (((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1406 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1407 ((__CHANNEL__) == LL_ADC_CHANNEL_VCORE))
1408
1409 /**
1410 * @brief Helper macro to define ADC analog watchdog parameter:
1411 * define a single channel to monitor with analog watchdog
1412 * from sequencer channel and groups definition.
1413 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1414 * Example:
1415 * LL_ADC_SetAnalogWDMonitChannels(
1416 * ADC1, LL_ADC_AWD1,
1417 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1418 * @param __CHANNEL__ This parameter can be one of the following values:
1419 * @arg @ref LL_ADC_CHANNEL_0
1420 * @arg @ref LL_ADC_CHANNEL_1
1421 * @arg @ref LL_ADC_CHANNEL_2
1422 * @arg @ref LL_ADC_CHANNEL_3
1423 * @arg @ref LL_ADC_CHANNEL_4
1424 * @arg @ref LL_ADC_CHANNEL_5
1425 * @arg @ref LL_ADC_CHANNEL_6
1426 * @arg @ref LL_ADC_CHANNEL_7
1427 * @arg @ref LL_ADC_CHANNEL_8
1428 * @arg @ref LL_ADC_CHANNEL_9
1429 * @arg @ref LL_ADC_CHANNEL_10
1430 * @arg @ref LL_ADC_CHANNEL_11
1431 * @arg @ref LL_ADC_CHANNEL_12
1432 * @arg @ref LL_ADC_CHANNEL_13
1433 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1434 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1435 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
1436 *
1437 * (1) For ADC channel read back from ADC register,
1438 * comparison with internal channel parameter to be done
1439 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1440 * @param __GROUP__ This parameter can be one of the following values:
1441 * @arg @ref LL_ADC_GROUP_REGULAR
1442 * @retval Returned value can be one of the following values:
1443 * @arg @ref LL_ADC_AWD_DISABLE
1444 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1445 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1446 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1447 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1448 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1449 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1450 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1451 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1452 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1453 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1454 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1455 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1456 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1457 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
1458 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
1459 * @arg @ref LL_ADC_AWD_CH_VCORE_REG
1460 */
1461 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1462 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
1463
1464 /**
1465 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1466 * or low in function of ADC resolution, when ADC resolution is
1467 * different of 12 bits.
1468 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
1469 * or @ref LL_ADC_SetAnalogWDThresholds().
1470 * Example, with a ADC resolution of 8 bits, to set the value of
1471 * analog watchdog threshold high (on 8 bits):
1472 * LL_ADC_SetAnalogWDThresholds
1473 * (< ADCx param >,
1474 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1475 * );
1476 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1477 * @arg @ref LL_ADC_RESOLUTION_12B
1478 * @arg @ref LL_ADC_RESOLUTION_10B
1479 * @arg @ref LL_ADC_RESOLUTION_8B
1480 * @arg @ref LL_ADC_RESOLUTION_6B
1481 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1482 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1483 */
1484 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1485 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_Pos - 1U )))
1486
1487 /**
1488 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1489 * or low in function of ADC resolution, when ADC resolution is
1490 * different of 12 bits.
1491 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1492 * Example, with a ADC resolution of 8 bits, to get the value of
1493 * analog watchdog threshold high (on 8 bits):
1494 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1495 * (LL_ADC_RESOLUTION_8B,
1496 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1497 * );
1498 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1499 * @arg @ref LL_ADC_RESOLUTION_12B
1500 * @arg @ref LL_ADC_RESOLUTION_10B
1501 * @arg @ref LL_ADC_RESOLUTION_8B
1502 * @arg @ref LL_ADC_RESOLUTION_6B
1503 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1504 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1505 */
1506 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1507 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_Pos - 1U )))
1508
1509 /**
1510 * @brief Helper macro to get the ADC analog watchdog threshold high
1511 * or low from raw value containing both thresholds concatenated.
1512 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1513 * Example, to get analog watchdog threshold high from the register raw value:
1514 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
1515 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
1516 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
1517 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
1518 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1519 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1520 */
1521 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
1522 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
1523 & LL_ADC_AWD_THRESHOLD_LOW)
1524
1525 /**
1526 * @brief Helper macro to select the ADC common instance
1527 * to which is belonging the selected ADC instance.
1528 * @note ADC common register instance can be used for:
1529 * - Set parameters common to several ADC instances
1530 * - Multimode (for devices with several ADC instances)
1531 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1532 * @param __ADCx__ ADC instance
1533 * @retval ADC common register instance
1534 */
1535 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1536 (ADC4_COMMON)
1537
1538 /**
1539 * @brief Helper macro to check if all ADC instances sharing the same
1540 * ADC common instance are disabled.
1541 * @note This check is required by functions with setting conditioned to
1542 * ADC state:
1543 * All ADC instances of the ADC common group must be disabled.
1544 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1545 * @note On devices with only 1 ADC common instance, parameter of this macro
1546 * is useless and can be ignored (parameter kept for compatibility
1547 * with devices featuring several ADC common instances).
1548 * @param __ADCXY_COMMON__ ADC common instance
1549 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1550 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1551 * are disabled.
1552 * Value "1" if at least one ADC instance sharing the same ADC common instance
1553 * is enabled.
1554 */
1555 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1556 LL_ADC_IsEnabled(ADC4)
1557
1558 /**
1559 * @brief Helper macro to define the ADC conversion data full-scale digital
1560 * value corresponding to the selected ADC resolution.
1561 * @note ADC conversion data full-scale corresponds to voltage range
1562 * determined by analog voltage references Vref+ and Vref-
1563 * (refer to reference manual).
1564 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1565 * @arg @ref LL_ADC_RESOLUTION_12B
1566 * @arg @ref LL_ADC_RESOLUTION_10B
1567 * @arg @ref LL_ADC_RESOLUTION_8B
1568 * @arg @ref LL_ADC_RESOLUTION_6B
1569 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
1570 */
1571 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1572 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_Pos - 1UL)))
1573
1574 /**
1575 * @brief Helper macro to convert the ADC conversion data from
1576 * a resolution to another resolution.
1577 * @param __DATA__ ADC conversion data to be converted
1578 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
1579 * This parameter can be one of the following values:
1580 * @arg @ref LL_ADC_RESOLUTION_12B
1581 * @arg @ref LL_ADC_RESOLUTION_10B
1582 * @arg @ref LL_ADC_RESOLUTION_8B
1583 * @arg @ref LL_ADC_RESOLUTION_6B
1584 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1585 * This parameter can be one of the following values:
1586 * @arg @ref LL_ADC_RESOLUTION_12B
1587 * @arg @ref LL_ADC_RESOLUTION_10B
1588 * @arg @ref LL_ADC_RESOLUTION_8B
1589 * @arg @ref LL_ADC_RESOLUTION_6B
1590 * @retval ADC conversion data to the requested resolution
1591 */
1592 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
1593 __ADC_RESOLUTION_CURRENT__,\
1594 __ADC_RESOLUTION_TARGET__) \
1595 (((__DATA__) \
1596 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_Pos - 1UL))) \
1597 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_Pos - 1UL)) \
1598 )
1599
1600 /**
1601 * @brief Helper macro to calculate the voltage (unit: mVolt)
1602 * corresponding to a ADC conversion data (unit: digital value).
1603 * @note Analog reference voltage (Vref+) must be either known from
1604 * user board environment or can be calculated using ADC measurement
1605 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1606 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1607 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1608 * (unit: digital value).
1609 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1610 * @arg @ref LL_ADC_RESOLUTION_12B
1611 * @arg @ref LL_ADC_RESOLUTION_10B
1612 * @arg @ref LL_ADC_RESOLUTION_8B
1613 * @arg @ref LL_ADC_RESOLUTION_6B
1614 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1615 */
1616 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1617 __ADC_DATA__,\
1618 __ADC_RESOLUTION__) \
1619 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1620 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1621 )
1622
1623 /**
1624 * @brief Helper macro to calculate analog reference voltage (Vref+)
1625 * (unit: mVolt) from ADC conversion data of internal voltage
1626 * reference VrefInt.
1627 * @note Computation is using VrefInt calibration value
1628 * stored in system memory for each device during production.
1629 * @note This voltage depends on user board environment: voltage level
1630 * connected to pin Vref+.
1631 * On devices with small package, the pin Vref+ is not present
1632 * and internally bonded to pin Vdda.
1633 * @note On this STM32 series, calibration data of internal voltage reference
1634 * VrefInt corresponds to a resolution of 12 bits,
1635 * this is the recommended ADC resolution to convert voltage of
1636 * internal voltage reference VrefInt.
1637 * Otherwise, this macro performs the processing to scale
1638 * ADC conversion data to 12 bits.
1639 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1640 * of internal voltage reference VrefInt (unit: digital value).
1641 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1642 * @arg @ref LL_ADC_RESOLUTION_12B
1643 * @arg @ref LL_ADC_RESOLUTION_10B
1644 * @arg @ref LL_ADC_RESOLUTION_8B
1645 * @arg @ref LL_ADC_RESOLUTION_6B
1646 * @retval Analog reference voltage (unit: mV)
1647 */
1648 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1649 __ADC_RESOLUTION__) \
1650 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1651 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1652 (__ADC_RESOLUTION__), \
1653 LL_ADC_RESOLUTION_12B) \
1654 )
1655
1656 /**
1657 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1658 * from ADC conversion data of internal temperature sensor.
1659 * @note Computation is using temperature sensor calibration values
1660 * stored in system memory for each device during production.
1661 * @note Calculation formula:
1662 * Temperature = ((TS_ADC_DATA - TS_CAL1)
1663 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1664 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1665 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1666 * Avg_Slope = (TS_CAL2 - TS_CAL1)
1667 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1668 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
1669 * TEMP_DEGC_CAL1 (calibrated in factory)
1670 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
1671 * TEMP_DEGC_CAL2 (calibrated in factory)
1672 * Caution: Calculation relevancy under reserve that calibration
1673 * parameters are correct (address and data).
1674 * To calculate temperature using temperature sensor
1675 * datasheet typical values (generic values less, therefore
1676 * less accurate than calibrated values),
1677 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
1678 * @note As calculation input, the analog reference voltage (Vref+) must be
1679 * defined as it impacts the ADC LSB equivalent voltage.
1680 * @note Analog reference voltage (Vref+) must be either known from
1681 * user board environment or can be calculated using ADC measurement
1682 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1683 * @note On this STM32 series, calibration data of temperature sensor
1684 * corresponds to a resolution of 12 bits,
1685 * this is the recommended ADC resolution to convert voltage of
1686 * temperature sensor.
1687 * Otherwise, this macro performs the processing to scale
1688 * ADC conversion data to 12 bits.
1689 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1690 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
1691 * temperature sensor (unit: digital value).
1692 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
1693 * sensor voltage has been measured.
1694 * This parameter can be one of the following values:
1695 * @arg @ref LL_ADC_RESOLUTION_12B
1696 * @arg @ref LL_ADC_RESOLUTION_10B
1697 * @arg @ref LL_ADC_RESOLUTION_8B
1698 * @arg @ref LL_ADC_RESOLUTION_6B
1699 * @retval Temperature (unit: degree Celsius)
1700 * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value)
1701 */
1702 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1703 __TEMPSENSOR_ADC_DATA__,\
1704 __ADC_RESOLUTION__)\
1705 ((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \
1706 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
1707 (__ADC_RESOLUTION__), \
1708 LL_ADC_RESOLUTION_12B) \
1709 * (__VREFANALOG_VOLTAGE__)) \
1710 / TEMPSENSOR_CAL_VREFANALOG) \
1711 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
1712 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
1713 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
1714 ) + TEMPSENSOR_CAL1_TEMP \
1715 ) \
1716 : \
1717 ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \
1718 )
1719
1720 /**
1721 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1722 * from ADC conversion data of internal temperature sensor.
1723 * @note Computation is using temperature sensor typical values
1724 * (refer to device datasheet).
1725 * @note Calculation formula:
1726 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1727 * / Avg_Slope + CALx_TEMP
1728 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1729 * (unit: digital value)
1730 * Avg_Slope = temperature sensor slope
1731 * (unit: uV/Degree Celsius)
1732 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1733 * temperature CALx_TEMP (unit: mV)
1734 * Caution: Calculation relevancy under reserve the temperature sensor
1735 * of the current device has characteristics in line with
1736 * datasheet typical values.
1737 * If temperature sensor calibration values are available on
1738 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1739 * temperature calculation will be more accurate using
1740 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1741 * @note As calculation input, the analog reference voltage (Vref+) must be
1742 * defined as it impacts the ADC LSB equivalent voltage.
1743 * @note Analog reference voltage (Vref+) must be either known from
1744 * user board environment or can be calculated using ADC measurement
1745 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1746 * @note ADC measurement data must correspond to a resolution of 12 bits
1747 * (full scale digital value 4095). If not the case, the data must be
1748 * preliminarily rescaled to an equivalent resolution of 12 bits.
1749 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
1750 (unit: uV/DegCelsius).
1751 * On this STM32 series, refer to device datasheet parameter "Avg_Slope".
1752 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
1753 (at temperature and Vref+ defined in parameters below) (unit: mV).
1754 * On this STM32 series, refer to datasheet parameter "V30" (corresponding
1755 * to TS_CAL1).
1756 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
1757 (see parameter above) is corresponding (unit: mV)
1758 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV)
1759 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
1760 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1761 * This parameter can be one of the following values:
1762 * @arg @ref LL_ADC_RESOLUTION_12B
1763 * @arg @ref LL_ADC_RESOLUTION_10B
1764 * @arg @ref LL_ADC_RESOLUTION_8B
1765 * @arg @ref LL_ADC_RESOLUTION_6B
1766 * @retval Temperature (unit: degree Celsius)
1767 */
1768 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1769 __TEMPSENSOR_TYP_CALX_V__,\
1770 __TEMPSENSOR_CALX_TEMP__,\
1771 __VREFANALOG_VOLTAGE__,\
1772 __TEMPSENSOR_ADC_DATA__,\
1773 __ADC_RESOLUTION__) \
1774 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1775 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1776 * 1000UL) \
1777 - \
1778 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1779 * 1000UL) \
1780 ) \
1781 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
1782 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
1783 )
1784
1785 /**
1786 * @}
1787 */
1788
1789 /**
1790 * @}
1791 */
1792
1793
1794 /* Exported functions --------------------------------------------------------*/
1795 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1796 * @{
1797 */
1798
1799 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1800 * @{
1801 */
1802 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1803 /* configuration of ADC instance, groups and multimode (if available): */
1804 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1805
1806 /**
1807 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1808 * ADC register address from ADC instance and a list of ADC registers
1809 * intended to be used (most commonly) with DMA transfer.
1810 * @note These ADC registers are data registers:
1811 * when ADC conversion data is available in ADC data registers,
1812 * ADC generates a DMA transfer request.
1813 * @note This macro is intended to be used with LL DMA driver, refer to
1814 * function "LL_DMA_ConfigAddresses()".
1815 * Example:
1816 * LL_DMA_ConfigAddresses(DMA1,
1817 * LL_DMA_CHANNEL_1,
1818 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1819 * (uint32_t)&< array or variable >,
1820 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1821 * @note For devices with several ADC: in multimode, some devices
1822 * use a different data register outside of ADC instance scope
1823 * (common data register). This macro manages this register difference,
1824 * only ADC instance has to be set as parameter.
1825 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
1826 * @param ADCx ADC instance
1827 * @param Register This parameter can be one of the following values:
1828 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1829 * @retval ADC register address
1830 */
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)1831 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
1832 {
1833 /* Prevent unused argument(s) compilation warning */
1834 (void)(Register);
1835
1836 /* Retrieve address of register DR */
1837 return (uint32_t) &(ADCx->DR);
1838 }
1839
1840 /**
1841 * @}
1842 */
1843
1844 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
1845 * ADC instances
1846 * @{
1847 */
1848
1849 /**
1850 * @brief Set parameter common to several ADC: Clock source and prescaler.
1851 * @note On this STM32 series, setting of this feature is conditioned to
1852 * ADC state:
1853 * All ADC instances of the ADC common group must be disabled.
1854 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1855 * ADC instance or by using helper macro helper macro
1856 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1857 * @rmtoll CCR PRESC LL_ADC_SetCommonClock
1858 * @param ADCxy_COMMON ADC common instance
1859 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1860 * @param CommonClock This parameter can be one of the following values:
1861 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
1862 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
1863 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
1864 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
1865 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
1866 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
1867 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
1868 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
1869 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
1870 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
1871 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
1872 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
1873 * @retval None
1874 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)1875 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
1876 {
1877 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
1878 }
1879
1880 /**
1881 * @brief Get parameter common to several ADC: Clock source and prescaler.
1882 * @rmtoll CCR PRESC LL_ADC_GetCommonClock
1883 * @param ADCxy_COMMON ADC common instance
1884 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1885 * @retval Returned value can be one of the following values:
1886 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
1887 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
1888 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
1889 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
1890 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
1891 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
1892 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
1893 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
1894 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
1895 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
1896 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
1897 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
1898 */
LL_ADC_GetCommonClock(const ADC_Common_TypeDef * ADCxy_COMMON)1899 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
1900 {
1901 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
1902 }
1903
1904 /**
1905 * @brief Set parameter common to several ADC: measurement path to
1906 * internal channels (VrefInt, temperature sensor, ...).
1907 * Configure all paths (overwrite current configuration).
1908 * @note One or several values can be selected.
1909 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1910 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1911 * The values not selected are removed from configuration.
1912 * @note Stabilization time of measurement path to internal channel:
1913 * After enabling internal paths, before starting ADC conversion,
1914 * a delay is required for internal voltage reference and
1915 * temperature sensor stabilization time.
1916 * Refer to device datasheet.
1917 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1918 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
1919 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
1920 * @note ADC internal channel sampling time constraint:
1921 * For ADC conversion of internal channels,
1922 * a sampling time minimum value is required.
1923 * Refer to device datasheet.
1924 * @note On this STM32 series, setting of this feature is conditioned to
1925 * ADC state:
1926 * All ADC instances of the ADC common group must be disabled.
1927 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1928 * ADC instance or by using helper macro helper macro
1929 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1930 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
1931 * CCR TSEN LL_ADC_SetCommonPathInternalCh
1932 * @param ADCxy_COMMON ADC common instance
1933 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1934 * @param PathInternal This parameter can be a combination of the following values:
1935 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1936 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1937 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1938 * @retval None
1939 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1940 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1941 {
1942 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
1943 }
1944
1945 /**
1946 * @brief Set parameter common to several ADC: measurement path to
1947 * internal channels (VrefInt, temperature sensor, ...).
1948 * Add paths to the current configuration.
1949 * @note One or several values can be selected.
1950 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1951 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1952 * @note Stabilization time of measurement path to internal channel:
1953 * After enabling internal paths, before starting ADC conversion,
1954 * a delay is required for internal voltage reference and
1955 * temperature sensor stabilization time.
1956 * Refer to device datasheet.
1957 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1958 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
1959 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
1960 * @note ADC internal channel sampling time constraint:
1961 * For ADC conversion of internal channels,
1962 * a sampling time minimum value is required.
1963 * Refer to device datasheet.
1964 * @note On this STM32 series, setting of this feature is conditioned to
1965 * ADC state:
1966 * All ADC instances of the ADC common group must be disabled.
1967 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1968 * ADC instance or by using helper macro helper macro
1969 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1970 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
1971 * CCR TSEN LL_ADC_SetCommonPathInternalCh
1972 * @param ADCxy_COMMON ADC common instance
1973 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1974 * @param PathInternal This parameter can be a combination of the following values:
1975 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1976 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1977 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1978 * @retval None
1979 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1980 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1981 {
1982 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
1983 }
1984
1985 /**
1986 * @brief Set parameter common to several ADC: measurement path to
1987 * internal channels (VrefInt, temperature sensor, ...).
1988 * Remove paths to the current configuration.
1989 * @note One or several values can be selected.
1990 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1991 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1992 * @note On this STM32 series, setting of this feature is conditioned to
1993 * ADC state:
1994 * All ADC instances of the ADC common group must be disabled.
1995 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1996 * ADC instance or by using helper macro helper macro
1997 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1998 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
1999 * CCR TSEN LL_ADC_SetCommonPathInternalChRem
2000 * @param ADCxy_COMMON ADC common instance
2001 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2002 * @param PathInternal This parameter can be a combination of the following values:
2003 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2004 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2005 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2006 * @retval None
2007 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2008 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2009 {
2010 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
2011 }
2012
2013 /**
2014 * @brief Get parameter common to several ADC: measurement path to internal
2015 * channels (VrefInt, temperature sensor, ...).
2016 * @note One or several values can be selected.
2017 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2018 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2019 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2020 * CCR TSEN LL_ADC_GetCommonPathInternalCh
2021 * @param ADCxy_COMMON ADC common instance
2022 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2023 * @retval Returned value can be a combination of the following values:
2024 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2025 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2026 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2027 */
LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef * ADCxy_COMMON)2028 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
2029 {
2030 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
2031 }
2032
2033 /**
2034 * @}
2035 */
2036
2037 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2038 * @{
2039 */
2040
2041 /**
2042 * @brief Set ADC calibration factor in the mode single-ended
2043 * or differential (for devices with differential mode available).
2044 * @note This function is intended to set calibration parameters
2045 * without having to perform a new calibration using
2046 * @ref LL_ADC_StartCalibration().
2047 * @note On this STM32 series, setting of this feature is conditioned to
2048 * ADC state:
2049 * ADC must be enabled, without calibration on going, without conversion
2050 * on going on group regular.
2051 * @rmtoll CALFACT CALFACT LL_ADC_SetCalibrationFactor
2052 * @param ADCx ADC instance
2053 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2054 * @retval None
2055 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t CalibrationFactor)2056 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
2057 {
2058 MODIFY_REG(ADCx->CALFACT,
2059 ADC_CALFACT_CALFACT,
2060 CalibrationFactor);
2061 }
2062
2063 /**
2064 * @brief Get ADC calibration factor in the mode single-ended
2065 * or differential (for devices with differential mode available).
2066 * @note Calibration factors are set by hardware after performing
2067 * a calibration run using function @ref LL_ADC_StartCalibration().
2068 * @rmtoll CALFACT CALFACT LL_ADC_GetCalibrationFactor
2069 * @param ADCx ADC instance
2070 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2071 */
LL_ADC_GetCalibrationFactor(const ADC_TypeDef * ADCx)2072 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx)
2073 {
2074 return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
2075 }
2076
2077 /**
2078 * @brief Set ADC resolution.
2079 * Refer to reference manual for alignments formats
2080 * dependencies to ADC resolutions.
2081 * @note On this STM32 series, setting of this feature is conditioned to
2082 * ADC state:
2083 * ADC must be disabled or enabled without conversion on going
2084 * on group regular.
2085 * @rmtoll CFGR1 RES LL_ADC_SetResolution
2086 * @param ADCx ADC instance
2087 * @param Resolution This parameter can be one of the following values:
2088 * @arg @ref LL_ADC_RESOLUTION_12B
2089 * @arg @ref LL_ADC_RESOLUTION_10B
2090 * @arg @ref LL_ADC_RESOLUTION_8B
2091 * @arg @ref LL_ADC_RESOLUTION_6B
2092 * @retval None
2093 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2094 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2095 {
2096 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
2097 }
2098
2099 /**
2100 * @brief Get ADC resolution.
2101 * Refer to reference manual for alignments formats
2102 * dependencies to ADC resolutions.
2103 * @rmtoll CFGR1 RES LL_ADC_GetResolution
2104 * @param ADCx ADC instance
2105 * @retval Returned value can be one of the following values:
2106 * @arg @ref LL_ADC_RESOLUTION_12B
2107 * @arg @ref LL_ADC_RESOLUTION_10B
2108 * @arg @ref LL_ADC_RESOLUTION_8B
2109 * @arg @ref LL_ADC_RESOLUTION_6B
2110 */
LL_ADC_GetResolution(const ADC_TypeDef * ADCx)2111 __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
2112 {
2113 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
2114 }
2115
2116 /**
2117 * @brief Set ADC conversion data alignment.
2118 * @note Refer to reference manual for alignments formats
2119 * dependencies to ADC resolutions.
2120 * @note On this STM32 series, setting of this feature is conditioned to
2121 * ADC state:
2122 * ADC must be disabled or enabled without conversion on going
2123 * on group regular.
2124 * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
2125 * @param ADCx ADC instance
2126 * @param DataAlignment This parameter can be one of the following values:
2127 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2128 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2129 * @retval None
2130 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)2131 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2132 {
2133 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
2134 }
2135
2136 /**
2137 * @brief Get ADC conversion data alignment.
2138 * @note Refer to reference manual for alignments formats
2139 * dependencies to ADC resolutions.
2140 * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
2141 * @param ADCx ADC instance
2142 * @retval Returned value can be one of the following values:
2143 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2144 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2145 */
LL_ADC_GetDataAlignment(const ADC_TypeDef * ADCx)2146 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
2147 {
2148 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
2149 }
2150
2151 /**
2152 * @brief Set ADC low power mode.
2153 * @note Description of ADC low power modes:
2154 * - ADC low power mode "auto wait": Dynamic low power mode,
2155 * ADC conversions occurrences are limited to the minimum necessary
2156 * in order to reduce power consumption.
2157 * New ADC conversion starts only when the previous
2158 * unitary conversion data (for ADC group regular)
2159 * has been retrieved by user software.
2160 * In the meantime, ADC remains idle: does not performs any
2161 * other conversion.
2162 * This mode allows to automatically adapt the ADC conversions
2163 * triggers to the speed of the software that reads the data.
2164 * Moreover, this avoids risk of overrun for low frequency
2165 * applications.
2166 * How to use this low power mode:
2167 * - It is not recommended to use with interruption or DMA
2168 * since these modes have to clear immediately the EOC flag
2169 * (by CPU to free the IRQ pending event or by DMA).
2170 * Auto wait will work but fort a very short time, discarding
2171 * its intended benefit (except specific case of high load of CPU
2172 * or DMA transfers which can justify usage of auto wait).
2173 * - Do use with polling: 1. Start conversion,
2174 * 2. Later on, when conversion data is needed: poll for end of
2175 * conversion to ensure that conversion is completed and
2176 * retrieve ADC conversion data. This will trig another
2177 * ADC conversion start.
2178 * @note With ADC low power mode "auto wait", the ADC conversion data read
2179 * is corresponding to previous ADC conversion start, independently
2180 * of delay during which ADC was idle.
2181 * Therefore, the ADC conversion data may be outdated: does not
2182 * correspond to the current voltage level on the selected
2183 * ADC channel.
2184 * @note On this STM32 series, setting of this feature is conditioned to
2185 * ADC state:
2186 * ADC must be disabled or enabled without conversion on going
2187 * on group regular.
2188 * @rmtoll CFGR WAIT LL_ADC_SetLPModeAutoWait
2189 * @param ADCx ADC instance
2190 * @param LowPowerMode This parameter can be one of the following values:
2191 * @arg @ref LL_ADC_LP_AUTOWAIT_DISABLE
2192 * @arg @ref LL_ADC_LP_AUTOWAIT_ENABLE
2193 * @retval None
2194 */
LL_ADC_SetLPModeAutoWait(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2195 __STATIC_INLINE void LL_ADC_SetLPModeAutoWait(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2196 {
2197 MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT), LowPowerMode);
2198 }
2199
2200 /**
2201 * @brief Get ADC low power mode:
2202 * @note Description of ADC low power modes:
2203 * - ADC low power mode "auto wait": Dynamic low power mode,
2204 * ADC conversions occurrences are limited to the minimum necessary
2205 * in order to reduce power consumption.
2206 * New ADC conversion starts only when the previous
2207 * unitary conversion data (for ADC group regular)
2208 * has been retrieved by user software.
2209 * In the meantime, ADC remains idle: does not performs any
2210 * other conversion.
2211 * This mode allows to automatically adapt the ADC conversions
2212 * triggers to the speed of the software that reads the data.
2213 * Moreover, this avoids risk of overrun for low frequency
2214 * applications.
2215 * How to use this low power mode:
2216 * - It is not recommended to use with interruption or DMA
2217 * since these modes have to clear immediately the EOC flag
2218 * (by CPU to free the IRQ pending event or by DMA).
2219 * Auto wait will work but fort a very short time, discarding
2220 * its intended benefit (except specific case of high load of CPU
2221 * or DMA transfers which can justify usage of auto wait).
2222 * - Do use with polling: 1. Start conversion,
2223 * 2. Later on, when conversion data is needed: poll for end of
2224 * conversion to ensure that conversion is completed and
2225 * retrieve ADC conversion data. This will trig another
2226 * ADC conversion start.
2227 * @note With ADC low power mode "auto wait", the ADC conversion data read
2228 * is corresponding to previous ADC conversion start, independently
2229 * of delay during which ADC was idle.
2230 * Therefore, the ADC conversion data may be outdated: does not
2231 * correspond to the current voltage level on the selected
2232 * ADC channel.
2233 * @rmtoll CFGR WAIT LL_ADC_GetLPModeAutoWait
2234 * @param ADCx ADC instance
2235 * @retval Returned value can be one of the following values:
2236 * @arg @ref LL_ADC_LP_AUTOWAIT_DISABLE
2237 * @arg @ref LL_ADC_LP_AUTOWAIT_ENABLE
2238 */
LL_ADC_GetLPModeAutoWait(const ADC_TypeDef * ADCx)2239 __STATIC_INLINE uint32_t LL_ADC_GetLPModeAutoWait(const ADC_TypeDef *ADCx)
2240 {
2241 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_WAIT));
2242 }
2243
2244 /* Definitions for backward compatibility with legacy STM32 series */
2245 #define LL_ADC_SetLowPowerMode LL_ADC_SetLPModeAutoWait /* Redefinition for legacy purpose */
2246 #define LL_ADC_GetLowPowerMode LL_ADC_GetLPModeAutoWait /* Redefinition for legacy purpose */
2247
2248 /**
2249 * @brief Set ADC low power mode: auto power off.
2250 * @note Description of ADC low power mode:
2251 * - ADC low power mode "auto power-off":
2252 * the ADC automatically powers-off after a conversion and
2253 * automatically wakes up when a new conversion is triggered
2254 * (with startup time between trigger and start of sampling).
2255 * This feature can be combined with low power mode "auto wait".
2256 * @note On this STM32 series, setting of this feature is conditioned to
2257 * ADC state:
2258 * ADC must be disabled.
2259 * @rmtoll PWRR AUTOFF LL_ADC_SetLPModeAutoPowerOff
2260 * @param ADCx ADC instance
2261 * @param LowPowerMode This parameter can be one of the following values:
2262 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_DISABLE
2263 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_ENABLE
2264 * @retval None
2265 */
LL_ADC_SetLPModeAutoPowerOff(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2266 __STATIC_INLINE void LL_ADC_SetLPModeAutoPowerOff(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2267 {
2268 MODIFY_REG(ADCx->PWRR, ADC_PWRR_AUTOFF, LowPowerMode);
2269 }
2270
2271 /**
2272 * @brief Get ADC low power mode: auto power off.
2273 * @note Description of ADC low power mode:
2274 * - ADC low power mode "auto power-off":
2275 * the ADC automatically powers-off after a conversion and
2276 * automatically wakes up when a new conversion is triggered
2277 * (with startup time between trigger and start of sampling).
2278 * This feature can be combined with low power mode "auto wait".
2279 * @rmtoll PWRR AUTOFF LL_ADC_GetLPModeAutoPowerOff
2280 * @param ADCx ADC instance
2281 * @retval Returned value can be one of the following values:
2282 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_DISABLE
2283 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_ENABLE
2284 */
LL_ADC_GetLPModeAutoPowerOff(const ADC_TypeDef * ADCx)2285 __STATIC_INLINE uint32_t LL_ADC_GetLPModeAutoPowerOff(const ADC_TypeDef *ADCx)
2286 {
2287 return (uint32_t)(READ_BIT(ADCx->PWRR, ADC_PWRR_AUTOFF));
2288 }
2289
2290 /**
2291 * @brief Set ADC low power mode: deep power down in autonomous mode
2292 * @note On this STM32 series, setting of this feature is conditioned to
2293 * ADC state:
2294 * ADC must be disabled.
2295 * @rmtoll PWRR DPD LL_ADC_SetLPModeAutonomousDPD
2296 * @param ADCx ADC instance
2297 * @param LowPowerMode This parameter can be one of the following values:
2298 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_DISABLE
2299 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_ENABLE
2300 * @retval None
2301 */
LL_ADC_SetLPModeAutonomousDPD(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2302 __STATIC_INLINE void LL_ADC_SetLPModeAutonomousDPD(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2303 {
2304 MODIFY_REG(ADCx->PWRR, ADC_PWRR_DPD, LowPowerMode);
2305 }
2306
2307 /**
2308 * @brief Get ADC low power mode: deep power down in autonomous mode
2309 * @rmtoll PWRR DPD LL_ADC_GetLPModeAutonomousDPD
2310 * @param ADCx ADC instance
2311 * @retval Returned value can be one of the following values:
2312 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_DISABLE
2313 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_ENABLE
2314 */
LL_ADC_GetLPModeAutonomousDPD(const ADC_TypeDef * ADCx)2315 __STATIC_INLINE uint32_t LL_ADC_GetLPModeAutonomousDPD(const ADC_TypeDef *ADCx)
2316 {
2317 return (uint32_t)(READ_BIT(ADCx->PWRR, ADC_PWRR_DPD));
2318 }
2319
2320
2321 /**
2322 * @brief Set ADC trigger frequency mode.
2323 * @note ADC trigger frequency mode must be set to low frequency when
2324 * a duration is exceeded before ADC conversion start trigger event
2325 * (between ADC enable and ADC conversion start trigger event
2326 * or between two ADC conversion start trigger event).
2327 * Duration value: Refer to device datasheet, parameter "tIdle".
2328 * @note When ADC trigger frequency mode is set to low frequency,
2329 * some rearm cycles are inserted before performing ADC conversion
2330 * start, inducing a delay of 2 ADC clock cycles.
2331 * @note Usage of ADC trigger frequency mode with ADC low power mode:
2332 * - Low power mode auto wait: Only the first ADC conversion
2333 * start trigger inserts the rearm delay.
2334 * @note On this STM32 series, setting of this feature is conditioned to
2335 * ADC state:
2336 * ADC must be disabled.
2337 * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode
2338 * @param ADCx ADC instance
2339 * @param TriggerFrequencyMode This parameter can be one of the following values:
2340 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
2341 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
2342 * @retval None
2343 */
LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef * ADCx,uint32_t TriggerFrequencyMode)2344 __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
2345 {
2346 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode);
2347 }
2348
2349 /**
2350 * @brief Get ADC trigger frequency mode.
2351 * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode
2352 * @param ADCx ADC instance
2353 * @retval Returned value can be one of the following values:
2354 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
2355 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
2356 */
LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef * ADCx)2357 __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx)
2358 {
2359 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG));
2360 }
2361
2362 /**
2363 * @brief Set sampling time common to a group of channels.
2364 * @note Unit: ADC clock cycles.
2365 * @note On this STM32 series, sampling time scope is on ADC instance:
2366 * Sampling time common to all channels.
2367 * (on some other STM32 series, sampling time is channel wise)
2368 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
2369 * converted:
2370 * sampling time constraints must be respected (sampling time can be
2371 * adjusted in function of ADC clock frequency and sampling time
2372 * setting).
2373 * Refer to device datasheet for timings values (parameters TS_vrefint,
2374 * TS_temp, ...).
2375 * @note Conversion time is the addition of sampling time and processing time.
2376 * On this STM32 series, ADC processing time is:
2377 * - 12.5 ADC clock cycles at ADC resolution 12 bits
2378 * - 10.5 ADC clock cycles at ADC resolution 10 bits
2379 * - 8.5 ADC clock cycles at ADC resolution 8 bits
2380 * - 6.5 ADC clock cycles at ADC resolution 6 bits
2381 * @note In case of ADC conversion of internal channel (VrefInt,
2382 * temperature sensor, ...), a sampling time minimum value
2383 * is required.
2384 * Refer to device datasheet.
2385 * @note On this STM32 series, setting of this feature is conditioned to
2386 * ADC state:
2387 * ADC must be disabled or enabled without conversion on going
2388 * on group regular.
2389 * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n
2390 * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels
2391 * @param ADCx ADC instance
2392 * @param SamplingTimeY This parameter can be one of the following values:
2393 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
2394 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
2395 * @param SamplingTime This parameter can be one of the following values:
2396 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2397 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2398 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2399 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2400 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2401 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2402 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2403 * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES_5
2404 * @retval None
2405 */
LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTimeY,uint32_t SamplingTime)2406 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY,
2407 uint32_t SamplingTime)
2408 {
2409 MODIFY_REG(ADCx->SMPR,
2410 ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK),
2411 SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
2412 }
2413
2414 /**
2415 * @brief Get sampling time common to a group of channels.
2416 * @note Unit: ADC clock cycles.
2417 * @note On this STM32 series, sampling time scope is on ADC instance:
2418 * Sampling time common to all channels.
2419 * (on some other STM32 series, sampling time is channel wise)
2420 * @note Conversion time is the addition of sampling time and processing time.
2421 * Refer to reference manual for ADC processing time of
2422 * this STM32 series.
2423 * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n
2424 * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels
2425 * @param ADCx ADC instance
2426 * @param SamplingTimeY This parameter can be one of the following values:
2427 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
2428 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
2429 * @retval Returned value can be one of the following values:
2430 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2431 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2432 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2433 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2434 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2435 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2436 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2437 * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES_5
2438 */
LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef * ADCx,uint32_t SamplingTimeY)2439 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
2440 {
2441 return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
2442 >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
2443 }
2444
2445 /**
2446 * @}
2447 */
2448
2449 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2450 * @{
2451 */
2452
2453 /**
2454 * @brief Set ADC group regular conversion trigger source:
2455 * internal (SW start) or from external peripheral (timer event,
2456 * external interrupt line).
2457 * @note On this STM32 series, setting trigger source to external trigger
2458 * also set trigger polarity to rising edge
2459 * (default setting for compatibility with some ADC on other
2460 * STM32 series having this setting set by HW default value).
2461 * In case of need to modify trigger edge, use
2462 * function @ref LL_ADC_REG_SetTriggerEdge().
2463 * @note On this STM32 series, ADC trigger frequency mode must be set
2464 * in function of frequency of ADC group regular conversion trigger.
2465 * Refer to description of function
2466 * @ref LL_ADC_SetTriggerFrequencyMode().
2467 * @note Availability of parameters of trigger sources from timer
2468 * depends on timers availability on the selected device.
2469 * @note On this STM32 series, setting of this feature is conditioned to
2470 * ADC state:
2471 * ADC must be disabled or enabled without conversion on going
2472 * on group regular.
2473 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n
2474 * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource
2475 * @param ADCx ADC instance
2476 * @param TriggerSource This parameter can be one of the following values:
2477 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2478 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2479 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
2480 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2481 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
2482 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE15
2483 * @retval None
2484 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2485 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2486 {
2487 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
2488 }
2489
2490 /**
2491 * @brief Get ADC group regular conversion trigger source:
2492 * internal (SW start) or from external peripheral (timer event,
2493 * external interrupt line).
2494 * @note To determine whether group regular trigger source is
2495 * internal (SW start) or external, without detail
2496 * of which peripheral is selected as external trigger,
2497 * (equivalent to
2498 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2499 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2500 * @note Availability of parameters of trigger sources from timer
2501 * depends on timers availability on the selected device.
2502 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n
2503 * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource
2504 * @param ADCx ADC instance
2505 * @retval Returned value can be one of the following values:
2506 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2507 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2508 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
2509 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2510 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
2511 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE15
2512 */
LL_ADC_REG_GetTriggerSource(const ADC_TypeDef * ADCx)2513 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
2514 {
2515 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
2516
2517 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2518 /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
2519 uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
2520
2521 /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
2522 /* to match with triggers literals definition. */
2523 return ((trigger_source
2524 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL)
2525 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
2526 );
2527 }
2528
2529 /**
2530 * @brief Get ADC group regular conversion trigger source internal (SW start)
2531 * or external.
2532 * @note In case of group regular trigger source set to external trigger,
2533 * to determine which peripheral is selected as external trigger,
2534 * use function @ref LL_ADC_REG_GetTriggerSource().
2535 * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2536 * @param ADCx ADC instance
2537 * @retval Value "0" if trigger source external trigger
2538 * Value "1" if trigger source SW start.
2539 */
LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)2540 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
2541 {
2542 return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
2543 }
2544
2545 /**
2546 * @brief Set ADC group regular conversion trigger polarity.
2547 * @note Applicable only for trigger source set to external trigger.
2548 * @note On this STM32 series, setting of this feature is conditioned to
2549 * ADC state:
2550 * ADC must be disabled or enabled without conversion on going
2551 * on group regular.
2552 * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge
2553 * @param ADCx ADC instance
2554 * @param ExternalTriggerEdge This parameter can be one of the following values:
2555 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2556 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2557 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2558 * @retval None
2559 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)2560 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
2561 {
2562 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
2563 }
2564
2565 /**
2566 * @brief Get ADC group regular conversion trigger polarity.
2567 * @note Applicable only for trigger source set to external trigger.
2568 * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge
2569 * @param ADCx ADC instance
2570 * @retval Returned value can be one of the following values:
2571 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2572 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2573 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2574 */
LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef * ADCx)2575 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
2576 {
2577 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
2578 }
2579
2580 /**
2581 * @brief Set ADC group regular sequencer configuration flexibility.
2582 * @note On this STM32 series, ADC group regular sequencer both modes
2583 * "fully configurable" or "not fully configurable" are
2584 * available:
2585 * - sequencer configured to fully configurable:
2586 * sequencer length and each rank
2587 * affectation to a channel are configurable.
2588 * Refer to description of function
2589 * @ref LL_ADC_REG_SetSequencerLength().
2590 * - sequencer configured to not fully configurable:
2591 * sequencer length and each rank affectation to a channel
2592 * are fixed by channel HW number.
2593 * Refer to description of function
2594 * @ref LL_ADC_REG_SetSequencerChannels().
2595 * @note On this STM32 series, setting of this feature is conditioned to
2596 * ADC state:
2597 * ADC must be disabled or enabled without conversion on going
2598 * on group regular.
2599 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
2600 * @param ADCx ADC instance
2601 * @param Configurability This parameter can be one of the following values:
2602 * @arg @ref LL_ADC_REG_SEQ_FIXED
2603 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
2604 * @retval None
2605 */
LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef * ADCx,uint32_t Configurability)2606 __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)
2607 {
2608 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability);
2609 }
2610
2611 /**
2612 * @brief Get ADC group regular sequencer configuration flexibility.
2613 * @note On this STM32 series, ADC group regular sequencer both modes
2614 * "fully configurable" or "not fully configurable" are
2615 * available:
2616 * - sequencer configured to fully configurable:
2617 * sequencer length and each rank
2618 * affectation to a channel are configurable.
2619 * Refer to description of function
2620 * @ref LL_ADC_REG_SetSequencerLength().
2621 * - sequencer configured to not fully configurable:
2622 * sequencer length and each rank affectation to a channel
2623 * are fixed by channel HW number.
2624 * Refer to description of function
2625 * @ref LL_ADC_REG_SetSequencerChannels().
2626 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
2627 * @param ADCx ADC instance
2628 * @retval Returned value can be one of the following values:
2629 * @arg @ref LL_ADC_REG_SEQ_FIXED
2630 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
2631 */
LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef * ADCx)2632 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef *ADCx)
2633 {
2634 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD));
2635 }
2636
2637 /**
2638 * @brief Set ADC group regular sequencer length and scan direction.
2639 * @note Description of ADC group regular sequencer features:
2640 * - For devices with sequencer fully configurable
2641 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2642 * sequencer length and each rank affectation to a channel
2643 * are configurable.
2644 * This function performs configuration of:
2645 * - Sequence length: Number of ranks in the scan sequence.
2646 * - Sequence direction: Unless specified in parameters, sequencer
2647 * scan direction is forward (from rank 1 to rank n).
2648 * Sequencer ranks are selected using
2649 * function "LL_ADC_REG_SetSequencerRanks()".
2650 * - For devices with sequencer not fully configurable
2651 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2652 * sequencer length and each rank affectation to a channel
2653 * are defined by channel number.
2654 * This function performs configuration of:
2655 * - Sequence length: Number of ranks in the scan sequence is
2656 * defined by number of channels set in the sequence,
2657 * rank of each channel is fixed by channel HW number.
2658 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2659 * - Sequence direction: Unless specified in parameters, sequencer
2660 * scan direction is forward (from lowest channel number to
2661 * highest channel number).
2662 * Sequencer ranks are selected using
2663 * function "LL_ADC_REG_SetSequencerChannels()".
2664 * To set scan direction differently, refer to function
2665 * @ref LL_ADC_REG_SetSequencerScanDirection().
2666 * @note On this STM32 series, ADC group regular sequencer both modes
2667 * "fully configurable" or "not fully configurable"
2668 * are available, they can be chosen using
2669 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2670 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2671 * ADC conversion on only 1 channel.
2672 * @note On this STM32 series, setting of this feature is conditioned to
2673 * ADC state:
2674 * ADC must be disabled or enabled without conversion on going
2675 * on group regular.
2676 * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerLength\n
2677 * CHSELR SQ2 LL_ADC_REG_SetSequencerLength\n
2678 * CHSELR SQ3 LL_ADC_REG_SetSequencerLength\n
2679 * CHSELR SQ4 LL_ADC_REG_SetSequencerLength\n
2680 * CHSELR SQ5 LL_ADC_REG_SetSequencerLength\n
2681 * CHSELR SQ6 LL_ADC_REG_SetSequencerLength\n
2682 * CHSELR SQ7 LL_ADC_REG_SetSequencerLength\n
2683 * CHSELR SQ8 LL_ADC_REG_SetSequencerLength
2684 * @param ADCx ADC instance
2685 * @param SequencerNbRanks This parameter can be one of the following values:
2686 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2687 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2688 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2689 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2690 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2691 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2692 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2693 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2694 * @retval None
2695 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2696 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2697 {
2698 SET_BIT(ADCx->CHSELR, SequencerNbRanks);
2699 }
2700
2701 /**
2702 * @brief Get ADC group regular sequencer length and scan direction.
2703 * @note Description of ADC group regular sequencer features:
2704 * - For devices with sequencer fully configurable
2705 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2706 * sequencer length and each rank affectation to a channel
2707 * are configurable.
2708 * This function retrieves:
2709 * - Sequence length: Number of ranks in the scan sequence.
2710 * - Sequence direction: Unless specified in parameters, sequencer
2711 * scan direction is forward (from rank 1 to rank n).
2712 * Sequencer ranks are selected using
2713 * function "LL_ADC_REG_SetSequencerRanks()".
2714 * - For devices with sequencer not fully configurable
2715 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2716 * sequencer length and each rank affectation to a channel
2717 * are defined by channel number.
2718 * This function retrieves:
2719 * - Sequence length: Number of ranks in the scan sequence is
2720 * defined by number of channels set in the sequence,
2721 * rank of each channel is fixed by channel HW number.
2722 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2723 * - Sequence direction: Unless specified in parameters, sequencer
2724 * scan direction is forward (from lowest channel number to
2725 * highest channel number).
2726 * Sequencer ranks are selected using
2727 * function "LL_ADC_REG_SetSequencerChannels()".
2728 * To set scan direction differently, refer to function
2729 * @ref LL_ADC_REG_SetSequencerScanDirection().
2730 * @note On this STM32 series, ADC group regular sequencer both modes
2731 * "fully configurable" or "not fully configurable"
2732 * are available, they can be chosen using
2733 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2734 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2735 * ADC conversion on only 1 channel.
2736 * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerLength\n
2737 * CHSELR SQ2 LL_ADC_REG_GetSequencerLength\n
2738 * CHSELR SQ3 LL_ADC_REG_GetSequencerLength\n
2739 * CHSELR SQ4 LL_ADC_REG_GetSequencerLength\n
2740 * CHSELR SQ5 LL_ADC_REG_GetSequencerLength\n
2741 * CHSELR SQ6 LL_ADC_REG_GetSequencerLength\n
2742 * CHSELR SQ7 LL_ADC_REG_GetSequencerLength\n
2743 * CHSELR SQ8 LL_ADC_REG_GetSequencerLength
2744 * @param ADCx ADC instance
2745 * @retval Returned value can be one of the following values:
2746 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2747 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2748 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2749 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2750 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2751 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2752 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2753 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2754 */
LL_ADC_REG_GetSequencerLength(const ADC_TypeDef * ADCx)2755 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
2756 {
2757 __IO uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
2758 uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
2759 uint32_t rank_index;
2760 uint32_t rank_shifted;
2761
2762 /* Parse register for end of sequence identifier */
2763 /* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank
2764 (ADC_CHSELR_SQ2), value "4" to length of end of sequence
2765 identifier (0xF) */
2766 for (rank_index = 0U; rank_index <= (28U - 4U); rank_index += 4U)
2767 {
2768 rank_shifted = (uint32_t)(0xF0UL << rank_index);
2769 if ((channels_ranks & rank_shifted) == rank_shifted)
2770 {
2771 sequencer_length = rank_shifted;
2772 break;
2773 }
2774 }
2775
2776 return sequencer_length;
2777 }
2778
2779 /**
2780 * @brief Set ADC group regular sequencer scan direction.
2781 * @note On this STM32 series, parameter relevant only is sequencer is set
2782 * to mode not fully configurable,
2783 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
2784 * @note On some other STM32 series, this setting is not available and
2785 * the default scan direction is forward.
2786 * @note On this STM32 series, setting of this feature is conditioned to
2787 * ADC state:
2788 * ADC must be disabled or enabled without conversion on going
2789 * on group regular.
2790 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
2791 * @param ADCx ADC instance
2792 * @param ScanDirection This parameter can be one of the following values:
2793 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
2794 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
2795 * @retval None
2796 */
LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef * ADCx,uint32_t ScanDirection)2797 __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
2798 {
2799 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
2800 }
2801
2802 /**
2803 * @brief Get ADC group regular sequencer scan direction.
2804 * @note On this STM32 series, parameter relevant only is sequencer is set
2805 * to mode not fully configurable,
2806 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
2807 * @note On some other STM32 series, this setting is not available and
2808 * the default scan direction is forward.
2809 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
2810 * @param ADCx ADC instance
2811 * @retval Returned value can be one of the following values:
2812 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
2813 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
2814 */
LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef * ADCx)2815 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef *ADCx)
2816 {
2817 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
2818 }
2819
2820 /**
2821 * @brief Set ADC group regular sequencer discontinuous mode:
2822 * sequence subdivided and scan conversions interrupted every selected
2823 * number of ranks.
2824 * @note It is not possible to enable both ADC group regular
2825 * continuous mode and sequencer discontinuous mode.
2826 * @note On this STM32 series, setting of this feature is conditioned to
2827 * ADC state:
2828 * ADC must be disabled or enabled without conversion on going
2829 * on group regular.
2830 * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2831 * @param ADCx ADC instance
2832 * @param SeqDiscont This parameter can be one of the following values:
2833 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2834 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2835 * @retval None
2836 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2837 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2838 {
2839 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
2840 }
2841
2842 /**
2843 * @brief Get ADC group regular sequencer discontinuous mode:
2844 * sequence subdivided and scan conversions interrupted every selected
2845 * number of ranks.
2846 * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2847 * @param ADCx ADC instance
2848 * @retval Returned value can be one of the following values:
2849 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2850 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2851 */
LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef * ADCx)2852 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
2853 {
2854 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
2855 }
2856
2857 /**
2858 * @brief Set ADC group regular sequence: channel on the selected
2859 * scan sequence rank.
2860 * @note This function performs configuration of:
2861 * - Channels ordering into each rank of scan sequence:
2862 * whatever channel can be placed into whatever rank.
2863 * @note On this STM32 series, ADC group regular sequencer is
2864 * fully configurable: sequencer length and each rank
2865 * affectation to a channel are configurable.
2866 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2867 * @note Depending on devices and packages, some channels may not be available.
2868 * Refer to device datasheet for channels availability.
2869 * @note On this STM32 series, to measure internal channels (VrefInt,
2870 * TempSensor, ...), measurement paths to internal channels must be
2871 * enabled separately.
2872 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2873 * @note On this STM32 series, setting of this feature is conditioned to
2874 * ADC state:
2875 * ADC must be disabled or enabled without conversion on going
2876 * on group regular.
2877 * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerRanks\n
2878 * CHSELR SQ2 LL_ADC_REG_SetSequencerRanks\n
2879 * CHSELR SQ3 LL_ADC_REG_SetSequencerRanks\n
2880 * CHSELR SQ4 LL_ADC_REG_SetSequencerRanks\n
2881 * CHSELR SQ5 LL_ADC_REG_SetSequencerRanks\n
2882 * CHSELR SQ6 LL_ADC_REG_SetSequencerRanks\n
2883 * CHSELR SQ7 LL_ADC_REG_SetSequencerRanks\n
2884 * CHSELR SQ8 LL_ADC_REG_SetSequencerRanks
2885 * @param ADCx ADC instance
2886 * @param Rank This parameter can be one of the following values:
2887 * @arg @ref LL_ADC_REG_RANK_1
2888 * @arg @ref LL_ADC_REG_RANK_2
2889 * @arg @ref LL_ADC_REG_RANK_3
2890 * @arg @ref LL_ADC_REG_RANK_4
2891 * @arg @ref LL_ADC_REG_RANK_5
2892 * @arg @ref LL_ADC_REG_RANK_6
2893 * @arg @ref LL_ADC_REG_RANK_7
2894 * @arg @ref LL_ADC_REG_RANK_8
2895 * @param Channel This parameter can be one of the following values:
2896 * @arg @ref LL_ADC_CHANNEL_0
2897 * @arg @ref LL_ADC_CHANNEL_1
2898 * @arg @ref LL_ADC_CHANNEL_2
2899 * @arg @ref LL_ADC_CHANNEL_3
2900 * @arg @ref LL_ADC_CHANNEL_4
2901 * @arg @ref LL_ADC_CHANNEL_5
2902 * @arg @ref LL_ADC_CHANNEL_6
2903 * @arg @ref LL_ADC_CHANNEL_7
2904 * @arg @ref LL_ADC_CHANNEL_8
2905 * @arg @ref LL_ADC_CHANNEL_9
2906 * @arg @ref LL_ADC_CHANNEL_10
2907 * @arg @ref LL_ADC_CHANNEL_11
2908 * @arg @ref LL_ADC_CHANNEL_12
2909 * @arg @ref LL_ADC_CHANNEL_13
2910 * @arg @ref LL_ADC_CHANNEL_VREFINT
2911 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2912 * @arg @ref LL_ADC_CHANNEL_VCORE
2913 * @retval None
2914 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)2915 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2916 {
2917 /* Set bits with content of parameter "Channel" with bits position */
2918 /* in register depending on parameter "Rank". */
2919 /* Parameters "Rank" and "Channel" are used with masks because containing */
2920 /* other bits reserved for other purpose. */
2921 MODIFY_REG(ADCx->CHSELR,
2922 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2923 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
2924 << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2925 }
2926
2927 /**
2928 * @brief Get ADC group regular sequence: channel on the selected
2929 * scan sequence rank.
2930 * @note On this STM32 series, ADC group regular sequencer is
2931 * fully configurable: sequencer length and each rank
2932 * affectation to a channel are configurable.
2933 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2934 * @note Depending on devices and packages, some channels may not be available.
2935 * Refer to device datasheet for channels availability.
2936 * @note Usage of the returned channel number:
2937 * - To reinject this channel into another function LL_ADC_xxx:
2938 * the returned channel number is only partly formatted on definition
2939 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2940 * with parts of literals LL_ADC_CHANNEL_x or using
2941 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2942 * Then the selected literal LL_ADC_CHANNEL_x can be used
2943 * as parameter for another function.
2944 * - To get the channel number in decimal format:
2945 * process the returned value with the helper macro
2946 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2947 * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerRanks\n
2948 * CHSELR SQ2 LL_ADC_REG_GetSequencerRanks\n
2949 * CHSELR SQ3 LL_ADC_REG_GetSequencerRanks\n
2950 * CHSELR SQ4 LL_ADC_REG_GetSequencerRanks\n
2951 * CHSELR SQ5 LL_ADC_REG_GetSequencerRanks\n
2952 * CHSELR SQ6 LL_ADC_REG_GetSequencerRanks\n
2953 * CHSELR SQ7 LL_ADC_REG_GetSequencerRanks\n
2954 * CHSELR SQ8 LL_ADC_REG_GetSequencerRanks
2955 * @param ADCx ADC instance
2956 * @param Rank This parameter can be one of the following values:
2957 * @arg @ref LL_ADC_REG_RANK_1
2958 * @arg @ref LL_ADC_REG_RANK_2
2959 * @arg @ref LL_ADC_REG_RANK_3
2960 * @arg @ref LL_ADC_REG_RANK_4
2961 * @arg @ref LL_ADC_REG_RANK_5
2962 * @arg @ref LL_ADC_REG_RANK_6
2963 * @arg @ref LL_ADC_REG_RANK_7
2964 * @arg @ref LL_ADC_REG_RANK_8
2965 * @retval Returned value can be one of the following values:
2966 * @arg @ref LL_ADC_CHANNEL_0
2967 * @arg @ref LL_ADC_CHANNEL_1
2968 * @arg @ref LL_ADC_CHANNEL_2
2969 * @arg @ref LL_ADC_CHANNEL_3
2970 * @arg @ref LL_ADC_CHANNEL_4
2971 * @arg @ref LL_ADC_CHANNEL_5
2972 * @arg @ref LL_ADC_CHANNEL_6
2973 * @arg @ref LL_ADC_CHANNEL_7
2974 * @arg @ref LL_ADC_CHANNEL_8
2975 * @arg @ref LL_ADC_CHANNEL_9
2976 * @arg @ref LL_ADC_CHANNEL_10
2977 * @arg @ref LL_ADC_CHANNEL_11
2978 * @arg @ref LL_ADC_CHANNEL_12
2979 * @arg @ref LL_ADC_CHANNEL_13
2980 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2981 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2982 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
2983 *
2984 * (1) For ADC channel read back from ADC register,
2985 * comparison with internal channel parameter to be done
2986 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2987 */
LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)2988 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
2989 {
2990 return (uint32_t)((READ_BIT(ADCx->CHSELR,
2991 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
2992 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
2993 ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
2994 );
2995 }
2996
2997 /**
2998 * @brief Set ADC group regular sequence: channel on rank corresponding to
2999 * channel number.
3000 * @note This function performs:
3001 * - Channels ordering into each rank of scan sequence:
3002 * rank of each channel is fixed by channel HW number
3003 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3004 * - Set channels selected by overwriting the current sequencer
3005 * configuration.
3006 * @note On this STM32 series, ADC group regular sequencer both modes
3007 * "fully configurable" or "not fully configurable"
3008 * are available, they can be chosen using
3009 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3010 * This function can be used with setting "not fully configurable".
3011 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3012 * and @ref LL_ADC_REG_SetSequencerLength().
3013 * @note Depending on devices and packages, some channels may not be available.
3014 * Refer to device datasheet for channels availability.
3015 * @note On this STM32 series, to measure internal channels (VrefInt,
3016 * TempSensor, ...), measurement paths to internal channels must be
3017 * enabled separately.
3018 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3019 * @note On this STM32 series, setting of this feature is conditioned to
3020 * ADC state:
3021 * ADC must be disabled or enabled without conversion on going
3022 * on group regular.
3023 * @note One or several values can be selected.
3024 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3025 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
3026 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
3027 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
3028 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
3029 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
3030 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
3031 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
3032 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
3033 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
3034 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
3035 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
3036 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
3037 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
3038 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
3039 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
3040 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
3041 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
3042 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
3043 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
3044 * @param ADCx ADC instance
3045 * @param Channel This parameter can be a combination of the following values:
3046 * @arg @ref LL_ADC_CHANNEL_0
3047 * @arg @ref LL_ADC_CHANNEL_1
3048 * @arg @ref LL_ADC_CHANNEL_2
3049 * @arg @ref LL_ADC_CHANNEL_3
3050 * @arg @ref LL_ADC_CHANNEL_4
3051 * @arg @ref LL_ADC_CHANNEL_5
3052 * @arg @ref LL_ADC_CHANNEL_6
3053 * @arg @ref LL_ADC_CHANNEL_7
3054 * @arg @ref LL_ADC_CHANNEL_8
3055 * @arg @ref LL_ADC_CHANNEL_9
3056 * @arg @ref LL_ADC_CHANNEL_10
3057 * @arg @ref LL_ADC_CHANNEL_11
3058 * @arg @ref LL_ADC_CHANNEL_12
3059 * @arg @ref LL_ADC_CHANNEL_13
3060 * @arg @ref LL_ADC_CHANNEL_VREFINT
3061 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3062 * @arg @ref LL_ADC_CHANNEL_VCORE
3063 * @retval None
3064 */
LL_ADC_REG_SetSequencerChannels(ADC_TypeDef * ADCx,uint32_t Channel)3065 __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
3066 {
3067 /* Parameter "Channel" is used with masks because containing */
3068 /* other bits reserved for other purpose. */
3069 WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3070 }
3071
3072 /**
3073 * @brief Add channel to ADC group regular sequence: channel on rank corresponding to
3074 * channel number.
3075 * @note This function performs:
3076 * - Channels ordering into each rank of scan sequence:
3077 * rank of each channel is fixed by channel HW number
3078 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3079 * - Set channels selected by adding them to the current sequencer
3080 * configuration.
3081 * @note On this STM32 series, ADC group regular sequencer both modes
3082 * "fully configurable" or "not fully configurable"
3083 * are available, they can be chosen using
3084 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3085 * This function can be used with setting "not fully configurable".
3086 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3087 * and @ref LL_ADC_REG_SetSequencerLength().
3088 * @note Depending on devices and packages, some channels may not be available.
3089 * Refer to device datasheet for channels availability.
3090 * @note On this STM32 series, to measure internal channels (VrefInt,
3091 * TempSensor, ...), measurement paths to internal channels must be
3092 * enabled separately.
3093 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3094 * @note On this STM32 series, setting of this feature is conditioned to
3095 * ADC state:
3096 * ADC must be disabled or enabled without conversion on going
3097 * on group regular.
3098 * @note One or several values can be selected.
3099 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3100 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
3101 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
3102 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
3103 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
3104 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
3105 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
3106 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
3107 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
3108 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
3109 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
3110 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
3111 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
3112 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
3113 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
3114 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
3115 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
3116 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
3117 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
3118 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
3119 * @param ADCx ADC instance
3120 * @param Channel This parameter can be a combination of the following values:
3121 * @arg @ref LL_ADC_CHANNEL_0
3122 * @arg @ref LL_ADC_CHANNEL_1
3123 * @arg @ref LL_ADC_CHANNEL_2
3124 * @arg @ref LL_ADC_CHANNEL_3
3125 * @arg @ref LL_ADC_CHANNEL_4
3126 * @arg @ref LL_ADC_CHANNEL_5
3127 * @arg @ref LL_ADC_CHANNEL_6
3128 * @arg @ref LL_ADC_CHANNEL_7
3129 * @arg @ref LL_ADC_CHANNEL_8
3130 * @arg @ref LL_ADC_CHANNEL_9
3131 * @arg @ref LL_ADC_CHANNEL_10
3132 * @arg @ref LL_ADC_CHANNEL_11
3133 * @arg @ref LL_ADC_CHANNEL_12
3134 * @arg @ref LL_ADC_CHANNEL_13
3135 * @arg @ref LL_ADC_CHANNEL_VREFINT
3136 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3137 * @arg @ref LL_ADC_CHANNEL_VCORE
3138 * @retval None
3139 */
LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef * ADCx,uint32_t Channel)3140 __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
3141 {
3142 /* Parameter "Channel" is used with masks because containing */
3143 /* other bits reserved for other purpose. */
3144 SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3145 }
3146
3147 /**
3148 * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
3149 * channel number.
3150 * @note This function performs:
3151 * - Channels ordering into each rank of scan sequence:
3152 * rank of each channel is fixed by channel HW number
3153 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3154 * - Set channels selected by removing them to the current sequencer
3155 * configuration.
3156 * @note On this STM32 series, ADC group regular sequencer both modes
3157 * "fully configurable" or "not fully configurable"
3158 * are available, they can be chosen using
3159 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3160 * This function can be used with setting "not fully configurable".
3161 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3162 * and @ref LL_ADC_REG_SetSequencerLength().
3163 * @note Depending on devices and packages, some channels may not be available.
3164 * Refer to device datasheet for channels availability.
3165 * @note On this STM32 series, to measure internal channels (VrefInt,
3166 * TempSensor, ...), measurement paths to internal channels must be
3167 * enabled separately.
3168 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3169 * @note On this STM32 series, setting of this feature is conditioned to
3170 * ADC state:
3171 * ADC must be disabled or enabled without conversion on going
3172 * on group regular.
3173 * @note One or several values can be selected.
3174 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3175 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
3176 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
3177 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
3178 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
3179 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
3180 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
3181 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
3182 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
3183 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
3184 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
3185 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
3186 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
3187 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
3188 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
3189 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
3190 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
3191 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
3192 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
3193 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
3194 * @param ADCx ADC instance
3195 * @param Channel This parameter can be a combination of the following values:
3196 * @arg @ref LL_ADC_CHANNEL_0
3197 * @arg @ref LL_ADC_CHANNEL_1
3198 * @arg @ref LL_ADC_CHANNEL_2
3199 * @arg @ref LL_ADC_CHANNEL_3
3200 * @arg @ref LL_ADC_CHANNEL_4
3201 * @arg @ref LL_ADC_CHANNEL_5
3202 * @arg @ref LL_ADC_CHANNEL_6
3203 * @arg @ref LL_ADC_CHANNEL_7
3204 * @arg @ref LL_ADC_CHANNEL_8
3205 * @arg @ref LL_ADC_CHANNEL_9
3206 * @arg @ref LL_ADC_CHANNEL_10
3207 * @arg @ref LL_ADC_CHANNEL_11
3208 * @arg @ref LL_ADC_CHANNEL_12
3209 * @arg @ref LL_ADC_CHANNEL_13
3210 * @arg @ref LL_ADC_CHANNEL_VREFINT
3211 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3212 * @arg @ref LL_ADC_CHANNEL_VCORE
3213 * @retval None
3214 */
LL_ADC_REG_SetSequencerChRem(ADC_TypeDef * ADCx,uint32_t Channel)3215 __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
3216 {
3217 /* Parameter "Channel" is used with masks because containing */
3218 /* other bits reserved for other purpose. */
3219 CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3220 }
3221
3222 /**
3223 * @brief Get ADC group regular sequence: channel on rank corresponding to
3224 * channel number.
3225 * @note This function performs:
3226 * - Channels order reading into each rank of scan sequence:
3227 * rank of each channel is fixed by channel HW number
3228 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3229 * @note On this STM32 series, ADC group regular sequencer both modes
3230 * "fully configurable" or "not fully configurable"
3231 * are available, they can be chosen using
3232 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3233 * This function can be used with setting "not fully configurable".
3234 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3235 * and @ref LL_ADC_REG_SetSequencerLength().
3236 * @note Depending on devices and packages, some channels may not be available.
3237 * Refer to device datasheet for channels availability.
3238 * @note On this STM32 series, to measure internal channels (VrefInt,
3239 * TempSensor, ...), measurement paths to internal channels must be
3240 * enabled separately.
3241 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3242 * @note On this STM32 series, setting of this feature is conditioned to
3243 * ADC state:
3244 * ADC must be disabled or enabled without conversion on going
3245 * on group regular.
3246 * @note One or several values can be retrieved.
3247 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3248 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
3249 * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
3250 * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
3251 * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
3252 * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
3253 * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
3254 * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
3255 * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
3256 * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
3257 * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
3258 * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
3259 * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
3260 * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
3261 * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
3262 * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
3263 * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
3264 * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
3265 * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
3266 * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
3267 * @param ADCx ADC instance
3268 * @retval Returned value can be a combination of the following values:
3269 * @arg @ref LL_ADC_CHANNEL_0
3270 * @arg @ref LL_ADC_CHANNEL_1
3271 * @arg @ref LL_ADC_CHANNEL_2
3272 * @arg @ref LL_ADC_CHANNEL_3
3273 * @arg @ref LL_ADC_CHANNEL_4
3274 * @arg @ref LL_ADC_CHANNEL_5
3275 * @arg @ref LL_ADC_CHANNEL_6
3276 * @arg @ref LL_ADC_CHANNEL_7
3277 * @arg @ref LL_ADC_CHANNEL_8
3278 * @arg @ref LL_ADC_CHANNEL_9
3279 * @arg @ref LL_ADC_CHANNEL_10
3280 * @arg @ref LL_ADC_CHANNEL_11
3281 * @arg @ref LL_ADC_CHANNEL_12
3282 * @arg @ref LL_ADC_CHANNEL_13
3283 * @arg @ref LL_ADC_CHANNEL_VREFINT
3284 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3285 * @arg @ref LL_ADC_CHANNEL_VCORE
3286 */
LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef * ADCx)3287 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx)
3288 {
3289 uint32_t channels_bitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
3290
3291 return ((((channels_bitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
3292 | (((channels_bitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
3293 | (((channels_bitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
3294 | (((channels_bitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
3295 | (((channels_bitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
3296 | (((channels_bitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
3297 | (((channels_bitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
3298 | (((channels_bitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
3299 | (((channels_bitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
3300 | (((channels_bitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
3301 | (((channels_bitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
3302 | (((channels_bitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
3303 );
3304 }
3305
3306 /**
3307 * @brief Set ADC continuous conversion mode on ADC group regular.
3308 * @note Description of ADC continuous conversion mode:
3309 * - single mode: one conversion per trigger
3310 * - continuous mode: after the first trigger, following
3311 * conversions launched successively automatically.
3312 * @note It is not possible to enable both ADC group regular
3313 * continuous mode and sequencer discontinuous mode.
3314 * @note On this STM32 series, setting of this feature is conditioned to
3315 * ADC state:
3316 * ADC must be disabled or enabled without conversion on going
3317 * on group regular.
3318 * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode
3319 * @param ADCx ADC instance
3320 * @param Continuous This parameter can be one of the following values:
3321 * @arg @ref LL_ADC_REG_CONV_SINGLE
3322 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3323 * @retval None
3324 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)3325 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
3326 {
3327 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
3328 }
3329
3330 /**
3331 * @brief Get ADC continuous conversion mode on ADC group regular.
3332 * @note Description of ADC continuous conversion mode:
3333 * - single mode: one conversion per trigger
3334 * - continuous mode: after the first trigger, following
3335 * conversions launched successively automatically.
3336 * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode
3337 * @param ADCx ADC instance
3338 * @retval Returned value can be one of the following values:
3339 * @arg @ref LL_ADC_REG_CONV_SINGLE
3340 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3341 */
LL_ADC_REG_GetContinuousMode(const ADC_TypeDef * ADCx)3342 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
3343 {
3344 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
3345 }
3346
3347 /**
3348 * @brief Set ADC group regular conversion data transfer: no transfer or
3349 * transfer by DMA, and DMA requests mode.
3350 * @note If transfer by DMA selected, specifies the DMA requests
3351 * mode:
3352 * - Limited mode (One shot mode): DMA transfer requests are stopped
3353 * when number of DMA data transfers (number of
3354 * ADC conversions) is reached.
3355 * This ADC mode is intended to be used with DMA mode non-circular.
3356 * - Unlimited mode: DMA transfer requests are unlimited,
3357 * whatever number of DMA data transfers (number of
3358 * ADC conversions).
3359 * This ADC mode is intended to be used with DMA mode circular.
3360 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3361 * mode non-circular:
3362 * when DMA transfers size will be reached, DMA will stop transfers of
3363 * ADC conversions data ADC will raise an overrun error
3364 * (overrun flag and interruption if enabled).
3365 * @note To configure DMA source address (peripheral address),
3366 * use function @ref LL_ADC_DMA_GetRegAddr().
3367 * @note On this STM32 series, setting of this feature is conditioned to
3368 * ADC state:
3369 * ADC must be disabled or enabled without conversion on going
3370 * on group regular.
3371 * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n
3372 * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
3373 * @param ADCx ADC instance
3374 * @param DMATransfer This parameter can be one of the following values:
3375 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3376 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3377 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3378 * @retval None
3379 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)3380 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
3381 {
3382 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
3383 }
3384
3385 /**
3386 * @brief Get ADC group regular conversion data transfer: no transfer or
3387 * transfer by DMA, and DMA requests mode.
3388 * @note If transfer by DMA selected, specifies the DMA requests
3389 * mode:
3390 * - Limited mode (One shot mode): DMA transfer requests are stopped
3391 * when number of DMA data transfers (number of
3392 * ADC conversions) is reached.
3393 * This ADC mode is intended to be used with DMA mode non-circular.
3394 * - Unlimited mode: DMA transfer requests are unlimited,
3395 * whatever number of DMA data transfers (number of
3396 * ADC conversions).
3397 * This ADC mode is intended to be used with DMA mode circular.
3398 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3399 * mode non-circular:
3400 * when DMA transfers size will be reached, DMA will stop transfers of
3401 * ADC conversions data ADC will raise an overrun error
3402 * (overrun flag and interruption if enabled).
3403 * @note To configure DMA source address (peripheral address),
3404 * use function @ref LL_ADC_DMA_GetRegAddr().
3405 * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n
3406 * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
3407 * @param ADCx ADC instance
3408 * @retval Returned value can be one of the following values:
3409 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3410 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3411 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3412 */
LL_ADC_REG_GetDMATransfer(const ADC_TypeDef * ADCx)3413 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
3414 {
3415 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
3416 }
3417
3418 /**
3419 * @brief Set ADC group regular behavior in case of overrun:
3420 * data preserved or overwritten.
3421 * @note Compatibility with devices without feature overrun:
3422 * other devices without this feature have a behavior
3423 * equivalent to data overwritten.
3424 * The default setting of overrun is data preserved.
3425 * Therefore, for compatibility with all devices, parameter
3426 * overrun should be set to data overwritten.
3427 * @note On this STM32 series, setting of this feature is conditioned to
3428 * ADC state:
3429 * ADC must be disabled or enabled without conversion on going
3430 * on group regular.
3431 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun
3432 * @param ADCx ADC instance
3433 * @param Overrun This parameter can be one of the following values:
3434 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3435 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3436 * @retval None
3437 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)3438 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
3439 {
3440 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
3441 }
3442
3443 /**
3444 * @brief Get ADC group regular behavior in case of overrun:
3445 * data preserved or overwritten.
3446 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun
3447 * @param ADCx ADC instance
3448 * @retval Returned value can be one of the following values:
3449 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3450 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3451 */
LL_ADC_REG_GetOverrun(const ADC_TypeDef * ADCx)3452 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
3453 {
3454 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
3455 }
3456
3457 /**
3458 * @}
3459 */
3460
3461 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3462 * @{
3463 */
3464
3465 /**
3466 * @brief Set sampling time of the selected ADC channel
3467 * Unit: ADC clock cycles.
3468 * @note On this device, sampling time is on channel scope: independently
3469 * of channel mapped on ADC group regular or injected.
3470 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3471 * converted:
3472 * sampling time constraints must be respected (sampling time can be
3473 * adjusted in function of ADC clock frequency and sampling time
3474 * setting).
3475 * Refer to device datasheet for timings values (parameters TS_vrefint,
3476 * TS_temp, ...).
3477 * @note Conversion time is the addition of sampling time and processing time.
3478 * Refer to reference manual for ADC processing time of
3479 * this STM32 series.
3480 * @note In case of ADC conversion of internal channel (VrefInt,
3481 * temperature sensor, ...), a sampling time minimum value
3482 * is required.
3483 * Refer to device datasheet.
3484 * @note On this STM32 series, setting of this feature is conditioned to
3485 * ADC state:
3486 * ADC must be disabled or enabled without conversion on going
3487 * on group regular.
3488 * @rmtoll SMPR SMPSEL0 LL_ADC_SetChannelSamplingTime\n
3489 * SMPR SMPSEL1 LL_ADC_SetChannelSamplingTime\n
3490 * SMPR SMPSEL2 LL_ADC_SetChannelSamplingTime\n
3491 * SMPR SMPSEL3 LL_ADC_SetChannelSamplingTime\n
3492 * SMPR SMPSEL4 LL_ADC_SetChannelSamplingTime\n
3493 * SMPR SMPSEL5 LL_ADC_SetChannelSamplingTime\n
3494 * SMPR SMPSEL6 LL_ADC_SetChannelSamplingTime\n
3495 * SMPR SMPSEL7 LL_ADC_SetChannelSamplingTime\n
3496 * SMPR SMPSEL8 LL_ADC_SetChannelSamplingTime\n
3497 * SMPR SMPSEL9 LL_ADC_SetChannelSamplingTime\n
3498 * SMPR SMPSEL10 LL_ADC_SetChannelSamplingTime\n
3499 * SMPR SMPSEL11 LL_ADC_SetChannelSamplingTime\n
3500 * SMPR SMPSEL12 LL_ADC_SetChannelSamplingTime\n
3501 * SMPR SMPSEL13 LL_ADC_SetChannelSamplingTime\n
3502 * SMPR SMPSEL14 LL_ADC_SetChannelSamplingTime\n
3503 * SMPR SMPSEL15 LL_ADC_SetChannelSamplingTime\n
3504 * SMPR SMPSEL16 LL_ADC_SetChannelSamplingTime\n
3505 * SMPR SMPSEL17 LL_ADC_SetChannelSamplingTime\n
3506 * SMPR SMPSEL18 LL_ADC_SetChannelSamplingTime
3507 * @param ADCx ADC instance
3508 * @param Channel This parameter can be a combination of the following values:
3509 * @arg @ref LL_ADC_CHANNEL_0
3510 * @arg @ref LL_ADC_CHANNEL_1
3511 * @arg @ref LL_ADC_CHANNEL_2
3512 * @arg @ref LL_ADC_CHANNEL_3
3513 * @arg @ref LL_ADC_CHANNEL_4
3514 * @arg @ref LL_ADC_CHANNEL_5
3515 * @arg @ref LL_ADC_CHANNEL_6
3516 * @arg @ref LL_ADC_CHANNEL_7
3517 * @arg @ref LL_ADC_CHANNEL_8
3518 * @arg @ref LL_ADC_CHANNEL_9
3519 * @arg @ref LL_ADC_CHANNEL_10
3520 * @arg @ref LL_ADC_CHANNEL_11
3521 * @arg @ref LL_ADC_CHANNEL_12
3522 * @arg @ref LL_ADC_CHANNEL_13
3523 * @arg @ref LL_ADC_CHANNEL_VREFINT
3524 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3525 * @arg @ref LL_ADC_CHANNEL_VCORE
3526 * @param SamplingTimeY This parameter can be one of the following values:
3527 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3528 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3529 * @retval None
3530 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTimeY)3531 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)
3532 {
3533 /* Parameter "Channel" is used with masks because containing */
3534 /* other bits reserved for other purpose. */
3535 MODIFY_REG(ADCx->SMPR,
3536 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),
3537 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)
3538 );
3539 }
3540
3541 /**
3542 * @brief Get sampling time of the selected ADC channel
3543 * Unit: ADC clock cycles.
3544 * @note On this device, sampling time is on channel scope: independently
3545 * of channel mapped on ADC group regular or injected.
3546 * @note Conversion time is the addition of sampling time and processing time.
3547 * Refer to reference manual for ADC processing time of
3548 * this STM32 series.
3549 * @rmtoll SMPR SMPSEL0 LL_ADC_GetChannelSamplingTime\n
3550 * SMPR SMPSEL1 LL_ADC_GetChannelSamplingTime\n
3551 * SMPR SMPSEL2 LL_ADC_GetChannelSamplingTime\n
3552 * SMPR SMPSEL3 LL_ADC_GetChannelSamplingTime\n
3553 * SMPR SMPSEL4 LL_ADC_GetChannelSamplingTime\n
3554 * SMPR SMPSEL5 LL_ADC_GetChannelSamplingTime\n
3555 * SMPR SMPSEL6 LL_ADC_GetChannelSamplingTime\n
3556 * SMPR SMPSEL7 LL_ADC_GetChannelSamplingTime\n
3557 * SMPR SMPSEL8 LL_ADC_GetChannelSamplingTime\n
3558 * SMPR SMPSEL9 LL_ADC_GetChannelSamplingTime\n
3559 * SMPR SMPSEL10 LL_ADC_GetChannelSamplingTime\n
3560 * SMPR SMPSEL11 LL_ADC_GetChannelSamplingTime\n
3561 * SMPR SMPSEL12 LL_ADC_GetChannelSamplingTime\n
3562 * SMPR SMPSEL13 LL_ADC_GetChannelSamplingTime\n
3563 * SMPR SMPSEL14 LL_ADC_GetChannelSamplingTime\n
3564 * SMPR SMPSEL15 LL_ADC_GetChannelSamplingTime\n
3565 * SMPR SMPSEL16 LL_ADC_GetChannelSamplingTime\n
3566 * SMPR SMPSEL17 LL_ADC_GetChannelSamplingTime\n
3567 * SMPR SMPSEL18 LL_ADC_GetChannelSamplingTime
3568 * @param ADCx ADC instance
3569 * @param Channel This parameter can be one of the following values:
3570 * @arg @ref LL_ADC_CHANNEL_0
3571 * @arg @ref LL_ADC_CHANNEL_1
3572 * @arg @ref LL_ADC_CHANNEL_2
3573 * @arg @ref LL_ADC_CHANNEL_3
3574 * @arg @ref LL_ADC_CHANNEL_4
3575 * @arg @ref LL_ADC_CHANNEL_5
3576 * @arg @ref LL_ADC_CHANNEL_6
3577 * @arg @ref LL_ADC_CHANNEL_7
3578 * @arg @ref LL_ADC_CHANNEL_8
3579 * @arg @ref LL_ADC_CHANNEL_9
3580 * @arg @ref LL_ADC_CHANNEL_10
3581 * @arg @ref LL_ADC_CHANNEL_11
3582 * @arg @ref LL_ADC_CHANNEL_12
3583 * @arg @ref LL_ADC_CHANNEL_13
3584 * @arg @ref LL_ADC_CHANNEL_VREFINT
3585 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3586 * @arg @ref LL_ADC_CHANNEL_VCORE
3587 * @retval Returned value can be one of the following values:
3588 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3589 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3590 */
LL_ADC_GetChannelSamplingTime(const ADC_TypeDef * ADCx,uint32_t Channel)3591 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
3592 {
3593 __IO uint32_t smpr = READ_REG(ADCx->SMPR);
3594
3595 /* Retrieve sampling time bit corresponding to the selected channel */
3596 /* and shift it to position 0. */
3597 uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
3598 >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
3599 + ADC_SMPR_SMPSEL0_BITOFFSET_POS)
3600 & 0x1FUL));
3601
3602 /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
3603 return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
3604 | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2));
3605 }
3606
3607 /**
3608 * @}
3609 */
3610
3611 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
3612 * @{
3613 */
3614
3615 /**
3616 * @brief Set ADC analog watchdog monitored channels:
3617 * a single channel, multiple channels or all channels,
3618 * on ADC group regular.
3619 * @note Once monitored channels are selected, analog watchdog
3620 * is enabled.
3621 * @note In case of need to define a single channel to monitor
3622 * with analog watchdog from sequencer channel definition,
3623 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
3624 * @note On this STM32 series, setting of this feature is conditioned to
3625 * ADC state:
3626 * ADC must be disabled or enabled without conversion on going
3627 * on group regular.
3628 * @rmtoll CFGR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
3629 * CFGR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
3630 * CFGR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
3631 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
3632 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
3633 * @param ADCx ADC instance
3634 * @param AWDy This parameter can be one of the following values:
3635 * @arg @ref LL_ADC_AWD1
3636 * @arg @ref LL_ADC_AWD2
3637 * @arg @ref LL_ADC_AWD3
3638 * @param AWDChannelGroup This parameter can be one of the following values:
3639 * @arg @ref LL_ADC_AWD_DISABLE
3640 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3641 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3642 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3643 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3644 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3645 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3646 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3647 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3648 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3649 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3650 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3651 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3652 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3653 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
3654 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
3655 * @arg @ref LL_ADC_AWD_CH_VCORE_REG
3656 * @retval None
3657 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)3658 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
3659 {
3660 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
3661 /* in register and register position depending on parameter "AWDy". */
3662 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
3663 /* containing other bits reserved for other purpose. */
3664 __IO uint32_t *preg;
3665
3666 if (AWDy == LL_ADC_AWD1)
3667 {
3668 preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
3669 }
3670 else
3671 {
3672 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR,
3673 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL));
3674 }
3675
3676 MODIFY_REG(*preg,
3677 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
3678 AWDChannelGroup & AWDy);
3679 }
3680
3681 /**
3682 * @brief Get ADC analog watchdog monitored channel.
3683 * @note Usage of the returned channel number:
3684 * - To reinject this channel into another function LL_ADC_xxx:
3685 * the returned channel number is only partly formatted on definition
3686 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3687 * with parts of literals LL_ADC_CHANNEL_x or using
3688 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3689 * Then the selected literal LL_ADC_CHANNEL_x can be used
3690 * as parameter for another function.
3691 * - To get the channel number in decimal format:
3692 * process the returned value with the helper macro
3693 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3694 * Applicable only when the analog watchdog is set to monitor
3695 * one channel.
3696 * @note On this STM32 series, setting of this feature is conditioned to
3697 * ADC state:
3698 * ADC must be disabled or enabled without conversion on going
3699 * on group regular.
3700 * @rmtoll CFGR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
3701 * CFGR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
3702 * CFGR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
3703 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
3704 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
3705 * @param ADCx ADC instance
3706 * @param AWDy This parameter can be one of the following values:
3707 * @arg @ref LL_ADC_AWD1
3708 * @arg @ref LL_ADC_AWD2 (1)
3709 * @arg @ref LL_ADC_AWD3 (1)
3710 *
3711 * (1) On this AWD number, monitored channel can be retrieved
3712 * if only 1 channel is programmed (or none or all channels).
3713 * This function cannot retrieve monitored channel if
3714 * multiple channels are programmed simultaneously
3715 * by bitfield.
3716 * @retval Returned value can be one of the following values:
3717 * @arg @ref LL_ADC_AWD_DISABLE
3718 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3719 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3720 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3721 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3722 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3723 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3724 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3725 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3726 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3727 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3728 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3729 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3730 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3731 */
LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef * ADCx,uint32_t AWDy)3732 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
3733 {
3734 __IO const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1,
3735 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
3736 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
3737 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
3738
3739 uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
3740
3741 /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
3742 /* (parameter value LL_ADC_AWD_DISABLE). */
3743 /* Else, the selected AWD is enabled and is monitoring a group of channels */
3744 /* or a single channel. */
3745 if (analog_wd_monit_channels != 0UL)
3746 {
3747 if (AWDy == LL_ADC_AWD1)
3748 {
3749 if ((analog_wd_monit_channels & ADC_CFGR1_AWD1SGL) == 0UL)
3750 {
3751 /* AWD monitoring a group of channels */
3752 analog_wd_monit_channels = ((analog_wd_monit_channels
3753 | (ADC_AWD_CR23_CHANNEL_MASK)
3754 )
3755 & (~(ADC_CFGR1_AWD1CH))
3756 );
3757 }
3758 else
3759 {
3760 /* AWD monitoring a single channel */
3761 analog_wd_monit_channels = (analog_wd_monit_channels
3762 | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR1_AWD1CH_Pos))
3763 );
3764 }
3765 }
3766 else
3767 {
3768 if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
3769 {
3770 /* AWD monitoring a group of channels */
3771 analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
3772 | (ADC_CFGR1_AWD1EN)
3773 );
3774 }
3775 else
3776 {
3777 /* AWD monitoring a single channel */
3778 /* AWD monitoring a group of channels */
3779 analog_wd_monit_channels = (analog_wd_monit_channels
3780 | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
3781 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR1_AWD1CH_Pos)
3782 );
3783 }
3784 }
3785 }
3786
3787 return analog_wd_monit_channels;
3788 }
3789
3790 /**
3791 * @brief Set ADC analog watchdog thresholds value of both thresholds
3792 * high and low.
3793 * @note If value of only one threshold high or low must be set,
3794 * use function @ref LL_ADC_SetAnalogWDThresholds().
3795 * @note In case of ADC resolution different of 12 bits,
3796 * analog watchdog thresholds data require a specific shift.
3797 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3798 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
3799 * impacted: the comparison of analog watchdog thresholds is done on
3800 * oversampling final computation (after ratio and shift application):
3801 * ADC data register bitfield [15:4] (12 most significant bits).
3802 * Examples:
3803 * - Oversampling ratio and shift selected to have ADC conversion data
3804 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
3805 * ADC analog watchdog thresholds must be divided by 16.
3806 * - Oversampling ratio and shift selected to have ADC conversion data
3807 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
3808 * ADC analog watchdog thresholds must be divided by 4.
3809 * - Oversampling ratio and shift selected to have ADC conversion data
3810 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
3811 * ADC analog watchdog thresholds match directly to ADC data register.
3812 * @note On this STM32 series, setting of this feature is conditioned to
3813 * ADC state:
3814 * ADC must be disabled or enabled without conversion on going
3815 * on group regular.
3816 * @rmtoll AWD1TR HT1 LL_ADC_ConfigAnalogWDThresholds\n
3817 * AWD2TR HT2 LL_ADC_ConfigAnalogWDThresholds\n
3818 * AWD3TR HT3 LL_ADC_ConfigAnalogWDThresholds\n
3819 * AWD1TR LT1 LL_ADC_ConfigAnalogWDThresholds\n
3820 * AWD2TR LT2 LL_ADC_ConfigAnalogWDThresholds\n
3821 * AWD3TR LT3 LL_ADC_ConfigAnalogWDThresholds
3822 * @param ADCx ADC instance
3823 * @param AWDy This parameter can be one of the following values:
3824 * @arg @ref LL_ADC_AWD1
3825 * @arg @ref LL_ADC_AWD2
3826 * @arg @ref LL_ADC_AWD3
3827 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
3828 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
3829 * @retval None
3830 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)3831 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
3832 uint32_t AWDThresholdLowValue)
3833 {
3834 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
3835 /* position in register and register position depending on parameter */
3836 /* "AWDy". */
3837 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
3838 /* containing other bits reserved for other purpose. */
3839 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
3840 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
3841 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
3842 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
3843 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))
3844 );
3845
3846 MODIFY_REG(*preg,
3847 ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1,
3848 (AWDThresholdHighValue << ADC_AWD1TR_HT1_Pos) | AWDThresholdLowValue);
3849 }
3850
3851 /**
3852 * @brief Set ADC analog watchdog threshold value of threshold
3853 * high or low.
3854 * @note If values of both thresholds high or low must be set,
3855 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
3856 * @note In case of ADC resolution different of 12 bits,
3857 * analog watchdog thresholds data require a specific shift.
3858 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3859 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
3860 * impacted: the comparison of analog watchdog thresholds is done on
3861 * oversampling final computation (after ratio and shift application):
3862 * ADC data register bitfield [15:4] (12 most significant bits).
3863 * Examples:
3864 * - Oversampling ratio and shift selected to have ADC conversion data
3865 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
3866 * ADC analog watchdog thresholds must be divided by 16.
3867 * - Oversampling ratio and shift selected to have ADC conversion data
3868 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
3869 * ADC analog watchdog thresholds must be divided by 4.
3870 * - Oversampling ratio and shift selected to have ADC conversion data
3871 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
3872 * ADC analog watchdog thresholds match directly to ADC data register.
3873 * @note On this STM32 series, setting of this feature is not conditioned to
3874 * ADC state:
3875 * ADC can be disabled, enabled with or without conversion on going
3876 * on ADC group regular.
3877 * @rmtoll AWD1TR HT1 LL_ADC_SetAnalogWDThresholds\n
3878 * AWD2TR HT2 LL_ADC_SetAnalogWDThresholds\n
3879 * AWD3TR HT3 LL_ADC_SetAnalogWDThresholds\n
3880 * AWD1TR LT1 LL_ADC_SetAnalogWDThresholds\n
3881 * AWD2TR LT2 LL_ADC_SetAnalogWDThresholds\n
3882 * AWD3TR LT3 LL_ADC_SetAnalogWDThresholds
3883 * @param ADCx ADC instance
3884 * @param AWDy This parameter can be one of the following values:
3885 * @arg @ref LL_ADC_AWD1
3886 * @arg @ref LL_ADC_AWD2
3887 * @arg @ref LL_ADC_AWD3
3888 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3889 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3890 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3891 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
3892 * @retval None
3893 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)3894 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
3895 uint32_t AWDThresholdValue)
3896 {
3897 /* Set bits with content of parameter "AWDThresholdValue" with bits */
3898 /* position in register and register position depending on parameters */
3899 /* "AWDThresholdsHighLow" and "AWDy". */
3900 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
3901 /* containing other bits reserved for other purpose. */
3902 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
3903 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
3904 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
3905 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
3906 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
3907
3908 MODIFY_REG(*preg,
3909 AWDThresholdsHighLow,
3910 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
3911 }
3912
3913 /**
3914 * @brief Get ADC analog watchdog threshold value of threshold high,
3915 * threshold low or raw data with ADC thresholds high and low
3916 * concatenated.
3917 * @note If raw data with ADC thresholds high and low is retrieved,
3918 * the data of each threshold high or low can be isolated
3919 * using helper macro:
3920 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
3921 * @note In case of ADC resolution different of 12 bits,
3922 * analog watchdog thresholds data require a specific shift.
3923 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
3924 * @rmtoll AWD1TR HT1 LL_ADC_GetAnalogWDThresholds\n
3925 * AWD2TR HT2 LL_ADC_GetAnalogWDThresholds\n
3926 * AWD3TR HT3 LL_ADC_GetAnalogWDThresholds\n
3927 * AWD1TR LT1 LL_ADC_GetAnalogWDThresholds\n
3928 * AWD2TR LT2 LL_ADC_GetAnalogWDThresholds\n
3929 * AWD3TR LT3 LL_ADC_GetAnalogWDThresholds
3930 * @param ADCx ADC instance
3931 * @param AWDy This parameter can be one of the following values:
3932 * @arg @ref LL_ADC_AWD1
3933 * @arg @ref LL_ADC_AWD2
3934 * @arg @ref LL_ADC_AWD3
3935 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3936 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3937 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3938 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
3939 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3940 */
LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)3941 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx,
3942 uint32_t AWDy, uint32_t AWDThresholdsHighLow)
3943 {
3944 /* Set bits with content of parameter "AWDThresholdValue" with bits */
3945 /* position in register and register position depending on parameters */
3946 /* "AWDThresholdsHighLow" and "AWDy". */
3947 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
3948 /* containing other bits reserved for other purpose. */
3949 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
3950 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
3951 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
3952 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
3953 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
3954
3955 return (uint32_t)(READ_BIT(*preg,
3956 (AWDThresholdsHighLow | ADC_AWD1TR_LT1))
3957 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
3958 & ~(AWDThresholdsHighLow & ADC_AWD1TR_LT1)));
3959 }
3960
3961 /**
3962 * @}
3963 */
3964
3965 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
3966 * @{
3967 */
3968
3969 /**
3970 * @brief Set ADC oversampling scope.
3971 * @note On this STM32 series, setting of this feature is conditioned to
3972 * ADC state:
3973 * ADC must be disabled.
3974 * @rmtoll CFGR2 OVSE LL_ADC_SetOverSamplingScope
3975 * @param ADCx ADC instance
3976 * @param OvsScope This parameter can be one of the following values:
3977 * @arg @ref LL_ADC_OVS_DISABLE
3978 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
3979 * @retval None
3980 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)3981 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
3982 {
3983 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
3984 }
3985
3986 /**
3987 * @brief Get ADC oversampling scope.
3988 * @rmtoll CFGR2 OVSE LL_ADC_GetOverSamplingScope
3989 * @param ADCx ADC instance
3990 * @retval Returned value can be one of the following values:
3991 * @arg @ref LL_ADC_OVS_DISABLE
3992 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
3993 */
LL_ADC_GetOverSamplingScope(const ADC_TypeDef * ADCx)3994 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
3995 {
3996 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
3997 }
3998
3999 /**
4000 * @brief Set ADC oversampling discontinuous mode (triggered mode)
4001 * on the selected ADC group.
4002 * @note Number of oversampled conversions are done either in:
4003 * - continuous mode (all conversions of oversampling ratio
4004 * are done from 1 trigger)
4005 * - discontinuous mode (each conversion of oversampling ratio
4006 * needs a trigger)
4007 * @note On this STM32 series, setting of this feature is conditioned to
4008 * ADC state:
4009 * ADC must be disabled or enabled without conversion on going
4010 * on group regular.
4011 * @rmtoll CFGR2 TOVS LL_ADC_SetOverSamplingDiscont
4012 * @param ADCx ADC instance
4013 * @param OverSamplingDiscont This parameter can be one of the following values:
4014 * @arg @ref LL_ADC_OVS_REG_CONT
4015 * @arg @ref LL_ADC_OVS_REG_DISCONT
4016 * @retval None
4017 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)4018 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
4019 {
4020 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
4021 }
4022
4023 /**
4024 * @brief Get ADC oversampling discontinuous mode (triggered mode)
4025 * on the selected ADC group.
4026 * @note Number of oversampled conversions are done either in:
4027 * - continuous mode (all conversions of oversampling ratio
4028 * are done from 1 trigger)
4029 * - discontinuous mode (each conversion of oversampling ratio
4030 * needs a trigger)
4031 * @rmtoll CFGR2 TOVS LL_ADC_GetOverSamplingDiscont
4032 * @param ADCx ADC instance
4033 * @retval Returned value can be one of the following values:
4034 * @arg @ref LL_ADC_OVS_REG_CONT
4035 * @arg @ref LL_ADC_OVS_REG_DISCONT
4036 */
LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef * ADCx)4037 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
4038 {
4039 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
4040 }
4041
4042 /**
4043 * @brief Set ADC oversampling
4044 * @note This function set the 2 items of oversampling configuration:
4045 * - ratio
4046 * - shift
4047 * @note On this STM32 series, setting of this feature is conditioned to
4048 * ADC state:
4049 * ADC must be disabled.
4050 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
4051 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
4052 * @param ADCx ADC instance
4053 * @param Ratio This parameter can be one of the following values:
4054 * @arg @ref LL_ADC_OVS_RATIO_2
4055 * @arg @ref LL_ADC_OVS_RATIO_4
4056 * @arg @ref LL_ADC_OVS_RATIO_8
4057 * @arg @ref LL_ADC_OVS_RATIO_16
4058 * @arg @ref LL_ADC_OVS_RATIO_32
4059 * @arg @ref LL_ADC_OVS_RATIO_64
4060 * @arg @ref LL_ADC_OVS_RATIO_128
4061 * @arg @ref LL_ADC_OVS_RATIO_256
4062 * @param Shift This parameter can be one of the following values:
4063 * @arg @ref LL_ADC_OVS_SHIFT_NONE
4064 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
4065 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
4066 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
4067 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
4068 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
4069 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
4070 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
4071 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
4072 * @retval None
4073 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)4074 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
4075 {
4076 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
4077 }
4078
4079 /**
4080 * @brief Get ADC oversampling ratio
4081 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
4082 * @param ADCx ADC instance
4083 * @retval Ratio This parameter can be one of the following values:
4084 * @arg @ref LL_ADC_OVS_RATIO_2
4085 * @arg @ref LL_ADC_OVS_RATIO_4
4086 * @arg @ref LL_ADC_OVS_RATIO_8
4087 * @arg @ref LL_ADC_OVS_RATIO_16
4088 * @arg @ref LL_ADC_OVS_RATIO_32
4089 * @arg @ref LL_ADC_OVS_RATIO_64
4090 * @arg @ref LL_ADC_OVS_RATIO_128
4091 * @arg @ref LL_ADC_OVS_RATIO_256
4092 */
LL_ADC_GetOverSamplingRatio(const ADC_TypeDef * ADCx)4093 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
4094 {
4095 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
4096 }
4097
4098 /**
4099 * @brief Get ADC oversampling shift
4100 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
4101 * @param ADCx ADC instance
4102 * @retval Shift This parameter can be one of the following values:
4103 * @arg @ref LL_ADC_OVS_SHIFT_NONE
4104 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
4105 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
4106 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
4107 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
4108 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
4109 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
4110 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
4111 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
4112 */
LL_ADC_GetOverSamplingShift(const ADC_TypeDef * ADCx)4113 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
4114 {
4115 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
4116 }
4117
4118 /**
4119 * @}
4120 */
4121
4122 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
4123 * @{
4124 */
4125
4126 /**
4127 * @brief Enable ADC instance internal voltage regulator.
4128 * @note On this STM32 series, there are three possibilities to enable
4129 * the voltage regulator:
4130 * - by enabling it manually
4131 * using function @ref LL_ADC_EnableInternalRegulator().
4132 * - by launching a calibration
4133 * using function @ref LL_ADC_StartCalibration().
4134 * - by enabling the ADC
4135 * using function @ref LL_ADC_Enable().
4136 * @note On this STM32 series, after ADC internal voltage regulator enable,
4137 * a delay for ADC internal voltage regulator stabilization
4138 * is required before performing a ADC calibration or ADC enable.
4139 * Refer to device datasheet, parameter "tADCVREG_STUP".
4140 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
4141 * @note On this STM32 series, setting of this feature is conditioned to
4142 * ADC state:
4143 * ADC must be ADC disabled.
4144 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
4145 * @param ADCx ADC instance
4146 * @retval None
4147 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)4148 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
4149 {
4150 /* Note: Write register with some additional bits forced to state reset */
4151 /* instead of modifying only the selected bit for this function, */
4152 /* to not interfere with bits with HW property "rs". */
4153 MODIFY_REG(ADCx->CR,
4154 ADC_CR_BITS_PROPERTY_RS,
4155 ADC_CR_ADVREGEN);
4156 }
4157
4158 /**
4159 * @brief Disable ADC internal voltage regulator.
4160 * @note On this STM32 series, setting of this feature is conditioned to
4161 * ADC state:
4162 * ADC must be ADC disabled.
4163 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
4164 * @param ADCx ADC instance
4165 * @retval None
4166 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)4167 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
4168 {
4169 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
4170 }
4171
4172 /**
4173 * @brief Get the selected ADC instance internal voltage regulator state.
4174 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
4175 * @param ADCx ADC instance
4176 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
4177 */
LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef * ADCx)4178 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
4179 {
4180 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
4181 }
4182
4183 /**
4184 * @brief Enable the selected ADC instance.
4185 * @note On this STM32 series, after ADC enable, a delay for
4186 * ADC internal analog stabilization is required before performing a
4187 * ADC conversion start.
4188 * Refer to device datasheet, parameter tSTAB.
4189 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4190 * is enabled and when conversion clock is active.
4191 * (not only core clock: this ADC has a dual clock domain)
4192 * @note On this STM32 series, setting of this feature is conditioned to
4193 * ADC state:
4194 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
4195 * @rmtoll CR ADEN LL_ADC_Enable
4196 * @param ADCx ADC instance
4197 * @retval None
4198 */
LL_ADC_Enable(ADC_TypeDef * ADCx)4199 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
4200 {
4201 /* Note: Write register with some additional bits forced to state reset */
4202 /* instead of modifying only the selected bit for this function, */
4203 /* to not interfere with bits with HW property "rs". */
4204 MODIFY_REG(ADCx->CR,
4205 ADC_CR_BITS_PROPERTY_RS,
4206 ADC_CR_ADEN);
4207 }
4208
4209 /**
4210 * @brief Disable the selected ADC instance.
4211 * @note On this STM32 series, setting of this feature is conditioned to
4212 * ADC state:
4213 * ADC must be not disabled. Must be enabled without conversion on going
4214 * on group regular.
4215 * @rmtoll CR ADDIS LL_ADC_Disable
4216 * @param ADCx ADC instance
4217 * @retval None
4218 */
LL_ADC_Disable(ADC_TypeDef * ADCx)4219 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
4220 {
4221 /* Note: Write register with some additional bits forced to state reset */
4222 /* instead of modifying only the selected bit for this function, */
4223 /* to not interfere with bits with HW property "rs". */
4224 MODIFY_REG(ADCx->CR,
4225 ADC_CR_BITS_PROPERTY_RS,
4226 ADC_CR_ADDIS);
4227 }
4228
4229 /**
4230 * @brief Get the selected ADC instance enable state.
4231 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4232 * is enabled and when conversion clock is active.
4233 * (not only core clock: this ADC has a dual clock domain)
4234 * @rmtoll CR ADEN LL_ADC_IsEnabled
4235 * @param ADCx ADC instance
4236 * @retval 0: ADC is disabled, 1: ADC is enabled.
4237 */
LL_ADC_IsEnabled(const ADC_TypeDef * ADCx)4238 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
4239 {
4240 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
4241 }
4242
4243 /**
4244 * @brief Get the selected ADC instance disable state.
4245 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
4246 * @param ADCx ADC instance
4247 * @retval 0: no ADC disable command on going.
4248 */
LL_ADC_IsDisableOngoing(const ADC_TypeDef * ADCx)4249 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
4250 {
4251 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
4252 }
4253
4254 /**
4255 * @brief Start ADC calibration in the mode single-ended
4256 * or differential (for devices with differential mode available).
4257 * @note On this STM32 series, a minimum number of ADC clock cycles
4258 * are required between ADC end of calibration and ADC enable.
4259 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
4260 * @note In case of usage of ADC with DMA transfer:
4261 * On this STM32 series, ADC DMA transfer request should be disabled
4262 * during calibration:
4263 * Calibration factor is available in data register
4264 * and also transferred by DMA.
4265 * To not insert ADC calibration factor among ADC conversion data
4266 * in array variable, DMA transfer must be disabled during
4267 * calibration.
4268 * (DMA transfer setting backup and disable before calibration,
4269 * DMA transfer setting restore after calibration.
4270 * Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
4271 * @ref LL_ADC_REG_SetDMATransfer() ).
4272 * @note In case of usage of feature auto power-off:
4273 * This mode must be disabled during calibration
4274 * Refer to function @ref LL_ADC_SetLowPowerMode().
4275 * @note On this STM32 series, setting of this feature is conditioned to
4276 * ADC state:
4277 * ADC must be ADC disabled.
4278 * @rmtoll CR ADCAL LL_ADC_StartCalibration
4279 * @param ADCx ADC instance
4280 * @retval None
4281 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx)4282 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
4283 {
4284 /* Note: Write register with some additional bits forced to state reset */
4285 /* instead of modifying only the selected bit for this function, */
4286 /* to not interfere with bits with HW property "rs". */
4287 MODIFY_REG(ADCx->CR,
4288 ADC_CR_BITS_PROPERTY_RS,
4289 ADC_CR_ADCAL);
4290 }
4291
4292 /**
4293 * @brief Get ADC calibration state.
4294 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
4295 * @param ADCx ADC instance
4296 * @retval 0: calibration complete, 1: calibration in progress.
4297 */
LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef * ADCx)4298 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
4299 {
4300 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
4301 }
4302
4303 /**
4304 * @}
4305 */
4306
4307 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
4308 * @{
4309 */
4310
4311 /**
4312 * @brief Start ADC group regular conversion.
4313 * @note On this STM32 series, this function is relevant for both
4314 * internal trigger (SW start) and external trigger:
4315 * - If ADC trigger has been set to software start, ADC conversion
4316 * starts immediately.
4317 * - If ADC trigger has been set to external trigger, ADC conversion
4318 * will start at next trigger event (on the selected trigger edge)
4319 * following the ADC start conversion command.
4320 * @note On this STM32 series, setting of this feature is conditioned to
4321 * ADC state:
4322 * ADC must be enabled without conversion on going on group regular,
4323 * without conversion stop command on going on group regular,
4324 * without ADC disable command on going.
4325 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
4326 * @param ADCx ADC instance
4327 * @retval None
4328 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)4329 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
4330 {
4331 /* Note: Write register with some additional bits forced to state reset */
4332 /* instead of modifying only the selected bit for this function, */
4333 /* to not interfere with bits with HW property "rs". */
4334 MODIFY_REG(ADCx->CR,
4335 ADC_CR_BITS_PROPERTY_RS,
4336 ADC_CR_ADSTART);
4337 }
4338
4339 /**
4340 * @brief Stop ADC group regular conversion.
4341 * @note On this STM32 series, setting of this feature is conditioned to
4342 * ADC state:
4343 * ADC must be enabled (potentially with conversion on going on group regular),
4344 * without ADC disable command on going.
4345 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
4346 * @param ADCx ADC instance
4347 * @retval None
4348 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)4349 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
4350 {
4351 /* Note: Write register with some additional bits forced to state reset */
4352 /* instead of modifying only the selected bit for this function, */
4353 /* to not interfere with bits with HW property "rs". */
4354 MODIFY_REG(ADCx->CR,
4355 ADC_CR_BITS_PROPERTY_RS,
4356 ADC_CR_ADSTP);
4357 }
4358
4359 /**
4360 * @brief Get ADC group regular conversion state.
4361 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
4362 * @param ADCx ADC instance
4363 * @retval 0: no conversion is on going on ADC group regular.
4364 */
LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef * ADCx)4365 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
4366 {
4367 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
4368 }
4369
4370 /**
4371 * @brief Get ADC group regular command of conversion stop state
4372 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
4373 * @param ADCx ADC instance
4374 * @retval 0: no command of conversion stop is on going on ADC group regular.
4375 */
LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef * ADCx)4376 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
4377 {
4378 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
4379 }
4380
4381 /**
4382 * @brief Get ADC group regular conversion data, range fit for
4383 * all ADC configurations: all ADC resolutions and
4384 * all oversampling increased data width (for devices
4385 * with feature oversampling).
4386 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32
4387 * @param ADCx ADC instance
4388 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4389 */
LL_ADC_REG_ReadConversionData32(const ADC_TypeDef * ADCx)4390 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
4391 {
4392 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4393 }
4394
4395 /**
4396 * @brief Get ADC group regular conversion data, range fit for
4397 * ADC resolution 12 bits.
4398 * @note For devices with feature oversampling: Oversampling
4399 * can increase data width, function for extended range
4400 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4401 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12
4402 * @param ADCx ADC instance
4403 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4404 */
LL_ADC_REG_ReadConversionData12(const ADC_TypeDef * ADCx)4405 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
4406 {
4407 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x00000FFFUL);
4408 }
4409
4410 /**
4411 * @brief Get ADC group regular conversion data, range fit for
4412 * ADC resolution 10 bits.
4413 * @note For devices with feature oversampling: Oversampling
4414 * can increase data width, function for extended range
4415 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4416 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10
4417 * @param ADCx ADC instance
4418 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4419 */
LL_ADC_REG_ReadConversionData10(const ADC_TypeDef * ADCx)4420 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
4421 {
4422 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000003FFUL);
4423 }
4424
4425 /**
4426 * @brief Get ADC group regular conversion data, range fit for
4427 * ADC resolution 8 bits.
4428 * @note For devices with feature oversampling: Oversampling
4429 * can increase data width, function for extended range
4430 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4431 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8
4432 * @param ADCx ADC instance
4433 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4434 */
LL_ADC_REG_ReadConversionData8(const ADC_TypeDef * ADCx)4435 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
4436 {
4437 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000000FFUL);
4438 }
4439
4440 /**
4441 * @brief Get ADC group regular conversion data, range fit for
4442 * ADC resolution 6 bits.
4443 * @note For devices with feature oversampling: Oversampling
4444 * can increase data width, function for extended range
4445 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4446 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6
4447 * @param ADCx ADC instance
4448 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4449 */
LL_ADC_REG_ReadConversionData6(const ADC_TypeDef * ADCx)4450 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
4451 {
4452 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x0000003FUL);
4453 }
4454
4455 /**
4456 * @}
4457 */
4458
4459 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4460 * @{
4461 */
4462
4463 /**
4464 * @brief Get flag ADC ready.
4465 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4466 * is enabled and when conversion clock is active.
4467 * (not only core clock: this ADC has a dual clock domain)
4468 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
4469 * @param ADCx ADC instance
4470 * @retval State of bit (1 or 0).
4471 */
LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef * ADCx)4472 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
4473 {
4474 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
4475 }
4476
4477 /**
4478 * @brief Get flag ADC internal voltage regulator ready.
4479 * @rmtoll ISR LDORDY LL_ADC_IsActiveFlag_LDORDY
4480 * @param ADCx ADC instance
4481 * @retval State of bit (1 or 0).
4482 */
LL_ADC_IsActiveFlag_LDORDY(const ADC_TypeDef * ADCx)4483 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(const ADC_TypeDef *ADCx)
4484 {
4485 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL);
4486 }
4487
4488 /**
4489 * @brief Get flag ADC group regular end of unitary conversion.
4490 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
4491 * @param ADCx ADC instance
4492 * @retval State of bit (1 or 0).
4493 */
LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef * ADCx)4494 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
4495 {
4496 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
4497 }
4498
4499 /**
4500 * @brief Get flag ADC group regular end of sequence conversions.
4501 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
4502 * @param ADCx ADC instance
4503 * @retval State of bit (1 or 0).
4504 */
LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef * ADCx)4505 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
4506 {
4507 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
4508 }
4509
4510 /**
4511 * @brief Get flag ADC group regular overrun.
4512 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
4513 * @param ADCx ADC instance
4514 * @retval State of bit (1 or 0).
4515 */
LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef * ADCx)4516 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
4517 {
4518 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
4519 }
4520
4521 /**
4522 * @brief Get flag ADC group regular end of sampling phase.
4523 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
4524 * @param ADCx ADC instance
4525 * @retval State of bit (1 or 0).
4526 */
LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef * ADCx)4527 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
4528 {
4529 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
4530 }
4531
4532 /**
4533 * @brief Get flag ADC analog watchdog 1 flag
4534 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
4535 * @param ADCx ADC instance
4536 * @retval State of bit (1 or 0).
4537 */
LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef * ADCx)4538 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
4539 {
4540 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
4541 }
4542
4543 /**
4544 * @brief Get flag ADC analog watchdog 2.
4545 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
4546 * @param ADCx ADC instance
4547 * @retval State of bit (1 or 0).
4548 */
LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef * ADCx)4549 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
4550 {
4551 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
4552 }
4553
4554 /**
4555 * @brief Get flag ADC analog watchdog 3.
4556 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
4557 * @param ADCx ADC instance
4558 * @retval State of bit (1 or 0).
4559 */
LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef * ADCx)4560 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
4561 {
4562 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
4563 }
4564
4565 /**
4566 * @brief Get flag ADC end of calibration.
4567 * @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL
4568 * @param ADCx ADC instance
4569 * @retval State of bit (1 or 0).
4570 */
LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef * ADCx)4571 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef *ADCx)
4572 {
4573 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL);
4574 }
4575
4576 /**
4577 * @brief Clear flag ADC ready.
4578 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4579 * is enabled and when conversion clock is active.
4580 * (not only core clock: this ADC has a dual clock domain)
4581 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
4582 * @param ADCx ADC instance
4583 * @retval None
4584 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)4585 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
4586 {
4587 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
4588 }
4589
4590 /**
4591 * @brief Clear flag ADC internal voltage regulator ready.
4592 * @rmtoll ISR LDORDY LL_ADC_ClearFlag_LDORDY
4593 * @param ADCx ADC instance
4594 * @retval State of bit (1 or 0).
4595 */
LL_ADC_ClearFlag_LDORDY(ADC_TypeDef * ADCx)4596 __STATIC_INLINE void LL_ADC_ClearFlag_LDORDY(ADC_TypeDef *ADCx)
4597 {
4598 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_LDORDY);
4599 }
4600
4601 /**
4602 * @brief Clear flag ADC group regular end of unitary conversion.
4603 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
4604 * @param ADCx ADC instance
4605 * @retval None
4606 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)4607 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
4608 {
4609 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
4610 }
4611
4612 /**
4613 * @brief Clear flag ADC group regular end of sequence conversions.
4614 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
4615 * @param ADCx ADC instance
4616 * @retval None
4617 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)4618 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
4619 {
4620 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
4621 }
4622
4623 /**
4624 * @brief Clear flag ADC group regular overrun.
4625 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
4626 * @param ADCx ADC instance
4627 * @retval None
4628 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)4629 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
4630 {
4631 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
4632 }
4633
4634 /**
4635 * @brief Clear flag ADC group regular end of sampling phase.
4636 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
4637 * @param ADCx ADC instance
4638 * @retval None
4639 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)4640 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
4641 {
4642 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
4643 }
4644
4645 /**
4646 * @brief Clear flag ADC analog watchdog 1.
4647 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
4648 * @param ADCx ADC instance
4649 * @retval None
4650 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)4651 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
4652 {
4653 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
4654 }
4655
4656 /**
4657 * @brief Clear flag ADC analog watchdog 2.
4658 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
4659 * @param ADCx ADC instance
4660 * @retval None
4661 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)4662 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
4663 {
4664 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
4665 }
4666
4667 /**
4668 * @brief Clear flag ADC analog watchdog 3.
4669 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
4670 * @param ADCx ADC instance
4671 * @retval None
4672 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)4673 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
4674 {
4675 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
4676 }
4677
4678 /**
4679 * @brief Clear flag ADC end of calibration.
4680 * @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL
4681 * @param ADCx ADC instance
4682 * @retval None
4683 */
LL_ADC_ClearFlag_EOCAL(ADC_TypeDef * ADCx)4684 __STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx)
4685 {
4686 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);
4687 }
4688
4689 /**
4690 * @}
4691 */
4692
4693 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
4694 * @{
4695 */
4696
4697 /**
4698 * @brief Enable ADC ready.
4699 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
4700 * @param ADCx ADC instance
4701 * @retval None
4702 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)4703 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
4704 {
4705 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
4706 }
4707
4708 /**
4709 * @brief Enable interruption ADC internal voltage regulator ready.
4710 * @rmtoll IER LDORDYIE LL_ADC_EnableIT_LDORDY
4711 * @param ADCx ADC instance
4712 * @retval State of bit (1 or 0).
4713 */
LL_ADC_EnableIT_LDORDY(ADC_TypeDef * ADCx)4714 __STATIC_INLINE void LL_ADC_EnableIT_LDORDY(ADC_TypeDef *ADCx)
4715 {
4716 SET_BIT(ADCx->IER, LL_ADC_FLAG_LDORDY);
4717 }
4718
4719 /**
4720 * @brief Enable interruption ADC group regular end of unitary conversion.
4721 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
4722 * @param ADCx ADC instance
4723 * @retval None
4724 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)4725 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
4726 {
4727 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
4728 }
4729
4730 /**
4731 * @brief Enable interruption ADC group regular end of sequence conversions.
4732 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
4733 * @param ADCx ADC instance
4734 * @retval None
4735 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)4736 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
4737 {
4738 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
4739 }
4740
4741 /**
4742 * @brief Enable ADC group regular interruption overrun.
4743 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
4744 * @param ADCx ADC instance
4745 * @retval None
4746 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)4747 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
4748 {
4749 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
4750 }
4751
4752 /**
4753 * @brief Enable interruption ADC group regular end of sampling.
4754 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
4755 * @param ADCx ADC instance
4756 * @retval None
4757 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)4758 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
4759 {
4760 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
4761 }
4762
4763 /**
4764 * @brief Enable interruption ADC analog watchdog 1.
4765 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
4766 * @param ADCx ADC instance
4767 * @retval None
4768 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)4769 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
4770 {
4771 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
4772 }
4773
4774 /**
4775 * @brief Enable interruption ADC analog watchdog 2.
4776 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
4777 * @param ADCx ADC instance
4778 * @retval None
4779 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)4780 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
4781 {
4782 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
4783 }
4784
4785 /**
4786 * @brief Enable interruption ADC analog watchdog 3.
4787 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
4788 * @param ADCx ADC instance
4789 * @retval None
4790 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)4791 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
4792 {
4793 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
4794 }
4795
4796 /**
4797 * @brief Enable interruption ADC end of calibration.
4798 * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL
4799 * @param ADCx ADC instance
4800 * @retval None
4801 */
LL_ADC_EnableIT_EOCAL(ADC_TypeDef * ADCx)4802 __STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
4803 {
4804 SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
4805 }
4806
4807 /**
4808 * @brief Disable interruption ADC ready.
4809 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
4810 * @param ADCx ADC instance
4811 * @retval None
4812 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)4813 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
4814 {
4815 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
4816 }
4817
4818 /**
4819 * @brief Disable interruption ADC internal voltage regulator ready.
4820 * @rmtoll IER LDORDYIE LL_ADC_DisableIT_LDORDY
4821 * @param ADCx ADC instance
4822 * @retval State of bit (1 or 0).
4823 */
LL_ADC_DisableIT_LDORDY(ADC_TypeDef * ADCx)4824 __STATIC_INLINE void LL_ADC_DisableIT_LDORDY(ADC_TypeDef *ADCx)
4825 {
4826 CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_LDORDY);
4827 }
4828
4829 /**
4830 * @brief Disable interruption ADC group regular end of unitary conversion.
4831 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
4832 * @param ADCx ADC instance
4833 * @retval None
4834 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)4835 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
4836 {
4837 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
4838 }
4839
4840 /**
4841 * @brief Disable interruption ADC group regular end of sequence conversions.
4842 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
4843 * @param ADCx ADC instance
4844 * @retval None
4845 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)4846 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
4847 {
4848 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
4849 }
4850
4851 /**
4852 * @brief Disable interruption ADC group regular overrun.
4853 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
4854 * @param ADCx ADC instance
4855 * @retval None
4856 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)4857 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
4858 {
4859 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
4860 }
4861
4862 /**
4863 * @brief Disable interruption ADC group regular end of sampling.
4864 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
4865 * @param ADCx ADC instance
4866 * @retval None
4867 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)4868 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
4869 {
4870 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
4871 }
4872
4873 /**
4874 * @brief Disable interruption ADC analog watchdog 1.
4875 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
4876 * @param ADCx ADC instance
4877 * @retval None
4878 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)4879 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
4880 {
4881 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
4882 }
4883
4884 /**
4885 * @brief Disable interruption ADC analog watchdog 2.
4886 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
4887 * @param ADCx ADC instance
4888 * @retval None
4889 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)4890 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
4891 {
4892 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
4893 }
4894
4895 /**
4896 * @brief Disable interruption ADC analog watchdog 3.
4897 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
4898 * @param ADCx ADC instance
4899 * @retval None
4900 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)4901 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
4902 {
4903 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
4904 }
4905
4906 /**
4907 * @brief Disable interruption ADC end of calibration.
4908 * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL
4909 * @param ADCx ADC instance
4910 * @retval None
4911 */
LL_ADC_DisableIT_EOCAL(ADC_TypeDef * ADCx)4912 __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
4913 {
4914 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
4915 }
4916
4917 /**
4918 * @brief Get state of interruption ADC ready
4919 * (0: interrupt disabled, 1: interrupt enabled).
4920 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
4921 * @param ADCx ADC instance
4922 * @retval State of bit (1 or 0).
4923 */
LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef * ADCx)4924 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
4925 {
4926 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
4927 }
4928
4929 /**
4930 * @brief Get state of interruption ADC internal voltage regulator ready.
4931 * @rmtoll IER LDORDYIE LL_ADC_IsEnabledIT_LDORDY
4932 * @param ADCx ADC instance
4933 * @retval State of bit (1 or 0).
4934 */
LL_ADC_IsEnabledIT_LDORDY(const ADC_TypeDef * ADCx)4935 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_LDORDY(const ADC_TypeDef *ADCx)
4936 {
4937 return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL);
4938 }
4939
4940 /**
4941 * @brief Get state of interruption ADC group regular end of unitary conversion
4942 * (0: interrupt disabled, 1: interrupt enabled).
4943 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
4944 * @param ADCx ADC instance
4945 * @retval State of bit (1 or 0).
4946 */
LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef * ADCx)4947 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
4948 {
4949 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
4950 }
4951
4952 /**
4953 * @brief Get state of interruption ADC group regular end of sequence conversions
4954 * (0: interrupt disabled, 1: interrupt enabled).
4955 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
4956 * @param ADCx ADC instance
4957 * @retval State of bit (1 or 0).
4958 */
LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef * ADCx)4959 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
4960 {
4961 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
4962 }
4963
4964 /**
4965 * @brief Get state of interruption ADC group regular overrun
4966 * (0: interrupt disabled, 1: interrupt enabled).
4967 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
4968 * @param ADCx ADC instance
4969 * @retval State of bit (1 or 0).
4970 */
LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef * ADCx)4971 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
4972 {
4973 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
4974 }
4975
4976 /**
4977 * @brief Get state of interruption ADC group regular end of sampling
4978 * (0: interrupt disabled, 1: interrupt enabled).
4979 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
4980 * @param ADCx ADC instance
4981 * @retval State of bit (1 or 0).
4982 */
LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef * ADCx)4983 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
4984 {
4985 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
4986 }
4987
4988 /**
4989 * @brief Get state of interruption ADC analog watchdog 1
4990 * (0: interrupt disabled, 1: interrupt enabled).
4991 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
4992 * @param ADCx ADC instance
4993 * @retval State of bit (1 or 0).
4994 */
LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef * ADCx)4995 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
4996 {
4997 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
4998 }
4999
5000 /**
5001 * @brief Get state of interruption Get ADC analog watchdog 2
5002 * (0: interrupt disabled, 1: interrupt enabled).
5003 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
5004 * @param ADCx ADC instance
5005 * @retval State of bit (1 or 0).
5006 */
LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef * ADCx)5007 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
5008 {
5009 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
5010 }
5011
5012 /**
5013 * @brief Get state of interruption Get ADC analog watchdog 3
5014 * (0: interrupt disabled, 1: interrupt enabled).
5015 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
5016 * @param ADCx ADC instance
5017 * @retval State of bit (1 or 0).
5018 */
LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef * ADCx)5019 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
5020 {
5021 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
5022 }
5023
5024 /**
5025 * @brief Get state of interruption ADC end of calibration
5026 * (0: interrupt disabled, 1: interrupt enabled).
5027 * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL
5028 * @param ADCx ADC instance
5029 * @retval State of bit (1 or 0).
5030 */
LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef * ADCx)5031 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx)
5032 {
5033 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
5034 }
5035
5036 /**
5037 * @}
5038 */
5039
5040 #if defined(USE_FULL_LL_DRIVER)
5041 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
5042 * @{
5043 */
5044
5045 /* Initialization of some features of ADC common parameters and multimode */
5046 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON);
5047 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
5048 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
5049
5050 /* De-initialization of ADC instance */
5051 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
5052
5053 /* Initialization of some features of ADC instance */
5054 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct);
5055 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
5056
5057 /* Initialization of some features of ADC instance and ADC group regular */
5058 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
5059 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
5060
5061 /**
5062 * @}
5063 */
5064 #endif /* USE_FULL_LL_DRIVER */
5065
5066 /**
5067 * @}
5068 */
5069
5070 /**
5071 * @}
5072 */
5073
5074 #endif /* ADC4 */
5075
5076 /**
5077 * @}
5078 */
5079
5080 #ifdef __cplusplus
5081 }
5082 #endif
5083
5084 #endif /* STM32WBAxx_LL_ADC_H */
5085
