1 /** 2 ****************************************************************************** 3 * @file stm32wbaxx_hal_spi.h 4 * @author MCD Application Team 5 * @brief Header file of SPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBAxx_HAL_SPI_H 21 #define STM32WBAxx_HAL_SPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbaxx_hal_def.h" 29 30 /** @addtogroup STM32WBAxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup SPI 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup SPI_Exported_Types SPI Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief SPI Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Mode; /*!< Specifies the SPI operating mode. 49 This parameter can be a value of @ref SPI_Mode */ 50 51 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. 52 This parameter can be a value of @ref SPI_Direction */ 53 54 uint32_t DataSize; /*!< Specifies the SPI data size. 55 This parameter can be a value of @ref SPI_Data_Size */ 56 57 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. 58 This parameter can be a value of @ref SPI_Clock_Polarity */ 59 60 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. 61 This parameter can be a value of @ref SPI_Clock_Phase */ 62 63 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by 64 hardware (NSS pin) or by software using the SSI bit. 65 This parameter can be a value of 66 @ref SPI_Slave_Select_Management */ 67 68 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be 69 used to configure the transmit and receive SCK clock. 70 This parameter can be a value of @ref SPI_BaudRate_Prescaler 71 @note The communication clock is derived from the master 72 clock. The slave clock does not need to be set. */ 73 74 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 75 This parameter can be a value of @ref SPI_MSB_LSB_Transmission */ 76 77 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. 78 This parameter can be a value of @ref SPI_TI_Mode */ 79 80 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. 81 This parameter can be a value of @ref SPI_CRC_Calculation */ 82 83 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. 84 This parameter must be an odd number between 85 Min_Data = 0 and Max_Data = 65535 */ 86 87 uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. 88 This parameter can be a value of @ref SPI_CRC_length */ 89 90 uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . 91 This parameter can be a value of @ref SPI_NSSP_Mode 92 This mode is activated by the SSOM bit in the SPIx_CR2 register 93 and it takes effect only if the SPI interface is configured 94 as Motorola SPI master (FRF=0). */ 95 96 uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal 97 (present on SS pin) is considered as active one. 98 This parameter can be a value of @ref SPI_NSS_Polarity */ 99 100 uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level. 101 This parameter can be a value of @ref SPI_Fifo_Threshold */ 102 103 uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for 104 the CRC calculation. This parameter can be a value of 105 @ref SPI_CRC_Calculation_Initialization_Pattern */ 106 107 uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for 108 the CRC calculation. This parameter can be a value of 109 @ref SPI_CRC_Calculation_Initialization_Pattern */ 110 111 uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle 112 periods, inserted additionally between active edge of SS 113 and first data transaction start in master mode. 114 This parameter can be a value of @ref SPI_Master_SS_Idleness */ 115 116 uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) 117 inserted between two consecutive data frames in master mode. 118 This parameter can be a value of 119 @ref SPI_Master_InterData_Idleness */ 120 121 uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode 122 and automatic management in order to avoid overrun condition. 123 This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/ 124 125 uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state 126 This parameter can be a value of @ref SPI_Master_Keep_IO_State */ 127 128 uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions 129 This parameter can be a value of @ref SPI_IO_Swap */ 130 131 uint32_t ReadyMasterManagement; /*!< Specifies if RDY Signal is managed internally or not. 132 This parameter can be a value of @ref SPI_RDY_Master_Management */ 133 134 uint32_t ReadyPolarity; /*!< Specifies which level of RDY Signal input (present on RDY pin) 135 is considered as active one. 136 This parameter can be a value of @ref SPI_RDY_Polarity */ 137 } SPI_InitTypeDef; 138 139 /** 140 * @brief HAL SPI State structure definition 141 */ 142 typedef enum 143 { 144 HAL_SPI_STATE_RESET = 0x00UL, /*!< Peripheral not Initialized */ 145 HAL_SPI_STATE_READY = 0x01UL, /*!< Peripheral Initialized and ready for use */ 146 HAL_SPI_STATE_BUSY = 0x02UL, /*!< an internal process is ongoing */ 147 HAL_SPI_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */ 148 HAL_SPI_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */ 149 HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */ 150 HAL_SPI_STATE_ERROR = 0x06UL, /*!< SPI error state */ 151 HAL_SPI_STATE_ABORT = 0x07UL /*!< SPI abort is ongoing */ 152 } HAL_SPI_StateTypeDef; 153 154 155 /** 156 * @brief SPI handle Structure definition 157 */ 158 typedef struct __SPI_HandleTypeDef 159 { 160 SPI_TypeDef *Instance; /*!< SPI registers base address */ 161 162 SPI_InitTypeDef Init; /*!< SPI communication parameters */ 163 164 const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ 165 166 uint16_t TxXferSize; /*!< SPI Tx Transfer size */ 167 168 __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ 169 170 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ 171 172 uint16_t RxXferSize; /*!< SPI Rx Transfer size */ 173 174 __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ 175 176 uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ 177 178 void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ 179 180 void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ 181 182 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ 183 184 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ 185 186 HAL_LockTypeDef Lock; /*!< Locking object */ 187 188 __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ 189 190 __IO uint32_t ErrorCode; /*!< SPI Error code */ 191 192 193 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 194 void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ 195 void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ 196 void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ 197 void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ 198 void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ 199 void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ 200 void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ 201 void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ 202 void (* SuspendCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Suspend callback */ 203 void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ 204 void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ 205 206 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 207 } SPI_HandleTypeDef; 208 209 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 210 /** 211 * @brief HAL SPI Callback ID enumeration definition 212 */ 213 typedef enum 214 { 215 HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, /*!< SPI Tx Completed callback ID */ 216 HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, /*!< SPI Rx Completed callback ID */ 217 HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< SPI TxRx Completed callback ID */ 218 HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< SPI Tx Half Completed callback ID */ 219 HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< SPI Rx Half Completed callback ID */ 220 HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */ 221 HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */ 222 HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */ 223 HAL_SPI_SUSPEND_CB_ID = 0x08UL, /*!< SPI Suspend callback ID */ 224 HAL_SPI_MSPINIT_CB_ID = 0x09UL, /*!< SPI Msp Init callback ID */ 225 HAL_SPI_MSPDEINIT_CB_ID = 0x0AUL /*!< SPI Msp DeInit callback ID */ 226 227 } HAL_SPI_CallbackIDTypeDef; 228 229 /** 230 * @brief HAL SPI Callback pointer definition 231 */ 232 typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ 233 234 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 235 /** 236 * @} 237 */ 238 239 /* Exported constants --------------------------------------------------------*/ 240 241 /** @defgroup SPI_Exported_Constants SPI Exported Constants 242 * @{ 243 */ 244 245 /** @defgroup SPI_FIFO_Type SPI FIFO Type 246 * @{ 247 */ 248 #define SPI_LOWEND_FIFO_SIZE 8UL 249 #define SPI_HIGHEND_FIFO_SIZE 16UL 250 /** 251 * @} 252 */ 253 254 /** @defgroup SPI_Error_Code SPI Error Codes 255 * @{ 256 */ 257 #define HAL_SPI_ERROR_NONE (0x00000000UL) /*!< No error */ 258 #define HAL_SPI_ERROR_MODF (0x00000001UL) /*!< MODF error */ 259 #define HAL_SPI_ERROR_CRC (0x00000002UL) /*!< CRC error */ 260 #define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */ 261 #define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */ 262 #define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */ 263 #define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXP/TXP/DXP/FTLVL/FRLVL Flag */ 264 #define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */ 265 #define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */ 266 #define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */ 267 #define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */ 268 #define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */ 269 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 270 #define HAL_SPI_ERROR_INVALID_CALLBACK (0x00001000UL) /*!< Invalid Callback error */ 271 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 272 /** 273 * @} 274 */ 275 276 /** @defgroup SPI_Mode SPI Mode 277 * @{ 278 */ 279 #define SPI_MODE_SLAVE (0x00000000UL) 280 #define SPI_MODE_MASTER SPI_CFG2_MASTER 281 /** 282 * @} 283 */ 284 285 /** @defgroup SPI_Direction SPI Direction Mode 286 * @{ 287 */ 288 #define SPI_DIRECTION_2LINES (0x00000000UL) 289 #define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0 290 #define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1 291 #define SPI_DIRECTION_1LINE SPI_CFG2_COMM 292 /** 293 * @} 294 */ 295 296 /** @defgroup SPI_Data_Size SPI Data Size 297 * @{ 298 */ 299 #define SPI_DATASIZE_4BIT (0x00000003UL) 300 #define SPI_DATASIZE_5BIT (0x00000004UL) 301 #define SPI_DATASIZE_6BIT (0x00000005UL) 302 #define SPI_DATASIZE_7BIT (0x00000006UL) 303 #define SPI_DATASIZE_8BIT (0x00000007UL) 304 #define SPI_DATASIZE_9BIT (0x00000008UL) 305 #define SPI_DATASIZE_10BIT (0x00000009UL) 306 #define SPI_DATASIZE_11BIT (0x0000000AUL) 307 #define SPI_DATASIZE_12BIT (0x0000000BUL) 308 #define SPI_DATASIZE_13BIT (0x0000000CUL) 309 #define SPI_DATASIZE_14BIT (0x0000000DUL) 310 #define SPI_DATASIZE_15BIT (0x0000000EUL) 311 #define SPI_DATASIZE_16BIT (0x0000000FUL) 312 #define SPI_DATASIZE_17BIT (0x00000010UL) 313 #define SPI_DATASIZE_18BIT (0x00000011UL) 314 #define SPI_DATASIZE_19BIT (0x00000012UL) 315 #define SPI_DATASIZE_20BIT (0x00000013UL) 316 #define SPI_DATASIZE_21BIT (0x00000014UL) 317 #define SPI_DATASIZE_22BIT (0x00000015UL) 318 #define SPI_DATASIZE_23BIT (0x00000016UL) 319 #define SPI_DATASIZE_24BIT (0x00000017UL) 320 #define SPI_DATASIZE_25BIT (0x00000018UL) 321 #define SPI_DATASIZE_26BIT (0x00000019UL) 322 #define SPI_DATASIZE_27BIT (0x0000001AUL) 323 #define SPI_DATASIZE_28BIT (0x0000001BUL) 324 #define SPI_DATASIZE_29BIT (0x0000001CUL) 325 #define SPI_DATASIZE_30BIT (0x0000001DUL) 326 #define SPI_DATASIZE_31BIT (0x0000001EUL) 327 #define SPI_DATASIZE_32BIT (0x0000001FUL) 328 /** 329 * @} 330 */ 331 332 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity 333 * @{ 334 */ 335 #define SPI_POLARITY_LOW (0x00000000UL) 336 #define SPI_POLARITY_HIGH SPI_CFG2_CPOL 337 /** 338 * @} 339 */ 340 341 /** @defgroup SPI_Clock_Phase SPI Clock Phase 342 * @{ 343 */ 344 #define SPI_PHASE_1EDGE (0x00000000UL) 345 #define SPI_PHASE_2EDGE SPI_CFG2_CPHA 346 /** 347 * @} 348 */ 349 350 /** @defgroup SPI_Slave_Select_Management SPI Slave Select Management 351 * @{ 352 */ 353 #define SPI_NSS_SOFT SPI_CFG2_SSM 354 #define SPI_NSS_HARD_INPUT (0x00000000UL) 355 #define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE 356 /** 357 * @} 358 */ 359 360 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode 361 * @{ 362 */ 363 #define SPI_NSS_PULSE_DISABLE (0x00000000UL) 364 #define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM 365 /** 366 * @} 367 */ 368 369 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler 370 * @{ 371 */ 372 #define SPI_BAUDRATEPRESCALER_BYPASS (0x80000000UL) 373 #define SPI_BAUDRATEPRESCALER_2 (0x00000000UL) 374 #define SPI_BAUDRATEPRESCALER_4 (0x10000000UL) 375 #define SPI_BAUDRATEPRESCALER_8 (0x20000000UL) 376 #define SPI_BAUDRATEPRESCALER_16 (0x30000000UL) 377 #define SPI_BAUDRATEPRESCALER_32 (0x40000000UL) 378 #define SPI_BAUDRATEPRESCALER_64 (0x50000000UL) 379 #define SPI_BAUDRATEPRESCALER_128 (0x60000000UL) 380 #define SPI_BAUDRATEPRESCALER_256 (0x70000000UL) 381 /** 382 * @} 383 */ 384 385 /** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission 386 * @{ 387 */ 388 #define SPI_FIRSTBIT_MSB (0x00000000UL) 389 #define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST 390 /** 391 * @} 392 */ 393 394 /** @defgroup SPI_TI_Mode SPI TI Mode 395 * @{ 396 */ 397 #define SPI_TIMODE_DISABLE (0x00000000UL) 398 #define SPI_TIMODE_ENABLE SPI_CFG2_SP_0 399 /** 400 * @} 401 */ 402 403 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation 404 * @{ 405 */ 406 #define SPI_CRCCALCULATION_DISABLE (0x00000000UL) 407 #define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN 408 /** 409 * @} 410 */ 411 412 /** @defgroup SPI_CRC_length SPI CRC Length 413 * @{ 414 */ 415 #define SPI_CRC_LENGTH_DATASIZE (0x00000000UL) 416 #define SPI_CRC_LENGTH_4BIT (0x00030000UL) 417 #define SPI_CRC_LENGTH_5BIT (0x00040000UL) 418 #define SPI_CRC_LENGTH_6BIT (0x00050000UL) 419 #define SPI_CRC_LENGTH_7BIT (0x00060000UL) 420 #define SPI_CRC_LENGTH_8BIT (0x00070000UL) 421 #define SPI_CRC_LENGTH_9BIT (0x00080000UL) 422 #define SPI_CRC_LENGTH_10BIT (0x00090000UL) 423 #define SPI_CRC_LENGTH_11BIT (0x000A0000UL) 424 #define SPI_CRC_LENGTH_12BIT (0x000B0000UL) 425 #define SPI_CRC_LENGTH_13BIT (0x000C0000UL) 426 #define SPI_CRC_LENGTH_14BIT (0x000D0000UL) 427 #define SPI_CRC_LENGTH_15BIT (0x000E0000UL) 428 #define SPI_CRC_LENGTH_16BIT (0x000F0000UL) 429 #define SPI_CRC_LENGTH_17BIT (0x00100000UL) 430 #define SPI_CRC_LENGTH_18BIT (0x00110000UL) 431 #define SPI_CRC_LENGTH_19BIT (0x00120000UL) 432 #define SPI_CRC_LENGTH_20BIT (0x00130000UL) 433 #define SPI_CRC_LENGTH_21BIT (0x00140000UL) 434 #define SPI_CRC_LENGTH_22BIT (0x00150000UL) 435 #define SPI_CRC_LENGTH_23BIT (0x00160000UL) 436 #define SPI_CRC_LENGTH_24BIT (0x00170000UL) 437 #define SPI_CRC_LENGTH_25BIT (0x00180000UL) 438 #define SPI_CRC_LENGTH_26BIT (0x00190000UL) 439 #define SPI_CRC_LENGTH_27BIT (0x001A0000UL) 440 #define SPI_CRC_LENGTH_28BIT (0x001B0000UL) 441 #define SPI_CRC_LENGTH_29BIT (0x001C0000UL) 442 #define SPI_CRC_LENGTH_30BIT (0x001D0000UL) 443 #define SPI_CRC_LENGTH_31BIT (0x001E0000UL) 444 #define SPI_CRC_LENGTH_32BIT (0x001F0000UL) 445 /** 446 * @} 447 */ 448 449 /** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold 450 * @{ 451 */ 452 #define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL) 453 #define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL) 454 #define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL) 455 #define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL) 456 #define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL) 457 #define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL) 458 #define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL) 459 #define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL) 460 #define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL) 461 #define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL) 462 #define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL) 463 #define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL) 464 #define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL) 465 #define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL) 466 #define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL) 467 #define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL) 468 /** 469 * @} 470 */ 471 472 /** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern 473 * @{ 474 */ 475 #define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL) 476 #define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL) 477 /** 478 * @} 479 */ 480 481 /** @defgroup SPI_NSS_Polarity SPI NSS Polarity 482 * @{ 483 */ 484 #define SPI_NSS_POLARITY_LOW (0x00000000UL) 485 #define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP 486 /** 487 * @} 488 */ 489 490 /** @defgroup SPI_Master_Keep_IO_State Keep IO State 491 * @{ 492 */ 493 #define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL) 494 #define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR 495 /** 496 * @} 497 */ 498 499 /** @defgroup SPI_IO_Swap Control SPI IO Swap 500 * @{ 501 */ 502 #define SPI_IO_SWAP_DISABLE (0x00000000UL) 503 #define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP 504 /** 505 * @} 506 */ 507 508 /** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness 509 * @{ 510 */ 511 #define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL) 512 #define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL) 513 #define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL) 514 #define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL) 515 #define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL) 516 #define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL) 517 #define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL) 518 #define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL) 519 #define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL) 520 #define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL) 521 #define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL) 522 #define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL) 523 #define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL) 524 #define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL) 525 #define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL) 526 #define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL) 527 /** 528 * @} 529 */ 530 531 /** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness 532 * @{ 533 */ 534 #define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL) 535 #define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL) 536 #define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL) 537 #define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL) 538 #define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL) 539 #define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL) 540 #define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL) 541 #define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL) 542 #define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL) 543 #define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL) 544 #define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL) 545 #define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL) 546 #define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL) 547 #define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL) 548 #define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL) 549 #define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL) 550 /** 551 * @} 552 */ 553 554 /** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend 555 * @{ 556 */ 557 #define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL) 558 #define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX 559 /** 560 * @} 561 */ 562 563 /** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior 564 * @{ 565 */ 566 #define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL) 567 #define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG 568 /** 569 * @} 570 */ 571 572 /** @defgroup SPI_RDY_Master_Management SPI RDY Signal Input Master Management 573 * @{ 574 */ 575 #define SPI_RDY_MASTER_MANAGEMENT_INTERNALLY (0x00000000UL) 576 #define SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY SPI_CFG2_RDIMM 577 /** 578 * @} 579 */ 580 581 /** @defgroup SPI_RDY_Polarity SPI RDY Signal Input/Output Polarity 582 * @{ 583 */ 584 #define SPI_RDY_POLARITY_HIGH (0x00000000UL) 585 #define SPI_RDY_POLARITY_LOW SPI_CFG2_RDIOP 586 /** 587 * @} 588 */ 589 590 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition 591 * @{ 592 */ 593 #define SPI_IT_RXP SPI_IER_RXPIE 594 #define SPI_IT_TXP SPI_IER_TXPIE 595 #define SPI_IT_DXP SPI_IER_DXPIE 596 #define SPI_IT_EOT SPI_IER_EOTIE 597 #define SPI_IT_TXTF SPI_IER_TXTFIE 598 #define SPI_IT_UDR SPI_IER_UDRIE 599 #define SPI_IT_OVR SPI_IER_OVRIE 600 #define SPI_IT_CRCERR SPI_IER_CRCEIE 601 #define SPI_IT_FRE SPI_IER_TIFREIE 602 #define SPI_IT_MODF SPI_IER_MODFIE 603 #define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR) 604 /** 605 * @} 606 */ 607 608 /** @defgroup SPI_Flags_definition SPI Flags Definition 609 * @{ 610 */ 611 #define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */ 612 #define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */ 613 #define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */ 614 #define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */ 615 #define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */ 616 #define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */ 617 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */ 618 #define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */ 619 #define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */ 620 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */ 621 #define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */ 622 #define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */ 623 #define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */ 624 #define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */ 625 /** 626 * @} 627 */ 628 629 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level 630 * @{ 631 */ 632 #define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */ 633 #define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) 634 #define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) 635 #define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) 636 /** 637 * @} 638 */ 639 640 /** 641 * @} 642 */ 643 644 /* Exported macros -----------------------------------------------------------*/ 645 /** @defgroup SPI_Exported_Macros SPI Exported Macros 646 * @{ 647 */ 648 649 /** @brief Reset SPI handle state. 650 * @param __HANDLE__: specifies the SPI Handle. 651 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 652 * @retval None 653 */ 654 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 655 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 656 (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ 657 (__HANDLE__)->MspInitCallback = NULL; \ 658 (__HANDLE__)->MspDeInitCallback = NULL; \ 659 } while(0) 660 #else 661 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) 662 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 663 664 /** @brief Enable the specified SPI interrupts. 665 * @param __HANDLE__: specifies the SPI Handle. 666 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 667 * @param __INTERRUPT__: specifies the interrupt source to enable or disable. 668 * This parameter can be one of the following values: 669 * @arg SPI_IT_RXP : Rx-Packet available interrupt 670 * @arg SPI_IT_TXP : Tx-Packet space available interrupt 671 * @arg SPI_IT_DXP : Duplex Packet interrupt 672 * @arg SPI_IT_EOT : End of transfer interrupt 673 * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt 674 * @arg SPI_IT_UDR : Underrun interrupt 675 * @arg SPI_IT_OVR : Overrun interrupt 676 * @arg SPI_IT_CRCERR : CRC error interrupt 677 * @arg SPI_IT_FRE : TI mode frame format error interrupt 678 * @arg SPI_IT_MODF : Mode fault interrupt 679 * @arg SPI_IT_ERR : Error interrupt 680 * @retval None 681 */ 682 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 683 684 /** @brief Disable the specified SPI interrupts. 685 * @param __HANDLE__: specifies the SPI Handle. 686 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 687 * @param __INTERRUPT__: specifies the interrupt source to enable or disable. 688 * This parameter can be one of the following values: 689 * @arg SPI_IT_RXP : Rx-Packet available interrupt 690 * @arg SPI_IT_TXP : Tx-Packet space available interrupt 691 * @arg SPI_IT_DXP : Duplex Packet interrupt 692 * @arg SPI_IT_EOT : End of transfer interrupt 693 * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt 694 * @arg SPI_IT_UDR : Underrun interrupt 695 * @arg SPI_IT_OVR : Overrun interrupt 696 * @arg SPI_IT_CRCERR : CRC error interrupt 697 * @arg SPI_IT_FRE : TI mode frame format error interrupt 698 * @arg SPI_IT_MODF : Mode fault interrupt 699 * @arg SPI_IT_ERR : Error interrupt 700 * @retval None 701 */ 702 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 703 704 /** @brief Check whether the specified SPI interrupt source is enabled or not. 705 * @param __HANDLE__: specifies the SPI Handle. 706 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 707 * @param __INTERRUPT__: specifies the SPI interrupt source to check. 708 * This parameter can be one of the following values: 709 * @arg SPI_IT_RXP : Rx-Packet available interrupt 710 * @arg SPI_IT_TXP : Tx-Packet space available interrupt 711 * @arg SPI_IT_DXP : Duplex Packet interrupt 712 * @arg SPI_IT_EOT : End of transfer interrupt 713 * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt 714 * @arg SPI_IT_UDR : Underrun interrupt 715 * @arg SPI_IT_OVR : Overrun interrupt 716 * @arg SPI_IT_CRCERR : CRC error interrupt 717 * @arg SPI_IT_FRE : TI mode frame format error interrupt 718 * @arg SPI_IT_MODF : Mode fault interrupt 719 * @arg SPI_IT_ERR : Error interrupt 720 * @retval The new state of __IT__ (TRUE or FALSE). 721 */ 722 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \ 723 (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 724 725 /** @brief Check whether the specified SPI flag is set or not. 726 * @param __HANDLE__: specifies the SPI Handle. 727 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 728 * @param __FLAG__: specifies the flag to check. 729 * This parameter can be one of the following values: 730 * @arg SPI_FLAG_RXP : Rx-Packet available flag 731 * @arg SPI_FLAG_TXP : Tx-Packet space available flag 732 * @arg SPI_FLAG_DXP : Duplex Packet flag 733 * @arg SPI_FLAG_EOT : End of transfer flag 734 * @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag 735 * @arg SPI_FLAG_UDR : Underrun flag 736 * @arg SPI_FLAG_OVR : Overrun flag 737 * @arg SPI_FLAG_CRCERR : CRC error flag 738 * @arg SPI_FLAG_FRE : TI mode frame format error flag 739 * @arg SPI_FLAG_MODF : Mode fault flag 740 * @arg SPI_FLAG_SUSP : Transfer suspend complete flag 741 * @arg SPI_FLAG_TXC : TxFIFO transmission complete flag 742 * @arg SPI_FLAG_FRLVL : Fifo reception level flag 743 * @arg SPI_FLAG_RXWNE : RxFIFO word not empty flag 744 * @retval The new state of __FLAG__ (TRUE or FALSE). 745 */ 746 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 747 748 /** @brief Clear the SPI CRCERR pending flag. 749 * @param __HANDLE__: specifies the SPI Handle. 750 * @retval None 751 */ 752 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC) 753 754 /** @brief Clear the SPI MODF pending flag. 755 * @param __HANDLE__: specifies the SPI Handle. 756 * @retval None 757 */ 758 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC)); 759 760 /** @brief Clear the SPI OVR pending flag. 761 * @param __HANDLE__: specifies the SPI Handle. 762 * @retval None 763 */ 764 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC) 765 766 /** @brief Clear the SPI FRE pending flag. 767 * @param __HANDLE__: specifies the SPI Handle. 768 * @retval None 769 */ 770 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC) 771 772 /** @brief Clear the SPI UDR pending flag. 773 * @param __HANDLE__: specifies the SPI Handle. 774 * @retval None 775 */ 776 #define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC) 777 778 /** @brief Clear the SPI EOT pending flag. 779 * @param __HANDLE__: specifies the SPI Handle. 780 * @retval None 781 */ 782 #define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC) 783 784 /** @brief Clear the SPI UDR pending flag. 785 * @param __HANDLE__: specifies the SPI Handle. 786 * @retval None 787 */ 788 #define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC) 789 790 /** @brief Clear the SPI SUSP pending flag. 791 * @param __HANDLE__: specifies the SPI Handle. 792 * @retval None 793 */ 794 #define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC) 795 796 /** @brief Enable the SPI peripheral. 797 * @param __HANDLE__: specifies the SPI Handle. 798 * @retval None 799 */ 800 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) 801 802 /** @brief Disable the SPI peripheral. 803 * @param __HANDLE__: specifies the SPI Handle. 804 * @retval None 805 */ 806 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) 807 /** 808 * @} 809 */ 810 811 812 /* Include SPI HAL Extension module */ 813 #include "stm32wbaxx_hal_spi_ex.h" 814 815 816 /* Exported functions --------------------------------------------------------*/ 817 /** @addtogroup SPI_Exported_Functions 818 * @{ 819 */ 820 821 /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions 822 * @{ 823 */ 824 /* Initialization/de-initialization functions ********************************/ 825 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); 826 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); 827 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); 828 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); 829 830 /* Callbacks Register/UnRegister functions ***********************************/ 831 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 832 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, 833 pSPI_CallbackTypeDef pCallback); 834 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); 835 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 836 /** 837 * @} 838 */ 839 840 /** @addtogroup SPI_Exported_Functions_Group2 IO operation functions 841 * @{ 842 */ 843 /* I/O operation functions ***************************************************/ 844 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); 845 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); 846 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, 847 uint16_t Size, uint32_t Timeout); 848 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); 849 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 850 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, 851 uint16_t Size); 852 853 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); 854 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 855 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, 856 uint16_t Size); 857 858 859 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); 860 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); 861 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); 862 863 /* Transfer Abort functions */ 864 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); 865 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); 866 867 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); 868 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); 869 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); 870 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); 871 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); 872 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); 873 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); 874 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); 875 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); 876 void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi); 877 /** 878 * @} 879 */ 880 881 /** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions 882 * @{ 883 */ 884 885 /* Peripheral State and Error functions ***************************************/ 886 HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); 887 uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); 888 /** 889 * @} 890 */ 891 892 /** 893 * @} 894 */ 895 896 /* Private macros ------------------------------------------------------------*/ 897 /** @defgroup SPI_Private_Macros SPI Private Macros 898 * @{ 899 */ 900 901 /** @brief Set the SPI transmit-only mode in 1Line configuration. 902 * @param __HANDLE__: specifies the SPI Handle. 903 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 904 * @retval None 905 */ 906 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) 907 908 /** @brief Set the SPI receive-only mode in 1Line configuration. 909 * @param __HANDLE__: specifies the SPI Handle. 910 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 911 * @retval None 912 */ 913 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) 914 915 /** @brief Set the SPI transmit-only mode in 2Lines configuration. 916 * @param __HANDLE__: specifies the SPI Handle. 917 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 918 * @retval None 919 */ 920 #define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0) 921 922 /** @brief Set the SPI receive-only mode in 2Lines configuration. 923 * @param __HANDLE__: specifies the SPI Handle. 924 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 925 * @retval None 926 */ 927 #define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1) 928 929 /** @brief Set the SPI Transmit-Receive mode in 2Lines configuration. 930 * @param __HANDLE__: specifies the SPI Handle. 931 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 932 * @retval None 933 */ 934 #define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL) 935 936 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ 937 ((MODE) == SPI_MODE_MASTER)) 938 939 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ 940 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ 941 ((MODE) == SPI_DIRECTION_1LINE) || \ 942 ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) 943 944 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) 945 946 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ 947 ((MODE) == SPI_DIRECTION_1LINE) || \ 948 ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) 949 950 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ 951 ((MODE) == SPI_DIRECTION_1LINE) || \ 952 ((MODE) == SPI_DIRECTION_2LINES_RXONLY)) 953 954 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \ 955 ((DATASIZE) == SPI_DATASIZE_31BIT) || \ 956 ((DATASIZE) == SPI_DATASIZE_30BIT) || \ 957 ((DATASIZE) == SPI_DATASIZE_29BIT) || \ 958 ((DATASIZE) == SPI_DATASIZE_28BIT) || \ 959 ((DATASIZE) == SPI_DATASIZE_27BIT) || \ 960 ((DATASIZE) == SPI_DATASIZE_26BIT) || \ 961 ((DATASIZE) == SPI_DATASIZE_25BIT) || \ 962 ((DATASIZE) == SPI_DATASIZE_24BIT) || \ 963 ((DATASIZE) == SPI_DATASIZE_23BIT) || \ 964 ((DATASIZE) == SPI_DATASIZE_22BIT) || \ 965 ((DATASIZE) == SPI_DATASIZE_21BIT) || \ 966 ((DATASIZE) == SPI_DATASIZE_20BIT) || \ 967 ((DATASIZE) == SPI_DATASIZE_22BIT) || \ 968 ((DATASIZE) == SPI_DATASIZE_19BIT) || \ 969 ((DATASIZE) == SPI_DATASIZE_18BIT) || \ 970 ((DATASIZE) == SPI_DATASIZE_17BIT) || \ 971 ((DATASIZE) == SPI_DATASIZE_16BIT) || \ 972 ((DATASIZE) == SPI_DATASIZE_15BIT) || \ 973 ((DATASIZE) == SPI_DATASIZE_14BIT) || \ 974 ((DATASIZE) == SPI_DATASIZE_13BIT) || \ 975 ((DATASIZE) == SPI_DATASIZE_12BIT) || \ 976 ((DATASIZE) == SPI_DATASIZE_11BIT) || \ 977 ((DATASIZE) == SPI_DATASIZE_10BIT) || \ 978 ((DATASIZE) == SPI_DATASIZE_9BIT) || \ 979 ((DATASIZE) == SPI_DATASIZE_8BIT) || \ 980 ((DATASIZE) == SPI_DATASIZE_7BIT) || \ 981 ((DATASIZE) == SPI_DATASIZE_6BIT) || \ 982 ((DATASIZE) == SPI_DATASIZE_5BIT) || \ 983 ((DATASIZE) == SPI_DATASIZE_4BIT)) 984 985 /** 986 * @brief DataSize for limited instance 987 */ 988 #define IS_SPI_LIMITED_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ 989 ((DATASIZE) == SPI_DATASIZE_8BIT)) 990 991 #define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \ 992 ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \ 993 ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \ 994 ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \ 995 ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \ 996 ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \ 997 ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \ 998 ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \ 999 ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \ 1000 ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \ 1001 ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \ 1002 ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \ 1003 ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \ 1004 ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \ 1005 ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \ 1006 ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA)) 1007 1008 /** 1009 * @brief FifoThreshold for limited instance 1010 */ 1011 #define IS_SPI_LIMITED_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \ 1012 ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \ 1013 ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \ 1014 ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \ 1015 ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \ 1016 ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \ 1017 ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \ 1018 ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA)) 1019 1020 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ 1021 ((CPOL) == SPI_POLARITY_HIGH)) 1022 1023 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ 1024 ((CPHA) == SPI_PHASE_2EDGE)) 1025 1026 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ 1027 ((NSS) == SPI_NSS_HARD_INPUT) || \ 1028 ((NSS) == SPI_NSS_HARD_OUTPUT)) 1029 1030 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ 1031 ((NSSP) == SPI_NSS_PULSE_DISABLE)) 1032 1033 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_BYPASS) || \ 1034 ((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ 1035 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ 1036 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ 1037 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ 1038 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ 1039 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ 1040 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ 1041 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) 1042 1043 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ 1044 ((BIT) == SPI_FIRSTBIT_LSB)) 1045 1046 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ 1047 ((MODE) == SPI_TIMODE_ENABLE)) 1048 1049 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ 1050 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) 1051 1052 #define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \ 1053 ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)) 1054 1055 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \ 1056 ((LENGTH) == SPI_CRC_LENGTH_32BIT) || \ 1057 ((LENGTH) == SPI_CRC_LENGTH_31BIT) || \ 1058 ((LENGTH) == SPI_CRC_LENGTH_30BIT) || \ 1059 ((LENGTH) == SPI_CRC_LENGTH_29BIT) || \ 1060 ((LENGTH) == SPI_CRC_LENGTH_28BIT) || \ 1061 ((LENGTH) == SPI_CRC_LENGTH_27BIT) || \ 1062 ((LENGTH) == SPI_CRC_LENGTH_26BIT) || \ 1063 ((LENGTH) == SPI_CRC_LENGTH_25BIT) || \ 1064 ((LENGTH) == SPI_CRC_LENGTH_24BIT) || \ 1065 ((LENGTH) == SPI_CRC_LENGTH_23BIT) || \ 1066 ((LENGTH) == SPI_CRC_LENGTH_22BIT) || \ 1067 ((LENGTH) == SPI_CRC_LENGTH_21BIT) || \ 1068 ((LENGTH) == SPI_CRC_LENGTH_20BIT) || \ 1069 ((LENGTH) == SPI_CRC_LENGTH_19BIT) || \ 1070 ((LENGTH) == SPI_CRC_LENGTH_18BIT) || \ 1071 ((LENGTH) == SPI_CRC_LENGTH_17BIT) || \ 1072 ((LENGTH) == SPI_CRC_LENGTH_16BIT) || \ 1073 ((LENGTH) == SPI_CRC_LENGTH_15BIT) || \ 1074 ((LENGTH) == SPI_CRC_LENGTH_14BIT) || \ 1075 ((LENGTH) == SPI_CRC_LENGTH_13BIT) || \ 1076 ((LENGTH) == SPI_CRC_LENGTH_12BIT) || \ 1077 ((LENGTH) == SPI_CRC_LENGTH_11BIT) || \ 1078 ((LENGTH) == SPI_CRC_LENGTH_10BIT) || \ 1079 ((LENGTH) == SPI_CRC_LENGTH_9BIT) || \ 1080 ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ 1081 ((LENGTH) == SPI_CRC_LENGTH_7BIT) || \ 1082 ((LENGTH) == SPI_CRC_LENGTH_6BIT) || \ 1083 ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ 1084 ((LENGTH) == SPI_CRC_LENGTH_4BIT)) 1085 1086 /** 1087 * @brief CRC Length for limited instance 1088 */ 1089 #define IS_SPI_LIMITED_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ 1090 ((LENGTH) == SPI_CRC_LENGTH_16BIT)) 1091 1092 1093 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) 1094 1095 1096 1097 #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ 1098 ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED)) 1099 1100 #define IS_SPI_RDY_MASTER_MANAGEMENT(MANAGEMENT) (((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_INTERNALLY) || \ 1101 ((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY)) 1102 1103 #define IS_SPI_RDY_POLARITY(POLARITY) (((POLARITY) == SPI_RDY_POLARITY_HIGH) || \ 1104 ((POLARITY) == SPI_RDY_POLARITY_LOW)) 1105 1106 #define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ 1107 ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) 1108 /** 1109 * @} 1110 */ 1111 1112 /** 1113 * @} 1114 */ 1115 1116 /** 1117 * @} 1118 */ 1119 1120 #ifdef __cplusplus 1121 } 1122 #endif 1123 1124 #endif /* STM32WBAxx_HAL_SPI_H */ 1125 1126 /** 1127 * @} 1128 */ 1129
