1 /** 2 ****************************************************************************** 3 * @file stm32wbaxx_hal_ramcfg.h 4 * @author MCD Application Team 5 * @brief Header file of RAMCFG HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBAxx_HAL_RAMCFG_H 21 #define STM32WBAxx_HAL_RAMCFG_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbaxx_hal_def.h" 29 30 /** @addtogroup STM32WBAxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RAMCFG 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup RAMCFG_Exported_Types RAMCFG Exported Types 41 * @brief RAMCFG Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief HAL RAMCFG State Enumeration Definition 47 */ 48 typedef enum 49 { 50 HAL_RAMCFG_STATE_RESET = 0x00U, /*!< RAMCFG not yet initialized or disabled */ 51 HAL_RAMCFG_STATE_READY = 0x01U, /*!< RAMCFG initialized and ready for use */ 52 HAL_RAMCFG_STATE_BUSY = 0x02U, /*!< RAMCFG process is ongoing */ 53 HAL_RAMCFG_STATE_ERROR = 0x03U, /*!< RAMCFG error state */ 54 } HAL_RAMCFG_StateTypeDef; 55 56 #if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1) 57 /** 58 * @brief HAL RAMCFG Callbacks IDs Enumeration Definition 59 */ 60 typedef enum 61 { 62 HAL_RAMCFG_MSPINIT_CB_ID = 0x00U, /*!< RAMCFG MSP Init Callback ID */ 63 HAL_RAMCFG_MSPDEINIT_CB_ID = 0x01U, /*!< RAMCFG MSP DeInit Callback ID */ 64 HAL_RAMCFG_PE_DETECT_CB_ID = 0x02U, /*!< RAMCFG Parity Error Detect Callback ID */ 65 HAL_RAMCFG_ALL_CB_ID = 0x03U, /*!< RAMCFG All callback ID */ 66 } HAL_RAMCFG_CallbackIDTypeDef; 67 #endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ 68 69 /** 70 * @brief RAMCFG Handle Structure Definition 71 */ 72 #if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1U) 73 typedef struct __RAMCFG_HandleTypeDef 74 #else 75 typedef struct 76 #endif /* (USE_HAL_RAMCFG_REGISTER_CALLBACKS) */ 77 { 78 RAMCFG_TypeDef *Instance; /*!< RAMCFG Register Base Address */ 79 __IO HAL_RAMCFG_StateTypeDef State; /*!< RAMCFG State */ 80 __IO uint32_t ErrorCode; /*!< RAMCFG Error Code */ 81 #if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1U) 82 void (* MspInitCallback)(struct __RAMCFG_HandleTypeDef *hramcfg); /*!< RAMCFG MSP Init Callback */ 83 void (* MspDeInitCallback)(struct __RAMCFG_HandleTypeDef *hramcfg); /*!< RAMCFG MSP DeInit Callback */ 84 void (* DetectParityErrorCallback)(struct __RAMCFG_HandleTypeDef *hramcfg); /*!< RAMCFG Parity Error Detect Callback */ 85 #endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ 86 } RAMCFG_HandleTypeDef; 87 88 /** 89 * @brief RAMCFG Parity Error Address Register Definition 90 */ 91 typedef struct 92 { 93 uint32_t Byte; /*!< Byte parity error flag */ 94 /*!< 1xxx: parity error detected on 4th byte in word aligned address */ 95 /*!< x1xx: parity error detected on 3rd byte in word aligned address */ 96 /*!< xx1x: parity error detected on 2th byte in word aligned address */ 97 /*!< xxx1: parity error detected on 1st byte in word aligned address */ 98 uint32_t BusMasterId; /*!< Parity error AHB bus master ID */ 99 uint32_t AddressOffset; /*!< Parity error SRAM word aligned address offset */ 100 } RAMCFG_PEAddressTypeDef; 101 102 /** 103 * @} 104 */ 105 106 /* Exported constants --------------------------------------------------------*/ 107 108 /** @defgroup RAMCFG_Exported_Constants RAMCFG Exported Constants 109 * @brief RAMCFG Exported Constants 110 * @{ 111 */ 112 113 /** @defgroup RAMCFG_Error_Codes RAMCFG Error Codes 114 * @brief RAMCFG Error Codes 115 * @{ 116 */ 117 #define HAL_RAMCFG_ERROR_NONE 0x00000000U /*!< RAMCFG No Error */ 118 #define HAL_RAMCFG_ERROR_TIMEOUT 0x00000001U /*!< RAMCFG Timeout Error */ 119 #define HAL_RAMCFG_ERROR_BUSY 0x00000002U /*!< RAMCFG Busy Error */ 120 #if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1U) 121 #define HAL_RAMCFG_ERROR_INVALID_CALLBACK 0x00000003U /*!< Invalid Callback error */ 122 #endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ 123 /** 124 * @} 125 */ 126 127 /** @defgroup RAMCFG_Interrupt RAMCFG Interrupts 128 * @brief RAMCFG Interrupts 129 * @{ 130 */ 131 #define RAMCFG_IT_PARITYERR RAMCFG_IER_PEIE /*!< RAMCFG Parity Error Interrupt */ 132 #define RAMCFG_IT_NMIERR RAMCFG_IER_PENMI /*!< RAMCFG Parity Error redirected to NMI Interrupt */ 133 #define RAMCFG_IT_ALL (RAMCFG_IER_PEIE | \ 134 RAMCFG_IER_PENMI) /*!< RAMCFG All RAMCFG interrupt */ 135 /** 136 * @} 137 */ 138 139 /** @defgroup RAMCFG_FLAG RAMCFG Monitor Flags 140 * @brief RAMCFG Monitor Flags 141 * @{ 142 */ 143 #define RAMCFG_FLAG_PARITYERR RAMCFG_ISR_PED /*!< RAMCFG Parity Error Detected Flag */ 144 #define RAMCFG_FLAG_SRAMBUSY RAMCFG_ISR_SRAMBUSY /*!< RAMCFG SRAM busy Flag */ 145 #define RAMCFG_FLAGS_ALL (RAMCFG_ISR_PED | \ 146 RAMCFG_ISR_SRAMBUSY) /*!< RAMCFG All Flags */ 147 /** 148 * @} 149 */ 150 151 /** @defgroup RAMCFG_WaitState RAMCFG Wait State 152 * @brief RAMCFG Wait State 153 * @{ 154 */ 155 #define RAMCFG_WAITSTATE_0 (0U) /*!< RAMCFG 0 Wait State */ 156 #define RAMCFG_WAITSTATE_1 (RAMCFG_CR_WSC_0) /*!< RAMCFG 1 Wait State */ 157 #define RAMCFG_WAITSTATE_2 (RAMCFG_CR_WSC_1) /*!< RAMCFG 2 Wait State */ 158 #define RAMCFG_WAITSTATE_3 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_1) /*!< RAMCFG 3 Wait State */ 159 #define RAMCFG_WAITSTATE_4 (RAMCFG_CR_WSC_2) /*!< RAMCFG 4 Wait State */ 160 #define RAMCFG_WAITSTATE_5 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_2) /*!< RAMCFG 5 Wait State */ 161 #define RAMCFG_WAITSTATE_6 (RAMCFG_CR_WSC_1 | RAMCFG_CR_WSC_2) /*!< RAMCFG 6 Wait State */ 162 #define RAMCFG_WAITSTATE_7 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_1 | RAMCFG_CR_WSC_2) /*!< RAMCFG 7 Wait State */ 163 /** 164 * @} 165 */ 166 167 /** @defgroup RAMCFG_Keys RAMCFG Keys 168 * @brief RAMCFG Keys 169 * @{ 170 */ 171 #define RAMCFG_ERASE_KEY1 (0xCAU) /*!< RAMCFG launch Erase Key 1 */ 172 #define RAMCFG_ERASE_KEY2 (0x53U) /*!< RAMCFG launch Erase Key 2 */ 173 174 #define RAMCFG_PED_KEY1 (0xAEU) /*!< RAMCFG launch PED Key 1 */ 175 #define RAMCFG_PED_KEY2 (0x75U) /*!< RAMCFG launch PED Key 2 */ 176 /** 177 * @} 178 */ 179 180 /** @defgroup RAMCFG_ParityError_BusMasterId RAMCFG Parity error AHB bus master IDs 181 * @brief RAMCFG Parity error AHB bus master IDs 182 * @{ 183 */ 184 #define RAMCFG_PARITY_ERROR_CPU_ACCESS (2U) 185 #define RAMCFG_PARITY_ERROR_DEBUGGER_ACCESS (3U) 186 #define RAMCFG_PARITY_ERROR_DMA_PORT0_ACCESS (6U) 187 #define RAMCFG_PARITY_ERROR_DMA_PORT1_ACCESS (7U) 188 /** 189 * @} 190 */ 191 192 /** 193 * @} 194 */ 195 196 /* Exported macro ------------------------------------------------------------*/ 197 198 /** @defgroup RAMCFG_Exported_Macros RAMCFG Exported Macros 199 * @brief RAMCFG Exported Macros 200 * @{ 201 */ 202 203 /** 204 * @brief Enable the specified RAMCFG interrupts. 205 * @param __HANDLE__ : Specifies RAMCFG handle. 206 * @param __INTERRUPT__: Specifies the RAMCFG interrupt sources to be enabled. 207 * This parameter can be one of the following values: 208 * @arg RAMCFG_IT_PARITYERR : Parity Error Interrupt Mask. 209 * @arg RAMCFG_IT_NMIERR : Parity Error Interrupt redirection to NMI Mask. 210 * @arg RAMCFG_IT_ALL : All Interrupt Mask. 211 * @retval None 212 */ 213 #define __HAL_RAMCFG_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 214 215 /** 216 * @brief Disable the specified RAMCFG interrupts. 217 * @note This macros is used only to disable RAMCFG_IT_PARITYERR interrupt. 218 * RAMCFG_IT_NMIERR interrupt can only be disabled by global 219 * peripheral reset or system reset. 220 * @param __HANDLE__ : Specifies RAMCFG handle. 221 * @param __INTERRUPT__: Specifies the RAMCFG interrupt sources to be disabled. 222 * This parameter can be one of the following values: 223 * @arg RAMCFG_IT_PARITYERR : Parity Error Interrupt Mask. 224 * @retval None 225 */ 226 #define __HAL_RAMCFG_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) 227 228 /** 229 * @brief Check whether the specified RAMCFG interrupt source is enabled or not. 230 * @param __HANDLE__ : Specifies the RAMCFG Handle. 231 * @param __INTERRUPT__ : Specifies the RAMCFG interrupt source to check. 232 * This parameter can be one of the following values: 233 * @arg RAMCFG_IT_PARITYERR : Parity Error Interrupt Mask. 234 * @arg RAMCFG_IT_NMIERR : Parity Error Interrupt redirection to NMI Mask. 235 * @retval The new state of __INTERRUPT__ (SET or RESET). 236 */ 237 #define __HAL_RAMCFG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ 238 & (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U) 239 240 /** 241 * @brief Get the RAMCFG pending flags. 242 * @param __HANDLE__ : Specifies RAMCFG handle. 243 * @param __FLAG__ : Specifies the flag to be checked. 244 * This parameter can be one of the following values: 245 * @arg RAMCFG_FLAG_PARITYERR : Parity Error Detected Flag. 246 * @arg RAMCFG_FLAG_SRAMBUSY : SRAM Busy Flag. 247 * @retval The state of FLAG (SET or RESET). 248 */ 249 #define __HAL_RAMCFG_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__)) 250 251 /** 252 * @brief Clear the RAMCFG pending flags. 253 * @param __HANDLE__ : Specifies RAMCFG handle. 254 * @param __FLAG__ : Specifies the flag to be cleared. 255 * This parameter can be any combination of the following values: 256 * @arg RAMCFG_FLAG_PARITYERR : Parity Error Detected and Flag. 257 * @retval None. 258 */ 259 #define __HAL_RAMCFG_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))) 260 261 /** @brief Reset the RAMCFG handle state. 262 * @param __HANDLE__ : Specifies the RAMCFG Handle. 263 * @retval None. 264 */ 265 #if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1) 266 #define __HAL_RAMCFG_RESET_HANDLE_STATE(__HANDLE__) do{\ 267 (__HANDLE__)->State = HAL_RAMCFG_STATE_RESET; \ 268 (__HANDLE__)->MspInitCallback = NULL; \ 269 (__HANDLE__)->MspDeInitCallback = NULL; \ 270 }while(0) 271 #else 272 #define __HAL_RAMCFG_RESET_HANDLE_STATE(__HANDLE__) do{\ 273 (__HANDLE__)->State = HAL_RAMCFG_STATE_RESET; \ 274 }while(0) 275 #endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ 276 277 /** 278 * @} 279 */ 280 281 /* Exported functions --------------------------------------------------------*/ 282 283 /** @defgroup RAMCFG_Exported_Functions RAMCFG Exported Functions 284 * @brief RAMCFG Exported Functions 285 * @{ 286 */ 287 288 /** @defgroup RAMCFG_Exported_Functions_Group1 Initialization and De-Initialization Functions 289 * @brief Initialization and De-Initialization Functions 290 * @{ 291 */ 292 HAL_StatusTypeDef HAL_RAMCFG_Init(RAMCFG_HandleTypeDef *hramcfg); 293 HAL_StatusTypeDef HAL_RAMCFG_DeInit(RAMCFG_HandleTypeDef *hramcfg); 294 void HAL_RAMCFG_MspInit(RAMCFG_HandleTypeDef *hramcfg); 295 void HAL_RAMCFG_MspDeInit(RAMCFG_HandleTypeDef *hramcfg); 296 /** 297 * @} 298 */ 299 300 /** @defgroup RAMCFG_Exported_Functions_Group2 Parity Error Detection Functions 301 * @brief Parity Error Detection Functions 302 * @{ 303 */ 304 HAL_StatusTypeDef HAL_RAMCFG_LatchParityErrorAddress(RAMCFG_HandleTypeDef *hramcfg); 305 HAL_StatusTypeDef HAL_RAMCFG_UnlatchParityErrorAddress(RAMCFG_HandleTypeDef *hramcfg); 306 HAL_StatusTypeDef HAL_RAMCFG_EnableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications); 307 HAL_StatusTypeDef HAL_RAMCFG_DisableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications); 308 uint32_t HAL_RAMCFG_IsParityErrorDetected(const RAMCFG_HandleTypeDef *hramcfg); 309 HAL_StatusTypeDef HAL_RAMCFG_GetParityErrorAddress(const RAMCFG_HandleTypeDef *hramcfg, RAMCFG_PEAddressTypeDef *sPEAddress); 310 /** 311 * @} 312 */ 313 314 /** @defgroup RAMCFG_Exported_Functions_Group3 Configure Wait State Functions 315 * @brief Configure Wait State Functions 316 * @{ 317 */ 318 HAL_StatusTypeDef HAL_RAMCFG_ConfigWaitState(RAMCFG_HandleTypeDef *hramcfg, uint32_t WaitState); 319 uint32_t HAL_RAMCFG_GetWaitState(const RAMCFG_HandleTypeDef *hramcfg); 320 /** 321 * @} 322 */ 323 324 /** @defgroup RAMCFG_Exported_Functions_Group4 Write Protection Functions 325 * @brief Write Protection Functions 326 * @{ 327 */ 328 HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg, uint32_t StartPage, uint32_t NbPage); 329 /** 330 * @} 331 */ 332 333 /** @defgroup RAMCFG_Exported_Functions_Group5 Erase Operation Functions 334 * @brief Erase Operation Functions 335 * @{ 336 */ 337 HAL_StatusTypeDef HAL_RAMCFG_Erase(RAMCFG_HandleTypeDef *hramcfg); 338 /** 339 * @} 340 */ 341 342 /** @defgroup RAMCFG_Exported_Functions_Group6 Handle Interrupt and Callbacks Functions 343 * @brief Handle Interrupt and Callbacks Functions 344 * @{ 345 */ 346 void HAL_RAMCFG_IRQHandler(RAMCFG_HandleTypeDef *hramcfg); 347 void HAL_RAMCFG_DetectParityErrorCallback(RAMCFG_HandleTypeDef *hramcfg); 348 #if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1) 349 HAL_StatusTypeDef HAL_RAMCFG_RegisterCallback(RAMCFG_HandleTypeDef *hramcfg, 350 HAL_RAMCFG_CallbackIDTypeDef CallbackID, 351 void (* pCallback)(RAMCFG_HandleTypeDef *_hramcfg)); 352 HAL_StatusTypeDef HAL_RAMCFG_UnRegisterCallback(RAMCFG_HandleTypeDef *hramcfg, HAL_RAMCFG_CallbackIDTypeDef CallbackID); 353 #endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ 354 /** 355 * @} 356 */ 357 358 /** @defgroup RAMCFG_Exported_Functions_Group7 State and Error Functions 359 * @brief State and Error Functions 360 * @{ 361 */ 362 uint32_t HAL_RAMCFG_GetError(const RAMCFG_HandleTypeDef *hramcfg); 363 HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(const RAMCFG_HandleTypeDef *hramcfg); 364 /** 365 * @} 366 */ 367 368 /** 369 * @} 370 */ 371 372 /* Private Constants ---------------------------------------------------------*/ 373 374 /** @defgroup RAMCFG_Private_Constants RAMCFG Private Defines and Constants 375 * @brief RAMCFG Private Defines and Constants 376 * @{ 377 */ 378 /** 379 * @} 380 */ 381 382 /* Private macros ------------------------------------------------------------*/ 383 384 /** @defgroup RAMCFG_Private_Macros RAMCFG Private Macros 385 * @brief RAMCFG Private Macros 386 * @{ 387 */ 388 #define IS_RAMCFG_INTERRUPT(INTERRUPT) (((INTERRUPT) != 0U) &&\ 389 (((INTERRUPT) & ~(RAMCFG_IT_PARITYERR | RAMCFG_IT_NMIERR)) == 0U)) 390 391 #define IS_RAMCFG_WAITSTATE(WAITSTATE) (((WAITSTATE) == RAMCFG_WAITSTATE_0) || ((WAITSTATE) == RAMCFG_WAITSTATE_1) || \ 392 ((WAITSTATE) == RAMCFG_WAITSTATE_2) || ((WAITSTATE) == RAMCFG_WAITSTATE_3) || \ 393 ((WAITSTATE) == RAMCFG_WAITSTATE_4) || ((WAITSTATE) == RAMCFG_WAITSTATE_5) || \ 394 ((WAITSTATE) == RAMCFG_WAITSTATE_6) || ((WAITSTATE) == RAMCFG_WAITSTATE_7)) 395 396 #define IS_RAMCFG_WRITEPROTECTION_PAGE(PAGE) ((PAGE) <= 64U) 397 398 399 400 /** 401 * @} 402 */ 403 404 405 406 407 408 /* Private functions ---------------------------------------------------------*/ 409 410 /** @defgroup RAMCFG_Private_Functions RAMCFG Private Functions 411 * @brief RAMCFG Private Functions 412 * @{ 413 */ 414 /** 415 * @} 416 */ 417 418 /** 419 * @} 420 */ 421 422 /** 423 * @} 424 */ 425 426 #ifdef __cplusplus 427 } 428 #endif 429 430 431 #endif /* STM32WBAxx_HAL_RAMCFG_H */ 432 433
