1 /** 2 ********************************************************************************************************************** 3 * @file stm32wbaxx_hal_dma_ex.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL extension module. 6 ********************************************************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ********************************************************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ 20 #ifndef STM32WBAxx_HAL_DMA_EX_H 21 #define STM32WBAxx_HAL_DMA_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ----------------------------------------------------------------------------------------------------------*/ 28 #include "stm32wbaxx_hal_def.h" 29 30 /** @addtogroup STM32WBAxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMAEx 35 * @{ 36 */ 37 38 /* Exported types ----------------------------------------------------------------------------------------------------*/ 39 /** @defgroup DMAEx_Exported_Types DMAEx Exported Types 40 * @brief DMAEx Exported types 41 * @{ 42 */ 43 44 /** 45 * @brief DMAEx Data Handling Configuration Structure Definition. 46 */ 47 typedef struct 48 { 49 uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode. 50 This parameter can be a value of @ref DMAEx_Data_Exchange */ 51 52 uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode 53 This parameter can be a value of @ref DMAEx_Data_Alignment */ 54 55 } DMA_DataHandlingConfTypeDef; 56 57 /** 58 * @brief DMAEx Trigger Configuration Structure Definition. 59 */ 60 typedef struct 61 { 62 uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode. 63 This parameter can be a value of @ref DMAEx_Trigger_Mode */ 64 65 uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity. 66 This parameter can be a value of @ref DMAEx_Trigger_Polarity */ 67 68 uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection. 69 This parameter can be a value of @ref DMAEx_Trigger_Selection */ 70 71 } DMA_TriggerConfTypeDef; 72 73 /** 74 * @brief DMAEx Queue State Enumeration Definition. 75 */ 76 typedef enum 77 { 78 HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */ 79 HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */ 80 HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */ 81 82 } HAL_DMA_QStateTypeDef; 83 84 /** 85 * @brief DMAEx Linked-List Node Configuration Structure Definition. 86 */ 87 typedef struct 88 { 89 uint32_t NodeType; /*!< Specifies the DMA channel node type. 90 This parameter can be a value of @ref DMAEx_Node_Type */ 91 92 DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */ 93 94 DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */ 95 96 DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */ 97 98 uint32_t SrcAddress; /*!< Specifies the source memory address */ 99 uint32_t DstAddress; /*!< Specifies the destination memory address */ 100 uint32_t DataSize; /*!< Specifies the source data size in bytes */ 101 102 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 103 uint32_t SrcSecure; /*!< Specifies the source security attribute */ 104 uint32_t DestSecure; /*!< Specifies the destination security attribute */ 105 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 106 107 } DMA_NodeConfTypeDef; 108 109 /** 110 * @brief DMAEx Linked-List Node Structure Definition. 111 */ 112 typedef struct 113 { 114 uint32_t LinkRegisters[6U]; /*!< Physical Node register description */ 115 uint32_t NodeInfo; /*!< Node information */ 116 117 } DMA_NodeTypeDef; 118 119 /** 120 * @brief DMAEx Linked-List Queue Structure Definition. 121 */ 122 typedef struct __DMA_QListTypeDef 123 { 124 DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */ 125 126 DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */ 127 128 uint32_t NodeNumber; /*!< Specifies the queue node number */ 129 130 __IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */ 131 132 __IO uint32_t ErrorCode; /*!< Specifies the queue error code */ 133 134 __IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */ 135 136 } DMA_QListTypeDef; 137 /** 138 * @} 139 */ 140 141 /* Exported constants ------------------------------------------------------------------------------------------------*/ 142 /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants 143 * @brief DMAEx Exported Constants 144 * @{ 145 */ 146 147 /** @defgroup Queue_Error_Codes Queue Error Codes 148 * @brief Queue Error Codes 149 * @{ 150 */ 151 #define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */ 152 #define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */ 153 #define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */ 154 #define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */ 155 #define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization 156 and queue circular types are incompatible */ 157 #define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */ 158 #define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */ 159 /** 160 * @} 161 */ 162 163 /** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode 164 * @brief DMAEx LinkedList Mode 165 * @{ 166 */ 167 #define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */ 168 #define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */ 169 /** 170 * @} 171 */ 172 173 /** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment 174 * @brief DMAEx Data Alignment 175 * @{ 176 */ 177 #define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width 178 => Right aligned padded with 0 up to destination data 179 width */ 180 #define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width 181 => Right aligned left Truncated down to destination 182 data width */ 183 #define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width 184 => Right Aligned padded with sign extended up to 185 destination data width */ 186 #define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width 187 => Left Aligned Right Truncated down to the 188 destination data width */ 189 #define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width 190 => Packed at the destination data width 191 (Available only for GPDMA) */ 192 #define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width 193 => Unpacked at the destination data width 194 (Available only for GPDMA) */ 195 /** 196 * @} 197 */ 198 199 /** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange 200 * @brief DMAEx Data Exchange 201 * @{ 202 */ 203 #define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */ 204 #define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */ 205 #define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */ 206 #define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */ 207 /** 208 * @} 209 */ 210 211 /** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity 212 * @brief DMAEx Trigger Polarity 213 * @{ 214 */ 215 #define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */ 216 #define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */ 217 #define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */ 218 /** 219 * @} 220 */ 221 222 /** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode 223 * @brief DMAEx Trigger Mode 224 * @{ 225 */ 226 #define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */ 227 #define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */ 228 #define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */ 229 /** 230 * @} 231 */ 232 233 /** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection 234 * @brief DMAEx Trigger Selection 235 * @{ 236 */ 237 /* GPDMA1 triggers */ 238 #define GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */ 239 #define GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */ 240 #define GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */ 241 #define GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */ 242 #define GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */ 243 #define GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */ 244 #define GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */ 245 #define GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */ 246 #define GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */ 247 #define GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */ 248 #define GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */ 249 #define GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ 250 #define GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ 251 #if defined (LPTIM2) 252 #define GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ 253 #define GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ 254 #endif /* defined (LPTIM2) */ 255 #if defined (COMP1) 256 #define GPDMA1_TRIGGER_COMP1_OUT 15U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ 257 #endif /* defined (COMP1) */ 258 #if defined (COMP2) 259 #define GPDMA1_TRIGGER_COMP2_OUT 16U /*!< GPDMA1 HW Trigger signal is COMP2_OUT */ 260 #endif /* defined (COMP2) */ 261 #define GPDMA1_TRIGGER_RTC_ALRA_TRG 17U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */ 262 #define GPDMA1_TRIGGER_RTC_ALRB_TRG 18U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */ 263 #define GPDMA1_TRIGGER_RTC_WUT_TRG 19U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */ 264 #define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 20U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ 265 #define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 21U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ 266 #define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ 267 #define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ 268 #define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ 269 #define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ 270 #define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ 271 #define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ 272 #define GPDMA1_TRIGGER_TIM2_TRGO 28U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ 273 #define GPDMA1_TRIGGER_ADC4_AWD1 29U /*!< GPDMA1 HW Trigger signal is ADC4_ADW1 */ 274 #if defined (TIM3) 275 #define GPDMA1_TRIGGER_TIM3_TRGO 30U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ 276 #endif /* defined (TIM3) */ 277 /** 278 * @} 279 */ 280 281 /** @defgroup DMAEx_Node_Type DMAEx Node Type 282 * @brief DMAEx Node Type 283 * @{ 284 */ 285 #define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port 291 * @brief DMAEx Linked-List Allocated Port 292 * @{ 293 */ 294 #define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */ 295 #define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */ 296 /** 297 * @} 298 */ 299 300 /** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode 301 * @brief DMAEx Link Step Mode 302 * @{ 303 */ 304 #define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */ 305 #define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */ 306 /** 307 * @} 308 */ 309 310 /** 311 * @} 312 */ 313 314 /* Exported functions ------------------------------------------------------------------------------------------------*/ 315 /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions 316 * @brief DMAEx Exported functions 317 * @{ 318 */ 319 320 /** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions 321 * @brief Linked-List Initialization and De-Initialization Functions 322 * @{ 323 */ 324 HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma); 325 HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma); 326 /** 327 * @} 328 */ 329 330 /** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions 331 * @brief Linked-List IO Operation Functions 332 * @{ 333 */ 334 HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma); 335 HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma); 336 /** 337 * @} 338 */ 339 340 /** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions 341 * @brief Linked-List Management Functions 342 * @{ 343 */ 344 HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, 345 DMA_NodeTypeDef *const pNode); 346 HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, 347 DMA_NodeTypeDef const *const pNode); 348 349 HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, 350 DMA_NodeTypeDef *const pPrevNode, 351 DMA_NodeTypeDef *const pNewNode); 352 HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, 353 DMA_NodeTypeDef *const pNewNode); 354 HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, 355 DMA_NodeTypeDef *const pNewNode); 356 357 HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, 358 DMA_NodeTypeDef *const pNode); 359 HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList); 360 HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList); 361 362 HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, 363 DMA_NodeTypeDef *const pOldNode, 364 DMA_NodeTypeDef *const pNewNode); 365 HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, 366 DMA_NodeTypeDef *const pNewNode); 367 HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, 368 DMA_NodeTypeDef *const pNewNode); 369 370 HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList); 371 372 HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, 373 DMA_NodeTypeDef const *const pPrevNode, 374 DMA_QListTypeDef *const pDestQList); 375 HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, 376 DMA_QListTypeDef *const pDestQList); 377 HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, 378 DMA_QListTypeDef *const pDestQList); 379 380 HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, 381 DMA_NodeTypeDef *const pFirstCircularNode); 382 HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList); 383 HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList); 384 385 HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList); 386 HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList); 387 388 HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, 389 DMA_QListTypeDef *const pQList); 390 HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma); 391 /** 392 * @} 393 */ 394 395 /** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions 396 * @brief Data Handling, Repeated Block and Trigger Configuration Functions 397 * @{ 398 */ 399 HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, 400 DMA_DataHandlingConfTypeDef const *const pConfigDataHandling); 401 HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, 402 DMA_TriggerConfTypeDef const *const pConfigTrigger); 403 /** 404 * @} 405 */ 406 407 /** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions 408 * @brief Suspend and Resume Operation Functions 409 * @{ 410 */ 411 HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma); 412 HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma); 413 HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma); 414 /** 415 * @} 416 */ 417 418 /** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function 419 * @brief FIFO Status Function 420 * @{ 421 */ 422 uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma); 423 /** 424 * @} 425 */ 426 427 /** 428 * @} 429 */ 430 431 /* Private types -----------------------------------------------------------------------------------------------------*/ 432 /** @defgroup DMAEx_Private_Types DMAEx Private Types 433 * @brief DMAEx Private Types 434 * @{ 435 */ 436 437 /** 438 * @brief DMA Node in Queue Information Structure Definition. 439 */ 440 typedef struct 441 { 442 uint32_t cllr_offset; /* CLLR register offset */ 443 444 uint32_t previousnode_addr; /* Previous node address */ 445 446 uint32_t currentnode_pos; /* Current node position */ 447 448 uint32_t currentnode_addr; /* Current node address */ 449 450 uint32_t nextnode_addr; /* Next node address */ 451 452 } DMA_NodeInQInfoTypeDef; 453 /** 454 * @} 455 */ 456 457 /* Private constants -------------------------------------------------------------------------------------------------*/ 458 /** @defgroup DMAEx_Private_Constants DMAEx Private Constants 459 * @brief DMAEx Private Constants 460 * @{ 461 */ 462 #define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */ 463 464 #define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */ 465 #define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */ 466 467 #define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */ 468 #define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */ 469 #define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */ 470 471 #define NODE_MAXIMUM_SIZE (0x0006U) /* Amount of registers of the node */ 472 473 #define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */ 474 #define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */ 475 476 #define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */ 477 #define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */ 478 479 #define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */ 480 #define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */ 481 482 #define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */ 483 #define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */ 484 485 #define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ 486 #define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */ 487 #define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */ 488 #define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */ 489 #define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */ 490 #define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */ 491 492 #define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */ 493 #define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */ 494 #define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */ 495 #define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */ 496 /** 497 * @} 498 */ 499 500 /* Private macros ----------------------------------------------------------------------------------------------------*/ 501 /** @defgroup DMAEx_Private_Macros DMAEx Private Macros 502 * @brief DMAEx Private Macros 503 * @{ 504 */ 505 #define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \ 506 (((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \ 507 ((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \ 508 ((ALIGNMENT) == DMA_DATA_PACK)) 509 510 #define IS_DMA_DATA_EXCHANGE(EXCHANGE) \ 511 (((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD))) == 0U) 512 513 #define IS_DMA_REPEAT_COUNT(COUNT) \ 514 (((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos))) 515 516 #define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \ 517 (((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \ 518 ((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX)) 519 520 #define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \ 521 (((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \ 522 ((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX)) 523 524 #define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \ 525 (((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U) 526 527 #define IS_DMA_LINK_STEP_MODE(MODE) \ 528 (((MODE) == DMA_LSM_FULL_EXECUTION) || \ 529 ((MODE) == DMA_LSM_1LINK_EXECUTION)) 530 531 #define IS_DMA_TRIGGER_MODE(MODE) \ 532 (((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \ 533 ((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \ 534 ((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER)) 535 536 #define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \ 537 (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ 538 ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ 539 ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) 540 541 #define IS_DMA_LINKEDLIST_MODE(MODE) \ 542 (((MODE) == DMA_LINKEDLIST_NORMAL) || \ 543 ((MODE) == DMA_LINKEDLIST_CIRCULAR)) 544 545 #define IS_DMA_TRIGGER_POLARITY(POLARITY) \ 546 (((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \ 547 ((POLARITY) == DMA_TRIG_POLARITY_RISING) || \ 548 ((POLARITY) == DMA_TRIG_POLARITY_FALLING)) 549 550 #if defined (TIM3) 551 #define IS_DMA_TRIGGER_SELECTION(TRIGGER) \ 552 ((TRIGGER) <= GPDMA1_TRIGGER_TIM3_TRGO) 553 #else 554 #define IS_DMA_TRIGGER_SELECTION(TRIGGER) \ 555 ((TRIGGER) <= GPDMA1_TRIGGER_ADC4_AWD1) 556 #endif /* defined (TIM3) */ 557 558 #define IS_DMA_NODE_TYPE(TYPE) \ 559 ((TYPE) == DMA_GPDMA_LINEAR_NODE) 560 /** 561 * @} 562 */ 563 564 565 /* Private functions -------------------------------------------------------------------------------------------------*/ 566 /** @defgroup DMAEx_Private_Functions DMAEx Private Functions 567 * @brief DMAEx Private Functions 568 * @{ 569 */ 570 571 /** 572 * @} 573 */ 574 575 /** 576 * @} 577 */ 578 579 /** 580 * @} 581 */ 582 583 /** 584 * @} 585 */ 586 587 #ifdef __cplusplus 588 } 589 #endif /* __cplusplus */ 590 591 #endif /* STM32WBAxx_HAL_DMA_EX_H */ 592
