1 /** 2 ********************************************************************************************************************** 3 * @file stm32wbaxx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ********************************************************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ********************************************************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ 20 #ifndef STM32WBAxx_HAL_DMA_H 21 #define STM32WBAxx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ----------------------------------------------------------------------------------------------------------*/ 28 #include "stm32wbaxx_hal_def.h" 29 30 /** @addtogroup STM32WBAxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 39 /* Exported types ----------------------------------------------------------------------------------------------------*/ 40 41 /** @defgroup DMA_Exported_Types DMA Exported Types 42 * @brief DMA Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief DMA Transfer Configuration Structure definition. 48 */ 49 typedef struct 50 { 51 uint32_t Request; /*!< Specifies the DMA channel request. 52 This parameter can be a value of @ref DMA_Request_Selection */ 53 54 uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel. 55 Block Hardware request feature can be used only with dedicated peripherals. 56 This parameter can be a value of @ref DMA_Block_Request */ 57 58 uint32_t Direction; /*!< Specifies the transfer direction for DMA channel. 59 This parameter can be a value of @ref DMA_Transfer_Direction */ 60 61 uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel. 62 This parameter can be a value of @ref DMA_Source_Increment_Mode */ 63 64 uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel. 65 This parameter can be a value of @ref DMA_Destination_Increment_Mode */ 66 67 uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel. 68 This parameter can be a value of @ref DMA_Source_Data_Width */ 69 70 uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel. 71 This parameter can be a value of @ref DMA_Destination_Data_Width */ 72 73 uint32_t Priority; /*!< Specifies the priority level for the DMA channel. 74 This parameter can be a value of @ref DMA_Priority_Level */ 75 76 uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA 77 channel. 78 This parameter can be a value between 1 and 64 */ 79 80 uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the 81 DMA channel. 82 This parameter can be a value between 1 and 64 */ 83 84 uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports. 85 This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */ 86 87 uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. 88 This parameter can be a value of @ref DMA_Transfer_Event_Mode */ 89 90 uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel. 91 This parameter can be a value of @ref DMA_Transfer_Mode */ 92 93 } DMA_InitTypeDef; 94 95 /** 96 * @brief DMA Linked-List Configuration Structure Definition. 97 */ 98 typedef struct 99 { 100 uint32_t Priority; /*!< Specifies the priority level for the DMA channel. 101 This parameter can be a value of @ref DMA_Priority_Level */ 102 103 uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel. 104 This parameter can be a value of @ref DMAEx_Link_Step_Mode */ 105 106 uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel. 107 This parameter can be a value of @ref DMAEx_Link_Allocated_Port */ 108 109 uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. 110 This parameter can be a value of @ref DMA_Transfer_Event_Mode */ 111 112 uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel. 113 This parameter can be a value of @ref DMAEx_LinkedList_Mode */ 114 115 } DMA_InitLinkedListTypeDef; 116 117 /** 118 * @brief HAL DMA State Enumeration Definition. 119 */ 120 typedef enum 121 { 122 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 123 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 124 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 125 HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ 126 HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ 127 HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */ 128 129 } HAL_DMA_StateTypeDef; 130 131 /** 132 * @brief HAL DMA Level Complete Enumeration Definition. 133 */ 134 typedef enum 135 { 136 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */ 137 HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */ 138 139 } HAL_DMA_LevelCompleteTypeDef; 140 141 /** 142 * @brief HAL DMA Callbacks IDs Enumeration Definition. 143 */ 144 typedef enum 145 { 146 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */ 147 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */ 148 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */ 149 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */ 150 HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */ 151 HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */ 152 153 } HAL_DMA_CallbackIDTypeDef; 154 155 /** 156 * @brief DMA handle Structure definition 157 */ 158 typedef struct __DMA_HandleTypeDef 159 { 160 DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */ 161 162 DMA_InitTypeDef Init; /*!< DMA channel init parameters */ 163 164 DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */ 165 166 HAL_LockTypeDef Lock; /*!< DMA locking object */ 167 168 uint32_t Mode; /*!< DMA transfer mode */ 169 170 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 171 172 __IO uint32_t ErrorCode; /*!< DMA error code */ 173 174 void *Parent; /*!< Parent object state */ 175 176 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 177 178 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */ 179 180 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 181 182 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */ 183 184 void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */ 185 186 struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */ 187 188 } DMA_HandleTypeDef; 189 /** 190 * @} 191 */ 192 193 194 /* Exported constants ------------------------------------------------------------------------------------------------*/ 195 /** @defgroup DMA_Exported_Constants DMA Exported Constants 196 * @brief DMA Exported constants 197 * @{ 198 */ 199 200 /** @defgroup DMA_Error_Codes DMA Error Codes 201 * @brief DMA Error Codes 202 * @{ 203 */ 204 #define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */ 205 #define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */ 206 #define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */ 207 #define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */ 208 #define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */ 209 #define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */ 210 #define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */ 211 #define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */ 212 #define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */ 213 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */ 214 /** 215 * @} 216 */ 217 218 /** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition 219 * @brief DMA Interrupt Enable Definition 220 * @{ 221 */ 222 #define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */ 223 #define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */ 224 #define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */ 225 #define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */ 226 #define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */ 227 #define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */ 228 #define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */ 229 /** 230 * @} 231 */ 232 233 /** @defgroup DMA_Flag_Definition DMA Flag Definition 234 * @brief DMA Flag Definition 235 * @{ 236 */ 237 #define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */ 238 #define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */ 239 #define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */ 240 #define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */ 241 #define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */ 242 #define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */ 243 #define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */ 244 #define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */ 245 /** 246 * @} 247 */ 248 249 /** @defgroup DMA_Request_Selection DMA Request Selection 250 * @brief DMA Request Selection 251 * @{ 252 */ 253 /* GPDMA1 requests */ 254 #define GPDMA1_REQUEST_ADC4 0U /*!< GPDMA1 HW request is ADC4 */ 255 #if defined (SPI1) 256 #define GPDMA1_REQUEST_SPI1_RX 1U /*!< GPDMA1 HW request is SPI1_RX */ 257 #define GPDMA1_REQUEST_SPI1_TX 2U /*!< GPDMA1 HW request is SPI1_TX */ 258 #endif /* defined (SPI1) */ 259 #define GPDMA1_REQUEST_SPI3_RX 3U /*!< GPDMA1 HW request is SPI3_RX */ 260 #define GPDMA1_REQUEST_SPI3_TX 4U /*!< GPDMA1 HW request is SPI3_TX */ 261 #if defined (I2C1) 262 #define GPDMA1_REQUEST_I2C1_RX 5U /*!< GPDMA1 HW request is I2C1_RX */ 263 #define GPDMA1_REQUEST_I2C1_TX 6U /*!< GPDMA1 HW request is I2C1_TX */ 264 #define GPDMA1_REQUEST_I2C1_EVC 7U /*!< GPDMA1 HW request is I2C1_EVC */ 265 #endif /* defined (I2C1) */ 266 #define GPDMA1_REQUEST_I2C3_RX 8U /*!< GPDMA1 HW request is I2C3_RX */ 267 #define GPDMA1_REQUEST_I2C3_TX 9U /*!< GPDMA1 HW request is I2C3_TX */ 268 #define GPDMA1_REQUEST_I2C3_EVC 10U /*!< GPDMA1 HW request is I2C3_EVC */ 269 #define GPDMA1_REQUEST_USART1_RX 11U /*!< GPDMA1 HW request is USART1_RX */ 270 #define GPDMA1_REQUEST_USART1_TX 12U /*!< GPDMA1 HW request is USART1_TX */ 271 #if defined (USART2) 272 #define GPDMA1_REQUEST_USART2_RX 13U /*!< GPDMA1 HW request is USART2_RX */ 273 #define GPDMA1_REQUEST_USART2_TX 14U /*!< GPDMA1 HW request is USART2_TX */ 274 #endif /* defined (USART2) */ 275 #define GPDMA1_REQUEST_LPUART1_RX 15U /*!< GPDMA1 HW request is LPUART1_RX */ 276 #define GPDMA1_REQUEST_LPUART1_TX 16U /*!< GPDMA1 HW request is LPUART1_TX */ 277 #if defined (SAI1) 278 #define GPDMA1_REQUEST_SAI1_A 17U /*!< GPDMA1 HW request is SAI1_A */ 279 #define GPDMA1_REQUEST_SAI1_B 18U /*!< GPDMA1 HW request is SAI1_B */ 280 #endif /* defined (SAI1) */ 281 #define GPDMA1_REQUEST_TIM1_CH1 19U /*!< GPDMA1 HW request is TIM1_CH1 */ 282 #define GPDMA1_REQUEST_TIM1_CH2 20U /*!< GPDMA1 HW request is TIM1_CH2 */ 283 #define GPDMA1_REQUEST_TIM1_CH3 21U /*!< GPDMA1 HW request is TIM1_CH3 */ 284 #define GPDMA1_REQUEST_TIM1_CH4 22U /*!< GPDMA1 HW request is TIM1_CH4 */ 285 #define GPDMA1_REQUEST_TIM1_UP 23U /*!< GPDMA1 HW request is TIM1_UP */ 286 #define GPDMA1_REQUEST_TIM1_TRIG 24U /*!< GPDMA1 HW request is TIM1_TRIG */ 287 #define GPDMA1_REQUEST_TIM1_COM 25U /*!< GPDMA1 HW request is TIM1_COM */ 288 #define GPDMA1_REQUEST_TIM2_CH1 26U /*!< GPDMA1 HW request is TIM2_CH1 */ 289 #define GPDMA1_REQUEST_TIM2_CH2 27U /*!< GPDMA1 HW request is TIM2_CH2 */ 290 #define GPDMA1_REQUEST_TIM2_CH3 28U /*!< GPDMA1 HW request is TIM2_CH3 */ 291 #define GPDMA1_REQUEST_TIM2_CH4 29U /*!< GPDMA1 HW request is TIM2_CH4 */ 292 #define GPDMA1_REQUEST_TIM2_UP 30U /*!< GPDMA1 HW request is TIM2_UP */ 293 #if defined (TIM3) 294 #define GPDMA1_REQUEST_TIM3_CH1 31U /*!< GPDMA1 HW request is TIM3_CH1 */ 295 #define GPDMA1_REQUEST_TIM3_CH2 32U /*!< GPDMA1 HW request is TIM3_CH2 */ 296 #define GPDMA1_REQUEST_TIM3_CH3 33U /*!< GPDMA1 HW request is TIM3_CH3 */ 297 #define GPDMA1_REQUEST_TIM3_CH4 34U /*!< GPDMA1 HW request is TIM3_CH4 */ 298 #define GPDMA1_REQUEST_TIM3_UP 35U /*!< GPDMA1 HW request is TIM3_UP */ 299 #define GPDMA1_REQUEST_TIM3_TRIG 36U /*!< GPDMA1 HW request is TIM3_TRIG */ 300 #endif /* defined (TIM3) */ 301 #define GPDMA1_REQUEST_TIM16_CH1 37U /*!< GPDMA1 HW request is TIM16_CH1 */ 302 #define GPDMA1_REQUEST_TIM16_UP 38U /*!< GPDMA1 HW request is TIM16_UP */ 303 #if defined (TIM17) 304 #define GPDMA1_REQUEST_TIM17_CH1 39U /*!< GPDMA1 HW request is TIM17_CH1 */ 305 #define GPDMA1_REQUEST_TIM17_UP 40U /*!< GPDMA1 HW request is TIM17_UP */ 306 #endif /* defined (TIM17) */ 307 #if defined (AES) 308 #define GPDMA1_REQUEST_AES_IN 41U /*!< GPDMA1 HW request is AES_IN */ 309 #define GPDMA1_REQUEST_AES_OUT 42U /*!< GPDMA1 HW request is AES_OUT */ 310 #endif /* defined (AES) */ 311 #define GPDMA1_REQUEST_HASH_IN 43U /*!< GPDMA1 HW request is HASH_IN */ 312 #if defined (SAES) 313 #define GPDMA1_REQUEST_SAES_IN 44U /*!< GPDMA1 HW request is SAES_IN */ 314 #define GPDMA1_REQUEST_SAES_OUT 45U /*!< GPDMA1 HW request is SAES_OUT */ 315 #endif /* defined (SAES) */ 316 #define GPDMA1_REQUEST_LPTIM1_IC1 46U /*!< GPDMA1 HW request is LPTIM1_IC1 */ 317 #define GPDMA1_REQUEST_LPTIM1_IC2 47U /*!< GPDMA1 HW request is LPTIM1_IC2 */ 318 #define GPDMA1_REQUEST_LPTIM1_UE 48U /*!< GPDMA1 HW request is LPTIM1_UE */ 319 #if defined (LPTIM2) 320 #define GPDMA1_REQUEST_LPTIM2_IC1 49U /*!< GPDMA1 HW request is LPTIM2_IC1 */ 321 #define GPDMA1_REQUEST_LPTIM2_IC2 50U /*!< GPDMA1 HW request is LPTIM2_IC2 */ 322 #define GPDMA1_REQUEST_LPTIM2_UE 51U /*!< GPDMA1 HW request is LPTIM2_UE */ 323 #endif /* defined (LPTIM2) */ 324 325 /* Software request */ 326 #define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ 327 /** 328 * @} 329 */ 330 331 /** @defgroup DMA_Block_Request DMA Block Request 332 * @brief DMA Block Request 333 * @{ 334 */ 335 #define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */ 336 #define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */ 337 /** 338 * @} 339 */ 340 341 /** @defgroup DMA_Transfer_Direction DMA Transfer Direction 342 * @brief DMA transfer direction 343 * @{ 344 */ 345 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 346 #define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ 347 #define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ 348 /** 349 * @} 350 */ 351 352 /** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode 353 * @brief DMA Source Increment Mode 354 * @{ 355 */ 356 #define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */ 357 #define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */ 358 /** 359 * @} 360 */ 361 362 /** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode 363 * @brief DMA Destination Increment Mode 364 * @{ 365 */ 366 #define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */ 367 #define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */ 368 /** 369 * @} 370 */ 371 372 /** @defgroup DMA_Source_Data_Width DMA Source Data Width 373 * @brief DMA Source Data Width 374 * @{ 375 */ 376 #define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */ 377 #define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */ 378 #define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */ 379 /** 380 * @} 381 */ 382 383 /** @defgroup DMA_Destination_Data_Width DMA destination Data Width 384 * @brief DMA destination Data Width 385 * @{ 386 */ 387 #define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */ 388 #define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */ 389 #define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */ 390 391 /** 392 * @} 393 */ 394 395 /** @defgroup DMA_Priority_Level DMA Priority Level 396 * @brief DMA Priority Level 397 * @{ 398 */ 399 #define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */ 400 #define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */ 401 #define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */ 402 #define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */ 403 /** 404 * @} 405 */ 406 407 /** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port 408 * @brief DMA Transfer Allocated Port 409 * @{ 410 */ 411 #define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */ 412 #define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */ 413 #define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */ 414 #define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */ 415 /** 416 * @} 417 */ 418 419 /** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode 420 * @brief DMA Transfer Event Mode 421 * @{ 422 */ 423 #define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the 424 HT event is generated at the half of each block */ 425 #define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list 426 item and the HT event is generated at the half of each 427 linked-list item */ 428 #define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last 429 linked-list item and the HT event is generated at the half 430 of the last linked-list item */ 431 /** 432 * @} 433 */ 434 435 /** @defgroup DMA_Transfer_Mode DMA Transfer Mode 436 * @brief DMA Transfer Mode 437 * @{ 438 */ 439 #define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */ 440 /** 441 * @} 442 */ 443 444 /** @defgroup DMA_Channel_Attributes DMA Channel Attributes 445 * @brief DMA Channel Security and Privilege Attributes 446 * @note Secure and non-secure attributes are only available from the secure world when TZEN = 1 447 * @{ 448 */ 449 #define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | 0x01U) /*!< Channel is privileged */ 450 #define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */ 451 452 #define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | 0x02U) /*!< Channel is secure */ 453 #define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */ 454 #define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | 0x04U) /*!< Channel source is secure */ 455 #define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */ 456 #define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | 0x08U) /*!< Channel destination is secure */ 457 #define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */ 458 459 #define DMA_CHANNEL_ATTRIBUTE_UNLOCKED (0x00U) /*!< Channel attribute is unlocked */ 460 #define DMA_CHANNEL_ATTRIBUTE_LOCKED (0x01U) /*!< Channel attribute is locked */ 461 /** 462 * @} 463 */ 464 465 466 467 /** 468 * @} 469 */ 470 471 472 /* Exported macro ----------------------------------------------------------------------------------------------------*/ 473 /** @defgroup DMA_Exported_Macros DMA Exported Macros 474 * @brief DMA Exported Macros 475 * @{ 476 */ 477 478 /** @brief Reset DMA handle state. 479 * @param __HANDLE__ : DMA handle. 480 * @retval None. 481 */ 482 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \ 483 ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 484 485 /** 486 * @brief Enable the specified DMA Channel. 487 * @param __HANDLE__ : DMA handle. 488 * @retval None 489 */ 490 #define __HAL_DMA_ENABLE(__HANDLE__) \ 491 ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 492 493 /** 494 * @brief Disable the specified DMA Channel. 495 * @param __HANDLE__ : DMA handle. 496 * @retval None 497 */ 498 #define __HAL_DMA_DISABLE(__HANDLE__) \ 499 ((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET)) 500 501 /** 502 * @brief Get the DMA channel pending flags. 503 * @param __HANDLE__ : DMA handle. 504 * @param __FLAG__ : Get the specified flag. 505 * This parameter can be any combination of the following values: 506 * @arg DMA_FLAG_TC : Transfer Complete flag. 507 * @arg DMA_FLAG_HT : Half Transfer Complete flag. 508 * @arg DMA_FLAG_DTE : Data Transfer Error flag. 509 * @arg DMA_FLAG_ULE : Update linked-list Error flag. 510 * @arg DMA_FLAG_USE : User Setting Error flag. 511 * @arg DMA_FLAG_TO : Trigger Overrun flag. 512 * @arg DMA_FLAG_SUSP : Completed Suspension flag. 513 * @arg DMA_FLAG_IDLEF : Idle flag. 514 * @retval The state of FLAG (SET or RESET). 515 */ 516 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \ 517 ((__HANDLE__)->Instance->CSR & (__FLAG__)) 518 519 /** 520 * @brief Clear the DMA Channel pending flags. 521 * @param __HANDLE__ : DMA handle. 522 * @param __FLAG__ : Specifies the flag to clear. 523 * This parameter can be any combination of the following values: 524 * @arg DMA_FLAG_TC : Transfer Complete flag. 525 * @arg DMA_FLAG_HT : Half Transfer Complete flag. 526 * @arg DMA_FLAG_DTE : Data Transfer Error flag. 527 * @arg DMA_FLAG_ULE : Update Linked-List Error flag. 528 * @arg DMA_FLAG_USE : User Setting Error flag. 529 * @arg DMA_FLAG_TO : Trigger Overrun flag. 530 * @arg DMA_FLAG_SUSP : Completed Suspension flag. 531 * @retval None 532 */ 533 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 534 ((__HANDLE__)->Instance->CFCR = (__FLAG__)) 535 536 /** 537 * @brief Enable the specified DMA Channel interrupts. 538 * @param __HANDLE__ : DMA handle. 539 * @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled. 540 * This parameter can be any combination of the following values: 541 * @arg DMA_IT_TC : Transfer Complete interrupt. 542 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 543 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 544 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 545 * @arg DMA_IT_USE : User Setting Error interrupt. 546 * @arg DMA_IT_TO : Trigger Overrun interrupt. 547 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 548 * @retval None 549 */ 550 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 551 ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 552 553 /** 554 * @brief Disable the specified DMA Channel interrupts. 555 * @param __HANDLE__ : DMA handle. 556 * @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled. 557 * This parameter can be any combination of the following values: 558 * @arg DMA_IT_TC : Transfer Complete interrupt. 559 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 560 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 561 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 562 * @arg DMA_IT_USE : User Setting Error interrupt. 563 * @arg DMA_IT_TO : Trigger Overrun interrupt. 564 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 565 * @retval None 566 */ 567 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 568 ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 569 570 /** 571 * @brief Checks whether the specified DMA Channel interrupt is enabled or not. 572 * @param __HANDLE__ : DMA handle. 573 * @param __INTERRUPT__ : specifies the DMA interrupt source to check. 574 * @arg DMA_IT_TC : Transfer Complete interrupt. 575 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 576 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 577 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 578 * @arg DMA_IT_USE : User Setting Error interrupt. 579 * @arg DMA_IT_TO : Trigger Overrun interrupt. 580 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 581 * @retval The state of DMA_IT (SET or RESET). 582 */ 583 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 584 (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 585 586 /** 587 * @brief Writes the block number of bytes to be transferred from the source on the DMA Channel. 588 * @param __HANDLE__ : DMA handle. 589 * @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535). 590 */ 591 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \ 592 MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__)) 593 594 /** 595 * @brief Returns the number of remaining data bytes in the current DMA Channel transfer. 596 * @param __HANDLE__ : DMA handle. 597 * @retval The number of remaining data units in the current DMA Stream transfer. 598 */ 599 #define __HAL_DMA_GET_COUNTER(__HANDLE__) \ 600 (((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT) 601 /** 602 * @} 603 */ 604 605 606 /* Include DMA HAL Extension module */ 607 #include "stm32wbaxx_hal_dma_ex.h" 608 609 610 /* Exported functions ------------------------------------------------------------------------------------------------*/ 611 /** @defgroup DMA_Exported_Functions DMA Exported Functions 612 * @brief DMA Exported Functions 613 * @{ 614 */ 615 616 /** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions 617 * @brief Initialization and De-Initialization Functions 618 * @{ 619 */ 620 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma); 621 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma); 622 /** 623 * @} 624 */ 625 626 /** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions 627 * @brief I/O Operation Functions 628 * @{ 629 */ 630 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, 631 uint32_t SrcAddress, 632 uint32_t DstAddress, 633 uint32_t SrcDataSize); 634 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, 635 uint32_t SrcAddress, 636 uint32_t DstAddress, 637 uint32_t SrcDataSize); 638 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma); 639 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma); 640 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, 641 HAL_DMA_LevelCompleteTypeDef CompleteLevel, 642 uint32_t Timeout); 643 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma); 644 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, 645 HAL_DMA_CallbackIDTypeDef CallbackID, 646 void (*const pCallback)(DMA_HandleTypeDef *const _hdma)); 647 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, 648 HAL_DMA_CallbackIDTypeDef CallbackID); 649 /** 650 * @} 651 */ 652 653 /** @defgroup DMA_Exported_Functions_Group3 State and Error Functions 654 * @brief State and Error Functions 655 * @{ 656 */ 657 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma); 658 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma); 659 /** 660 * @} 661 */ 662 663 /** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions 664 * @brief DMA Attributes Functions 665 * @{ 666 */ 667 #if defined (DMA_PRIVCFGR_PRIV0) 668 HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, 669 uint32_t ChannelAttributes); 670 HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, 671 uint32_t *const pChannelAttributes); 672 #if defined (DMA_RCFGLOCKR_LOCK0) 673 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 674 HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); 675 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 676 HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, 677 uint32_t *const pLockState); 678 679 #endif /* defined (DMA_RCFGLOCKR_LOCK0) */ 680 #endif /* defined (DMA_PRIVCFGR_PRIV0) */ 681 /** 682 * @} 683 */ 684 685 /** 686 * @} 687 */ 688 689 690 /* Private constants -------------------------------------------------------------------------------------------------*/ 691 /** @defgroup DMA_Private_Constants DMA Private Constants 692 * @brief DMA Private Constants 693 * @{ 694 */ 695 #define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */ 696 #define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */ 697 #define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */ 698 #define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */ 699 #define DMA_CHANNEL_ATTR_PRIV_MASK (0x00000010U) /* DMA channel privilege mask */ 700 #define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */ 701 #define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */ 702 #define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */ 703 #define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */ 704 #define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */ 705 #define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */ 706 #define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */ 707 /** 708 * @} 709 */ 710 711 712 /* Private macros ----------------------------------------------------------------------------------------------------*/ 713 /** @defgroup DMA_Private_Macros DMA Private Macros 714 * @brief DMA Private Macros 715 * @{ 716 */ 717 #define GET_DMA_INSTANCE(__HANDLE__) \ 718 ((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK))) 719 720 #define GET_DMA_CHANNEL(__HANDLE__) \ 721 ((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE) 722 723 #define IS_DMA_MODE(MODE) \ 724 ((MODE) == DMA_NORMAL) 725 726 #define IS_DMA_DIRECTION(DIRECTION) \ 727 (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \ 728 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 729 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 730 731 #define IS_DMA_LEVEL_COMPLETE(LEVEL) \ 732 (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \ 733 ((LEVEL) == HAL_DMA_HALF_TRANSFER)) 734 735 #define IS_DMA_SOURCE_INC(INC) \ 736 (((INC) == DMA_SINC_FIXED) || \ 737 ((INC) == DMA_SINC_INCREMENTED)) 738 739 #define IS_DMA_DESTINATION_INC(INC) \ 740 (((INC) == DMA_DINC_FIXED) || \ 741 ((INC) == DMA_DINC_INCREMENTED)) 742 743 #define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \ 744 (((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \ 745 ((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \ 746 ((WIDTH) == DMA_SRC_DATAWIDTH_WORD)) 747 748 #define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \ 749 (((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \ 750 ((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \ 751 ((WIDTH) == DMA_DEST_DATAWIDTH_WORD)) 752 753 #define IS_DMA_BURST_LENGTH(LENGTH) \ 754 (((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \ 755 ((LENGTH) <= DMA_CHANNEL_BURST_MAX)) 756 757 #define IS_DMA_PRIORITY(PRIORITY) \ 758 (((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \ 759 ((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \ 760 ((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \ 761 ((PRIORITY) == DMA_HIGH_PRIORITY)) 762 763 #define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \ 764 (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U) 765 766 #if defined (LPTIM2) 767 #define IS_DMA_REQUEST(REQUEST) \ 768 (((REQUEST) == DMA_REQUEST_SW) || \ 769 ((REQUEST) <= GPDMA1_REQUEST_LPTIM2_UE)) 770 #else 771 #define IS_DMA_REQUEST(REQUEST) \ 772 (((REQUEST) == DMA_REQUEST_SW) || \ 773 ((REQUEST) <= GPDMA1_REQUEST_LPTIM1_UE)) 774 #endif /* defined (LPTIM2) */ 775 776 #define IS_DMA_BLOCK_HW_REQUEST(MODE) \ 777 (((MODE) == DMA_BREQ_SINGLE_BURST) || \ 778 ((MODE) == DMA_BREQ_BLOCK)) 779 780 #define IS_DMA_TCEM_EVENT_MODE(MODE) \ 781 (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ 782 ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ 783 ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) 784 785 #define IS_DMA_BLOCK_SIZE(SIZE) \ 786 (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT)) 787 788 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 789 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ 790 (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \ 791 (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \ 792 (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U))) 793 #else 794 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ 795 (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ 796 ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) 797 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 798 799 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 800 #define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \ 801 (((INSTANCE)->SMISR & (GLOBAL_FLAG))) 802 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 803 #define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \ 804 (((INSTANCE)->MISR & (GLOBAL_FLAG))) 805 806 /** 807 * @} 808 */ 809 810 811 /* Private functions -------------------------------------------------------------------------------------------------*/ 812 /** @defgroup DMA_Private_Functions DMA Private Functions 813 * @brief DMA Private Functions 814 * @{ 815 */ 816 817 /** 818 * @} 819 */ 820 821 /** 822 * @} 823 */ 824 825 /** 826 * @} 827 */ 828 829 /** 830 * @} 831 */ 832 833 #ifdef __cplusplus 834 } 835 #endif 836 837 #endif /* STM32WBAxx_HAL_DMA_H */ 838
