1 /** 2 ****************************************************************************** 3 * @file stm32wbaxx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBAxx_HAL_ADC_H 21 #define STM32WBAxx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbaxx_hal_def.h" 29 30 /* Include low level driver */ 31 #include "stm32wbaxx_ll_adc.h" 32 33 /** @addtogroup STM32WBAxx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ADC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup ADC_Exported_Types ADC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief ADC group regular oversampling structure definition 48 */ 49 typedef struct 50 { 51 uint32_t Ratio; /*!< Configures the oversampling ratio. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 53 54 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 55 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 56 57 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 58 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 59 60 } ADC_OversamplingTypeDef; 61 62 /** 63 * @brief Structure definition of ADC instance and ADC group regular. 64 * @note Parameters of this structure are shared within 2 scopes: 65 * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC 66 * groups regular and injected): ClockPrescaler, Resolution, DataAlign, 67 * ScanConvMode, EOCSelection, LowPowerAutoWait. 68 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, 69 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 70 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 71 * ADC state can be either: 72 * - For all parameters: ADC disabled 73 * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on 74 * group regular. 75 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 76 * without error reporting (as it can be the expected behavior in case of intended action to update another 77 * parameter (which fulfills the ADC state condition) on the fly). 78 */ 79 typedef struct 80 { 81 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous 82 clock derived from system clock or PLL (Refer to reference manual for list of 83 clocks available)) and clock prescaler. 84 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 85 Note: The ADC clock configuration is common to all ADC instances. 86 Note: In case of synchronous clock mode based on HCLK/1, the configuration must 87 be enabled only if the system clock has a 50% duty clock cycle (APB 88 prescaler configured inside RCC must be bypassed and PCLK clock must have 89 50% duty cycle). Refer to reference manual for details. 90 Note: In case of usage of asynchronous clock, the selected clock must be 91 preliminarily enabled at RCC top level. 92 Note: This parameter can be modified only if all ADC instances are disabled. */ 93 94 uint32_t Resolution; /*!< Configure the ADC resolution. 95 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 96 97 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 98 Refer to reference manual for alignments formats versus resolutions. 99 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ 100 101 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC group regular. 102 On this STM32 series, ADC group regular sequencer both modes "fully configurable" 103 or "not fully configurable" are available: 104 - sequencer configured to fully configurable: 105 sequencer length and each rank affectation to a channel are configurable. 106 - Sequence length: Set number of ranks in the scan sequence. 107 - Sequence direction: Unless specified in parameters, sequencer 108 scan direction is forward (from rank 1 to rank n). 109 - sequencer configured to not fully configurable: 110 sequencer length and each rank affectation to a channel are fixed by channel 111 HW number. 112 - Sequence length: Number of ranks in the scan sequence is 113 defined by number of channels set in the sequence, 114 rank of each channel is fixed by channel HW number. 115 (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 116 - Sequence direction: Unless specified in parameters, sequencer 117 scan direction is forward (from lowest channel number to 118 highest channel number). 119 This parameter can be associated to parameter 'DiscontinuousConvMode' to have 120 main sequence subdivided in successive parts. Sequencer is automatically enabled 121 if several channels are set (sequencer cannot be disabled, as it can be the case 122 on other STM32 devices): 123 If only 1 channel is set: Conversion is performed in single mode. 124 If several channels are set: Conversions are performed in sequence mode. 125 This parameter can be a value of @ref ADC_Scan_mode */ 126 127 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and 128 interruption: end of unitary conversion or end of sequence conversions. 129 This parameter can be a value of @ref ADC_EOCSelection. */ 130 131 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the 132 previous conversion (for ADC group regular) has been retrieved by user software, 133 using function HAL_ADC_GetValue(). 134 This feature automatically adapts the frequency of ADC conversions triggers to 135 the speed of the system that reads the data. Moreover, this avoids risk of 136 overrun for low frequency applications. 137 This parameter can be set to ENABLE or DISABLE. 138 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), 139 HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC 140 flag (by CPU to free the IRQ pending event or by DMA). 141 Auto wait will work but fort a very short time, discarding its intended 142 benefit (except specific case of high load of CPU or DMA transfers which 143 can justify usage of auto wait). 144 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, 145 when ADC conversion data is needed: 146 use HAL_ADC_PollForConversion() to ensure that conversion is completed and 147 HAL_ADC_GetValue() to retrieve conversion result and trig another 148 conversion start. */ 149 150 FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a 151 conversion and automatically wakes-up when a new conversion is triggered 152 (with startup time between trigger and start of sampling). 153 This feature can be combined with automatic wait mode 154 (parameter 'LowPowerAutoWait'). 155 This parameter can be set to ENABLE or DISABLE. */ 156 157 uint32_t LowPowerAutonomousDPD; /*!< Set ADC low power mode: deep power down in autonomous mode. 158 This parameter can be a value of 159 @ref ADC_HAL_EC_AUTONOMOUS_DEEP_POWER_DOWN_MODE. */ 160 161 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) 162 or continuous mode for ADC group regular, after the first ADC conversion 163 start trigger occurred (software start or external trigger). This parameter 164 can be set to ENABLE or DISABLE. */ 165 166 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group 167 sequencer. 168 This parameter is dependent on ScanConvMode: 169 - sequencer configured to fully configurable: 170 Number of ranks in the scan sequence is configurable using this parameter. 171 Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to 172 parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. 173 Afterwards, when all needed sequencer ranks are set, parameter 174 'NbrOfConversion' can be updated without modifying configuration of 175 sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded). 176 - sequencer configured to not fully configurable: 177 Number of ranks in the scan sequence is defined by number of channels set in 178 the sequence. This parameter is discarded. 179 This parameter must be a number between Min_Data = 1 and Max_Data = 8. 180 Note: This parameter must be modified when no conversion is on going on regular 181 group (ADC disabled, or ADC enabled without continuous mode or external 182 trigger that could launch a conversion). */ 183 184 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed 185 in Complete-sequence/Discontinuous-sequence (main sequence subdivided in 186 successive parts). 187 Discontinuous mode is used only if sequencer is enabled (parameter 188 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 189 Discontinuous mode can be enabled only if continuous mode is disabled. 190 If continuous mode is enabled, this parameter setting is discarded. 191 This parameter can be set to ENABLE or DISABLE. 192 Note: On this STM32 series, ADC group regular number of discontinuous 193 ranks increment is fixed to one-by-one. */ 194 195 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion 196 start. 197 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger 198 is used instead. 199 This parameter can be a value of @ref ADC_regular_external_trigger_source. 200 Caution: external trigger source is common to all ADC instances. */ 201 202 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start 203 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 204 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 205 206 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA 207 transfer stops when number of conversions is reached) or in continuous 208 mode (DMA transfer unlimited, whatever number of conversions). 209 This parameter can be set to ENABLE or DISABLE. 210 Note: In continuous mode, DMA must be configured in circular mode. 211 Otherwise an overrun will be triggered when DMA buffer maximum 212 pointer is reached. */ 213 214 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 215 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 216 Note: In case of overrun set to data preserved and usage with programming model 217 with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of 218 conversion flags, this induces the release of the preserved data. If 219 needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), 220 placed in user program code (called before end of conversion flags clear) 221 Note: Error reporting with respect to the conversion mode: 222 - Usage with ADC conversion by polling for event or interruption: Error is 223 reported only if overrun is set to data preserved. If overrun is set to 224 data overwritten, user can willingly not read all the converted data, 225 this is not considered as an erroneous case. 226 - Usage with ADC conversion by DMA: Error is reported whatever overrun 227 setting (DMA is expected to process all data from data register). */ 228 229 uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels. 230 Unit: ADC clock cycles 231 Conversion time is the addition of sampling time and processing time 232 (12.5 ADC clock cycles at ADC resolution 12 bits, 233 10.5 cycles at 10 bits, 234 8.5 cycles at 8 bits, 235 6.5 cycles at 6 bits). 236 Note: On this STM32 family, two different sampling time settings are available, 237 each channel can use one of these two settings. On some other STM32 devices 238 this parameter in channel wise and is located into ADC channel 239 initialization structure. 240 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 241 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor) 242 sampling time constraints must be respected (sampling time can be adjusted 243 in function of ADC clock frequency and sampling time setting) 244 Refer to device datasheet for timings values, parameters TS_vrefint, 245 TS_vbat, TS_temp (values rough order: few tens of microseconds). */ 246 247 uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible. 248 Unit: ADC clock cycles 249 Conversion time is the addition of sampling time and processing time 250 (12.5 ADC clock cycles at ADC resolution 12 bits, 251 10.5 cycles at 10 bits, 252 8.5 cycles at 8 bits, 253 6.5 cycles at 6 bits). 254 Note: On this STM32 family, two different sampling time settings are available, 255 each channel can use one of these two settings. On some other STM32 devices 256 this parameter in channel wise and is located into ADC channel 257 initialization structure. 258 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 259 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor) 260 sampling time constraints must be respected (sampling time can be adjusted 261 in function of ADC clock frequency and sampling time setting) 262 Refer to device datasheet for timings values, parameters TS_vrefint, 263 TS_vbat, TS_temp (values rough order: few tens of microseconds). */ 264 265 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 266 This parameter can be set to ENABLE or DISABLE. 267 Note: This parameter can be modified only if there is no conversion is 268 ongoing on ADC group regular. */ 269 270 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 271 Caution: this setting overwrites the previous oversampling configuration 272 if oversampling is already enabled. */ 273 274 uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode. 275 This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ. 276 Note: ADC trigger frequency mode must be set to low frequency when 277 a duration is exceeded before ADC conversion start trigger event 278 (between ADC enable and ADC conversion start trigger event 279 or between two ADC conversion start trigger event). 280 Duration value: Refer to device datasheet, parameter "tIdle". 281 Note: When ADC trigger frequency mode is set to low frequency, 282 some rearm cycles are inserted before performing ADC conversion 283 start, inducing a delay of 2 ADC clock cycles. */ 284 285 } ADC_InitTypeDef; 286 287 /** 288 * @brief Structure definition of ADC channel for regular group 289 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 290 * ADC state can be either: 291 * - For all parameters: ADC disabled or enabled without conversion on going on regular group. 292 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 293 * without error reporting (as it can be the expected behavior in case of intended action to update another 294 * parameter (which fulfills the ADC state condition) on the fly). 295 */ 296 typedef struct 297 { 298 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 299 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 300 Note: Depending on devices and ADC instances, some channels may not be available 301 on device package pins. Refer to device datasheet for channels 302 availability. */ 303 304 uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer and specify its 305 conversion rank. 306 This parameter is dependent on ScanConvMode: 307 - sequencer configured to fully configurable: 308 Channels ordering into each rank of scan sequence: 309 whatever channel can be placed into whatever rank. 310 - sequencer configured to not fully configurable: 311 rank of each channel is fixed by channel HW number. 312 (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 313 Despite the channel rank is fixed, this parameter allow an additional 314 possibility: to remove the selected rank (selected channel) from sequencer. 315 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */ 316 317 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 318 Unit: ADC clock cycles 319 Conversion time is the addition of sampling time and processing time 320 (12.5 ADC clock cycles at ADC resolution 12 bits, 321 10.5 cycles at 10 bits, 322 8.5 cycles at 8 bits, 323 6.5 cycles at 6 bits). 324 This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON 325 Note: On this STM32 family, two different sampling time settings are available 326 (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), 327 each channel can use one of these two settings. 328 329 Note: In case of usage of internal measurement channels (VrefInt/Vbat/ 330 TempSensor), sampling time constraints must be respected (sampling time 331 can be adjusted in function of ADC clock frequency and sampling time 332 setting) 333 Refer to device datasheet for timings values. */ 334 335 } ADC_ChannelConfTypeDef; 336 337 /** 338 * @brief Structure definition of ADC analog watchdog 339 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 340 * ADC state can be either: 341 * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion 342 on going on ADC groups regular. 343 * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular. 344 */ 345 typedef struct 346 { 347 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 348 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels 349 by setting parameter 'WatchdogMode') 350 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls 351 of 'HAL_ADC_AnalogWDGConfig()' for each channel) 352 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 353 354 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 355 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all 356 channels, ADC group regular. 357 For Analog Watchdog 2 and 3: Several channels can be monitored by applying 358 successively the AWD init structure. 359 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 360 361 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 362 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' 363 is configured on single channel (only 1 channel can be 364 monitored). 365 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, 366 call successively the function HAL_ADC_AnalogWDGConfig() 367 for each channel to be added (or removed with value 368 'ADC_ANALOGWATCHDOG_NONE'). 369 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 370 371 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 372 This parameter can be set to ENABLE or DISABLE */ 373 374 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 375 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a 376 number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F 377 respectively. 378 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC 379 resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 380 LSB are ignored. 381 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 382 impacted: the comparison of analog watchdog thresholds is done on 383 oversampling final computation (after ratio and shift application): 384 ADC data register bitfield [15:4] (12 most significant bits). */ 385 386 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 387 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a 388 number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F 389 respectively. 390 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC 391 resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 392 LSB are ignored. 393 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 394 impacted: the comparison of analog watchdog thresholds is done on 395 oversampling final computation (after ratio and shift application): 396 ADC data register bitfield [15:4] (12 most significant bits).*/ 397 } ADC_AnalogWDGConfTypeDef; 398 399 /** @defgroup ADC_States ADC States 400 * @{ 401 */ 402 403 /** 404 * @brief HAL ADC state machine: ADC states definition (bitfields) 405 * @note ADC state machine is managed by bitfields, state must be compared 406 * with bit by bit. 407 * For example: 408 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 409 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 410 */ 411 /* States of ADC global scope */ 412 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 413 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 414 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy from internal process (ex : calibration, ...) */ 415 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 416 417 /* States of ADC errors */ 418 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 419 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 420 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 421 422 /* States of ADC group regular */ 423 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur 424 (either by continuous mode, external trigger, low power 425 auto power-on (if feature available), multimode ADC master 426 control (if feature available)) */ 427 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 428 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 429 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag 430 raised */ 431 432 /* States of ADC group injected */ 433 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< Not available on this STM32 series: A conversion on group 434 injected is ongoing or can occur (either by auto-injection 435 mode, external trigger, low power auto power-on (if feature 436 available), multimode ADC master control (if feature 437 available))*/ 438 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Not available on this STM32 series: Conversion data 439 available on group injected */ 440 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Not available on this STM32 series: Injected queue overflow 441 occurrence */ 442 443 /* States of ADC analog watchdogs */ 444 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 445 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 446 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 447 448 /* States of ADC multi-mode */ 449 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave 450 state, controlled by another ADC master (when feature 451 available) */ 452 453 454 /** 455 * @} 456 */ 457 458 /** 459 * @brief ADC handle Structure definition 460 */ 461 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 462 typedef struct __ADC_HandleTypeDef 463 #else 464 typedef struct 465 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 466 { 467 ADC_TypeDef *Instance; /*!< Register base address */ 468 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ 469 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 470 HAL_LockTypeDef Lock; /*!< ADC locking object */ 471 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 472 __IO uint32_t ErrorCode; /*!< ADC Error code */ 473 474 uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks 475 setting, used in mode "fully configurable" (refer to 476 parameter 'ScanConvMode') */ 477 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 478 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 479 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer 480 callback */ 481 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 482 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 483 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 484 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 485 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 486 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 487 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 488 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 489 } ADC_HandleTypeDef; 490 491 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 492 /** 493 * @brief HAL ADC Callback ID enumeration definition 494 */ 495 typedef enum 496 { 497 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 498 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 499 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 500 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 501 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 502 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 503 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 504 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 505 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 506 } HAL_ADC_CallbackIDTypeDef; 507 508 /** 509 * @brief HAL ADC Callback pointer definition 510 */ 511 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 512 513 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 514 515 /** 516 * @} 517 */ 518 519 520 /* Exported constants --------------------------------------------------------*/ 521 522 /** @defgroup ADC_Exported_Constants ADC Exported Constants 523 * @{ 524 */ 525 526 /** @defgroup ADC_Error_Code ADC Error Code 527 * @{ 528 */ 529 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 530 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 531 enable/disable, erroneous state, ...) */ 532 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 533 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 534 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 535 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 536 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 537 /** 538 * @} 539 */ 540 541 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 542 * @{ 543 */ 544 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without 545 prescaler */ 546 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler 547 division by 2 */ 548 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler 549 division by 4 */ 550 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler 551 division by 6 */ 552 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler 553 division by 8 */ 554 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler 555 division by 10 */ 556 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler 557 division by 12 */ 558 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler 559 division by 16 */ 560 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler 561 division by 32 */ 562 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler 563 division by 64 */ 564 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler 565 division by 128 */ 566 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler 567 division by 256 */ 568 /** 569 * @} 570 */ 571 572 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 573 * @{ 574 */ 575 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 576 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 577 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 578 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ 579 /** 580 * @} 581 */ 582 583 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 584 * @{ 585 */ 586 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned 587 (alignment on data register LSB bit 0)*/ 588 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned 589 (alignment on data register MSB bit 15)*/ 590 /** 591 * @} 592 */ 593 594 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 595 * @{ 596 */ 597 /* Note: On this STM32 family, ADC group regular sequencer both modes */ 598 /* "fully configurable" or "not fully configurable" are */ 599 /* available. */ 600 /* Scan mode values must be compatible with other STM32 devices having */ 601 /* a configurable sequencer. */ 602 /* Scan direction setting values are defined by taking in account */ 603 /* already defined values for other STM32 devices: */ 604 /* ADC_SCAN_DISABLE (0x00000000UL) */ 605 /* ADC_SCAN_ENABLE (0x00000001UL) */ 606 /* Sequencer fully configurable with only rank 1 enabled is considered */ 607 /* as default setting equivalent to scan enable. */ 608 /* In case of migration from another STM32 device, the user will be */ 609 /* warned of change of setting choices with assert check. */ 610 /* Sequencer set to fully configurable */ 611 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: 612 only the rank 1 is enabled (no scan sequence on several ranks) */ 613 #define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: 614 sequencer length and each rank affectation to a channel are configurable. */ 615 616 /* Sequencer set to not fully configurable */ 617 #define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: 618 sequencer length and each rank affectation to a channel are fixed by 619 channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 620 Scan direction forward: from channel 0 to channel 18 */ 621 #define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT \ 622 | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: 623 sequencer length and each rank affectation to a channel are fixed by 624 channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 625 Scan direction backward: from channel 18 to channel 0 */ 626 627 #define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 series */ 628 #define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 series */ 629 /** 630 * @} 631 */ 632 633 /** @defgroup ADC_HAL_EC_AUTONOMOUS_DEEP_POWER_DOWN_MODE ADC autonomous deep power down mode 634 * @{ 635 */ 636 #define ADC_LP_AUTONOMOUS_DPD_DISABLE (LL_ADC_LP_AUTONOMOUS_DPD_DISABLE) /*!< ADC deep power down in autonomous 637 mode disabled */ 638 #define ADC_LP_AUTONOMOUS_DPD_ENABLE (LL_ADC_LP_AUTONOMOUS_DPD_ENABLE) /*!< ADC deep power down in autonomous 639 mode enabled */ 640 /** 641 * @} 642 */ 643 644 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 645 * @{ 646 */ 647 /* ADC group regular trigger sources for all ADC instances */ 648 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion 649 trigger software start */ 650 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion 651 trigger from external peripheral: TIM1 TRGO. */ 652 #define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< TIM1 channel 4 event (capture 653 compare: input capture or output capture). 654 Trigger edge set to rising edge (default setting). */ 655 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion 656 trigger from external peripheral: TIM1 channel 4 event (capture compare). */ 657 #define ADC_EXTERNALTRIG_LPTIM1_CC1 (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) /*!< ADC group regular conversion 658 trigger from external peripheral: LPTIM1 channel 1 event. */ 659 #define ADC_EXTERNALTRIG_EXT_IT15 (LL_ADC_REG_TRIG_EXT_EXTI_LINE15) /*!< ADC group regular conversion 660 trigger from external peripheral: external interrupt line 15. */ 661 /** 662 * @} 663 */ 664 665 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 666 * @{ 667 */ 668 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger 669 disabled (SW start)*/ 670 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion 671 trigger polarity set to rising edge */ 672 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion 673 trigger polarity set to falling edge */ 674 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion 675 trigger polarity set to both rising and falling edges */ 676 /** 677 * @} 678 */ 679 680 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 681 * @{ 682 */ 683 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 684 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 685 /** 686 * @} 687 */ 688 689 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 690 * @{ 691 */ 692 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case 693 of overrun: data preserved */ 694 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case 695 of overrun: data overwritten */ 696 /** 697 * @} 698 */ 699 700 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 701 * @{ 702 */ 703 #define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Enable the rank of the selected channels. Number of 704 ranks in the sequence is defined by number of channels enabled, rank of 705 each channel is defined by channel number (channel 0 fixed on rank 0, 706 channel 1 fixed on rank1, ...). 707 Setting relevant if parameter "ScanConvMode" is set to sequencer not fully 708 configurable. */ 709 #define ADC_RANK_NONE (0x00000002U) /*!< Disable the selected rank (selected channel) from 710 sequencer. 711 Setting relevant if parameter "ScanConvMode" is set to sequencer not fully 712 configurable. */ 713 714 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 715 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 716 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 717 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 718 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 719 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 720 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 721 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 722 /** 723 * @} 724 */ 725 726 /** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels 727 * @{ 728 */ 729 #define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of 730 channels: sampling time nb 1 */ 731 #define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of 732 channels: sampling time nb 2 */ 733 /** 734 * @} 735 */ 736 737 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 738 * @{ 739 */ 740 #define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ 741 #define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ 742 #define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ 743 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ 744 #define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ 745 #define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ 746 #define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycle */ 747 #define ADC_SAMPLETIME_814CYCLES_5 (LL_ADC_SAMPLINGTIME_814CYCLES_5) /*!< Sampling time 814.5 ADC clock cycles */ 748 /** 749 * @} 750 */ 751 752 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 753 * @{ 754 */ 755 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ 756 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ 757 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ 758 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ 759 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ 760 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ 761 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ 762 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ 763 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ 764 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ 765 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ 766 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ 767 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ 768 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ 769 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal 770 voltage reference. */ 771 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor. */ 772 #define ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_VCORE) /*!< ADC internal channel to Vcore. */ 773 /** 774 * @} 775 */ 776 777 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number 778 * @{ 779 */ 780 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 781 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 782 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 783 /** 784 * @} 785 */ 786 787 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode 788 * @{ 789 */ 790 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */ 791 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to a regular 792 group single channel */ 793 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to regular 794 group all channels */ 795 /** 796 * @} 797 */ 798 799 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 800 * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed 801 * to result as the ADC oversampling conversion data (before potential shift) 802 * @{ 803 */ 804 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */ 805 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */ 806 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */ 807 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */ 808 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */ 809 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */ 810 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */ 811 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */ 812 /** 813 * @} 814 */ 815 816 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 817 * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling 818 * conversion data 819 * @{ 820 */ 821 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ 822 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 rank */ 823 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 rank */ 824 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 rank */ 825 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 rank */ 826 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 rank */ 827 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 rank */ 828 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 rank */ 829 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 rank */ 830 /** 831 * @} 832 */ 833 834 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 835 * @{ 836 */ 837 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: 838 continuous mode (all conversions of OVS ratio are done from 1 trigger) */ 839 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: 840 discontinuous mode (each conversion of OVS ratio needs a trigger) */ 841 /** 842 * @} 843 */ 844 845 /** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode 846 * @note ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion 847 * start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion 848 * start trigger event). 849 * Duration value: Refer to device datasheet, parameter "tIdle". 850 * @{ 851 */ 852 #define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< Trigger frequency mode set to high frequency. */ 853 #define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< Trigger frequency mode set to low frequency. */ 854 /** 855 * @} 856 */ 857 858 /** @defgroup ADC_Event_type ADC Event type 859 * @note Analog watchdog 1 is available on all stm32 series 860 * Analog watchdog 2 and 3 are not available on all series 861 * @{ 862 */ 863 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 864 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ 865 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */ 866 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */ 867 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 868 /** 869 * @} 870 */ 871 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility 872 with other STM32 devices having only one analog watchdog */ 873 874 /** @defgroup ADC_interrupts_definition ADC interrupts definition 875 * @{ 876 */ 877 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 878 #define ADC_IT_LDORDY ADC_IER_LDORDYIE /*!< ADC internal voltage regulator ready interrupt source */ 879 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 880 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 881 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 882 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 883 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 884 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog 885 watchdog) */ 886 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog 887 watchdog) */ 888 /** 889 * @} 890 */ 891 892 /** @defgroup ADC_flags_definition ADC flags definition 893 * @{ 894 */ 895 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 896 #define ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC internal voltage regulator ready flag */ 897 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 898 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 899 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 900 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 901 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 902 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 903 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 904 /** 905 * @} 906 */ 907 908 /** 909 * @} 910 */ 911 912 /* Private macro -------------------------------------------------------------*/ 913 914 /** @defgroup ADC_Private_Macros ADC Private Macros 915 * @{ 916 */ 917 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 918 /* code of final user. */ 919 920 /** 921 * @brief Test if conversion trigger of regular group is software start 922 * or external trigger. 923 * @param __HANDLE__ ADC handle 924 * @retval SET (software start) or RESET (external trigger) 925 */ 926 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 927 (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == 0UL) 928 929 /** 930 * @brief Return resolution bits in CFGR1 register RES[1:0] field. 931 * @param __HANDLE__ ADC handle 932 * @retval Value of bitfield RES in CFGR1 register. 933 */ 934 #define ADC_GET_RESOLUTION(__HANDLE__) \ 935 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 936 937 /** 938 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 939 * @param __HANDLE__ ADC handle 940 * @retval None 941 */ 942 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 943 944 /** 945 * @brief Simultaneously clear and set specific bits of the handle State. 946 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 947 * the first parameter is the ADC handle State, the second parameter is the 948 * bit field to clear, the third and last parameter is the bit field to set. 949 * @retval None 950 */ 951 #define ADC_STATE_CLR_SET MODIFY_REG 952 953 /** 954 * @brief Enable ADC discontinuous conversion mode for regular group 955 * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode. 956 * @retval None 957 */ 958 #define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ 959 ((_REG_DISCONTINUOUS_MODE_) << 16U) 960 961 /** 962 * @brief Enable the ADC auto off mode. 963 * @param _AUTOOFF_ Auto off bit enable or disable. 964 * @retval None 965 */ 966 #define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ 967 ((_AUTOOFF_) << 15U) 968 969 /** 970 * @brief Enable the ADC auto delay mode. 971 * @param _AUTOWAIT_ Auto delay bit enable or disable. 972 * @retval None 973 */ 974 #define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ 975 ((_AUTOWAIT_) << 14U) 976 977 /** 978 * @brief Enable ADC continuous conversion mode. 979 * @param _CONTINUOUS_MODE_ Continuous mode. 980 * @retval None 981 */ 982 #define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ 983 ((_CONTINUOUS_MODE_) << 13U) 984 985 /** 986 * @brief Enable ADC overrun mode. 987 * @param _OVERRUN_MODE_ Overrun mode. 988 * @retval Overrun bit setting to be programmed into CFGR register 989 */ 990 /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ 991 /* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ 992 /* as the default case to be compliant with other STM32 devices. */ 993 #define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ 994 ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ 995 )? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \ 996 ) 997 998 /** 999 * @brief Set ADC scan mode with differentiation of sequencer setting 1000 * fixed or configurable 1001 * @param _SCAN_MODE_ Scan conversion mode. 1002 * @retval None 1003 */ 1004 /* Note: Scan mode set using this macro (instead of parameter direct set) */ 1005 /* due to different modes on other STM32 devices: */ 1006 /* if scan mode is disabled, sequencer is set to fully configurable */ 1007 /* with setting of only rank 1 enabled afterwards. */ 1008 #define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \ 1009 ( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL \ 1010 )? \ 1011 ((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT)) \ 1012 : \ 1013 (ADC_CFGR1_CHSELRMOD) \ 1014 ) 1015 1016 /** 1017 * @brief Enable the ADC DMA continuous request. 1018 * @param _DMACONTREQ_MODE_: DMA continuous request mode. 1019 * @retval None 1020 */ 1021 #define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ 1022 ((_DMACONTREQ_MODE_) << 1U) 1023 1024 /** 1025 * @brief Shift the AWD threshold in function of the selected ADC resolution. 1026 * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 1027 * If resolution 12 bits, no shift. 1028 * If resolution 10 bits, shift of 2 ranks on the left. 1029 * If resolution 8 bits, shift of 4 ranks on the left. 1030 * If resolution 6 bits, shift of 6 ranks on the left. 1031 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) 1032 * @param __HANDLE__ ADC handle 1033 * @param _Threshold_ Value to be shifted 1034 * @retval None 1035 */ 1036 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ 1037 ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 2U)*2U)) 1038 1039 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\ 1040 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\ 1041 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\ 1042 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\ 1043 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\ 1044 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\ 1045 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\ 1046 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\ 1047 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\ 1048 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\ 1049 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\ 1050 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256)) 1051 1052 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ 1053 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ 1054 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ 1055 ((RESOLUTION) == ADC_RESOLUTION_6B) ) 1056 1057 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 1058 ((ALIGN) == ADC_DATAALIGN_LEFT) ) 1059 1060 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ 1061 ((SCAN_MODE) == ADC_SCAN_ENABLE) || \ 1062 ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED) || \ 1063 ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED_BACKWARD) ) 1064 1065 #define IS_ADC_AUTONOMOUS_DPD(AUTONOMOUS_DPD) (((AUTONOMOUS_DPD) == ADC_LP_AUTONOMOUS_DPD_DISABLE) || \ 1066 ((AUTONOMOUS_DPD) == ADC_LP_AUTONOMOUS_DPD_ENABLE) ) 1067 1068 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 1069 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 1070 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 1071 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 1072 1073 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1074 ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) || \ 1075 ((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1076 ((REGTRIG) == ADC_EXTERNALTRIG_LPTIM1_CC1) || \ 1077 ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT15) || \ 1078 ((REGTRIG) == ADC_SOFTWARE_START) ) 1079 1080 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ 1081 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)) 1082 1083 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ 1084 ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) 1085 1086 #define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \ 1087 ((RANK) == ADC_RANK_NONE) ) 1088 1089 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \ 1090 ((RANK) == ADC_REGULAR_RANK_2 ) || \ 1091 ((RANK) == ADC_REGULAR_RANK_3 ) || \ 1092 ((RANK) == ADC_REGULAR_RANK_4 ) || \ 1093 ((RANK) == ADC_REGULAR_RANK_5 ) || \ 1094 ((RANK) == ADC_REGULAR_RANK_6 ) || \ 1095 ((RANK) == ADC_REGULAR_RANK_7 ) || \ 1096 ((RANK) == ADC_REGULAR_RANK_8 ) ) 1097 1098 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 1099 ((CHANNEL) == ADC_CHANNEL_1) || \ 1100 ((CHANNEL) == ADC_CHANNEL_2) || \ 1101 ((CHANNEL) == ADC_CHANNEL_3) || \ 1102 ((CHANNEL) == ADC_CHANNEL_4) || \ 1103 ((CHANNEL) == ADC_CHANNEL_5) || \ 1104 ((CHANNEL) == ADC_CHANNEL_6) || \ 1105 ((CHANNEL) == ADC_CHANNEL_7) || \ 1106 ((CHANNEL) == ADC_CHANNEL_8) || \ 1107 ((CHANNEL) == ADC_CHANNEL_9) || \ 1108 ((CHANNEL) == ADC_CHANNEL_10) || \ 1109 ((CHANNEL) == ADC_CHANNEL_11) || \ 1110 ((CHANNEL) == ADC_CHANNEL_12) || \ 1111 ((CHANNEL) == ADC_CHANNEL_13) || \ 1112 ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ 1113 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ 1114 ((CHANNEL) == ADC_CHANNEL_VCORE) ) 1115 1116 #define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \ 1117 ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2) ) 1118 1119 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ 1120 ((TIME) == ADC_SAMPLETIME_3CYCLES_5) || \ 1121 ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ 1122 ((TIME) == ADC_SAMPLETIME_12CYCLES_5) || \ 1123 ((TIME) == ADC_SAMPLETIME_19CYCLES_5) || \ 1124 ((TIME) == ADC_SAMPLETIME_39CYCLES_5) || \ 1125 ((TIME) == ADC_SAMPLETIME_79CYCLES_5) || \ 1126 ((TIME) == ADC_SAMPLETIME_814CYCLES_5) ) 1127 1128 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \ 1129 ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \ 1130 ((WATCHDOG) == ADC_ANALOGWATCHDOG_3) ) 1131 1132 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ 1133 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1134 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) 1135 1136 #define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \ 1137 ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) ) 1138 1139 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_EOSMP_EVENT) || \ 1140 ((EVENT) == ADC_AWD1_EVENT) || \ 1141 ((EVENT) == ADC_AWD2_EVENT) || \ 1142 ((EVENT) == ADC_AWD3_EVENT) || \ 1143 ((EVENT) == ADC_OVR_EVENT) ) 1144 1145 /** 1146 * @brief Verify that a given value is aligned with the ADC resolution range. 1147 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 1148 * @param __ADC_VALUE__ value checked against the resolution. 1149 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 1150 */ 1151 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 1152 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 1153 1154 /** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification 1155 * @{ 1156 */ 1157 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL)) 1158 /** 1159 * @} 1160 */ 1161 1162 1163 /* Private constants ---------------------------------------------------------*/ 1164 1165 /** @defgroup ADC_Private_Constants ADC Private Constants 1166 * @{ 1167 */ 1168 1169 /* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ 1170 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) 1171 1172 /* Internal definition to differentiate sequencer setting fixed or configurable */ 1173 #define ADC_SCAN_SEQ_FIXED_INT 0x80000000U 1174 1175 /** 1176 * @} 1177 */ 1178 1179 /* Exported macro ------------------------------------------------------------*/ 1180 1181 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1182 * @{ 1183 */ 1184 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1185 /* final user. */ 1186 1187 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1188 * @{ 1189 */ 1190 1191 /** @brief Reset ADC handle state. 1192 * @param __HANDLE__ ADC handle 1193 * @retval None 1194 */ 1195 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1196 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1197 do{ \ 1198 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1199 (__HANDLE__)->MspInitCallback = NULL; \ 1200 (__HANDLE__)->MspDeInitCallback = NULL; \ 1201 } while(0) 1202 #else 1203 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1204 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1205 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1206 1207 /** 1208 * @brief Enable ADC interrupt. 1209 * @param __HANDLE__ ADC handle 1210 * @param __INTERRUPT__ ADC Interrupt 1211 * This parameter can be one of the following values: 1212 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1213 * @arg @ref ADC_IT_LDORDY ADC channel internal voltage regulator ready interrupt source 1214 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1215 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1216 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1217 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1218 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1219 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1220 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1221 * @retval None 1222 */ 1223 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1224 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1225 1226 /** 1227 * @brief Disable ADC interrupt. 1228 * @param __HANDLE__ ADC handle 1229 * @param __INTERRUPT__ ADC Interrupt 1230 * This parameter can be one of the following values: 1231 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1232 * @arg @ref ADC_IT_LDORDY ADC channel internal voltage regulator ready interrupt source 1233 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1234 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1235 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1236 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1237 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1238 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1239 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1240 * @retval None 1241 */ 1242 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1243 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1244 1245 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1246 * @param __HANDLE__ ADC handle 1247 * @param __INTERRUPT__ ADC interrupt source to check 1248 * This parameter can be one of the following values: 1249 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1250 * @arg @ref ADC_IT_LDORDY ADC channel internal voltage regulator ready interrupt source 1251 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1252 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1253 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1254 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1255 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1256 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1257 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1258 * @retval State of interruption (SET or RESET) 1259 */ 1260 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1261 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1262 1263 /** 1264 * @brief Check whether the specified ADC flag is set or not. 1265 * @param __HANDLE__ ADC handle 1266 * @param __FLAG__ ADC flag 1267 * This parameter can be one of the following values: 1268 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1269 * @arg @ref ADC_FLAG_LDORDY ADC channel internal voltage regulator ready flag 1270 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1271 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1272 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1273 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1274 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1275 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1276 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1277 * @retval State of flag (TRUE or FALSE). 1278 */ 1279 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1280 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1281 1282 /** 1283 * @brief Clear the specified ADC flag. 1284 * @param __HANDLE__ ADC handle 1285 * @param __FLAG__ ADC flag 1286 * This parameter can be one of the following values: 1287 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1288 * @arg @ref ADC_FLAG_LDORDY ADC channel internal voltage regulator ready flag 1289 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1290 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1291 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1292 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1293 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1294 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1295 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1296 * @retval None 1297 */ 1298 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1299 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1300 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1301 1302 /** 1303 * @} 1304 */ 1305 1306 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1307 * @{ 1308 */ 1309 1310 /** 1311 * @brief Helper macro to get ADC channel number in decimal format 1312 * from literals ADC_CHANNEL_x. 1313 * @note Example: 1314 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1315 * will return decimal number "4". 1316 * @note The input can be a value from functions where a channel 1317 * number is returned, either defined with number 1318 * or with bitfield (only one bit must be set). 1319 * @param __CHANNEL__ This parameter can be one of the following values: 1320 * @arg @ref ADC_CHANNEL_0 1321 * @arg @ref ADC_CHANNEL_1 1322 * @arg @ref ADC_CHANNEL_2 1323 * @arg @ref ADC_CHANNEL_3 1324 * @arg @ref ADC_CHANNEL_4 1325 * @arg @ref ADC_CHANNEL_5 1326 * @arg @ref ADC_CHANNEL_6 1327 * @arg @ref ADC_CHANNEL_7 1328 * @arg @ref ADC_CHANNEL_8 1329 * @arg @ref ADC_CHANNEL_9 1330 * @arg @ref ADC_CHANNEL_10 1331 * @arg @ref ADC_CHANNEL_11 1332 * @arg @ref ADC_CHANNEL_12 1333 * @arg @ref ADC_CHANNEL_13 1334 * @arg @ref ADC_CHANNEL_VREFINT 1335 * @arg @ref ADC_CHANNEL_TEMPSENSOR 1336 * @arg @ref ADC_CHANNEL_VCORE 1337 * @retval Value between Min_Data=0 and Max_Data=18 1338 */ 1339 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1340 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1341 1342 /** 1343 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1344 * from number in decimal format. 1345 * @note Example: 1346 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1347 * will return a data equivalent to "ADC_CHANNEL_4". 1348 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1349 * @retval Returned value can be one of the following values: 1350 * @arg @ref ADC_CHANNEL_0 1351 * @arg @ref ADC_CHANNEL_1 1352 * @arg @ref ADC_CHANNEL_2 1353 * @arg @ref ADC_CHANNEL_3 1354 * @arg @ref ADC_CHANNEL_4 1355 * @arg @ref ADC_CHANNEL_5 1356 * @arg @ref ADC_CHANNEL_6 1357 * @arg @ref ADC_CHANNEL_7 1358 * @arg @ref ADC_CHANNEL_8 1359 * @arg @ref ADC_CHANNEL_9 1360 * @arg @ref ADC_CHANNEL_10 1361 * @arg @ref ADC_CHANNEL_11 1362 * @arg @ref ADC_CHANNEL_12 1363 * @arg @ref ADC_CHANNEL_13 1364 * @arg @ref ADC_CHANNEL_VREFINT (1) 1365 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1366 * @arg @ref ADC_CHANNEL_VCORE (1) 1367 * 1368 * (1) For ADC channel read back from ADC register, 1369 * comparison with internal channel parameter to be done 1370 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1371 */ 1372 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1373 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1374 1375 /** 1376 * @brief Helper macro to determine whether the selected channel 1377 * corresponds to literal definitions of driver. 1378 * @note The different literal definitions of ADC channels are: 1379 * - ADC internal channel: 1380 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 1381 * - ADC external channel (channel connected to a GPIO pin): 1382 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1383 * @note The channel parameter must be a value defined from literal 1384 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1385 * ADC_CHANNEL_TEMPSENSOR, ...), 1386 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1387 * must not be a value from functions where a channel number is 1388 * returned from ADC registers, 1389 * because internal and external channels share the same channel 1390 * number in ADC registers. The differentiation is made only with 1391 * parameters definitions of driver. 1392 * @param __CHANNEL__ This parameter can be one of the following values: 1393 * @arg @ref ADC_CHANNEL_0 1394 * @arg @ref ADC_CHANNEL_1 1395 * @arg @ref ADC_CHANNEL_2 1396 * @arg @ref ADC_CHANNEL_3 1397 * @arg @ref ADC_CHANNEL_4 1398 * @arg @ref ADC_CHANNEL_5 1399 * @arg @ref ADC_CHANNEL_6 1400 * @arg @ref ADC_CHANNEL_7 1401 * @arg @ref ADC_CHANNEL_8 1402 * @arg @ref ADC_CHANNEL_9 1403 * @arg @ref ADC_CHANNEL_10 1404 * @arg @ref ADC_CHANNEL_11 1405 * @arg @ref ADC_CHANNEL_12 1406 * @arg @ref ADC_CHANNEL_13 1407 * @arg @ref ADC_CHANNEL_VREFINT 1408 * @arg @ref ADC_CHANNEL_TEMPSENSOR 1409 * @arg @ref ADC_CHANNEL_VCORE 1410 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel 1411 * (channel connected to a GPIO pin). 1412 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1413 */ 1414 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1415 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1416 1417 /** 1418 * @brief Helper macro to convert a channel defined from parameter 1419 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1420 * ADC_CHANNEL_TEMPSENSOR, ...), 1421 * to its equivalent parameter definition of a ADC external channel 1422 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1423 * @note The channel parameter can be, additionally to a value 1424 * defined from parameter definition of a ADC internal channel 1425 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 1426 * a value defined from parameter definition of 1427 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1428 * or a value from functions where a channel number is returned 1429 * from ADC registers. 1430 * @param __CHANNEL__ This parameter can be one of the following values: 1431 * @arg @ref ADC_CHANNEL_0 1432 * @arg @ref ADC_CHANNEL_1 1433 * @arg @ref ADC_CHANNEL_2 1434 * @arg @ref ADC_CHANNEL_3 1435 * @arg @ref ADC_CHANNEL_4 1436 * @arg @ref ADC_CHANNEL_5 1437 * @arg @ref ADC_CHANNEL_6 1438 * @arg @ref ADC_CHANNEL_7 1439 * @arg @ref ADC_CHANNEL_8 1440 * @arg @ref ADC_CHANNEL_9 1441 * @arg @ref ADC_CHANNEL_10 1442 * @arg @ref ADC_CHANNEL_11 1443 * @arg @ref ADC_CHANNEL_12 1444 * @arg @ref ADC_CHANNEL_13 1445 * @arg @ref ADC_CHANNEL_VREFINT 1446 * @arg @ref ADC_CHANNEL_TEMPSENSOR 1447 * @arg @ref ADC_CHANNEL_VCORE 1448 * @retval Returned value can be one of the following values: 1449 * @arg @ref ADC_CHANNEL_0 1450 * @arg @ref ADC_CHANNEL_1 1451 * @arg @ref ADC_CHANNEL_2 1452 * @arg @ref ADC_CHANNEL_3 1453 * @arg @ref ADC_CHANNEL_4 1454 * @arg @ref ADC_CHANNEL_5 1455 * @arg @ref ADC_CHANNEL_6 1456 * @arg @ref ADC_CHANNEL_7 1457 * @arg @ref ADC_CHANNEL_8 1458 * @arg @ref ADC_CHANNEL_9 1459 * @arg @ref ADC_CHANNEL_10 1460 * @arg @ref ADC_CHANNEL_11 1461 * @arg @ref ADC_CHANNEL_12 1462 * @arg @ref ADC_CHANNEL_13 1463 */ 1464 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1465 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1466 1467 /** 1468 * @brief Helper macro to determine whether the internal channel 1469 * selected is available on the ADC instance selected. 1470 * @note The channel parameter must be a value defined from parameter 1471 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1472 * ADC_CHANNEL_TEMPSENSOR, ...), 1473 * must not be a value defined from parameter definition of 1474 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1475 * or a value from functions where a channel number is 1476 * returned from ADC registers, 1477 * because internal and external channels share the same channel 1478 * number in ADC registers. The differentiation is made only with 1479 * parameters definitions of driver. 1480 * @param __ADC_INSTANCE__ ADC instance 1481 * @param __CHANNEL__ This parameter can be one of the following values: 1482 * @arg @ref ADC_CHANNEL_VREFINT 1483 * @arg @ref ADC_CHANNEL_TEMPSENSOR 1484 * @arg @ref ADC_CHANNEL_VCORE 1485 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1486 * Value "1" if the internal channel selected is available on the ADC instance selected. 1487 */ 1488 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1489 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 1490 1491 /** 1492 * @brief Helper macro to select the ADC common instance 1493 * to which is belonging the selected ADC instance. 1494 * @note ADC common register instance can be used for: 1495 * - Set parameters common to several ADC instances 1496 * - Multimode (for devices with several ADC instances) 1497 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1498 * @param __ADCx__ ADC instance 1499 * @retval ADC common register instance 1500 */ 1501 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 1502 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 1503 1504 /** 1505 * @brief Helper macro to check if all ADC instances sharing the same 1506 * ADC common instance are disabled. 1507 * @note This check is required by functions with setting conditioned to 1508 * ADC state: 1509 * All ADC instances of the ADC common group must be disabled. 1510 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1511 * @note On devices with only 1 ADC common instance, parameter of this macro 1512 * is useless and can be ignored (parameter kept for compatibility 1513 * with devices featuring several ADC common instances). 1514 * @param __ADCXY_COMMON__ ADC common instance 1515 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1516 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1517 * are disabled. 1518 * Value "1" if at least one ADC instance sharing the same ADC common instance 1519 * is enabled. 1520 */ 1521 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1522 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 1523 1524 /** 1525 * @brief Helper macro to define the ADC conversion data full-scale digital 1526 * value corresponding to the selected ADC resolution. 1527 * @note ADC conversion data full-scale corresponds to voltage range 1528 * determined by analog voltage references Vref+ and Vref- 1529 * (refer to reference manual). 1530 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1531 * @arg @ref ADC_RESOLUTION_12B 1532 * @arg @ref ADC_RESOLUTION_10B 1533 * @arg @ref ADC_RESOLUTION_8B 1534 * @arg @ref ADC_RESOLUTION_6B 1535 * @retval ADC conversion data full-scale digital value 1536 */ 1537 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1538 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 1539 1540 /** 1541 * @brief Helper macro to convert the ADC conversion data from 1542 * a resolution to another resolution. 1543 * @param __DATA__ ADC conversion data to be converted 1544 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1545 * This parameter can be one of the following values: 1546 * @arg @ref ADC_RESOLUTION_12B 1547 * @arg @ref ADC_RESOLUTION_10B 1548 * @arg @ref ADC_RESOLUTION_8B 1549 * @arg @ref ADC_RESOLUTION_6B 1550 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1551 * This parameter can be one of the following values: 1552 * @arg @ref ADC_RESOLUTION_12B 1553 * @arg @ref ADC_RESOLUTION_10B 1554 * @arg @ref ADC_RESOLUTION_8B 1555 * @arg @ref ADC_RESOLUTION_6B 1556 * @retval ADC conversion data to the requested resolution 1557 */ 1558 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 1559 __ADC_RESOLUTION_CURRENT__,\ 1560 __ADC_RESOLUTION_TARGET__) \ 1561 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 1562 (__ADC_RESOLUTION_CURRENT__),\ 1563 (__ADC_RESOLUTION_TARGET__)) 1564 1565 /** 1566 * @brief Helper macro to calculate the voltage (unit: mVolt) 1567 * corresponding to a ADC conversion data (unit: digital value). 1568 * @note Analog reference voltage (Vref+) must be either known from 1569 * user board environment or can be calculated using ADC measurement 1570 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1571 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1572 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1573 * (unit: digital value). 1574 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1575 * @arg @ref ADC_RESOLUTION_12B 1576 * @arg @ref ADC_RESOLUTION_10B 1577 * @arg @ref ADC_RESOLUTION_8B 1578 * @arg @ref ADC_RESOLUTION_6B 1579 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1580 */ 1581 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1582 __ADC_DATA__,\ 1583 __ADC_RESOLUTION__) \ 1584 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 1585 (__ADC_DATA__),\ 1586 (__ADC_RESOLUTION__)) 1587 1588 /** 1589 * @brief Helper macro to calculate analog reference voltage (Vref+) 1590 * (unit: mVolt) from ADC conversion data of internal voltage 1591 * reference VrefInt. 1592 * @note Computation is using VrefInt calibration value 1593 * stored in system memory for each device during production. 1594 * @note This voltage depends on user board environment: voltage level 1595 * connected to pin Vref+. 1596 * On devices with small package, the pin Vref+ is not present 1597 * and internally bonded to pin Vdda. 1598 * @note On this STM32 series, calibration data of internal voltage reference 1599 * VrefInt corresponds to a resolution of 12 bits, 1600 * this is the recommended ADC resolution to convert voltage of 1601 * internal voltage reference VrefInt. 1602 * Otherwise, this macro performs the processing to scale 1603 * ADC conversion data to 12 bits. 1604 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 1605 * of internal voltage reference VrefInt (unit: digital value). 1606 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1607 * @arg @ref ADC_RESOLUTION_12B 1608 * @arg @ref ADC_RESOLUTION_10B 1609 * @arg @ref ADC_RESOLUTION_8B 1610 * @arg @ref ADC_RESOLUTION_6B 1611 * @retval Analog reference voltage (unit: mV) 1612 */ 1613 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 1614 __ADC_RESOLUTION__) \ 1615 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 1616 (__ADC_RESOLUTION__)) 1617 1618 /** 1619 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1620 * from ADC conversion data of internal temperature sensor. 1621 * @note Computation is using temperature sensor calibration values 1622 * stored in system memory for each device during production. 1623 * @note Calculation formula: 1624 * Temperature = ((TS_ADC_DATA - TS_CAL1) 1625 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 1626 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 1627 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1628 * Avg_Slope = (TS_CAL2 - TS_CAL1) 1629 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 1630 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 1631 * TEMP_DEGC_CAL1 (calibrated in factory) 1632 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 1633 * TEMP_DEGC_CAL2 (calibrated in factory) 1634 * Caution: Calculation relevancy under reserve that calibration 1635 * parameters are correct (address and data). 1636 * To calculate temperature using temperature sensor 1637 * datasheet typical values (generic values less, therefore 1638 * less accurate than calibrated values), 1639 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 1640 * @note As calculation input, the analog reference voltage (Vref+) must be 1641 * defined as it impacts the ADC LSB equivalent voltage. 1642 * @note Analog reference voltage (Vref+) must be either known from 1643 * user board environment or can be calculated using ADC measurement 1644 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1645 * @note On this STM32 series, calibration data of temperature sensor 1646 * corresponds to a resolution of 12 bits, 1647 * this is the recommended ADC resolution to convert voltage of 1648 * temperature sensor. 1649 * Otherwise, this macro performs the processing to scale 1650 * ADC conversion data to 12 bits. 1651 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1652 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 1653 * temperature sensor (unit: digital value). 1654 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 1655 * sensor voltage has been measured. 1656 * This parameter can be one of the following values: 1657 * @arg @ref ADC_RESOLUTION_12B 1658 * @arg @ref ADC_RESOLUTION_10B 1659 * @arg @ref ADC_RESOLUTION_8B 1660 * @arg @ref ADC_RESOLUTION_6B 1661 * @retval Temperature (unit: degree Celsius) 1662 */ 1663 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 1664 __TEMPSENSOR_ADC_DATA__,\ 1665 __ADC_RESOLUTION__) \ 1666 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ 1667 (__TEMPSENSOR_ADC_DATA__),\ 1668 (__ADC_RESOLUTION__)) 1669 1670 /** 1671 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1672 * from ADC conversion data of internal temperature sensor. 1673 * @note Computation is using temperature sensor typical values 1674 * (refer to device datasheet). 1675 * @note Calculation formula: 1676 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 1677 * / Avg_Slope + CALx_TEMP 1678 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1679 * (unit: digital value) 1680 * Avg_Slope = temperature sensor slope 1681 * (unit: uV/Degree Celsius) 1682 * TS_TYP_CALx_VOLT = temperature sensor digital value at 1683 * temperature CALx_TEMP (unit: mV) 1684 * Caution: Calculation relevancy under reserve the temperature sensor 1685 * of the current device has characteristics in line with 1686 * datasheet typical values. 1687 * If temperature sensor calibration values are available on 1688 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 1689 * temperature calculation will be more accurate using 1690 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 1691 * @note As calculation input, the analog reference voltage (Vref+) must be 1692 * defined as it impacts the ADC LSB equivalent voltage. 1693 * @note Analog reference voltage (Vref+) must be either known from 1694 * user board environment or can be calculated using ADC measurement 1695 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1696 * @note ADC measurement data must correspond to a resolution of 12bits 1697 * (full scale digital value 4095). If not the case, the data must be 1698 * preliminarily rescaled to an equivalent resolution of 12 bits. 1699 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value 1700 (unit: uV/DegCelsius). 1701 * On this STM32 series, refer to device datasheet parameter "Avg_Slope". 1702 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at 1703 temperature and Vref+ defined in parameters below) (unit: mV). 1704 * On this STM32 series, refer to device datasheet parameter "V30" 1705 * (corresponding to TS_CAL1). 1706 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see 1707 parameter above) is corresponding (unit: mV) 1708 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 1709 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 1710 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 1711 * This parameter can be one of the following values: 1712 * @arg @ref ADC_RESOLUTION_12B 1713 * @arg @ref ADC_RESOLUTION_10B 1714 * @arg @ref ADC_RESOLUTION_8B 1715 * @arg @ref ADC_RESOLUTION_6B 1716 * @retval Temperature (unit: degree Celsius) 1717 */ 1718 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 1719 __TEMPSENSOR_TYP_CALX_V__,\ 1720 __TEMPSENSOR_CALX_TEMP__,\ 1721 __VREFANALOG_VOLTAGE__,\ 1722 __TEMPSENSOR_ADC_DATA__,\ 1723 __ADC_RESOLUTION__) \ 1724 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 1725 (__TEMPSENSOR_TYP_CALX_V__),\ 1726 (__TEMPSENSOR_CALX_TEMP__),\ 1727 (__VREFANALOG_VOLTAGE__),\ 1728 (__TEMPSENSOR_ADC_DATA__),\ 1729 (__ADC_RESOLUTION__)) 1730 1731 /** 1732 * @} 1733 */ 1734 1735 /** 1736 * @} 1737 */ 1738 1739 /* Include ADC HAL Extended module */ 1740 #include "stm32wbaxx_hal_adc_ex.h" 1741 1742 /* Exported functions --------------------------------------------------------*/ 1743 /** @addtogroup ADC_Exported_Functions 1744 * @{ 1745 */ 1746 1747 /** @addtogroup ADC_Exported_Functions_Group1 1748 * @brief Initialization and Configuration functions 1749 * @{ 1750 */ 1751 /* Initialization and de-initialization functions ****************************/ 1752 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 1753 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1754 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 1755 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 1756 1757 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1758 /* Callbacks Register/UnRegister functions ***********************************/ 1759 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, 1760 pADC_CallbackTypeDef pCallback); 1761 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1762 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1763 /** 1764 * @} 1765 */ 1766 1767 /** @addtogroup ADC_Exported_Functions_Group2 1768 * @brief IO operation functions 1769 * @{ 1770 */ 1771 /* IO operation functions *****************************************************/ 1772 1773 /* Blocking mode: Polling */ 1774 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 1775 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 1776 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1777 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 1778 1779 /* Non-blocking mode: Interruption */ 1780 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 1781 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 1782 1783 /* Non-blocking mode: DMA */ 1784 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1785 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 1786 1787 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1788 uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); 1789 1790 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1791 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 1792 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 1793 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 1794 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 1795 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1796 /** 1797 * @} 1798 */ 1799 1800 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 1801 * @brief Peripheral Control functions 1802 * @{ 1803 */ 1804 /* Peripheral Control functions ***********************************************/ 1805 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig); 1806 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, 1807 const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); 1808 1809 /** 1810 * @} 1811 */ 1812 1813 /* Peripheral State functions *************************************************/ 1814 /** @addtogroup ADC_Exported_Functions_Group4 1815 * @{ 1816 */ 1817 uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); 1818 uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); 1819 1820 /** 1821 * @} 1822 */ 1823 1824 /** 1825 * @} 1826 */ 1827 1828 /* Private functions ---------------------------------------------------------*/ 1829 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc); 1830 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 1831 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 1832 1833 /** 1834 * @} 1835 */ 1836 1837 /** 1838 * @} 1839 */ 1840 1841 /** 1842 * @} 1843 */ 1844 1845 #ifdef __cplusplus 1846 } 1847 #endif 1848 1849 1850 #endif /* STM32WBAxx_HAL_ADC_H */ 1851
