1 /**
2 ******************************************************************************
3 * @file partition_stm32u545xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32U545xx Device Initial Setup for Secure / Non-Secure Zones
6 * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template.
7 *
8 * This file contains:
9 * - Initialize Security Attribution Unit (SAU) CTRL register
10 * - Setup behavior of Sleep and Exception Handling
11 * - Setup behavior of Floating Point Unit
12 * - Setup Interrupt Target
13 *
14 ******************************************************************************/
15 /**
16 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
17 * Portions Copyright (c) 2023 STMicroelectronics, all rights reserved
18 *
19 * SPDX-License-Identifier: Apache-2.0
20 *
21 * Licensed under the Apache License, Version 2.0 (the License); you may
22 * not use this file except in compliance with the License.
23 * You may obtain a copy of the License at
24 *
25 * http://www.apache.org/licenses/LICENSE-2.0
26 *
27 * Unless required by applicable law or agreed to in writing, software
28 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
29 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
30 * See the License for the specific language governing permissions and
31 * limitations under the License.
32 */
33
34 #ifndef PARTITION_STM32U545XX_H
35 #define PARTITION_STM32U545XX_H
36
37 /*
38 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
39 */
40
41 /*
42 // <e>Initialize Security Attribution Unit (SAU) CTRL register
43 */
44 #define SAU_INIT_CTRL 1
45
46 /*
47 // <q> Enable SAU
48 // <i> Value for SAU->CTRL register bit ENABLE
49 */
50 #define SAU_INIT_CTRL_ENABLE 0
51
52 /*
53 // <o> When SAU is disabled
54 // <0=> All Memory is Secure
55 // <1=> All Memory is Non-Secure
56 // <i> Value for SAU->CTRL register bit ALLNS
57 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
58 */
59 #define SAU_INIT_CTRL_ALLNS 1
60
61 /*
62 // </e>
63 */
64
65 /*
66 // <h>Initialize Security Attribution Unit (SAU) Address Regions
67 // <i>SAU configuration specifies regions to be one of:
68 // <i> - Secure and Non-Secure Callable
69 // <i> - Non-Secure
70 // <i>Note: All memory regions not configured by SAU are Secure
71 */
72 #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
73
74 /*
75 // <e>Initialize SAU Region 0
76 // <i> Setup SAU Region 0 memory attributes
77 */
78 #define SAU_INIT_REGION0 0
79
80 /*
81 // <o>Start Address <0-0xFFFFFFE0>
82 */
83 #define SAU_INIT_START0 0x0C03E000 /* start address of SAU region 0 */
84
85 /*
86 // <o>End Address <0x1F-0xFFFFFFFF>
87 */
88 #define SAU_INIT_END0 0x0C03FFFF /* end address of SAU region 0 */
89
90 /*
91 // <o>Region is
92 // <0=>Non-Secure
93 // <1=>Secure, Non-Secure Callable
94 */
95 #define SAU_INIT_NSC0 1
96 /*
97 // </e>
98 */
99
100 /*
101 // <e>Initialize SAU Region 1
102 // <i> Setup SAU Region 1 memory attributes
103 */
104 #define SAU_INIT_REGION1 0
105
106 /*
107 // <o>Start Address <0-0xFFFFFFE0>
108 */
109 #define SAU_INIT_START1 0x08040000 /* start address of SAU region 1 */
110
111 /*
112 // <o>End Address <0x1F-0xFFFFFFFF>
113 */
114 #define SAU_INIT_END1 0x0807FFFF /* end address of SAU region 1 */
115
116 /*
117 // <o>Region is
118 // <0=>Non-Secure
119 // <1=>Secure, Non-Secure Callable
120 */
121 #define SAU_INIT_NSC1 0
122 /*
123 // </e>
124 */
125
126 /*
127 // <e>Initialize SAU Region 2
128 // <i> Setup SAU Region 2 memory attributes
129 */
130 #define SAU_INIT_REGION2 0
131
132 /*
133 // <o>Start Address <0-0xFFFFFFE0>
134 */
135 #define SAU_INIT_START2 0x20030000 /* start address of SAU region 2 */
136
137 /*
138 // <o>End Address <0x1F-0xFFFFFFFF>
139 */
140 #define SAU_INIT_END2 0x2003FFFF /* end address of SAU region 2 */
141
142 /*
143 // <o>Region is
144 // <0=>Non-Secure
145 // <1=>Secure, Non-Secure Callable
146 */
147 #define SAU_INIT_NSC2 0
148 /*
149 // </e>
150 */
151
152 /*
153 // <e>Initialize SAU Region 3
154 // <i> Setup SAU Region 3 memory attributes
155 */
156 #define SAU_INIT_REGION3 0
157
158 /*
159 // <o>Start Address <0-0xFFFFFFE0>
160 */
161 #define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */
162
163 /*
164 // <o>End Address <0x1F-0xFFFFFFFF>
165 */
166 #define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */
167
168 /*
169 // <o>Region is
170 // <0=>Non-Secure
171 // <1=>Secure, Non-Secure Callable
172 */
173 #define SAU_INIT_NSC3 0
174 /*
175 // </e>
176 */
177
178 /*
179 // <e>Initialize SAU Region 4
180 // <i> Setup SAU Region 4 memory attributes
181 */
182 #define SAU_INIT_REGION4 0
183
184 /*
185 // <o>Start Address <0-0xFFFFFFE0>
186 */
187 #define SAU_INIT_START4 0x90000000 /* start address of SAU region 4 */
188
189 /*
190 // <o>End Address <0x1F-0xFFFFFFFF>
191 */
192 #define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */
193
194 /*
195 // <o>Region is
196 // <0=>Non-Secure
197 // <1=>Secure, Non-Secure Callable
198 */
199 #define SAU_INIT_NSC4 0
200 /*
201 // </e>
202 */
203
204 /*
205 // <e>Initialize SAU Region 5
206 // <i> Setup SAU Region 5 memory attributes
207 */
208 #define SAU_INIT_REGION5 0
209
210 /*
211 // <o>Start Address <0-0xFFFFFFE0>
212 */
213 #define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */
214
215 /*
216 // <o>End Address <0x1F-0xFFFFFFFF>
217 */
218 #define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */
219
220 /*
221 // <o>Region is
222 // <0=>Non-Secure
223 // <1=>Secure, Non-Secure Callable
224 */
225 #define SAU_INIT_NSC5 0
226 /*
227 // </e>
228 */
229
230 /*
231 // <e>Initialize SAU Region 6
232 // <i> Setup SAU Region 6 memory attributes
233 */
234 #define SAU_INIT_REGION6 0
235
236 /*
237 // <o>Start Address <0-0xFFFFFFE0>
238 */
239 #define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
240
241 /*
242 // <o>End Address <0x1F-0xFFFFFFFF>
243 */
244 #define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
245
246 /*
247 // <o>Region is
248 // <0=>Non-Secure
249 // <1=>Secure, Non-Secure Callable
250 */
251 #define SAU_INIT_NSC6 0
252 /*
253 // </e>
254 */
255
256 /*
257 // <e>Initialize SAU Region 7
258 // <i> Setup SAU Region 7 memory attributes
259 */
260 #define SAU_INIT_REGION7 0
261
262 /*
263 // <o>Start Address <0-0xFFFFFFE0>
264 */
265 #define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
266
267 /*
268 // <o>End Address <0x1F-0xFFFFFFFF>
269 */
270 #define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
271
272 /*
273 // <o>Region is
274 // <0=>Non-Secure
275 // <1=>Secure, Non-Secure Callable
276 */
277 #define SAU_INIT_NSC7 0
278 /*
279 // </e>
280 */
281
282 /*
283 // </h>
284 */
285
286 /*
287 // <e>Setup behaviour of Sleep and Exception Handling
288 */
289 #define SCB_CSR_AIRCR_INIT 0
290
291 /*
292 // <o> Deep Sleep can be enabled by
293 // <0=>Secure and Non-Secure state
294 // <1=>Secure state only
295 // <i> Value for SCB->CSR register bit DEEPSLEEPS
296 */
297 #define SCB_CSR_DEEPSLEEPS_VAL 0
298
299 /*
300 // <o>System reset request accessible from
301 // <0=> Secure and Non-Secure state
302 // <1=> Secure state only
303 // <i> Value for SCB->AIRCR register bit SYSRESETREQS
304 */
305 #define SCB_AIRCR_SYSRESETREQS_VAL 0
306
307 /*
308 // <o>Priority of Non-Secure exceptions is
309 // <0=> Not altered
310 // <1=> Lowered to 0x04-0x07
311 // <i> Value for SCB->AIRCR register bit PRIS
312 */
313 #define SCB_AIRCR_PRIS_VAL 0
314
315 /*
316 // <o>BusFault, HardFault, and NMI target
317 // <0=> Secure state
318 // <1=> Non-Secure state
319 // <i> Value for SCB->AIRCR register bit BFHFNMINS
320 */
321 #define SCB_AIRCR_BFHFNMINS_VAL 0
322
323 /*
324 // </e>
325 */
326
327 /*
328 // <e>Setup behaviour of Floating Point Unit
329 */
330 #define TZ_FPU_NS_USAGE 1
331
332 /*
333 // <o>Floating Point Unit usage
334 // <0=> Secure state only
335 // <3=> Secure and Non-Secure state
336 // <i> Value for SCB->NSACR register bits CP10, CP11
337 */
338 #define SCB_NSACR_CP10_11_VAL 3
339
340 /*
341 // <o>Treat floating-point registers as Secure
342 // <0=> Disabled
343 // <1=> Enabled
344 // <i> Value for FPU->FPCCR register bit TS
345 */
346 #define FPU_FPCCR_TS_VAL 0
347
348 /*
349 // <o>Clear on return (CLRONRET) accessibility
350 // <0=> Secure and Non-Secure state
351 // <1=> Secure state only
352 // <i> Value for FPU->FPCCR register bit CLRONRETS
353 */
354 #define FPU_FPCCR_CLRONRETS_VAL 0
355
356 /*
357 // <o>Clear floating-point caller saved registers on exception return
358 // <0=> Disabled
359 // <1=> Enabled
360 // <i> Value for FPU->FPCCR register bit CLRONRET
361 */
362 #define FPU_FPCCR_CLRONRET_VAL 1
363
364 /*
365 // </e>
366 */
367
368 /*
369 // <h>Setup Interrupt Target
370 */
371
372 /*
373 // <e>Initialize ITNS 0 (Interrupts 0..31)
374 */
375 #define NVIC_INIT_ITNS0 1
376
377 /*
378 // Interrupts 0..31
379 // <o.0> WWDG_IRQn <0=> Secure state <1=> Non-Secure state
380 // <o.1> PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state
381 // <o.2> RTC_IRQn <0=> Secure state <1=> Non-Secure state
382 // <o.3> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
383 // <o.4> TAMP_IRQn <0=> Secure state <1=> Non-Secure state
384 // <o.5> RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state
385 // <o.6> FLASH_IRQn <0=> Secure state <1=> Non-Secure state
386 // <o.7> FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state
387 // <o.8> GTZC_IRQn <0=> Secure state <1=> Non-Secure state
388 // <o.9> RCC_IRQn <0=> Secure state <1=> Non-Secure state
389 // <o.10> RCC_S_IRQn <0=> Secure state <1=> Non-Secure state
390 // <o.11> EXTI0_IRQn <0=> Secure state <1=> Non-Secure state
391 // <o.12> EXTI1_IRQn <0=> Secure state <1=> Non-Secure state
392 // <o.13> EXTI2_IRQn <0=> Secure state <1=> Non-Secure state
393 // <o.14> EXTI3_IRQn <0=> Secure state <1=> Non-Secure state
394 // <o.15> EXTI4_IRQn <0=> Secure state <1=> Non-Secure state
395 // <o.16> EXTI5_IRQn <0=> Secure state <1=> Non-Secure state
396 // <o.17> EXTI6_IRQn <0=> Secure state <1=> Non-Secure state
397 // <o.18> EXTI7_IRQn <0=> Secure state <1=> Non-Secure state
398 // <o.19> EXTI8_IRQn <0=> Secure state <1=> Non-Secure state
399 // <o.20> EXTI9_IRQn <0=> Secure state <1=> Non-Secure state
400 // <o.21> EXTI10_IRQn <0=> Secure state <1=> Non-Secure state
401 // <o.22> EXTI11_IRQn <0=> Secure state <1=> Non-Secure state
402 // <o.23> EXTI12_IRQn <0=> Secure state <1=> Non-Secure state
403 // <o.24> EXTI13_IRQn <0=> Secure state <1=> Non-Secure state
404 // <o.25> EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
405 // <o.26> EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
406 // <o.27> IWDG_IRQn <0=> Secure state <1=> Non-Secure state
407 // <o.28> SAES_IRQn <0=> Secure state <1=> Non-Secure state
408 // <o.29> GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
409 // <o.30> GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
410 // <o.31> GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
411 */
412 #define NVIC_INIT_ITNS0_VAL 0x00000000
413
414 /*
415 // </e>
416 */
417
418 /*
419 // <e>Initialize ITNS 1 (Interrupts 32..63)
420 */
421 #define NVIC_INIT_ITNS1 1
422
423 /*
424 // Interrupts 32..63
425 // <o.0> GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
426 // <o.1> GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
427 // <o.2> GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
428 // <o.3> GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
429 // <o.4> GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
430 // <o.5> ADC1_IRQn <0=> Secure state <1=> Non-Secure state
431 // <o.6> DAC1_IRQn <0=> Secure state <1=> Non-Secure state
432 // <o.7> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
433 // <o.8> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
434 // <o.9> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
435 // <o.10> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
436 // <o.11> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
437 // <o.12> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
438 // <o.13> TIM2_IRQn <0=> Secure state <1=> Non-Secure state
439 // <o.14> TIM3_IRQn <0=> Secure state <1=> Non-Secure state
440 // <o.15> TIM4_IRQn <0=> Secure state <1=> Non-Secure state
441 // <o.16> TIM5_IRQn <0=> Secure state <1=> Non-Secure state
442 // <o.17> TIM6_IRQn <0=> Secure state <1=> Non-Secure state
443 // <o.18> TIM7_IRQn <0=> Secure state <1=> Non-Secure state
444 // <o.19> TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
445 // <o.20> TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
446 // <o.21> TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
447 // <o.22> TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
448 // <o.23> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
449 // <o.24> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
450 // <o.25> I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
451 // <o.26> I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
452 // <o.27> SPI1_IRQn <0=> Secure state <1=> Non-Secure state
453 // <o.28> SPI2_IRQn <0=> Secure state <1=> Non-Secure state
454 // <o.29> USART1_IRQn <0=> Secure state <1=> Non-Secure state
455 // <o.31> USART3_IRQn <0=> Secure state <1=> Non-Secure state
456 */
457 #define NVIC_INIT_ITNS1_VAL 0x00000000
458
459 /*
460 // </e>
461 */
462
463 /*
464 // <e>Initialize ITNS 2 (Interrupts 64..95)
465 */
466 #define NVIC_INIT_ITNS2 1
467
468 /*
469 // Interrupts 64..95
470 // <o.0> UART4_IRQn <0=> Secure state <1=> Non-Secure state
471 // <o.1> UART5_IRQn <0=> Secure state <1=> Non-Secure state
472 // <o.2> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
473 // <o.3> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
474 // <o.4> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
475 // <o.5> TIM15_IRQn <0=> Secure state <1=> Non-Secure state
476 // <o.6> TIM16_IRQn <0=> Secure state <1=> Non-Secure state
477 // <o.7> TIM17_IRQn <0=> Secure state <1=> Non-Secure state
478 // <o.8> COMP_IRQn <0=> Secure state <1=> Non-Secure state
479 // <o.9> USB_IRQn <0=> Secure state <1=> Non-Secure state
480 // <o.10> CRS_IRQn <0=> Secure state <1=> Non-Secure state
481 // <o.12> OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state
482 // <o.13> PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state
483 // <o.14> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
484 // <o.16> GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state
485 // <o.17> GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state
486 // <o.18> GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
487 // <o.19> GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
488 // <o.20> GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
489 // <o.21> GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
490 // <o.22> GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
491 // <o.23> GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
492 // <o.24> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
493 // <o.25> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
494 // <o.26> SAI1_IRQn <0=> Secure state <1=> Non-Secure state
495 // <o.28> TSC_IRQn <0=> Secure state <1=> Non-Secure state
496 // <o.29> AES_IRQn <0=> Secure state <1=> Non-Secure state
497 // <o.30> RNG_IRQn <0=> Secure state <1=> Non-Secure state
498 // <o.31> FPU_IRQn <0=> Secure state <1=> Non-Secure state
499 */
500 #define NVIC_INIT_ITNS2_VAL 0x00000000
501
502 /*
503 // </e>
504 */
505
506 /*
507 // <e>Initialize ITNS 3 (Interrupts 96..125)
508 */
509 #define NVIC_INIT_ITNS3 1
510
511 /*
512 // Interrupts 96..125
513 // <o.0> HASH_IRQn <0=> Secure state <1=> Non-Secure state
514 // <o.1> PKA_IRQn <0=> Secure state <1=> Non-Secure state
515 // <o.2> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
516 // <o.3> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
517 // <o.4> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
518 // <o.5> I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
519 // <o.6> MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state
520 // <o.7> MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state
521 // <o.11> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
522 // <o.12> OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state
523 // <o.14> LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state
524 // <o.15> DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state
525 // <o.16> ADF1_IRQn <0=> Secure state <1=> Non-Secure state
526 // <o.17> ADC4_IRQn <0=> Secure state <1=> Non-Secure state
527 // <o.18> LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
528 // <o.19> LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
529 // <o.20> LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
530 // <o.21> LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
531 // <o.23> DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state
532 // <o.27> CORDIC_IRQn <0=> Secure state <1=> Non-Secure state
533 // <o.28> FMAC_IRQn <0=> Secure state <1=> Non-Secure state
534 // <o.29> LSECSSD_IRQn <0=> Secure state <1=> Non-Secure state
535 */
536 #define NVIC_INIT_ITNS3_VAL 0x00000000
537
538 /*
539 // </e>
540 */
541
542 /*
543 // </h>
544 */
545
546 /*
547 max 8 SAU regions.
548 SAU regions are defined in partition.h
549 */
550
551 #define SAU_INIT_REGION(n) \
552 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
553 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
554 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
555 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
556
557 /**
558 \brief Setup a SAU Region
559 \details Writes the region information contained in SAU_Region to the
560 registers SAU_RNR, SAU_RBAR, and SAU_RLAR
561 */
TZ_SAU_Setup(void)562 __STATIC_INLINE void TZ_SAU_Setup (void)
563 {
564
565 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
566
567 #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
568 SAU_INIT_REGION(0);
569 #endif
570
571 #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
572 SAU_INIT_REGION(1);
573 #endif
574
575 #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
576 SAU_INIT_REGION(2);
577 #endif
578
579 #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
580 SAU_INIT_REGION(3);
581 #endif
582
583 #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
584 SAU_INIT_REGION(4);
585 #endif
586
587 #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
588 SAU_INIT_REGION(5);
589 #endif
590
591 #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
592 SAU_INIT_REGION(6);
593 #endif
594
595 #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
596 SAU_INIT_REGION(7);
597 #endif
598
599 /* repeat this for all possible SAU regions */
600
601 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
602
603
604 #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
605 SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
606 ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
607 #endif
608
609 #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
610 SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
611 ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
612
613 SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
614 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
615 ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
616 ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
617 ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
618 ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
619 #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
620
621 #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
622 defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
623
624 SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
625 ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
626
627 FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
628 ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
629 ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
630 ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
631 #endif
632
633 #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
634 NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
635 #endif
636
637 #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
638 NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
639 #endif
640
641 #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
642 NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
643 #endif
644
645 #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
646 NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
647 #endif
648
649 }
650
651 #endif /* PARTITION_STM32U545XX_H */
652
