1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32u5xx_ll_rcc.h"
22 #ifdef USE_FULL_ASSERT
23 #include "stm32_assert.h"
24 #else
25 #define assert_param(expr) ((void)0U)
26 #endif /* USE_FULL_ASSERT */
27 /** @addtogroup STM32U5xx_LL_Driver
28 * @{
29 */
30
31 #if defined(RCC)
32
33 /** @addtogroup RCC_LL
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /* Private constants ---------------------------------------------------------*/
40 /* Private macros ------------------------------------------------------------*/
41 /** @addtogroup RCC_LL_Private_Macros
42 * @{
43 */
44 #if defined(USART6)
45 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
46 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
47 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)\
48 || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE))
49 #elif defined(USART2)
50 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
51 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
52 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
53 #else
54 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
55 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
56 #endif /* defined(USART6) */
57
58 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
59 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
60
61 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
62
63 #if defined(I2C5) & defined(I2C6)
64 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
65 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
66 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
67 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE)\
68 || ((__VALUE__) == LL_RCC_I2C5_CLKSOURCE)\
69 || ((__VALUE__) == LL_RCC_I2C6_CLKSOURCE))
70 #else
71 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
72 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
73 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
74 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
75 #endif /* defined(I2C5) & defined(I2C6) */
76
77 #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \
78 || ((__VALUE__) == LL_RCC_SPI2_CLKSOURCE) \
79 || ((__VALUE__) == LL_RCC_SPI3_CLKSOURCE))
80
81 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
82 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \
83 || ((__VALUE__) == LL_RCC_LPTIM34_CLKSOURCE))
84 #if defined(SAI2)
85 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
86 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
87 #else
88 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE))
89 #endif /* SAI2 */
90
91 #define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC_KERNELCLKSOURCE))
92
93 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC_CLKSOURCE))
94
95 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
96
97 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
98
99 #define IS_LL_RCC_ADCDAC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADCDAC_CLKSOURCE))
100
101 #define IS_LL_RCC_MDF1_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_MDF1_CLKSOURCE))
102
103 #define IS_LL_RCC_DAC1_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DAC1_CLKSOURCE))
104
105 #define IS_LL_RCC_ADF1_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADF1_CLKSOURCE))
106
107 #define IS_LL_RCC_OCTOSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OCTOSPI_CLKSOURCE))
108
109 #if defined(HSPI1)
110 #define IS_LL_RCC_HSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_HSPI_CLKSOURCE))
111 #endif /* defined(HSPI1) */
112
113 #define IS_LL_RCC_SAES_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAES_CLKSOURCE))
114
115 #define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))
116
117 #if defined(DSI)
118 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
119 #endif /* defined(DSI) */
120
121 #if defined(LTDC)
122 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
123 #endif /* defined(LTDC) */
124
125 /**
126 * @}
127 */
128
129 /* Private function prototypes -----------------------------------------------*/
130 /** @defgroup RCC_LL_Private_Functions RCC Private functions
131 * @{
132 */
133 static uint32_t RCC_GetSystemClockFreq(void);
134 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
135 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
136 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
137 static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
138 static uint32_t RCC_PLL1_GetFreqDomain_SYS(void);
139 static uint32_t RCC_PLL1_GetFreqDomain_SAI(void);
140 static uint32_t RCC_PLL1_GetFreqDomain_48M(void);
141 static uint32_t RCC_PLL2_GetFreqDomain_SAI(void);
142 static uint32_t RCC_PLL2_GetFreqDomain_48M(void);
143 static uint32_t RCC_PLL2_GetFreqDomain_ADC(void);
144 static uint32_t RCC_PLL3_GetFreqDomain_SAI(void);
145 static uint32_t RCC_PLL3_GetFreqDomain_48M(void);
146 #if defined(HSPI1) || defined(LTDC)
147 static uint32_t RCC_PLL3_GetFreqDomain_HSPI_LTDC(void);
148 #endif /* HSPI1 || LTDC */
149 /**
150 * @}
151 */
152
153 /* Exported functions --------------------------------------------------------*/
154 /** @addtogroup RCC_LL_Exported_Functions
155 * @{
156 */
157
158 /** @addtogroup RCC_LL_EF_Init
159 * @{
160 */
161
162 /**
163 * @brief Reset the RCC clock configuration to the default reset state.
164 * @note The default reset state of the clock configuration is given below:
165 * - MSI ON and used as system clock source
166 * - HSE, HSI, PLL1, PLL2 and PLL3 OFF
167 * - AHB, APB1, APB2 and APB3 prescaler set to 1.
168 * - CSS, MCO OFF
169 * - All interrupts disabled
170 * @note This function doesn't modify the configuration of the
171 * - Peripheral clocks
172 * - LSI, LSE and RTC clocks
173 * @retval An ErrorStatus enumeration value:
174 * - SUCCESS: RCC registers are de-initialized
175 * - ERROR: not applicable
176 */
LL_RCC_DeInit(void)177 ErrorStatus LL_RCC_DeInit(void)
178 {
179 uint32_t vl_mask;
180
181 /* Set MSION bit */
182 LL_RCC_MSIS_Enable();
183
184 /* Insure MSIRDY bit is set before writing default MSIRANGE value */
185 while (LL_RCC_MSIS_IsReady() == 0U)
186 {
187 }
188
189 /* Set MSIRANGE default value */
190 LL_RCC_MSIS_SetRange(LL_RCC_MSISRANGE_4);
191
192 /* Set MSITRIM bits to the reset value*/
193 LL_RCC_MSI_SetCalibTrimming(0, LL_RCC_MSI_OSCILLATOR_1);
194
195 /* Set HSITRIM bits to the reset value*/
196 LL_RCC_HSI_SetCalibTrimming(0x40U);
197
198 /* Reset CFGR register */
199 LL_RCC_WriteReg(CFGR1, 0x00000000U);
200 LL_RCC_WriteReg(CFGR2, 0x00000000U);
201 LL_RCC_WriteReg(CFGR3, 0x00000000U);
202
203 /* Read CR register */
204 vl_mask = LL_RCC_ReadReg(CR);
205
206 /* Reset HSION, HSIKERON, HSEON, PLL1ON, PLL2ON and PLL3ON bits */
207 CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSEON |
208 RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON));
209
210 /* Write new mask in CR register */
211 LL_RCC_WriteReg(CR, vl_mask);
212
213 /* Wait for PLL1RDY, PLL2RDY and PLL3RDY bits to be reset */
214 while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY | RCC_CR_PLL2RDY | RCC_CR_PLL3RDY) != 0U)
215 {
216 }
217
218 /* Reset PLL1DIVR register */
219 LL_RCC_WriteReg(PLL1DIVR, 0x01010280U);
220
221 /* Reset PLL2DIVR register */
222 LL_RCC_WriteReg(PLL2DIVR, 0x01010280U);
223
224 /* Reset PLL3DIVR register */
225 LL_RCC_WriteReg(PLL3DIVR, 0x01010280U);
226
227 /* Reset HSEBYP bit */
228 LL_RCC_HSE_DisableBypass();
229
230 /* Disable all interrupts */
231 LL_RCC_WriteReg(CIER, 0x00000000U);
232
233 /* Clear all interrupt flags */
234 vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSISRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | \
235 RCC_CICR_PLL1RDYC | RCC_CICR_PLL2RDYC | RCC_CICR_PLL3RDYC | RCC_CICR_HSI48RDYC | RCC_CICR_CSSC | \
236 RCC_CICR_MSIKRDYC;
237 LL_RCC_WriteReg(CICR, vl_mask);
238
239 /* Clear reset flags */
240 LL_RCC_ClearResetFlags();
241
242 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
243 /* Reset secure configuration */
244 LL_RCC_ConfigSecure(LL_RCC_ALL_NSEC);
245 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
246 return SUCCESS;
247 }
248
249 /**
250 * @}
251 */
252
253 /** @addtogroup RCC_LL_EF_Get_Freq
254 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
255 * and different peripheral clocks available on the device.
256 * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(*)
257 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
258 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
259 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
260 * or HSI_VALUE(**) or MSI_VALUE(*) multiplied/divided by the PLL factors.
261 * @note (*) MSI_VALUE is a constant defined in this file (default value
262 * 4 MHz) but the real value may vary depending on the variations
263 * in voltage and temperature.
264 * @note (**) HSI_VALUE is a constant defined in this file (default value
265 * 16 MHz) but the real value may vary depending on the variations
266 * in voltage and temperature.
267 * @note (***) HSE_VALUE is a constant defined in this file (default value
268 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
269 * frequency of the crystal used. Otherwise, this function may
270 * have wrong result.
271 * @note The result of this function could be incorrect when using fractional
272 * value for HSE crystal.
273 * @note This function can be used by the user application to compute the
274 * baud-rate for the communication peripherals or configure other parameters.
275 * @{
276 */
277
278 /**
279 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
280 * @note Each time SYSCLK, HCLK, PCLK1, PCLK2 and/or PCLK3 clock changes, this function
281 * must be called to update structure fields. Otherwise, any
282 * configuration based on this function will be incorrect.
283 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
284 * @retval None
285 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)286 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
287 {
288 /* Get SYSCLK frequency */
289 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
290
291 /* HCLK clock frequency */
292 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
293
294 /* PCLK1 clock frequency */
295 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
296
297 /* PCLK2 clock frequency */
298 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
299
300 /* PCLK3 clock frequency */
301 RCC_Clocks->PCLK3_Frequency = RCC_GetPCLK3ClockFreq(RCC_Clocks->HCLK_Frequency);
302 }
303
304 /**
305 * @brief Return USARTx clock frequency
306 * @param USARTxSource This parameter can be one of the following values:
307 * @arg @ref LL_RCC_USART1_CLKSOURCE
308 * @arg @ref LL_RCC_USART2_CLKSOURCE
309 * @arg @ref LL_RCC_USART3_CLKSOURCE
310 * @arg @ref LL_RCC_USART6_CLKSOURCE (*)
311 * @retval USART clock frequency (in Hz)
312 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
313 *
314 * (*) : USART6 is available only for STM32U59xxx and STM32U5Axxx devices.
315 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)316 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
317 {
318 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
319
320 /* Check parameter */
321 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
322
323 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
324 {
325 /* USART1CLK clock frequency */
326 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
327 {
328 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
329 usart_frequency = RCC_GetSystemClockFreq();
330 break;
331
332 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
333 if (LL_RCC_HSI_IsReady() == 1U)
334 {
335 usart_frequency = HSI_VALUE;
336 }
337 break;
338
339 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
340 if (LL_RCC_LSE_IsReady() == 1U)
341 {
342 usart_frequency = LSE_VALUE;
343 }
344 break;
345
346 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
347 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
348 break;
349
350 default:
351 /* unreachable code */
352 break;
353 }
354 }
355 #if defined (USART2)
356 else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
357 {
358 /* USART2CLK clock frequency */
359 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
360 {
361 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
362 usart_frequency = RCC_GetSystemClockFreq();
363 break;
364
365 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
366 if (LL_RCC_HSI_IsReady() == 1U)
367 {
368 usart_frequency = HSI_VALUE;
369 }
370 break;
371
372 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
373 if (LL_RCC_LSE_IsReady() == 1U)
374 {
375 usart_frequency = LSE_VALUE;
376 }
377 break;
378
379 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
380 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
381 break;
382
383 default:
384 /* unreachable code */
385 break;
386 }
387 }
388 #endif /* USART2 */
389 else if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
390 {
391 /* USART3CLK clock frequency */
392 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
393 {
394 case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
395 usart_frequency = RCC_GetSystemClockFreq();
396 break;
397
398 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
399 if (LL_RCC_HSI_IsReady() == 1U)
400 {
401 usart_frequency = HSI_VALUE;
402 }
403 break;
404
405 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
406 if (LL_RCC_LSE_IsReady() == 1U)
407 {
408 usart_frequency = LSE_VALUE;
409 }
410 break;
411
412 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
413 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
414 break;
415
416 default:
417 /* unreachable code */
418 break;
419 }
420 }
421 #if defined (USART6)
422 else if (USARTxSource == LL_RCC_USART6_CLKSOURCE)
423 {
424 /* USART6CLK clock frequency */
425 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
426 {
427 case LL_RCC_USART6_CLKSOURCE_SYSCLK: /* USART6 Clock is System Clock */
428 usart_frequency = RCC_GetSystemClockFreq();
429 break;
430
431 case LL_RCC_USART6_CLKSOURCE_HSI: /* USART6 Clock is HSI Osc. */
432 if (LL_RCC_HSI_IsReady() == 1U)
433 {
434 usart_frequency = HSI_VALUE;
435 }
436 break;
437
438 case LL_RCC_USART6_CLKSOURCE_LSE: /* USART6 Clock is LSE Osc. */
439 if (LL_RCC_LSE_IsReady() == 1U)
440 {
441 usart_frequency = LSE_VALUE;
442 }
443 break;
444
445 case LL_RCC_USART6_CLKSOURCE_PCLK1: /* USART6 Clock is PCLK1 */
446 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
447 break;
448
449 default:
450 /* unreachable code */
451 break;
452 }
453 }
454 #endif /* USART6 */
455 else
456 {
457 /* nothing to do */
458 }
459
460 return usart_frequency;
461 }
462
463 /**
464 * @brief Return UARTx clock frequency
465 * @param UARTxSource This parameter can be one of the following values:
466 * @arg @ref LL_RCC_UART4_CLKSOURCE
467 * @arg @ref LL_RCC_UART5_CLKSOURCE
468 * @retval UART clock frequency (in Hz)
469 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
470 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)471 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
472 {
473 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
474
475 /* Check parameter */
476 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
477
478 if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
479 {
480 /* UART4CLK clock frequency */
481 switch (LL_RCC_GetUARTClockSource(UARTxSource))
482 {
483 case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
484 uart_frequency = RCC_GetSystemClockFreq();
485 break;
486
487 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
488 if (LL_RCC_HSI_IsReady() == 1U)
489 {
490 uart_frequency = HSI_VALUE;
491 }
492 break;
493
494 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
495 if (LL_RCC_LSE_IsReady() == 1U)
496 {
497 uart_frequency = LSE_VALUE;
498 }
499 break;
500
501 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
502 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
503 break;
504
505 default:
506 /* unreachable code */
507 break;
508 }
509 }
510 else if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
511 {
512 /* UART5CLK clock frequency */
513 switch (LL_RCC_GetUARTClockSource(UARTxSource))
514 {
515 case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
516 uart_frequency = RCC_GetSystemClockFreq();
517 break;
518
519 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
520 if (LL_RCC_HSI_IsReady() == 1U)
521 {
522 uart_frequency = HSI_VALUE;
523 }
524 break;
525
526 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
527 if (LL_RCC_LSE_IsReady() == 1U)
528 {
529 uart_frequency = LSE_VALUE;
530 }
531 break;
532
533 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
534 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
535 break;
536
537 default:
538 /* unreachable code */
539 break;
540 }
541 }
542 else
543 {
544 /* nothing to do */
545 }
546
547 return uart_frequency;
548 }
549
550 /**
551 * @brief Return SPIx clock frequency
552 * @param SPIxSource This parameter can be one of the following values:
553 * @arg @ref LL_RCC_SPI1_CLKSOURCE
554 * @arg @ref LL_RCC_SPI2_CLKSOURCE
555 * @arg @ref LL_RCC_SPI3_CLKSOURCE
556 * @retval SPI clock frequency (in Hz)
557 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or MSIK) is not ready
558 */
LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)559 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
560 {
561 uint32_t SPI_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
562
563 /* Check parameter */
564 assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
565
566 if (SPIxSource == LL_RCC_SPI1_CLKSOURCE)
567 {
568 /* SPI1 CLK clock frequency */
569 switch (LL_RCC_GetSPIClockSource(SPIxSource))
570 {
571 case LL_RCC_SPI1_CLKSOURCE_SYSCLK: /* SPI1 Clock is System Clock */
572 SPI_frequency = RCC_GetSystemClockFreq();
573 break;
574
575 case LL_RCC_SPI1_CLKSOURCE_HSI: /* SPI1 Clock is HSI Osc. */
576 if (LL_RCC_HSI_IsReady() == 1U)
577 {
578 SPI_frequency = HSI_VALUE;
579 }
580 break;
581
582 case LL_RCC_SPI1_CLKSOURCE_MSIK: /* SPI1 Clock is MSIK Osc.*/
583 SPI_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
584 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
585 LL_RCC_MSIK_GetRange() :
586 LL_RCC_MSIK_GetRangeAfterStandby()));
587 break;
588
589 case LL_RCC_SPI1_CLKSOURCE_PCLK2: /* SPI1 Clock is PCLK2 */
590 SPI_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
591 break;
592
593 default:
594 /* unreachable code */
595 break;
596 }
597 }
598 else if (SPIxSource == LL_RCC_SPI2_CLKSOURCE)
599 {
600 /* SPI2 CLK clock frequency */
601 switch (LL_RCC_GetSPIClockSource(SPIxSource))
602 {
603 case LL_RCC_SPI2_CLKSOURCE_SYSCLK: /* SPI2 Clock is System Clock */
604 SPI_frequency = RCC_GetSystemClockFreq();
605 break;
606
607 case LL_RCC_SPI2_CLKSOURCE_HSI: /* SPI2 Clock is HSI Osc. */
608 if (LL_RCC_HSI_IsReady() == 1U)
609 {
610 SPI_frequency = HSI_VALUE;
611 }
612 break;
613
614 case LL_RCC_SPI2_CLKSOURCE_MSIK: /* SPI2 Clock is MSIK Osc.*/
615 SPI_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
616 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
617 LL_RCC_MSIK_GetRange() :
618 LL_RCC_MSIK_GetRangeAfterStandby()));
619 break;
620
621 case LL_RCC_SPI2_CLKSOURCE_PCLK1: /* SPI2 Clock is PCLK1 */
622 SPI_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
623 break;
624
625 default:
626 /* unreachable code */
627 break;
628
629 }
630 }
631 else if (SPIxSource == LL_RCC_SPI3_CLKSOURCE)
632 {
633 /* SPI3 CLK clock frequency */
634 switch (LL_RCC_GetSPIClockSource(SPIxSource))
635 {
636 case LL_RCC_SPI3_CLKSOURCE_SYSCLK: /* SPI3 Clock is System Clock */
637 SPI_frequency = RCC_GetSystemClockFreq();
638 break;
639
640 case LL_RCC_SPI3_CLKSOURCE_HSI: /* SPI3 Clock is HSI Osc. */
641 if (LL_RCC_HSI_IsReady() == 1U)
642 {
643 SPI_frequency = HSI_VALUE;
644 }
645 break;
646
647 case LL_RCC_SPI3_CLKSOURCE_MSIK: /* SPI3 Clock is MSIK Osc. */
648 SPI_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
649 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
650 LL_RCC_MSIK_GetRange() :
651 LL_RCC_MSIK_GetRangeAfterStandby()));
652 break;
653
654 case LL_RCC_SPI3_CLKSOURCE_PCLK3: /* SPI3 Clock is PCLK3 */
655 SPI_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
656 break;
657
658 default:
659 /* unreachable code */
660 break;
661 }
662 }
663 else
664 {
665 /* nothing to do */
666 }
667
668 return SPI_frequency;
669 }
670
671 /**
672 * @brief Return I2Cx clock frequency
673 * @param I2CxSource This parameter can be one of the following values:
674 * @arg @ref LL_RCC_I2C1_CLKSOURCE
675 * @arg @ref LL_RCC_I2C2_CLKSOURCE
676 * @arg @ref LL_RCC_I2C3_CLKSOURCE
677 * @arg @ref LL_RCC_I2C4_CLKSOURCE
678 * @retval I2C clock frequency (in Hz)
679 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or MSIK) is not ready
680 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)681 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
682 {
683 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
684
685 /* Check parameter */
686 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
687
688 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
689 {
690 /* I2C1 CLK clock frequency */
691 switch (LL_RCC_GetI2CClockSource(I2CxSource))
692 {
693 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
694 i2c_frequency = RCC_GetSystemClockFreq();
695 break;
696
697 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
698 if (LL_RCC_HSI_IsReady() == 1U)
699 {
700 i2c_frequency = HSI_VALUE;
701 }
702 break;
703
704 case LL_RCC_I2C1_CLKSOURCE_MSIK: /* I2C1 Clock is MSIK Osc.*/
705 i2c_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
706 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
707 LL_RCC_MSIK_GetRange() :
708 LL_RCC_MSIK_GetRangeAfterStandby()));
709 break;
710
711 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
712 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
713 break;
714
715 default:
716 /* unreachable code */
717 break;
718 }
719 }
720 else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
721 {
722 /* I2C2 CLK clock frequency */
723 switch (LL_RCC_GetI2CClockSource(I2CxSource))
724 {
725 case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
726 i2c_frequency = RCC_GetSystemClockFreq();
727 break;
728
729 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
730 if (LL_RCC_HSI_IsReady() == 1U)
731 {
732 i2c_frequency = HSI_VALUE;
733 }
734 break;
735
736 case LL_RCC_I2C2_CLKSOURCE_MSIK: /* I2C2 Clock is MSIK Osc.*/
737 i2c_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
738 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
739 LL_RCC_MSIK_GetRange() :
740 LL_RCC_MSIK_GetRangeAfterStandby()));
741 break;
742 case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
743 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
744 break;
745
746 default:
747 /* unreachable code */
748 break;
749 }
750 }
751 else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
752 {
753 /* I2C3 CLK clock frequency */
754 switch (LL_RCC_GetI2CClockSource(I2CxSource))
755 {
756 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
757 i2c_frequency = RCC_GetSystemClockFreq();
758 break;
759
760 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
761 if (LL_RCC_HSI_IsReady() == 1U)
762 {
763 i2c_frequency = HSI_VALUE;
764 }
765 break;
766
767 case LL_RCC_I2C3_CLKSOURCE_MSIK: /* I2C3 Clock is MSIK Osc.*/
768 i2c_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
769 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
770 LL_RCC_MSIK_GetRange() :
771 LL_RCC_MSIK_GetRangeAfterStandby()));
772 break;
773 case LL_RCC_I2C3_CLKSOURCE_PCLK3: /* I2C3 Clock is PCLK3 */
774 i2c_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
775 break;
776
777 default:
778 /* unreachable code */
779 break;
780 }
781 }
782 else if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
783 {
784 /* I2C4 CLK clock frequency */
785 switch (LL_RCC_GetI2CClockSource(I2CxSource))
786 {
787 case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
788 i2c_frequency = RCC_GetSystemClockFreq();
789 break;
790
791 case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
792 if (LL_RCC_HSI_IsReady() == 1U)
793 {
794 i2c_frequency = HSI_VALUE;
795 }
796 break;
797
798 case LL_RCC_I2C4_CLKSOURCE_MSIK: /* I2C4 Clock is MSIK Osc.*/
799 i2c_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
800 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
801 LL_RCC_MSIK_GetRange() :
802 LL_RCC_MSIK_GetRangeAfterStandby()));
803 break;
804 case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */
805 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
806 break;
807
808 default:
809 /* unreachable code */
810 break;
811 }
812 }
813 #if defined(I2C5)
814 else if (I2CxSource == LL_RCC_I2C5_CLKSOURCE)
815 {
816 /* I2C5 CLK clock frequency */
817 switch (LL_RCC_GetI2CClockSource(I2CxSource))
818 {
819 case LL_RCC_I2C5_CLKSOURCE_SYSCLK: /* I2C5 Clock is System Clock */
820 i2c_frequency = RCC_GetSystemClockFreq();
821 break;
822
823 case LL_RCC_I2C5_CLKSOURCE_HSI: /* I2C5 Clock is HSI Osc. */
824 if (LL_RCC_HSI_IsReady() == 1U)
825 {
826 i2c_frequency = HSI_VALUE;
827 }
828 break;
829
830 case LL_RCC_I2C5_CLKSOURCE_MSIK: /* I2C5 Clock is MSIK Osc.*/
831 i2c_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
832 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
833 LL_RCC_MSIK_GetRange() :
834 LL_RCC_MSIK_GetRangeAfterStandby()));
835 break;
836 case LL_RCC_I2C5_CLKSOURCE_PCLK1: /* I2C5 Clock is PCLK1 */
837 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
838 break;
839
840 default:
841 /* unreachable code */
842 break;
843 }
844 }
845 #endif /* I2C5 */
846 #if defined(I2C6)
847 else if (I2CxSource == LL_RCC_I2C6_CLKSOURCE)
848 {
849 /* I2C6 CLK clock frequency */
850 switch (LL_RCC_GetI2CClockSource(I2CxSource))
851 {
852 case LL_RCC_I2C6_CLKSOURCE_SYSCLK: /* I2C6 Clock is System Clock */
853 i2c_frequency = RCC_GetSystemClockFreq();
854 break;
855
856 case LL_RCC_I2C6_CLKSOURCE_HSI: /* I2C6 Clock is HSI Osc. */
857 if (LL_RCC_HSI_IsReady() == 1U)
858 {
859 i2c_frequency = HSI_VALUE;
860 }
861 break;
862
863 case LL_RCC_I2C6_CLKSOURCE_MSIK: /* I2C6 Clock is MSIK Osc.*/
864 i2c_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
865 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
866 LL_RCC_MSIK_GetRange() :
867 LL_RCC_MSIK_GetRangeAfterStandby()));
868 break;
869 case LL_RCC_I2C6_CLKSOURCE_PCLK1: /* I2C6 Clock is PCLK1 */
870 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
871 break;
872
873 default:
874 /* unreachable code */
875 break;
876 }
877 }
878 #endif /* I2C6 */
879 else
880 {
881 /* nothing to do */
882 }
883
884 return i2c_frequency;
885 }
886
887 /**
888 * @brief Return LPUARTx clock frequency
889 * @param LPUARTxSource This parameter can be one of the following values:
890 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
891 * @retval LPUART clock frequency (in Hz)
892 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
893 */
LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)894 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
895 {
896 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
897
898 /* Check parameter */
899 assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
900
901 /* LPUART1CLK clock frequency */
902 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
903 {
904 case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
905 lpuart_frequency = RCC_GetSystemClockFreq();
906 break;
907
908 case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
909 if (LL_RCC_HSI_IsReady() == 1U)
910 {
911 lpuart_frequency = HSI_VALUE;
912 }
913 break;
914
915 case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
916 if (LL_RCC_LSE_IsReady() == 1U)
917 {
918 lpuart_frequency = LSE_VALUE;
919 }
920 break;
921
922 case LL_RCC_LPUART1_CLKSOURCE_PCLK3: /* LPUART1 Clock is PCLK3 */
923 lpuart_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
924 break;
925
926 default:
927 /* unreachable code */
928 break;
929 }
930
931 return lpuart_frequency;
932 }
933
934 /**
935 * @brief Return LPTIMx clock frequency
936 * @param LPTIMxSource This parameter can be one of the following values:
937 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
938 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
939 * @arg @ref LL_RCC_LPTIM34_CLKSOURCE
940 * @retval LPTIM clock frequency (in Hz)
941 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
942 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)943 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
944 {
945 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
946
947 /* Check parameter */
948 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
949
950 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
951 {
952 /* LPTIM1CLK clock frequency */
953 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
954 {
955 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
956 if (LL_RCC_LSI_IsReady() == 1U)
957 {
958 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV) == RCC_BDCR_LSIPREDIV)
959 {
960 lptim_frequency = LSI_VALUE / 128U;
961 }
962 else
963 {
964 lptim_frequency = LSI_VALUE;
965 }
966 }
967 break;
968
969 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
970 if (LL_RCC_HSI_IsReady() == 1U)
971 {
972 lptim_frequency = HSI_VALUE;
973 }
974 break;
975
976 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
977 if (LL_RCC_LSE_IsReady() == 1U)
978 {
979 lptim_frequency = LSE_VALUE;
980 }
981 break;
982
983 case LL_RCC_LPTIM1_CLKSOURCE_MSIK: /* LPTIM1 Clock is MSIK Osc.*/
984 lptim_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
985 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
986 LL_RCC_MSIK_GetRange() :
987 LL_RCC_MSIK_GetRangeAfterStandby()));
988 break;
989
990 default:
991 /* unreachable code */
992 break;
993 }
994 }
995 else if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE)
996 {
997 /* LPTIM2CLK clock frequency */
998 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
999 {
1000 case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */
1001 if (LL_RCC_LSI_IsReady() == 1U)
1002 {
1003 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV) == RCC_BDCR_LSIPREDIV)
1004 {
1005 lptim_frequency = LSI_VALUE / 128U;
1006 }
1007 else
1008 {
1009 lptim_frequency = LSI_VALUE;
1010 }
1011 }
1012 break;
1013
1014 case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */
1015 if (LL_RCC_HSI_IsReady() == 1U)
1016 {
1017 lptim_frequency = HSI_VALUE;
1018 }
1019 break;
1020
1021 case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */
1022 if (LL_RCC_LSE_IsReady() == 1U)
1023 {
1024 lptim_frequency = LSE_VALUE;
1025 }
1026 break;
1027
1028 case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */
1029 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1030 break;
1031
1032 default:
1033 /* unreachable code */
1034 break;
1035 }
1036 }
1037 else if (LPTIMxSource == LL_RCC_LPTIM34_CLKSOURCE)
1038 {
1039 /* LPTIM34CLK clock frequency */
1040 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
1041 {
1042 case LL_RCC_LPTIM34_CLKSOURCE_LSI: /* LPTIM34 Clock is LSI Osc. */
1043 if (LL_RCC_LSI_IsReady() == 1U)
1044 {
1045 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV) == RCC_BDCR_LSIPREDIV)
1046 {
1047 lptim_frequency = LSI_VALUE / 128U;
1048 }
1049 else
1050 {
1051 lptim_frequency = LSI_VALUE;
1052 }
1053 }
1054 break;
1055
1056 case LL_RCC_LPTIM34_CLKSOURCE_HSI: /* LPTIM34 Clock is HSI Osc. */
1057 if (LL_RCC_HSI_IsReady() == 1U)
1058 {
1059 lptim_frequency = HSI_VALUE;
1060 }
1061 break;
1062
1063 case LL_RCC_LPTIM34_CLKSOURCE_LSE: /* LPTIM34 Clock is LSE Osc. */
1064 if (LL_RCC_LSE_IsReady() == 1U)
1065 {
1066 lptim_frequency = LSE_VALUE;
1067 }
1068 break;
1069
1070 case LL_RCC_LPTIM34_CLKSOURCE_MSIK: /* LPTIM34 Clock is MSIK */
1071 lptim_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1072 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1073 LL_RCC_MSIK_GetRange() :
1074 LL_RCC_MSIK_GetRangeAfterStandby()));
1075 break;
1076
1077 default:
1078 /* unreachable code */
1079 break;
1080 }
1081 }
1082 else
1083 {
1084 /* nothing to do */
1085 }
1086
1087 return lptim_frequency;
1088 }
1089
1090 /**
1091 * @brief Return SAIx clock frequency
1092 * @param SAIxSource This parameter can be one of the following values:
1093 * @arg @ref LL_RCC_SAI1_CLKSOURCE
1094 * @arg @ref LL_RCC_SAI2_CLKSOURCE
1095 * @retval SAI clock frequency (in Hz)
1096 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
1097 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)1098 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
1099 {
1100 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1101
1102 /* Check parameter */
1103 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
1104
1105 if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
1106 {
1107 /* SAI1CLK clock frequency */
1108 switch (LL_RCC_GetSAIClockSource(SAIxSource))
1109 {
1110 case LL_RCC_SAI1_CLKSOURCE_PLL2: /* PLL2 clock used as SAI1 clock source */
1111 if (LL_RCC_PLL2_IsReady() == 1U)
1112 {
1113 if (LL_RCC_PLL2_IsEnabledDomain_SAI() != 0U)
1114 {
1115 sai_frequency = RCC_PLL2_GetFreqDomain_SAI();
1116 }
1117 }
1118 break;
1119
1120 case LL_RCC_SAI1_CLKSOURCE_PLL3: /* PLL3 clock used as SAI1 clock source */
1121 if (LL_RCC_PLL3_IsReady() == 1U)
1122 {
1123 if (LL_RCC_PLL3_IsEnabledDomain_SAI() != 0U)
1124 {
1125 sai_frequency = RCC_PLL3_GetFreqDomain_SAI();
1126 }
1127 }
1128 break;
1129
1130 case LL_RCC_SAI1_CLKSOURCE_PLL1: /* PLL1 clock used as SAI1 clock source */
1131 if (LL_RCC_PLL1_IsReady() == 1U)
1132 {
1133 if (LL_RCC_PLL1_IsEnabledDomain_SAI() != 0U)
1134 {
1135 sai_frequency = RCC_PLL1_GetFreqDomain_SAI();
1136 }
1137 }
1138 break;
1139
1140 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
1141 sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
1142 break;
1143
1144 default:
1145 /* unreachable code */
1146 break;
1147 }
1148 }
1149 #if defined(SAI2)
1150 else if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
1151 {
1152 /* SAI2CLK clock frequency */
1153 switch (LL_RCC_GetSAIClockSource(SAIxSource))
1154 {
1155 case LL_RCC_SAI2_CLKSOURCE_PLL2: /* PLL2 clock used as SAI2 clock source */
1156 if (LL_RCC_PLL2_IsReady() == 1U)
1157 {
1158 if (LL_RCC_PLL2_IsEnabledDomain_SAI() != 0U)
1159 {
1160 sai_frequency = RCC_PLL2_GetFreqDomain_SAI();
1161 }
1162 }
1163 break;
1164
1165 case LL_RCC_SAI2_CLKSOURCE_PLL3: /* PLL3 clock used as SAI2 clock source */
1166 if (LL_RCC_PLL3_IsReady() == 1U)
1167 {
1168 if (LL_RCC_PLL3_IsEnabledDomain_SAI() != 0U)
1169 {
1170 sai_frequency = RCC_PLL3_GetFreqDomain_SAI();
1171 }
1172 }
1173 break;
1174
1175 case LL_RCC_SAI2_CLKSOURCE_PLL1: /* PLL1 clock used as SAI2 clock source */
1176 if (LL_RCC_PLL1_IsReady() == 1U)
1177 {
1178 if (LL_RCC_PLL1_IsEnabledDomain_SAI() != 0U)
1179 {
1180 sai_frequency = RCC_PLL1_GetFreqDomain_SAI();
1181 }
1182 }
1183 break;
1184
1185 case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
1186 sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE;
1187 break;
1188
1189 default:
1190 /* unreachable code */
1191 break;
1192 }
1193 }
1194 #endif /* SAI2 */
1195 else
1196 {
1197 /* nothing to do */
1198 }
1199
1200 return sai_frequency;
1201 }
1202
1203 /**
1204 * @brief Return SDMMCx kernel clock frequency
1205 * @param SDMMCxSource This parameter can be one of the following values:
1206 * @arg @ref LL_RCC_SDMMC_KERNELCLKSOURCE
1207 * @retval SDMMC clock frequency (in Hz)
1208 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
1209 */
LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource)1210 uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource)
1211 {
1212 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1213
1214 /* Check parameter */
1215 assert_param(IS_LL_RCC_SDMMC_KERNELCLKSOURCE(SDMMCxSource));
1216
1217 /* SDMMC12CLK kernel clock frequency */
1218 switch (LL_RCC_GetSDMMCKernelClockSource(SDMMCxSource))
1219 {
1220 case LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK: /* 48MHz clock from internal multiplexor used as SDMMC1/2 clock source */
1221 sdmmc_frequency = LL_RCC_GetSDMMCClockFreq(LL_RCC_SDMMC_CLKSOURCE);
1222 break;
1223
1224 case LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1: /* PLL1 "P" output (PLL1CLK) clock used as SDMMC1/2 clock source */
1225 if (LL_RCC_PLL1_IsReady() == 1U)
1226 {
1227 if (LL_RCC_PLL1_IsEnabledDomain_SAI() != 0U)
1228 {
1229 sdmmc_frequency = RCC_PLL1_GetFreqDomain_SAI();
1230 }
1231 }
1232 break;
1233
1234 default:
1235 /* unreachable code */
1236 break;
1237 }
1238
1239 return sdmmc_frequency;
1240 }
1241
1242 /**
1243 * @brief Return SDMMCx clock frequency
1244 * @param SDMMCxSource This parameter can be one of the following values:
1245 * @arg @ref LL_RCC_SDMMC_CLKSOURCE
1246 * @retval SDMMC clock frequency (in Hz)
1247 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI /MSIK /HSI) or PLL is not ready
1248 */
LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)1249 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
1250 {
1251 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1252
1253 /* Check parameter */
1254 assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
1255
1256 /* SDMMC1CLK clock frequency */
1257 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
1258 {
1259 case LL_RCC_SDMMC12_CLKSOURCE_PLL2: /* PLL2 clock used as SDMMC12 clock source */
1260 if (LL_RCC_PLL2_IsReady() == 1U)
1261 {
1262 if (LL_RCC_PLL2_IsEnabledDomain_48M() != 0U)
1263 {
1264 sdmmc_frequency = RCC_PLL2_GetFreqDomain_48M();
1265 }
1266 }
1267 break;
1268
1269 case LL_RCC_SDMMC12_CLKSOURCE_PLL1: /* PLL1 clock used as SDMMC12 clock source */
1270 if (LL_RCC_PLL1_IsReady() == 1U)
1271 {
1272 if (LL_RCC_PLL1_IsEnabledDomain_48M() != 0U)
1273 {
1274 sdmmc_frequency = RCC_PLL1_GetFreqDomain_48M();
1275 }
1276 }
1277 break;
1278
1279 case LL_RCC_SDMMC12_CLKSOURCE_MSIK: /* MSIK clock used as SDMMC12 clock source */
1280 if (LL_RCC_MSIS_IsReady() == 1U)
1281 {
1282 sdmmc_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1283 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1284 LL_RCC_MSIK_GetRange() :
1285 LL_RCC_MSIK_GetRangeAfterStandby()));
1286 }
1287 break;
1288
1289 case LL_RCC_SDMMC12_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */
1290 if (LL_RCC_HSI48_IsReady() == 1U)
1291 {
1292 sdmmc_frequency = HSI48_VALUE;
1293 }
1294 break;
1295
1296 default:
1297 /* unreachable code */
1298 break;
1299 }
1300
1301 return sdmmc_frequency;
1302 }
1303
1304 /**
1305 * @brief Return RNGx clock frequency
1306 * @param RNGxSource This parameter can be one of the following values:
1307 * @arg @ref LL_RCC_RNG_CLKSOURCE
1308 * @retval RNG clock frequency (in Hz)
1309 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI48) or PLL is not ready
1310 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)1311 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
1312 {
1313 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1314
1315 /* Check parameter */
1316 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
1317
1318 /* RNGCLK clock frequency */
1319 switch (LL_RCC_GetRNGClockSource(RNGxSource))
1320 {
1321 case LL_RCC_RNG_CLKSOURCE_HSI: /* HSI clock used as RNG clock source */
1322 if (LL_RCC_HSI_IsReady() == 1U)
1323 {
1324 rng_frequency = HSI_VALUE;
1325 }
1326 break;
1327
1328 case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 clock used as RNG clock source */
1329 if (LL_RCC_HSI48_IsReady() == 1U)
1330 {
1331 rng_frequency = HSI48_VALUE;
1332 }
1333 break;
1334
1335 case LL_RCC_RNG_CLKSOURCE_HSI48_DIV2: /* HSI48DIV2 clock used as RNG clock source */
1336 if (LL_RCC_HSI48_IsReady() == 1U)
1337 {
1338 rng_frequency = (HSI48_VALUE / 2U);
1339 }
1340 break;
1341
1342 default:
1343 /* unreachable code */
1344 break;
1345
1346 }
1347
1348 return rng_frequency;
1349 }
1350
1351 /**
1352 * @brief Return USBx clock frequency
1353 * @param USBxSource This parameter can be one of the following values:
1354 * @arg @ref LL_RCC_USB_CLKSOURCE
1355 * @retval USB clock frequency (in Hz)
1356 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI /HSI48) or PLL is not ready
1357 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)1358 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
1359 {
1360 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1361
1362 /* Check parameter */
1363 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
1364
1365 /* USBCLK clock frequency */
1366 switch (LL_RCC_GetUSBClockSource(USBxSource))
1367 {
1368 case LL_RCC_USB_CLKSOURCE_PLL2: /* PLL2 clock used as USB clock source */
1369 if (LL_RCC_PLL2_IsReady() == 1U)
1370 {
1371 if (LL_RCC_PLL2_IsEnabledDomain_48M() != 0U)
1372 {
1373 usb_frequency = RCC_PLL2_GetFreqDomain_48M();
1374 }
1375 }
1376 break;
1377
1378 case LL_RCC_USB_CLKSOURCE_PLL1: /* PLL1 clock used as USB clock source */
1379 if (LL_RCC_PLL1_IsReady() == 1U)
1380 {
1381 if (LL_RCC_PLL1_IsEnabledDomain_48M() != 0U)
1382 {
1383 usb_frequency = RCC_PLL1_GetFreqDomain_48M();
1384 }
1385 }
1386 break;
1387
1388 case LL_RCC_USB_CLKSOURCE_MSIK: /* MSIK clock used as USB clock source */
1389 if (LL_RCC_MSIK_IsReady() == 1U)
1390 {
1391 usb_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1392 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1393 LL_RCC_MSIK_GetRange() :
1394 LL_RCC_MSIK_GetRangeAfterStandby()));
1395 }
1396 break;
1397
1398 case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */
1399 if (LL_RCC_HSI48_IsReady() == 1U)
1400 {
1401 usb_frequency = HSI48_VALUE;
1402 }
1403 break;
1404
1405 default:
1406 /* unreachable code */
1407 break;
1408 }
1409
1410 return usb_frequency;
1411 }
1412
1413 /**
1414 * @brief Return ADCxDAC clock frequency
1415 * @param ADCxSource This parameter can be one of the following values:
1416 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE
1417 * @retval ADC/DAC clock frequency (in Hz)
1418 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI /HSI /MSIK) or PLL is not ready
1419 */
LL_RCC_GetADCDACClockFreq(uint32_t ADCxSource)1420 uint32_t LL_RCC_GetADCDACClockFreq(uint32_t ADCxSource)
1421 {
1422 uint32_t adcdac_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1423
1424 /* Check parameter */
1425 assert_param(IS_LL_RCC_ADCDAC_CLKSOURCE(ADCxSource));
1426
1427 /* ADCCLK clock frequency */
1428 switch (LL_RCC_GetADCDACClockSource(ADCxSource))
1429 {
1430 case LL_RCC_ADCDAC_CLKSOURCE_HCLK: /* ADCDAC Clock is SYSCLK */
1431 adcdac_frequency = RCC_GetSystemClockFreq();
1432 break;
1433
1434 case LL_RCC_ADCDAC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADCDAC clock source */
1435 adcdac_frequency = RCC_GetSystemClockFreq();
1436 break;
1437
1438 case LL_RCC_ADCDAC_CLKSOURCE_PLL2: /* PLL2 clock used as ADCDAC clock source */
1439 if (LL_RCC_PLL2_IsReady() == 1U)
1440 {
1441 if (LL_RCC_PLL2_IsEnabledDomain_ADC() != 0U)
1442 {
1443 adcdac_frequency = RCC_PLL2_GetFreqDomain_ADC();
1444 }
1445 }
1446 break;
1447
1448 case LL_RCC_ADCDAC_CLKSOURCE_HSI: /*HSI clock used as ADCDAC clock source */
1449 if (LL_RCC_HSI_IsReady() == 1U)
1450 {
1451 adcdac_frequency = HSI_VALUE;
1452 }
1453 break;
1454
1455 case LL_RCC_ADCDAC_CLKSOURCE_HSE: /*HSE clock used as ADCDAC clock source */
1456 if (LL_RCC_HSE_IsReady() == 1U)
1457 {
1458 adcdac_frequency = HSE_VALUE;
1459 }
1460 break;
1461
1462 case LL_RCC_ADCDAC_CLKSOURCE_MSIK: /* MSIK clock used as ADCDAC clock source */
1463 if (LL_RCC_MSIK_IsReady() == 1U)
1464 {
1465 adcdac_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1466 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1467 LL_RCC_MSIK_GetRange() :
1468 LL_RCC_MSIK_GetRangeAfterStandby()));
1469 }
1470 break;
1471
1472 default:
1473 /* unreachable code */
1474 break;
1475 }
1476
1477 return adcdac_frequency;
1478 }
1479
1480 /**
1481 * @brief Return ADF1 clock frequency
1482 * @param ADF1Source This parameter can be one of the following values:
1483 * @arg @ref LL_RCC_ADF1_CLKSOURCE
1484 * @retval ADF1 clock frequency (in Hz)
1485 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSIK) or PLL is not ready
1486 */
LL_RCC_GetADF1ClockFreq(uint32_t ADF1Source)1487 uint32_t LL_RCC_GetADF1ClockFreq(uint32_t ADF1Source)
1488 {
1489 uint32_t ADF1_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1490
1491 /* Check parameter */
1492 assert_param(IS_LL_RCC_ADF1_CLKSOURCE(ADF1Source));
1493
1494 /* ADF11CLK clock frequency */
1495 switch (LL_RCC_GetADF1ClockSource(ADF1Source))
1496 {
1497 case LL_RCC_ADF1_CLKSOURCE_HCLK: /* ADF1 Clock is SYSCLK */
1498 ADF1_frequency = RCC_GetSystemClockFreq();
1499 break;
1500
1501 case LL_RCC_ADF1_CLKSOURCE_PLL1: /* ADF1 Clock is PLL1 */
1502 if (LL_RCC_PLL1_IsReady() != 0U)
1503 {
1504 if (LL_RCC_PLL1_IsEnabledDomain_SAI() != 0U)
1505 {
1506 ADF1_frequency = RCC_PLL1_GetFreqDomain_SAI();
1507 }
1508 }
1509 break;
1510
1511 case LL_RCC_ADF1_CLKSOURCE_PLL3: /* ADF1 Clock is PLL3 */
1512 if (LL_RCC_PLL3_IsReady() != 0U)
1513 {
1514 if (LL_RCC_PLL3_IsEnabledDomain_48M() != 0U)
1515 {
1516 ADF1_frequency = RCC_PLL3_GetFreqDomain_48M();
1517 }
1518 }
1519 break;
1520
1521 case LL_RCC_ADF1_CLKSOURCE_PIN: /* External input clock used as ADF1 clock source */
1522 ADF1_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
1523 break;
1524
1525 case LL_RCC_ADF1_CLKSOURCE_MSIK: /* ADF1 Clock is MSIK */
1526 ADF1_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1527 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1528 LL_RCC_MSIK_GetRange() :
1529 LL_RCC_MSIK_GetRangeAfterStandby()));
1530 break;
1531
1532 default:
1533 /* unreachable code */
1534 break;
1535 }
1536
1537 return ADF1_frequency;
1538 }
1539
1540 /**
1541 * @brief Return MDF1 clock frequency
1542 * @param MDF1Source This parameter can be one of the following values:
1543 * @arg @ref LL_RCC_MDF1_CLKSOURCE
1544 * @retval MDF1 clock frequency (in Hz)
1545 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSIK) or PLL is not ready
1546 */
LL_RCC_GetMDF1ClockFreq(uint32_t MDF1Source)1547 uint32_t LL_RCC_GetMDF1ClockFreq(uint32_t MDF1Source)
1548 {
1549 uint32_t MDF1_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1550
1551 /* Check parameter */
1552 assert_param(IS_LL_RCC_MDF1_CLKSOURCE(MDF1Source));
1553
1554 /* MDF11CLK clock frequency */
1555 switch (LL_RCC_GetMDF1ClockSource(MDF1Source))
1556 {
1557 case LL_RCC_MDF1_CLKSOURCE_HCLK: /* MDF1 Clock is SYSCLK */
1558 MDF1_frequency = RCC_GetSystemClockFreq();
1559 break;
1560
1561 case LL_RCC_MDF1_CLKSOURCE_PLL1: /* MDF1 Clock is PLL1 */
1562 if (LL_RCC_PLL1_IsReady() != 0U)
1563 {
1564 if (LL_RCC_PLL1_IsEnabledDomain_SAI() != 0U)
1565 {
1566 MDF1_frequency = RCC_PLL1_GetFreqDomain_SAI();
1567 }
1568 }
1569 break;
1570
1571 case LL_RCC_MDF1_CLKSOURCE_PLL3: /* MDF1 Clock is PLL3 */
1572 if (LL_RCC_PLL3_IsReady() != 0U)
1573 {
1574 if (LL_RCC_PLL3_IsEnabledDomain_48M() != 0U)
1575 {
1576 MDF1_frequency = RCC_PLL3_GetFreqDomain_48M();
1577 }
1578 }
1579 break;
1580
1581 case LL_RCC_MDF1_CLKSOURCE_PIN: /* External input clock used as MDF1 clock source */
1582 MDF1_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
1583 break;
1584
1585 case LL_RCC_MDF1_CLKSOURCE_MSIK: /* MDF1 Clock is MSIK */
1586 MDF1_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1587 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1588 LL_RCC_MSIK_GetRange() :
1589 LL_RCC_MSIK_GetRangeAfterStandby()));
1590 break;
1591
1592 default:
1593 /* unreachable code */
1594 break;
1595 }
1596
1597 return MDF1_frequency;
1598 }
1599
1600 /**
1601 * @brief Return DAC1 clock frequency
1602 * @param DAC1Source This parameter can be one of the following values:
1603 * @arg @ref LL_RCC_DAC1_CLKSOURCE
1604 * @retval DAC1 clock frequency (in Hz)
1605 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that LSI or LSE oscillator is not ready
1606 */
LL_RCC_GetDAC1ClockFreq(uint32_t DAC1Source)1607 uint32_t LL_RCC_GetDAC1ClockFreq(uint32_t DAC1Source)
1608 {
1609 uint32_t DAC1_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1610
1611 /* Check parameter */
1612 assert_param(IS_LL_RCC_DAC1_CLKSOURCE(DAC1Source));
1613
1614 /* DAC1CLK clock frequency */
1615 switch (LL_RCC_GetDAC1ClockSource(DAC1Source))
1616 {
1617 case LL_RCC_DAC1_CLKSOURCE_LSI: /* DAC1 Clock is LSI */
1618 DAC1_frequency = LSI_VALUE;
1619 break;
1620
1621 case LL_RCC_DAC1_CLKSOURCE_LSE: /* DAC1 Clock is LSE */
1622 DAC1_frequency = LSE_VALUE;
1623 break;
1624
1625 default:
1626 /* unreachable code */
1627 break;
1628 }
1629
1630 return DAC1_frequency;
1631 }
1632
1633 /**
1634 * @brief Return OCTOSPI clock frequency
1635 * @param OCTOSPIxSource This parameter can be one of the following values:
1636 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
1637 * @retval OCTOSPI clock frequency (in Hz)
1638 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator MSIK or PLL is not ready
1639 */
LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)1640 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)
1641 {
1642 uint32_t octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1643
1644 /* Check parameter */
1645 assert_param(IS_LL_RCC_OCTOSPI_CLKSOURCE(OCTOSPIxSource));
1646
1647 /* OCTOSPI clock frequency */
1648 switch (LL_RCC_GetOCTOSPIClockSource(OCTOSPIxSource))
1649 {
1650 case LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK: /* OCTOSPI clock is SYSCLK */
1651 octospi_frequency = RCC_GetSystemClockFreq();
1652 break;
1653
1654 case LL_RCC_OCTOSPI_CLKSOURCE_MSIK: /* MSIk clock used as OCTOSPI clock */
1655 if (LL_RCC_MSIK_IsReady() == 1U)
1656 {
1657 octospi_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1658 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1659 LL_RCC_MSIK_GetRange() :
1660 LL_RCC_MSIK_GetRangeAfterStandby()));
1661 }
1662 break;
1663
1664 case LL_RCC_OCTOSPI_CLKSOURCE_PLL1: /* PLL1 clock used as OCTOSPI source */
1665 if (LL_RCC_PLL1_IsReady() == 1U)
1666 {
1667 if (LL_RCC_PLL1_IsEnabledDomain_48M() != 0U)
1668 {
1669 octospi_frequency = RCC_PLL1_GetFreqDomain_48M();
1670 }
1671 }
1672 break;
1673 case LL_RCC_OCTOSPI_CLKSOURCE_PLL2: /* PLL2 clock used as OCTOSPI source */
1674 if (LL_RCC_PLL2_IsReady() == 1U)
1675 {
1676 if (LL_RCC_PLL2_IsEnabledDomain_48M() != 0U)
1677 {
1678 octospi_frequency = RCC_PLL2_GetFreqDomain_48M();
1679 }
1680 }
1681 break;
1682
1683 default:
1684 /* unreachable code */
1685 break;
1686 }
1687
1688 return octospi_frequency;
1689 }
1690
1691 #if defined(SAES)
1692 /**
1693 * @brief Return SAESx clock frequency
1694 * @param SAESxSource This parameter can be one of the following values:
1695 * @arg @ref LL_RCC_SAES_CLKSOURCE
1696 * @retval SAEx clock frequency (in Hz)
1697 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator SHSI is not ready
1698 */
LL_RCC_GetSAESClockFreq(uint32_t SAESxSource)1699 uint32_t LL_RCC_GetSAESClockFreq(uint32_t SAESxSource)
1700 {
1701 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1702
1703 /* Check parameter */
1704 assert_param(IS_LL_RCC_SAES_CLKSOURCE(SAESxSource));
1705
1706 /* SAESCLK clock frequency */
1707 switch (LL_RCC_GetSAESClockSource(SAESxSource))
1708 {
1709
1710 case LL_RCC_SAES_CLKSOURCE_SHSI: /* SHSI clock used as SAES clock source */
1711 if (LL_RCC_SHSI_IsReady() == 1U)
1712 {
1713 rng_frequency = HSI_VALUE;
1714 }
1715 break;
1716
1717 case LL_RCC_SAES_CLKSOURCE_SHSI_DIV2: /* SHSIDIV2 clock used as SAES clock source */
1718 if (LL_RCC_SHSI_IsReady() == 1U)
1719 {
1720 rng_frequency = (HSI_VALUE / 2U);
1721 }
1722 break;
1723
1724 default:
1725 /* unreachable code */
1726 break;
1727 }
1728
1729 return rng_frequency;
1730 }
1731 #endif /* SAES */
1732
1733 /**
1734 * @brief Return FDCAN kernel clock frequency
1735 * @param FDCANxSource This parameter can be one of the following values:
1736 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
1737 * @retval FDCAN kernel clock frequency (in Hz)
1738 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator HSE or PLL is not ready
1739 */
LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)1740 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
1741 {
1742 uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1743
1744 /* Check parameter */
1745 assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource));
1746
1747 /* FDCAN kernel clock frequency */
1748 switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
1749 {
1750 case LL_RCC_FDCAN_CLKSOURCE_HSE: /* HSE clock used as FDCAN kernel clock */
1751 if (LL_RCC_HSE_IsReady() == 1U)
1752 {
1753 fdcan_frequency = HSE_VALUE;
1754 }
1755 break;
1756
1757 case LL_RCC_FDCAN_CLKSOURCE_PLL1: /* PLL2 clock used as FDCAN kernel clock */
1758 if (LL_RCC_PLL1_IsReady() == 1U)
1759 {
1760 if (LL_RCC_PLL1_IsEnabledDomain_48M() != 0U)
1761 {
1762 fdcan_frequency = RCC_PLL1_GetFreqDomain_48M();
1763 }
1764 }
1765 break;
1766
1767 case LL_RCC_FDCAN_CLKSOURCE_PLL2: /* PLL2 clock used as FDCAN kernel clock */
1768 if (LL_RCC_PLL2_IsReady() == 1U)
1769 {
1770 if (LL_RCC_PLL2_IsEnabledDomain_SAI() != 0U)
1771 {
1772 fdcan_frequency = RCC_PLL2_GetFreqDomain_SAI();
1773 }
1774 }
1775 break;
1776
1777 default:
1778 /* unreachable code */
1779 break;
1780 }
1781
1782 return fdcan_frequency;
1783 }
1784 #if defined(DSI)
1785 /**
1786 * @brief Return DSI clock frequency
1787 * @param DSIxSource This parameter can be one of the following values:
1788 * @arg @ref LL_RCC_DSI_CLKSOURCE
1789 * @retval DSI clock frequency (in Hz)
1790 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1791 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1792 */
LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)1793 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1794 {
1795 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1796
1797 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1798 {
1799 case LL_RCC_LTDC_CLKSOURCE_PLL3:
1800 if (LL_RCC_PLL3_IsReady() != 0U)
1801 {
1802 if (LL_RCC_PLL3_IsEnabledDomain_SAI() != 0U)
1803 {
1804 dsi_frequency = RCC_PLL3_GetFreqDomain_SAI();
1805 }
1806 }
1807 break;
1808
1809 case LL_RCC_DSI_CLKSOURCE_PHY:
1810 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1811 break;
1812
1813 default:
1814 /* Nothing to do */
1815 break;
1816 }
1817
1818 return dsi_frequency;
1819 }
1820 #endif /* defined(DSI) */
1821
1822 #if defined(HSPI1)
1823 /**
1824 * @brief Return HSPI clock frequency
1825 * @param HSPIxSource This parameter can be one of the following values:
1826 * @arg @ref LL_RCC_HSPI_CLKSOURCE
1827 * @retval HSPI clock frequency (in Hz)
1828 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1829 */
1830
LL_RCC_GetHSPIClockFreq(uint32_t HSPIxSource)1831 uint32_t LL_RCC_GetHSPIClockFreq(uint32_t HSPIxSource)
1832 {
1833 uint32_t hspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1834
1835 switch (LL_RCC_GetHSPIClockSource(HSPIxSource))
1836 {
1837 case LL_RCC_HSPI_CLKSOURCE_SYSCLK:
1838 hspi_frequency = RCC_GetSystemClockFreq();
1839 break;
1840
1841 case LL_RCC_HSPI_CLKSOURCE_PLL1:
1842 if (LL_RCC_PLL1_IsReady() != 0U)
1843 {
1844 if (LL_RCC_PLL1_IsEnabledDomain_48M() != 0U)
1845 {
1846 hspi_frequency = RCC_PLL1_GetFreqDomain_48M();
1847 }
1848 }
1849 break;
1850
1851 case LL_RCC_HSPI_CLKSOURCE_PLL2:
1852 if (LL_RCC_PLL2_IsReady() != 0U)
1853 {
1854 if (LL_RCC_PLL2_IsEnabledDomain_48M() != 0U)
1855 {
1856 hspi_frequency = RCC_PLL2_GetFreqDomain_48M();
1857 }
1858 }
1859 break;
1860
1861 case LL_RCC_HSPI_CLKSOURCE_PLL3:
1862 if (LL_RCC_PLL3_IsReady() != 0U)
1863 {
1864 if (LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC() != 0U)
1865 {
1866 hspi_frequency = RCC_PLL3_GetFreqDomain_HSPI_LTDC();
1867 }
1868 }
1869 break;
1870
1871 default:
1872 /* Nothing to do */
1873 break;
1874 }
1875
1876 return hspi_frequency;
1877 }
1878 #endif /* defined(HSPI1) */
1879
1880 #if defined(LTDC)
1881 /**
1882 * @brief Return LTDC clock frequency
1883 * @param LTDCxSource This parameter can be one of the following values:
1884 * @arg @ref LL_RCC_LTDC_CLKSOURCE
1885 * @retval HSPI clock frequency (in Hz)
1886 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1887 */
1888
LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)1889 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
1890 {
1891 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1892
1893 switch (LL_RCC_GetHSPIClockSource(LTDCxSource))
1894 {
1895 case LL_RCC_LTDC_CLKSOURCE_PLL2:
1896 if (LL_RCC_PLL2_IsReady() != 0U)
1897 {
1898 if (LL_RCC_PLL2_IsEnabledDomain_ADC() != 0U)
1899 {
1900 ltdc_frequency = RCC_PLL2_GetFreqDomain_ADC();
1901 }
1902 }
1903 break;
1904
1905 case LL_RCC_LTDC_CLKSOURCE_PLL3:
1906 if (LL_RCC_PLL3_IsReady() != 0U)
1907 {
1908 if (LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC() != 0U)
1909 {
1910 ltdc_frequency = RCC_PLL3_GetFreqDomain_HSPI_LTDC();
1911 }
1912 }
1913 break;
1914
1915 default:
1916 /* Nothing to do */
1917 break;
1918 }
1919
1920 return ltdc_frequency;
1921 }
1922 #endif /* defined(LTDC) */
1923 /**
1924 * @}
1925 */
1926
1927 /**
1928 * @}
1929 */
1930
1931 /** @addtogroup RCC_LL_Private_Functions
1932 * @{
1933 */
1934
1935 /**
1936 * @brief Return SYSTEM clock frequency
1937 * @retval SYSTEM clock frequency (in Hz)
1938 */
RCC_GetSystemClockFreq(void)1939 static uint32_t RCC_GetSystemClockFreq(void)
1940 {
1941 uint32_t frequency;
1942
1943 /* Get SYSCLK source -------------------------------------------------------*/
1944 switch (LL_RCC_GetSysClkSource())
1945 {
1946 case LL_RCC_SYS_CLKSOURCE_STATUS_MSIS: /* MSIS used as system clock source */
1947 frequency = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1948 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1949 LL_RCC_MSIS_GetRange() :
1950 LL_RCC_MSIS_GetRangeAfterStandby()));
1951 break;
1952
1953 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1954 frequency = HSI_VALUE;
1955 break;
1956
1957 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1958 frequency = HSE_VALUE;
1959 break;
1960
1961 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1: /* PLL1 used as system clock source */
1962 frequency = RCC_PLL1_GetFreqDomain_SYS();
1963 break;
1964
1965 default:
1966 frequency = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1967 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1968 LL_RCC_MSIS_GetRange() :
1969 LL_RCC_MSIS_GetRangeAfterStandby()));
1970 break;
1971 }
1972
1973 return frequency;
1974 }
1975
1976 /**
1977 * @brief Return HCLK clock frequency
1978 * @param SYSCLK_Frequency SYSCLK clock frequency
1979 * @retval HCLK clock frequency (in Hz)
1980 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)1981 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1982 {
1983 /* HCLK clock frequency */
1984 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1985 }
1986
1987 /**
1988 * @brief Return PCLK1 clock frequency
1989 * @param HCLK_Frequency HCLK clock frequency
1990 * @retval PCLK1 clock frequency (in Hz)
1991 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1992 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1993 {
1994 /* PCLK1 clock frequency */
1995 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1996 }
1997
1998 /**
1999 * @brief Return PCLK2 clock frequency
2000 * @param HCLK_Frequency HCLK clock frequency
2001 * @retval PCLK2 clock frequency (in Hz)
2002 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)2003 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
2004 {
2005 /* PCLK2 clock frequency */
2006 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
2007 }
2008
2009
2010 /**
2011 * @brief Return PCLK3 clock frequency
2012 * @param HCLK_Frequency HCLK clock frequency
2013 * @retval PCLK3 clock frequency (in Hz)
2014 */
RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)2015 static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
2016 {
2017 /* PCLK2 clock frequency */
2018 return __LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler());
2019 }
2020
2021 /**
2022 * @brief Return PLL1 clock frequency used for system domain
2023 * @retval PLL1 clock frequency (in Hz)
2024 */
RCC_PLL1_GetFreqDomain_SYS(void)2025 static uint32_t RCC_PLL1_GetFreqDomain_SYS(void)
2026 {
2027 uint32_t pllinputfreq;
2028 uint32_t pllsource;
2029
2030 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
2031 SYSCLK = PLL_VCO / PLLR
2032 */
2033 pllsource = LL_RCC_PLL1_GetMainSource();
2034
2035 switch (pllsource)
2036 {
2037 case LL_RCC_PLL1SOURCE_MSIS: /* MSIS used as PLL1 clock source */
2038 pllinputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2039 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2040 LL_RCC_MSIS_GetRange() :
2041 LL_RCC_MSIS_GetRangeAfterStandby()));
2042 break;
2043
2044 case LL_RCC_PLL1SOURCE_HSI: /* HSI used as PLL1 clock source */
2045 pllinputfreq = HSI_VALUE;
2046 break;
2047
2048 case LL_RCC_PLL1SOURCE_HSE: /* HSE used as PLL1 clock source */
2049 pllinputfreq = HSE_VALUE;
2050 break;
2051
2052 default:
2053 pllinputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2054 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2055 LL_RCC_MSIS_GetRange() :
2056 LL_RCC_MSIS_GetRangeAfterStandby()));
2057 break;
2058 }
2059 return __LL_RCC_CALC_PLL1CLK_FREQ(pllinputfreq, LL_RCC_PLL1_GetDivider(),
2060 LL_RCC_PLL1_GetN(), LL_RCC_PLL1_GetR());
2061 }
2062 /**
2063 * @brief Return PLL1 clock frequency used for SAI domain
2064 * @retval PLL1 clock frequency (in Hz)
2065 */
RCC_PLL1_GetFreqDomain_SAI(void)2066 static uint32_t RCC_PLL1_GetFreqDomain_SAI(void)
2067 {
2068 uint32_t pll1inputfreq;
2069 uint32_t pll1outputfreq;
2070 uint32_t pll1source;
2071 uint32_t pll1n;
2072 uint32_t pll1pdiv;
2073
2074 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN
2075 SAI Domain clock = PLL_VCO / PLL1P
2076 */
2077 pll1source = LL_RCC_PLL1_GetMainSource();
2078
2079 switch (pll1source)
2080 {
2081 case LL_RCC_PLL1SOURCE_MSIS: /* MSI used as PLL1 clock source */
2082 pll1inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2083 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2084 LL_RCC_MSIS_GetRange() :
2085 LL_RCC_MSIS_GetRangeAfterStandby()));
2086 break;
2087
2088 case LL_RCC_PLL1SOURCE_HSI: /* HSI used as PLL1 clock source */
2089 pll1inputfreq = HSI_VALUE;
2090 break;
2091
2092 case LL_RCC_PLL1SOURCE_HSE: /* HSE used as PLL1 clock source */
2093 pll1inputfreq = HSE_VALUE;
2094 break;
2095
2096 default:
2097 pll1inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2098 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2099 LL_RCC_MSIS_GetRange() :
2100 LL_RCC_MSIS_GetRangeAfterStandby()));
2101 break;
2102 }
2103
2104 pll1n = LL_RCC_PLL1_GetN();
2105 pll1pdiv = LL_RCC_PLL1_GetP();
2106 if ((pll1n >= 8U) && (pll1pdiv >= 2U))
2107 {
2108 pll1outputfreq = __LL_RCC_CALC_PLL1CLK_SAI_FREQ(pll1inputfreq, LL_RCC_PLL1_GetDivider(),
2109 pll1n, pll1pdiv);
2110 }
2111 else
2112 {
2113 pll1outputfreq = 0; /* Invalid PLL1N or PLL1PDIV value */
2114 }
2115 return pll1outputfreq;
2116 }
2117
2118 /**
2119 * @brief Return PLL clock frequency used for 48 MHz domain
2120 * @retval PLL clock frequency (in Hz)
2121 */
RCC_PLL1_GetFreqDomain_48M(void)2122 static uint32_t RCC_PLL1_GetFreqDomain_48M(void)
2123 {
2124 uint32_t pll1inputfreq;
2125 uint32_t pll1source;
2126
2127 /* PLL1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLL1M) * PLL1N
2128 48M Domain clock = PLL1_VCO / PLL1Q
2129 */
2130 pll1source = LL_RCC_PLL1_GetMainSource();
2131
2132 switch (pll1source)
2133 {
2134 case LL_RCC_PLL1SOURCE_MSIS: /* MSI used as PLL1 clock source */
2135 pll1inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2136 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2137 LL_RCC_MSIS_GetRange() :
2138 LL_RCC_MSIS_GetRangeAfterStandby()));
2139 break;
2140
2141 case LL_RCC_PLL1SOURCE_HSI: /* HSI used as PLL1 clock source */
2142 pll1inputfreq = HSI_VALUE;
2143 break;
2144
2145 case LL_RCC_PLL1SOURCE_HSE: /* HSE used as PLL1 clock source */
2146 pll1inputfreq = HSE_VALUE;
2147 break;
2148
2149 default:
2150 pll1inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2151 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2152 LL_RCC_MSIS_GetRange() :
2153 LL_RCC_MSIS_GetRangeAfterStandby()));
2154 break;
2155 }
2156 return __LL_RCC_CALC_PLL1CLK_48M_FREQ(pll1inputfreq, LL_RCC_PLL1_GetDivider(),
2157 LL_RCC_PLL1_GetN(), LL_RCC_PLL1_GetQ());
2158 }
2159
2160 /**
2161 * @brief Return PLL2 clock frequency used for SAI domain
2162 * @retval PLL2 clock frequency (in Hz)
2163 */
RCC_PLL2_GetFreqDomain_SAI(void)2164 static uint32_t RCC_PLL2_GetFreqDomain_SAI(void)
2165 {
2166 uint32_t pll2inputfreq;
2167 uint32_t pll2outputfreq;
2168 uint32_t pll2source;
2169 uint32_t pll2n;
2170 uint32_t pll2pdiv;
2171
2172 /* PLL2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLL2M) * PLL2N */
2173 /* SAI Domain clock = PLL2_VCO / PLL2P */
2174 pll2source = LL_RCC_PLL2_GetSource();
2175
2176 switch (pll2source)
2177 {
2178 case LL_RCC_PLL2SOURCE_MSIS: /* MSI used as PLLSAI1 clock source */
2179 pll2inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2180 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2181 LL_RCC_MSIS_GetRange() :
2182 LL_RCC_MSIS_GetRangeAfterStandby()));
2183 break;
2184
2185 case LL_RCC_PLL2SOURCE_HSI: /* HSI used as PLL2 clock source */
2186 pll2inputfreq = HSI_VALUE;
2187 break;
2188
2189 case LL_RCC_PLL2SOURCE_HSE: /* HSE used as PLL2 clock source */
2190 pll2inputfreq = HSE_VALUE;
2191 break;
2192
2193 default:
2194 pll2inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2195 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2196 LL_RCC_MSIS_GetRange() :
2197 LL_RCC_MSIS_GetRangeAfterStandby()));
2198 break;
2199 }
2200
2201 pll2n = LL_RCC_PLL2_GetN();
2202 pll2pdiv = LL_RCC_PLL2_GetP();
2203 if ((pll2n >= 8U) && (pll2pdiv >= 2U))
2204 {
2205 pll2outputfreq = __LL_RCC_CALC_PLL2CLK_SAI_FREQ(pll2inputfreq, LL_RCC_PLL2_GetDivider(),
2206 pll2n, pll2pdiv);
2207 }
2208 else
2209 {
2210 pll2outputfreq = 0; /* Invalid PLL2N or PLL2PDIV value */
2211 }
2212 return pll2outputfreq;
2213 }
2214
2215 /**
2216 * @brief Return PLL2 clock frequency used for 48Mhz domain
2217 * @retval PLL2 clock frequency (in Hz)
2218 */
RCC_PLL2_GetFreqDomain_48M(void)2219 static uint32_t RCC_PLL2_GetFreqDomain_48M(void)
2220 {
2221 uint32_t pll2inputfreq;
2222 uint32_t pll2source;
2223
2224 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLL2M) * PLL2N */
2225 /* 48M Domain clock = PLL2_VCO / PLL2Q */
2226 pll2source = LL_RCC_PLL2_GetSource();
2227
2228 switch (pll2source)
2229 {
2230 case LL_RCC_PLL2SOURCE_MSIS: /* MSI used as PLL2 clock source */
2231 pll2inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2232 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2233 LL_RCC_MSIS_GetRange() :
2234 LL_RCC_MSIS_GetRangeAfterStandby()));
2235 break;
2236
2237 case LL_RCC_PLL2SOURCE_HSI: /* HSI used as PLL2 clock source */
2238 pll2inputfreq = HSI_VALUE;
2239 break;
2240
2241 case LL_RCC_PLL2SOURCE_HSE: /* HSE used as PLL2 clock source */
2242 pll2inputfreq = HSE_VALUE;
2243 break;
2244
2245 default:
2246 pll2inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2247 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2248 LL_RCC_MSIS_GetRange() :
2249 LL_RCC_MSIS_GetRangeAfterStandby()));
2250 break;
2251 }
2252 return __LL_RCC_CALC_PLL2CLK_48M_FREQ(pll2inputfreq, LL_RCC_PLL2_GetDivider(),
2253 LL_RCC_PLL2_GetN(), LL_RCC_PLL2_GetQ());
2254 }
2255
2256 /**
2257 * @brief Return PLL2 clock frequency used for ADC domain
2258 * @retval PLL2 clock frequency (in Hz)
2259 */
RCC_PLL2_GetFreqDomain_ADC(void)2260 static uint32_t RCC_PLL2_GetFreqDomain_ADC(void)
2261 {
2262 uint32_t pll2inputfreq;
2263 uint32_t pll2source;
2264
2265 /* PLL2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLL2M) * PLL2N */
2266 /* 48M Domain clock = PLL2_VCO / PLL2R */
2267 pll2source = LL_RCC_PLL2_GetSource();
2268
2269 switch (pll2source)
2270 {
2271 case LL_RCC_PLL2SOURCE_MSIS: /* MSI used as PLL2 clock source */
2272 pll2inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2273 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2274 LL_RCC_MSIS_GetRange() :
2275 LL_RCC_MSIS_GetRangeAfterStandby()));
2276 break;
2277
2278 case LL_RCC_PLL2SOURCE_HSI: /* HSI used as PLL2 clock source */
2279 pll2inputfreq = HSI_VALUE;
2280 break;
2281
2282 case LL_RCC_PLL2SOURCE_HSE: /* HSE used as PLL2 clock source */
2283 pll2inputfreq = HSE_VALUE;
2284 break;
2285
2286 default:
2287 pll2inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2288 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2289 LL_RCC_MSIS_GetRange() :
2290 LL_RCC_MSIS_GetRangeAfterStandby()));
2291 break;
2292 }
2293 return __LL_RCC_CALC_PLL2CLK_ADC_FREQ(pll2inputfreq, LL_RCC_PLL2_GetDivider(),
2294 LL_RCC_PLL2_GetN(), LL_RCC_PLL2_GetR());
2295 }
2296
2297 /**
2298 * @brief Return PLL3 clock frequency used for SAI domain
2299 * @retval PLL3 clock frequency (in Hz)
2300 */
RCC_PLL3_GetFreqDomain_SAI(void)2301 static uint32_t RCC_PLL3_GetFreqDomain_SAI(void)
2302 {
2303 uint32_t pll3inputfreq;
2304 uint32_t pll3outputfreq;
2305 uint32_t pll3source;
2306 uint32_t pll3n;
2307 uint32_t pll3pdiv;
2308
2309 /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLL3M) * PLL3N */
2310 /* SAI Domain clock = PLL3_VCO / PLL3P */
2311 pll3source = LL_RCC_PLL3_GetSource();
2312
2313 switch (pll3source)
2314 {
2315 case LL_RCC_PLL3SOURCE_MSIS: /* MSI used as PLL3 clock source */
2316 pll3inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2317 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2318 LL_RCC_MSIS_GetRange() :
2319 LL_RCC_MSIS_GetRangeAfterStandby()));
2320 break;
2321
2322 case LL_RCC_PLL3SOURCE_HSI: /* HSI used as PLL3 clock source */
2323 pll3inputfreq = HSI_VALUE;
2324 break;
2325
2326 case LL_RCC_PLL3SOURCE_HSE: /* HSE used as PLL3 clock source */
2327 pll3inputfreq = HSE_VALUE;
2328 break;
2329
2330 default:
2331 pll3inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2332 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2333 LL_RCC_MSIS_GetRange() :
2334 LL_RCC_MSIS_GetRangeAfterStandby()));
2335 break;
2336 }
2337
2338 pll3n = LL_RCC_PLL3_GetN();
2339 pll3pdiv = LL_RCC_PLL3_GetP();
2340 if ((pll3n >= 8U) && (pll3pdiv >= 2U))
2341 {
2342 pll3outputfreq = __LL_RCC_CALC_PLL3CLK_SAI_FREQ(pll3inputfreq, LL_RCC_PLL3_GetDivider(),
2343 pll3n, pll3pdiv);
2344 }
2345 else
2346 {
2347 pll3outputfreq = 0; /* Invalid PLL3N or PLL3PDIV value */
2348 }
2349 return pll3outputfreq;
2350 }
2351
2352 /**
2353 * @}
2354 */
2355
2356 /**
2357 * @brief Return PLL3clock frequency used for 48Mhz domain
2358 * @retval PLL3 clock frequency (in Hz)
2359 */
RCC_PLL3_GetFreqDomain_48M(void)2360 static uint32_t RCC_PLL3_GetFreqDomain_48M(void)
2361 {
2362 uint32_t PLL3inputfreq;
2363 uint32_t PLL3source;
2364
2365 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLL3M) * PLL3N */
2366 /* 48M Domain clock = PLL3_VCO / PLL3Q */
2367 PLL3source = LL_RCC_PLL3_GetSource();
2368
2369 switch (PLL3source)
2370 {
2371 case LL_RCC_PLL3SOURCE_MSIS: /* MSI used as PLL3 clock source */
2372 PLL3inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2373 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2374 LL_RCC_MSIS_GetRange() :
2375 LL_RCC_MSIS_GetRangeAfterStandby()));
2376 break;
2377
2378 case LL_RCC_PLL3SOURCE_HSI: /* HSI used as PLL3 clock source */
2379 PLL3inputfreq = HSI_VALUE;
2380 break;
2381
2382 case LL_RCC_PLL3SOURCE_HSE: /* HSE used as PLL3 clock source */
2383 PLL3inputfreq = HSE_VALUE;
2384 break;
2385
2386 default:
2387 PLL3inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2388 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2389 LL_RCC_MSIS_GetRange() :
2390 LL_RCC_MSIS_GetRangeAfterStandby()));
2391 break;
2392 }
2393 return __LL_RCC_CALC_PLL3CLK_48M_FREQ(PLL3inputfreq, LL_RCC_PLL3_GetDivider(),
2394 LL_RCC_PLL3_GetN(), LL_RCC_PLL3_GetQ());
2395 }
2396 #if defined(HSPI1) || defined(LTDC)
2397 /**
2398 * @brief Return PLL3 clock frequency used for HSPI_LTDC domain
2399 * @retval PLL3 clock frequency (in Hz)
2400 */
RCC_PLL3_GetFreqDomain_HSPI_LTDC(void)2401 static uint32_t RCC_PLL3_GetFreqDomain_HSPI_LTDC(void)
2402 {
2403 uint32_t pll3inputfreq;
2404 uint32_t pll3source;
2405
2406 /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLL2M) * PLL3N */
2407
2408 pll3source = LL_RCC_PLL3_GetSource();
2409
2410 switch (pll3source)
2411 {
2412 case LL_RCC_PLL3SOURCE_MSIS: /* MSI used as PLL2 clock source */
2413 pll3inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2414 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2415 LL_RCC_MSIS_GetRange() :
2416 LL_RCC_MSIS_GetRangeAfterStandby()));
2417 break;
2418
2419 case LL_RCC_PLL3SOURCE_HSI: /* HSI used as PLL2 clock source */
2420 pll3inputfreq = HSI_VALUE;
2421 break;
2422
2423 case LL_RCC_PLL3SOURCE_HSE: /* HSE used as PLL2 clock source */
2424 pll3inputfreq = HSE_VALUE;
2425 break;
2426
2427 default:
2428 pll3inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2429 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
2430 LL_RCC_MSIS_GetRange() :
2431 LL_RCC_MSIS_GetRangeAfterStandby()));
2432 break;
2433 }
2434 return __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ(pll3inputfreq, LL_RCC_PLL3_GetDivider(),
2435 LL_RCC_PLL3_GetN(), LL_RCC_PLL3_GetR());
2436 }
2437
2438 #endif /* HSPI1 || LTDC */
2439 /**
2440 * @}
2441 */
2442
2443 #endif /* defined(RCC) */
2444
2445 /**
2446 * @}
2447 */
2448
2449 #endif /* USE_FULL_LL_DRIVER */
2450
