1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization/De-Initialization Functions.
9 * + Peripheral Control Functions.
10 * + PWR Attributes Functions.
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2021 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### PWR peripheral overview #####
26 ==============================================================================
27 [..]
28 (#) The Power control (PWR) provides an overview of the supply architecture
29 for the different power domains and of the supply configuration
30 controller.
31
32 (#) Domain architecture overview for the U5 devices:
33 (+) U5 devices have 2 power domains (CD and SRD).
34 The core domain (CD) contains a CPU (Cortex-M33), a Flash memory and
35 some peripherals dedicated for general purpose. The SRD domain
36 contains the system control and low-power peripherals.
37
38 (#) Every entity has low power mode as described below :
39 (#) The CPU low power modes are :
40 (+) CPU CRun.
41 (+) CPU CSleep.
42 (+) CPU CStop.
43 (#) The system low power modes are :
44 (+) Run.
45 (+) Stop 0.
46 (+) Stop 1.
47 (+) Stop 2.
48 (+) Stop 3.
49 (+) Standby.
50 (+) Shutdown.
51
52 ==============================================================================
53 ##### How to use this driver #####
54 ==============================================================================
55 [..]
56 (#) After startup, power management peripheral is not active by default. Use
57 __HAL_RCC_PWR_CLK_ENABLE() macro to enable power interface.
58
59 (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
60 to enable/disable access to the backup domain (RCC Backup domain control
61 register RCC_BDCR, RTC registers, TAMP registers, backup registers and
62 backup SRAM).
63
64 (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
65 mode and voltage threshold) in order to set up the Programmed Voltage
66 Detector, then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD()
67 functions to start and stop the PVD detection.
68 (+) PVD level can be one of the following values :
69 (++) 2V0
70 (++) 2V2
71 (++) 2V4
72 (++) 2V5
73 (++) 2V6
74 (++) 2V8
75 (++) 2V9
76 (++) External input analog voltage PVD_IN (compared internally to
77 VREFINT)
78
79 (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
80 with the right parameter to configure the wake up pin polarity (Low or
81 High), the wake up pin selection and to enable and disable it.
82
83 (#) Call HAL_PWR_EnterSLEEPMode() function to enter the CPU in Sleep mode.
84 Wake-up from Sleep mode could be following to an event or an
85 interrupt according to low power mode intrinsic request called (__WFI()
86 or __WFE()).
87
88 (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0
89 mode. Wake-up from Stop 0 mode could be following to an event or an
90 interrupt according to low power mode intrinsic request called (__WFI()
91 or __WFE()). (Regulator state on U5 devices is managed internally but
92 regulator parameter is kept for product compatibility).
93
94 (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
95 Standby mode. Wake-up from Standby mode can be following only by an
96 interrupt.
97
98 (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
99 enable and disable the Cortex-M33 re-entry in Sleep mode after an
100 interruption handling is over.
101
102 (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
103 to configure the Cortex-M33 to wake-up after any pending event / interrupt
104 even if it's disabled or has insufficient priority to cause exception
105 entry.
106
107 (#) Call HAL_PWR_PVD_IRQHandler() under PVD_AVD_IRQHandler() function to
108 handle the PWR PVD interrupt request.
109
110 (#) Call HAL_PWR_ConfigAttributes() function to configure PWR item secure and
111 privilege attributes and call HAL_PWR_GetConfigAttributes() function to
112 get the attribute configuration for the selected item.
113
114 *** PWR HAL driver macros list ***
115 =============================================
116 [..]
117 Below the list of most used macros in PWR HAL driver.
118
119 (+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags.
120 (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags.
121
122 @endverbatim
123 ******************************************************************************
124 */
125
126 /* Includes ------------------------------------------------------------------*/
127 #include "stm32u5xx_hal.h"
128
129 /** @addtogroup STM32U5xx_HAL_Driver
130 * @{
131 */
132
133 /** @defgroup PWR PWR
134 * @brief PWR HAL module driver
135 * @{
136 */
137
138 #if defined (HAL_PWR_MODULE_ENABLED)
139
140 /* Private typedef -----------------------------------------------------------*/
141 /* Private define ------------------------------------------------------------*/
142
143 /** @defgroup PWR_Private_Defines PWR Private Defines
144 * @{
145 */
146
147 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
148 * @{
149 */
150 #define PVD_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVD trigger */
151 #define PVD_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVD trigger */
152 #define PVD_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVD threshold crossing */
153 #define PVD_MODE_EVT (0x08U) /*!< Mask for event yielded by PVD threshold crossing */
154 /**
155 * @}
156 */
157
158 /**
159 * @}
160 */
161
162 /* Private macro -------------------------------------------------------------*/
163 /* Private variables ---------------------------------------------------------*/
164 /* Private function prototypes -----------------------------------------------*/
165 /* Exported functions --------------------------------------------------------*/
166
167 /** @defgroup PWR_Exported_Functions PWR Exported Functions
168 * @{
169 */
170
171 /** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
172 * @brief Initialization and de-Initialization functions
173 *
174 @verbatim
175 ===============================================================================
176 ##### Initialization and De-Initialization Functions #####
177 ===============================================================================
178 [..]
179 This section provides functions allowing to deinitialize power peripheral
180 and to manage backup domain access.
181
182 [..]
183 After system reset, the backup domain (RCC Backup domain control register
184 RCC_BDCR, RTC registers, TAMP registers, backup registers and backup SRAM)
185 is protected against possible unwanted write accesses.
186 The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
187 domain.
188 The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
189 domain.
190
191 @endverbatim
192 * @{
193 */
194
195 /**
196 * @brief Deinitialize the HAL PWR peripheral registers to their default reset
197 * values.
198 * @note This functionality is not available in this product.
199 * The prototype is kept just to maintain compatibility with other
200 * products.
201 * @retval None.
202 */
HAL_PWR_DeInit(void)203 void HAL_PWR_DeInit(void)
204 {
205 }
206
207 /**
208 * @brief Enable access to the backup domain (RCC Backup domain control
209 * register RCC_BDCR, RTC registers, TAMP registers, backup registers
210 * and backup SRAM).
211 * @note After a system reset, the backup domain is protected against
212 * possible unwanted write accesses.
213 * @retval None.
214 */
HAL_PWR_EnableBkUpAccess(void)215 void HAL_PWR_EnableBkUpAccess(void)
216 {
217 SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
218 }
219
220 /**
221 * @brief Disable access to the backup domain (RCC Backup domain control
222 * register RCC_BDCR, RTC registers, TAMP registers, backup registers
223 * and backup SRAM).
224 * @retval None.
225 */
HAL_PWR_DisableBkUpAccess(void)226 void HAL_PWR_DisableBkUpAccess(void)
227 {
228 CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP);
229 }
230 /**
231 * @}
232 */
233
234
235 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
236 * @brief Low power modes configuration functions
237 *
238 @verbatim
239 ===============================================================================
240 ##### Peripheral Control functions #####
241 ===============================================================================
242 [..]
243 This section provides functions allowing to control power peripheral.
244
245 *** PVD configuration ***
246 =========================
247 [..]
248 (+) The PVD can be used to monitor the VDD power supply by comparing it
249 to a threshold selected by the PVDLS[2:0] bits in the PWR supply
250 voltage monitoring control register (PWR_SVMCR) and can be enabled by
251 setting the PVDE bit.
252
253 (+) A PVDO flag is available in the PWR supply voltage monitoring control
254 register (PWR_SVMCR) to indicate if VDD is higher or lower than the
255 PVD threshold. This event is internally connected to the EXTI line 16
256 and can generate an interrupt if enabled through the EXTI registers.
257 It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
258
259 (+) The PVD can remain active in Stop 0, Stop 1, Stop 2 modes, and the PVM
260 interrupt can wake up from the Stop mode. The PVD is not functional in
261 Stop 3 mode.
262
263 (+) During Stop 1, Stop 2 and Stop 3 modes, it is possible to set the PVD
264 in ultra-low-power mode to further reduce the current consumption by
265 setting the ULPMEN bit in PWR_CR1 register.
266
267 *** Wake-up pin configuration ***
268 =================================
269 [..]
270 (+) Wake-up pin is used to wake up the system from Stop 3, Standby and
271 Shutdown mode.
272 The pin selection is configurable through the WUCR3 register to map
273 internal signal to wake up pin line.
274 The pin polarity is configurable through the WUCR2 register to be
275 active on rising or falling edges.
276
277 (+) There are up to 24 wake-up signals that can be mapped to up to 8
278 wake-up lines in the STM32U5 family.
279
280 *** Low Power modes configuration ***
281 =====================================
282 [..]
283 This section presents 3 principles low-power modes :
284 (+) Sleep mode : Cortex-M33 is stopped and all PWR domains are remaining
285 active (powered and clocked).
286
287 (+) Stop 0 mode : Cortex-M33 is stopped, clocks are stopped and the
288 regulator is running.
289
290 (+) Standby mode : All PWR domains enter DSTANDBY mode and the VCORE
291 supply regulator is powered off.
292
293 *** Sleep mode ***
294 ==================
295 [..]
296 (+) Entry :
297 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode()
298 function.
299
300 (++) PWR_SLEEPENTRY_WFI: enter Sleep mode with WFI instruction.
301 (++) PWR_SLEEPENTRY_WFE: enter Sleep mode with WFE instruction.
302
303 -@@- The Regulator parameter is not used for the STM32U5 family and is
304 kept as parameter just to maintain compatibility with other families.
305
306 (+) Exit :
307 According to Sleep entry, any event when entry is __WFE() intrinsic
308 and any interrupt when entry is __WFI() intrinsic can wake up the
309 device from Sleep mode.
310
311 *** Stop 0 mode ***
312 ===================
313 [..]
314 The Stop 0 mode is based on the Cortex-M33 Deepsleep mode combined with
315 the peripheral clock gating. The voltage regulator is configured in main
316 regulator mode. In Stop 0 mode, all clocks in the VCORE domain are stopped.
317 The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
318 Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or
319 MSIK for transferring data. All SRAMs and register contents are preserved,
320 but the SRAMs can be totally or partially switched off to further reduced
321 consumption.
322 The BOR is always available in Stop 0 mode.
323
324 (+) Entry:
325 The Stop mode is entered using the HAL_PWR_EnterSTOPMode() function
326 with :
327
328 (++) StopEntry:
329 (+++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction.
330 (+++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction.
331
332 -@@- The Regulator parameter is not used for the STM32U5 family and is
333 kept as parameter just to maintain compatibility with other families.
334
335 (+) Exit:
336 Any EXTI line configured in interrupt mode (the corresponding EXTI
337 interrupt vector must be enabled in the NVIC). The interrupt source
338 can be external interrupts or peripherals with wakeup capability.
339 Any peripheral interrupt occurring when the AHB/APB clocks are present
340 due to an autonomous peripheral clock request (the peripheral vector
341 must be enabled in the NVIC).
342
343 *** Standby mode ***
344 ====================
345 [..]
346 The Standby mode is used to achieve the lowest power consumption with BOR.
347 The internal regulator is switched off so that the VCORE domain is powered
348 off.
349 The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and the HSE crystal
350 oscillators are also switched off.
351 The RTC can remain active (Standby mode with RTC, Standby mode without
352 RTC).
353 The Brownout reset (BOR) always remains active in Standby mode.
354 The state of each I/O during Standby mode can be selected by software:
355 I/O with internal pull-up, internal pull-down or floating.
356 After entering Standby mode, SRAMs and register contents are lost except
357 for registers and backup SRAM in the Backup domain and Standby circuitry.
358 Optionally, the full SRAM2 or 8 Kbytes or 56 Kbytes can be retained in
359 Standby mode, supplied by the low-power regulator (Standby with RAM2
360 retention mode).
361 The BORL (Brownout reset detector low) can be configured in ultra low
362 power mode to further reduce power consumption during Standby mode.
363 The device exits Standby mode upon an external reset (NRST pin), an IWDG
364 reset, WKUP pin event (configurable rising or falling edge), an RTC event
365 occurs (alarm, periodic wakeup, timestamp), or a tamper detection.
366 The system clock after wakeup is MSIS up to 4 MHz.
367
368 (++) Entry:
369 The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode()
370 function.
371
372 (++) Exit:
373 WKUPx pin edge, RTC event, external Reset in NRST pin, IWDG Reset,
374 BOR reset.
375
376 @endverbatim
377 * @{
378 */
379
380 /**
381 * @brief Configure the voltage threshold detected by the Programmed Voltage
382 * Detector (PVD).
383 * @param pConfigPVD : Pointer to a PWR_PVDTypeDef structure that contains the
384 * PVD configuration information (PVDLevel and EventMode).
385 * @retval HAL Status.
386 */
HAL_PWR_ConfigPVD(PWR_PVDTypeDef * pConfigPVD)387 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *pConfigPVD)
388 {
389 /* Check the PVD parameter */
390 if (pConfigPVD == NULL)
391 {
392 return HAL_ERROR;
393 }
394
395 /* Check the parameters */
396 assert_param(IS_PWR_PVD_LEVEL(pConfigPVD->PVDLevel));
397 assert_param(IS_PWR_PVD_MODE(pConfigPVD->Mode));
398
399 /* Set PVDLS[2:0] bits according to PVDLevel value */
400 MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, pConfigPVD->PVDLevel);
401
402 /* Disable PVD Event/Interrupt */
403 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
404 __HAL_PWR_PVD_EXTI_DISABLE_IT();
405 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
406 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
407
408 /* Configure the PVD in interrupt mode */
409 if ((pConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
410 {
411 __HAL_PWR_PVD_EXTI_ENABLE_IT();
412 }
413
414 /* Configure the PVD in event mode */
415 if ((pConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
416 {
417 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
418 }
419
420 /* Configure the PVD in rising edge */
421 if ((pConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
422 {
423 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
424 }
425
426 /* Configure the PVD in falling edge */
427 if ((pConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
428 {
429 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
430 }
431
432 return HAL_OK;
433 }
434
435 /**
436 * @brief Enable the programmable voltage detector (PVD).
437 * @retval None.
438 */
HAL_PWR_EnablePVD(void)439 void HAL_PWR_EnablePVD(void)
440 {
441 SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
442 }
443
444 /**
445 * @brief Disable the programmable voltage detector (PVD).
446 * @retval None.
447 */
HAL_PWR_DisablePVD(void)448 void HAL_PWR_DisablePVD(void)
449 {
450 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
451 }
452
453 /**
454 * @brief Enable the wake up line functionality.
455 * @note Wake up lines are used to wake up the system from Stop 3, Standby and
456 * Shutdown modes.
457 * @param WakeUpPin : Specifies which wake up line to enable. This parameter
458 * can be one of PWR_WakeUp_Pins_High_Polarity define
459 * group where every param select the wake up line, the
460 * wake up source with high polarity detection and the wake
461 * up selected I/O or can be one of
462 * PWR_WakeUp_Pins_Low_Polarity define group where every
463 * param select the wake up line, the wake up source with
464 * low polarity and the wake up selected I/O or can be one
465 * of PWR_WakeUp_Pins define group where every param select
466 * the wake up line, the wake up source with
467 * high polarity and the first wake up I/O.
468 * @retval None.
469 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)470 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
471 {
472 /* Check the parameter */
473 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin));
474
475 /* Specifies the wake up line polarity for the event detection (rising or falling edge) */
476 MODIFY_REG(PWR->WUCR2, (PWR_EWUP_MASK & WakeUpPin), (WakeUpPin >> PWR_WUP_POLARITY_SHIFT));
477
478 /* Specifies the wake up line I/O selection */
479 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(PWR_EWUP_MASK & WakeUpPin) * 2U)),
480 (WakeUpPin >> PWR_WUP_SELECT_SIGNAL_SHIFT));
481
482 /* Enable wake-up line */
483 SET_BIT(PWR->WUCR1, (PWR_EWUP_MASK & WakeUpPin));
484 }
485
486 /**
487 * @brief Disable the wake up line functionality.
488 * @param WakeUpPin : Specifies the wake up line to disable.
489 * This parameter can be a combination of all the following
490 * values :
491 * @arg @ref PWR_WAKEUP_PIN1
492 * @arg @ref PWR_WAKEUP_PIN2
493 * @arg @ref PWR_WAKEUP_PIN3
494 * @arg @ref PWR_WAKEUP_PIN4
495 * @arg @ref PWR_WAKEUP_PIN6
496 * @arg @ref PWR_WAKEUP_PIN5
497 * @arg @ref PWR_WAKEUP_PIN7
498 * @arg @ref PWR_WAKEUP_PIN8
499 * @retval None
500 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)501 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
502 {
503 /* Check the parameters */
504 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin));
505
506 /* Disable wake-up pin */
507 CLEAR_BIT(PWR->WUCR1, (PWR_EWUP_MASK & WakeUpPin));
508 }
509
510 /**
511 * @brief Enter the CPU in Sleep mode.
512 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
513 * @note CPU clock is off and all peripherals including Cortex-M33 core such
514 * as NVIC and SysTick can run and wake up the CPU when an interrupt
515 * or an event occurs.
516 * @param Regulator : Specifies the regulator state in Sleep mode.
517 * This parameter can be one of the following values :
518 * @arg @ref PWR_MAINREGULATOR_ON
519 * @arg @ref PWR_LOWPOWERREGULATOR_ON
520 * @note This parameter is not available in this product.
521 * The parameter is kept just to maintain compatibility with other
522 * products.
523 * @param SleepEntry : Specifies if Sleep mode is entered with WFI or WFE
524 * instruction.
525 * This parameter can be one of the following values :
526 * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep mode with Wait
527 * For Interrupt request.
528 * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep mode with Wait
529 * For Event request.
530 * @note When WFI entry is used, ticks interrupt must be disabled to avoid
531 * unexpected CPU wake up.
532 * @retval None.
533 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SleepEntry)534 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry)
535 {
536 UNUSED(Regulator);
537
538 /* Check the parameter */
539 assert_param(IS_PWR_SLEEP_ENTRY(SleepEntry));
540
541 /* Clear SLEEPDEEP bit of Cortex System Control Register */
542 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
543
544 /* Select Sleep mode entry */
545 if (SleepEntry == PWR_SLEEPENTRY_WFI)
546 {
547 /* Wait For Interrupt Request */
548 __WFI();
549 }
550 else
551 {
552 /* Wait For Event Request */
553 __SEV();
554 __WFE();
555 __WFE();
556 }
557 }
558
559 /**
560 * @brief Enter the whole system to Stop 0 mode.
561 * @note In Stop 0 mode, the regulator remains in main regulator mode,
562 * allowing a very fast wakeup time but with much higher consumption
563 * comparing to other Stop modes.
564 * @note Stop 0 offers the largest number of active peripherals and wakeup
565 * sources, a smaller wakeup time but a higher consumption.
566 * Stop mode achieves the lowest power consumption while retaining
567 * the content of SRAM and registers. All clocks in the VCORE domain
568 * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and
569 * the HSE crystal oscillators are disabled. The LSE or LSI is still
570 * running.
571 * @note The system clock when exiting from Stop mode can be either MSIS up
572 * to 24 MHz or HSI16, depending on software configuration.
573 * @param Regulator : Specifies the regulator state in Stop mode.
574 * This parameter can be one of the following values :
575 * @arg @ref PWR_MAINREGULATOR_ON
576 * @arg @ref PWR_LOWPOWERREGULATOR_ON
577 * @note This parameter is not available in this product.
578 * The parameter is kept just to maintain compatibility with other
579 * products.
580 * @param StopEntry : Specifies if Stop mode is entered with WFI or WFE
581 * instruction.
582 * This parameter can be one of the following values :
583 * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
584 * For Interrupt request.
585 * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
586 * For Event request.
587 * @retval None.
588 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t StopEntry)589 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t StopEntry)
590 {
591 UNUSED(Regulator);
592
593 /* Check the parameter */
594 assert_param(IS_PWR_STOP_ENTRY(StopEntry));
595
596 /* Select Stop 0 mode */
597 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, 0U);
598
599 /* Set SLEEPDEEP bit of Cortex System Control Register */
600 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
601
602 /* Select Stop mode entry */
603 if (StopEntry == PWR_STOPENTRY_WFI)
604 {
605 /* Wait For Interrupt Request */
606 __WFI();
607 }
608 else
609 {
610 /* Wait For Event Request */
611 __SEV();
612 __WFE();
613 __WFE();
614 }
615
616 /* Reset SLEEPDEEP bit of Cortex System Control Register */
617 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
618 }
619
620 /**
621 * @brief Enter the whole system to Standby mode.
622 * @note The Standby mode is used to achieve the lowest power consumption
623 * with BOR. The internal regulator is switched off so that the VCORE
624 * domain is powered off. The PLL, the MSI (MSIS and MSIK) RC, the
625 * HSI16 RC and the HSE crystal oscillators are also switched off.
626 * @note After entering Standby mode, SRAMs and register contents are lost
627 * except for registers and backup SRAM in the Backup domain and
628 * Standby circuitry. Optionally, the full SRAM2 or 8 Kbytes or 56
629 * Kbytes can be retained in Standby mode, supplied by the low-power
630 * regulator (Standby with RAM2 retention mode) through
631 * HAL_PWREx_EnableSRAM2ContentStandbyRetention().
632 * @note The state of each I/O during Standby mode can be selected by
633 * software : I/O with internal pull-up through
634 * HAL_PWREx_EnableGPIOPullUp() and internal pull-down through
635 * HAL_PWREx_EnableGPIOPullDown().
636 * @retval None.
637 */
HAL_PWR_EnterSTANDBYMode(void)638 void HAL_PWR_EnterSTANDBYMode(void)
639 {
640 /* Select Standby mode */
641 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_2);
642
643 /* Set SLEEPDEEP bit of Cortex System Control Register */
644 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
645
646 /* Wait For Interrupt Request */
647 __WFI();
648 }
649
650 /**
651 * @brief Indicate SLEEP-ON-EXIT feature when returning from handler mode to
652 * thread mode.
653 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
654 * processor re-enters Sleep mode when an interruption handling is over.
655 * Setting this bit is useful when the processor is expected to run
656 * only on interruptions handling.
657 * @retval None.
658 */
HAL_PWR_EnableSleepOnExit(void)659 void HAL_PWR_EnableSleepOnExit(void)
660 {
661 /* Set SLEEPONEXIT bit of Cortex-M33 System Control Register */
662 SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
663 }
664
665 /**
666 * @brief Disable SLEEP-ON-EXIT feature when returning from handler mode to
667 * thread mode.
668 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
669 * processor re-enters Sleep mode when an interruption handling is over.
670 * @retval None.
671 */
HAL_PWR_DisableSleepOnExit(void)672 void HAL_PWR_DisableSleepOnExit(void)
673 {
674 /* Clear SLEEPONEXIT bit of Cortex-M33 System Control Register */
675 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
676 }
677
678 /**
679 * @brief Enable CORTEX SEV-ON-PEND feature.
680 * @note Sets SEVONPEND bit of SCR register. When this bit is set, any
681 * pending event / interrupt even if it's disabled or has insufficient
682 * priority to cause exception entry wakes up the Cortex-M33.
683 * @retval None.
684 */
HAL_PWR_EnableSEVOnPend(void)685 void HAL_PWR_EnableSEVOnPend(void)
686 {
687 /* Set SEVONPEND bit of Cortex-M33 System Control Register */
688 SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
689 }
690
691 /**
692 * @brief Disable CORTEX SEVONPEND feature.
693 * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only enabled
694 * pending event / interrupt to cause exception entry wakes up the Cortex-M33.
695 * @retval None.
696 */
HAL_PWR_DisableSEVOnPend(void)697 void HAL_PWR_DisableSEVOnPend(void)
698 {
699 /* Clear SEVONPEND bit of Cortex-M33 System Control Register */
700 CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
701 }
702
703 /**
704 * @brief This function handles the PWR PVD interrupt request.
705 * @note This API should be called under the PVD_AVD_IRQHandler().
706 * @retval None.
707 */
HAL_PWR_PVD_IRQHandler(void)708 void HAL_PWR_PVD_IRQHandler(void)
709 {
710 uint32_t rising_flag;
711 uint32_t falling_flag;
712
713 /* Get pending flags */
714 rising_flag = READ_REG(EXTI->RPR1);
715 falling_flag = READ_REG(EXTI->FPR1);
716
717 /* Check PWR EXTI flags for PVD */
718 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVD) != 0U)
719 {
720 /* PWR PVD interrupt user callback */
721 HAL_PWR_PVDCallback();
722
723 /* Clear PVD EXTI pending bit */
724 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD);
725 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD);
726 }
727 }
728
729 /**
730 * @brief PWR PVD interrupt callback.
731 * @retval None.
732 */
HAL_PWR_PVDCallback(void)733 __weak void HAL_PWR_PVDCallback(void)
734 {
735 /* NOTE : This function should not be modified, when the callback is needed,
736 the HAL_PWR_PVDCallback can be implemented in the user file
737 */
738 }
739 /**
740 * @}
741 */
742
743 /** @defgroup PWR_Exported_Functions_Group3 Attributes Management Functions
744 * @brief Attributes management functions
745 *
746 @verbatim
747 ===============================================================================
748 ##### PWR Attributes Functions #####
749 ===============================================================================
750 [..]
751 When the TrustZone security is activated by the TZEN option bit in the
752 FLASH_OPTR register, some PWR register fields can be secured against
753 non-secure access.
754 The PWR TrustZone security allows the following features to be secured
755 through the PWR_SECCFGR register :
756
757 (++) Low-power mode.
758 (++) Wake-up (WKUP) pins.
759 (++) Voltage detection and monitoring.
760 (++) VBAT mode.
761 (++) I/Os pull-up/pull-down configuration.
762
763 Other PWR configuration bits are secure when :
764 (++) The system clock selection is secure in RCC: the voltage scaling
765 (VOS) configuration and the regulator booster (BOOSTEN) are secure.
766 (++) A GPIO is configured as secure: its corresponding bit for pull-up /
767 pull-down configuration in Standby mode is secure.
768 (++) The UCPD1 is secure in the GTZC: the PWR_UCPDR register is secure.
769
770 A non-secure access to a secure-protected register bit is denied :
771 (++) The secured bits are not written (WI) with a non-secure write access.
772 (++) The secured bits are read as 0 (RAZ) with a non-secure read access.
773
774 [..]
775 When the TrustZone security is disabled (TZEN = 0), PWR_SECCFGR is RAZ/WI
776 and all other registers are non-secure.
777
778 [..]
779 By default, after a reset, all PWR registers can be read or written with
780 both privileged and unprivileged accesses, except PWR_PRIVCFGR that can be
781 written with privileged access only. PWR_PRIVCFGR can be read by secure
782 and non secure, privileged and unprivileged accesses.
783 The SPRIV bit in PWR_PRIVCFGR can be written with secure privileged access
784 only. This bit configures the privileged access of all PWR secure
785 functions (defined by PWR_SECCFGR, GTZC, RCC or GPIO).
786 When the SPRIV bit is set in PWR_PRIVCFGR:
787 (++) The PWR secure bits can be written only with privileged access,
788 including PWR_SECCFGR.
789 (++) The PWR secure bits can be read only with privileged access except
790 PWR_SECCFGR and PWR_PRIVCFGR that can be read by privileged or
791 unprivileged access.
792 (++) An unprivileged access to a privileged PWR bit or register is
793 discarded : the bits are read as zero and the write to these bits is
794 ignored (RAZ/WI).
795 The NSPRIV bit of PWR_PRIVCFGR can be written with privileged access only,
796 secure or non-secure. This bit configures the privileged access of all PWR
797 securable functions that are configured as non-secure (defined by
798 PWR_SECCFGR, GTZC, RCC or GPIO).
799 When the NSPRIV bit is set in PWR_PRIVCFGR :
800 (++) The PWR securable bits that are configured as non-secure, can be
801 written only with privileged access.
802 (++) The PWR securable bits that are configured as non-secure, can be read
803 only with privileged access except PWR_PRIVCFGR that can be read by
804 privileged or unprivileged accesses.
805 (++) The VOSRDY and BOOSTRDY bits in PWR_VOSR, PWR_SR, PWR_SVMSR, PWR_BDSR
806 and PWR_WUSR, can be read with privileged or unprivileged accesses.
807 (++) An unprivileged access to a privileged PWR bit or register is
808 discarded : the bits are read as zero and the write to these bits is
809 ignored (RAZ/WI).
810
811 @endverbatim
812 * @{
813 */
814
815 /**
816 * @brief Configure the PWR item attributes.
817 * @note Available attributes are security and privilege protection.
818 * @note Security attribute can only be set only by secure access.
819 * @note Privilege attribute for secure items can be managed only by a secure
820 * privileged access.
821 * @note Privilege attribute for nsecure items can be managed by a secure
822 * privileged access or by a nsecure privileged access.
823 * @param Item : Specifies the item(s) to set attributes on.
824 * This parameter can be a combination of @ref PWR_Items.
825 * @param Attributes : Specifies the available attribute(s).
826 * This parameter can be one of @ref PWR_Attributes.
827 * @retval None.
828 */
HAL_PWR_ConfigAttributes(uint32_t Item,uint32_t Attributes)829 void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes)
830 {
831 /* Check the parameters */
832 assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
833 assert_param(IS_PWR_ATTRIBUTES(Attributes));
834
835 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
836 /* Secure item management (TZEN = 1) */
837 if ((Attributes & PWR_ITEM_ATTR_SEC_PRIV_MASK) == PWR_ITEM_ATTR_SEC_PRIV_MASK)
838 {
839 /* Privilege item management */
840 if ((Attributes & PWR_SEC_PRIV) == PWR_SEC_PRIV)
841 {
842 SET_BIT(PWR->SECCFGR, Item);
843 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
844 }
845 else
846 {
847 SET_BIT(PWR->SECCFGR, Item);
848 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
849 }
850 }
851 /* NSecure item management */
852 else
853 {
854 /* Privilege item management */
855 if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV)
856 {
857 CLEAR_BIT(PWR->SECCFGR, Item);
858 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
859 }
860 else
861 {
862 CLEAR_BIT(PWR->SECCFGR, Item);
863 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
864 }
865 }
866 #else
867 /* Prevent unused argument(s) compilation warning */
868 UNUSED(Item);
869
870 /* NSecure item management (TZEN = 0) */
871 if ((Attributes & PWR_ITEM_ATTR_NSEC_PRIV_MASK) == PWR_ITEM_ATTR_NSEC_PRIV_MASK)
872 {
873 /* Privilege item management */
874 if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV)
875 {
876 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
877 }
878 else
879 {
880 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
881 }
882 }
883 #endif /* __ARM_FEATURE_CMSE */
884 }
885
886 /**
887 * @brief Get attribute(s) of a PWR item.
888 * @param Item : Specifies the item(s) to get attributes of.
889 * This parameter can be one of @ref PWR_Items.
890 * @param pAttributes : Pointer to return attribute(s).
891 * Returned value could be one of @ref PWR_Attributes.
892 * @retval HAL Status.
893 */
HAL_PWR_GetConfigAttributes(uint32_t Item,uint32_t * pAttributes)894 HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes)
895 {
896 uint32_t attributes;
897
898 /* Check attribute pointer */
899 if (pAttributes == NULL)
900 {
901 return HAL_ERROR;
902 }
903
904 /* Check the parameter */
905 assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
906
907 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
908 /* Check item security */
909 if ((PWR->SECCFGR & Item) == Item)
910 {
911 /* Get Secure privileges attribute */
912 attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_SPRIV) == 0U) ? PWR_SEC_NPRIV : PWR_SEC_PRIV;
913 }
914 else
915 {
916 /* Get Non-Secure privileges attribute */
917 attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV;
918 }
919 #else
920 /* Get Non-Secure privileges attribute */
921 attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV;
922 #endif /* __ARM_FEATURE_CMSE */
923
924 /* return value */
925 *pAttributes = attributes;
926
927 return HAL_OK;
928 }
929 /**
930 * @}
931 */
932
933 /**
934 * @}
935 */
936
937 #endif /* defined (HAL_PWR_MODULE_ENABLED) */
938 /**
939 * @}
940 */
941
942 /**
943 * @}
944 */
945
