1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_lptim.c
4 * @author MCD Application Team
5 * @brief LPTIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Low Power Timer (LPTIM) peripheral:
8 * + Initialization and de-initialization functions.
9 * + Start/Stop operation functions in polling mode.
10 * + Start/Stop operation functions in interrupt mode.
11 * + Reading operation functions.
12 * + Peripheral State functions.
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2021 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### How to use this driver #####
28 ==============================================================================
29 [..]
30 The LPTIM HAL driver can be used as follows:
31
32 (#)Initialize the LPTIM low level resources by implementing the
33 HAL_LPTIM_MspInit():
34 (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
35 (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
36 (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
37 (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
38 (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
39
40 (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
41 configures mainly:
42 (++) The instance: LPTIM1, LPTIM2, LPTIM3 or LPTIM4.
43 (++) Clock: the counter clock.
44 (+++) Source : it can be either the ULPTIM input (IN1) or one of
45 the internal clock; (APB, LSE, LSI or MSI).
46 (+++) Prescaler: select the clock divider.
47 (++) UltraLowPowerClock : To be used only if the ULPTIM is selected
48 as counter clock source.
49 (+++) Polarity: polarity of the active edge for the counter unit
50 if the ULPTIM input is selected.
51 (+++) SampleTime: clock sampling time to configure the clock glitch
52 filter.
53 (++) Trigger: How the counter start.
54 (+++) Source: trigger can be software or one of the hardware triggers.
55 (+++) ActiveEdge : only for hardware trigger.
56 (+++) SampleTime : trigger sampling time to configure the trigger
57 glitch filter.
58 (++) OutputPolarity : 2 opposite polarities are possible.
59 (++) UpdateMode: specifies whether the update of the autoreload and
60 the compare values is done immediately or after the end of current
61 period.
62 (++) Input1Source: Source selected for input1 (GPIO or comparator output).
63 (++) Input2Source: Source selected for input2 (GPIO or comparator output).
64 Input2 is used only for encoder feature so is used only for LPTIM1 instance.
65
66 (#)Six modes are available:
67
68 (++) PWM Mode: To generate a PWM signal with specified period and pulse,
69 call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
70 mode.
71
72 (++) One Pulse Mode: To generate pulse with specified width in response
73 to a stimulus, call HAL_LPTIM_OnePulse_Start() or
74 HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
75
76 (++) Set once Mode: In this mode, the output changes the level (from
77 low level to high level if the output polarity is configured high, else
78 the opposite) when a compare match occurs. To start this mode, call
79 HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
80 interruption mode.
81
82 (++) Encoder Mode: To use the encoder interface call
83 HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
84 interruption mode. Only available for LPTIM1 instance.
85
86 (++) Time out Mode: an active edge on one selected trigger input rests
87 the counter. The first trigger event will start the timer, any
88 successive trigger event will reset the counter and the timer will
89 restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
90 HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
91
92 (++) Counter Mode: counter can be used to count external events on
93 the LPTIM Input1 or it can be used to count internal clock cycles.
94 To start this mode, call HAL_LPTIM_Counter_Start() or
95 HAL_LPTIM_Counter_Start_IT() for interruption mode.
96
97
98 (#) User can stop any process by calling the corresponding API:
99 HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
100 already started in interruption mode.
101
102 (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
103
104 *** Callback registration ***
105 =============================================
106 [..]
107 The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
108 allows the user to configure dynamically the driver callbacks.
109 [..]
110 Use Function HAL_LPTIM_RegisterCallback() to register a callback.
111 HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
112 the Callback ID and a pointer to the user callback function.
113 [..]
114 Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
115 default weak function.
116 HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
117 and the Callback ID.
118 [..]
119 These functions allow to register/unregister following callbacks:
120
121 (+) MspInitCallback : LPTIM Base Msp Init Callback.
122 (+) MspDeInitCallback : LPTIM Base Msp DeInit Callback.
123 (+) CompareMatchCallback : Compare match Callback.
124 (+) AutoReloadMatchCallback : Auto-reload match Callback.
125 (+) TriggerCallback : External trigger event detection Callback.
126 (+) CompareWriteCallback : Compare register write complete Callback.
127 (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
128 (+) DirectionUpCallback : Up-counting direction change Callback.
129 (+) DirectionDownCallback : Down-counting direction change Callback.
130 (+) UpdateEventCallback : Update event detection Callback.
131 (+) RepCounterWriteCallback : Repetition counter register write complete Callback.
132
133 [..]
134 By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
135 all interrupt callbacks are set to the corresponding weak functions:
136 examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().
137
138 [..]
139 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
140 functionalities in the Init/DeInit only when these callbacks are null
141 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
142 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
143
144 [..]
145 Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
146 Exception done MspInit/MspDeInit that can be registered/unregistered
147 in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
148 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
149 In that case first register the MspInit/MspDeInit user callbacks
150 using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
151
152 [..]
153 When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
154 not defined, the callback registration feature is not available and all callbacks
155 are set to the corresponding weak functions.
156
157 @endverbatim
158 ******************************************************************************
159 */
160
161 /* Includes ------------------------------------------------------------------*/
162 #include "stm32u5xx_hal.h"
163
164 /** @addtogroup STM32U5xx_HAL_Driver
165 * @{
166 */
167
168 /** @defgroup LPTIM LPTIM
169 * @brief LPTIM HAL module driver.
170 * @{
171 */
172
173 #ifdef HAL_LPTIM_MODULE_ENABLED
174
175 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4)
176
177 /* Private typedef -----------------------------------------------------------*/
178 /* Private define ------------------------------------------------------------*/
179 /** @addtogroup LPTIM_Private_Constants
180 * @{
181 */
182 #define TIMEOUT 1000UL /* Timeout is 1s */
183 /**
184 * @}
185 */
186
187 /* Private macro -------------------------------------------------------------*/
188 /* Private variables ---------------------------------------------------------*/
189 /* Private function prototypes -----------------------------------------------*/
190 static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig);
191 static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig);
192 static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig);
193 static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig);
194 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
195 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
196 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
197 static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag);
198 void LPTIM_DMAError(DMA_HandleTypeDef *hdma);
199 void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
200 void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
201 void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma);
202 void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma);
203 HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
204 uint32_t length);
205
206 /* Exported functions --------------------------------------------------------*/
207
208 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
209 * @{
210 */
211
212 /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
213 * @brief Initialization and Configuration functions.
214 *
215 @verbatim
216 ==============================================================================
217 ##### Initialization and de-initialization functions #####
218 ==============================================================================
219 [..] This section provides functions allowing to:
220 (+) Initialize the LPTIM according to the specified parameters in the
221 LPTIM_InitTypeDef and initialize the associated handle.
222 (+) DeInitialize the LPTIM peripheral.
223 (+) Initialize the LPTIM MSP.
224 (+) DeInitialize the LPTIM MSP.
225
226 @endverbatim
227 * @{
228 */
229
230 /**
231 * @brief Initialize the LPTIM according to the specified parameters in the
232 * LPTIM_InitTypeDef and initialize the associated handle.
233 * @param hlptim LPTIM handle
234 * @retval HAL status
235 */
HAL_LPTIM_Init(LPTIM_HandleTypeDef * hlptim)236 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
237 {
238 uint32_t tmpcfgr;
239
240 /* Check the LPTIM handle allocation */
241 if (hlptim == NULL)
242 {
243 return HAL_ERROR;
244 }
245
246 /* Check the parameters */
247 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
248 assert_param(IS_LPTIM_PERIOD(hlptim->Init.Period));
249
250 assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
251 assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
252 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
253 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
254 {
255 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
256 assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
257 }
258 assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
259 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
260 {
261 assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
262 assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
263 }
264 assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
265 assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
266 assert_param(IS_LPTIM_REPETITION(hlptim->Init.RepetitionCounter));
267
268 if (hlptim->State == HAL_LPTIM_STATE_RESET)
269 {
270 /* Allocate lock resource and initialize it */
271 hlptim->Lock = HAL_UNLOCKED;
272
273 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
274 /* Reset interrupt callbacks to legacy weak callbacks */
275 LPTIM_ResetCallback(hlptim);
276
277 if (hlptim->MspInitCallback == NULL)
278 {
279 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
280 }
281
282 /* Init the low level hardware : GPIO, CLOCK, NVIC */
283 hlptim->MspInitCallback(hlptim);
284 #else
285 /* Init the low level hardware : GPIO, CLOCK, NVIC */
286 HAL_LPTIM_MspInit(hlptim);
287 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
288 }
289
290 /* Change the LPTIM state */
291 hlptim->State = HAL_LPTIM_STATE_BUSY;
292
293 /* Enable the Peripheral */
294 __HAL_LPTIM_ENABLE(hlptim);
295
296 /* Clear flag */
297 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
298
299 /* Set the repetition counter */
300 __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter);
301
302 /* Wait for the completion of the write operation to the LPTIM_RCR register */
303 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_REPOK) == HAL_TIMEOUT)
304 {
305 return HAL_TIMEOUT;
306 }
307
308
309 /* Clear flag */
310 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
311
312 /* Set LPTIM Period */
313 __HAL_LPTIM_AUTORELOAD_SET(hlptim, hlptim->Init.Period);
314
315 /* Wait for the completion of the write operation to the LPTIM_ARR register */
316 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
317 {
318 return HAL_TIMEOUT;
319 }
320
321 /* Disable the Peripheral */
322 __HAL_LPTIM_DISABLE(hlptim);
323
324 /* Get the LPTIMx CFGR value */
325 tmpcfgr = hlptim->Instance->CFGR;
326
327 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
328 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
329 {
330 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
331 }
332 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
333 {
334 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
335 }
336
337 /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
338 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
339 LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
340
341 /* Set initialization parameters */
342 tmpcfgr |= (hlptim->Init.Clock.Source |
343 hlptim->Init.Clock.Prescaler |
344 hlptim->Init.UpdateMode |
345 hlptim->Init.CounterSource);
346
347 /* Glitch filters for internal triggers and external inputs are configured
348 * only if an internal clock source is provided to the LPTIM
349 */
350 if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
351 {
352 tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
353 hlptim->Init.UltraLowPowerClock.SampleTime);
354 }
355
356 /* Configure LPTIM external clock polarity and digital filter */
357 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
358 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
359 {
360 tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
361 hlptim->Init.UltraLowPowerClock.SampleTime);
362 }
363
364 /* Configure LPTIM external trigger */
365 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
366 {
367 /* Enable External trigger and set the trigger source */
368 tmpcfgr |= (hlptim->Init.Trigger.Source |
369 hlptim->Init.Trigger.ActiveEdge |
370 hlptim->Init.Trigger.SampleTime);
371 }
372
373 /* Write to LPTIMx CFGR */
374 hlptim->Instance->CFGR = tmpcfgr;
375
376 /* Configure LPTIM input sources */
377 if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2))
378 {
379 /* Check LPTIM Input1 and Input2 sources */
380 assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
381 assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source));
382
383 /* Configure LPTIM Input1 and Input2 sources */
384 hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
385 }
386 else
387 {
388 if ((hlptim->Instance == LPTIM3) || (hlptim->Instance == LPTIM4))
389 {
390 /* Check LPTIM3 Input1 source */
391 assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
392
393 /* Configure LPTIM3 Input1 source */
394 hlptim->Instance->CFGR2 = hlptim->Init.Input1Source;
395 }
396 }
397
398 /* Initialize the LPTIM channels state */
399 LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_READY);
400
401 /* Change the LPTIM state */
402 hlptim->State = HAL_LPTIM_STATE_READY;
403
404 /* Return function status */
405 return HAL_OK;
406 }
407
408 /**
409 * @brief DeInitialize the LPTIM peripheral.
410 * @param hlptim LPTIM handle
411 * @retval HAL status
412 */
HAL_LPTIM_DeInit(LPTIM_HandleTypeDef * hlptim)413 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
414 {
415 /* Check the LPTIM handle allocation */
416 if (hlptim == NULL)
417 {
418 return HAL_ERROR;
419 }
420
421 /* Change the LPTIM state */
422 hlptim->State = HAL_LPTIM_STATE_BUSY;
423
424 __HAL_LPTIM_ENABLE(hlptim);
425 if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
426 {
427 hlptim->Instance->CCMR1 = 0;
428 }
429
430 /* Clear flag */
431 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
432
433 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, 0);
434 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
435 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
436 {
437 return HAL_TIMEOUT;
438 }
439
440 if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
441 {
442 /* Clear flag */
443 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
444
445 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, 0);
446 /* Wait for the completion of the write operation to the LPTIM_CCR2 register */
447 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) == HAL_TIMEOUT)
448 {
449 return HAL_TIMEOUT;
450 }
451 }
452
453 /* Clear flag */
454 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
455
456 __HAL_LPTIM_AUTORELOAD_SET(hlptim, 0);
457
458 /* Wait for the completion of the write operation to the LPTIM_ARR register */
459 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
460 {
461 return HAL_TIMEOUT;
462 }
463
464 /* Disable the LPTIM Peripheral Clock */
465 __HAL_LPTIM_DISABLE(hlptim);
466
467 hlptim->Instance->CFGR = 0;
468 hlptim->Instance->CFGR2 = 0;
469
470 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
471 if (hlptim->MspDeInitCallback == NULL)
472 {
473 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
474 }
475
476 /* DeInit the low level hardware: CLOCK, NVIC.*/
477 hlptim->MspDeInitCallback(hlptim);
478 #else
479 /* DeInit the low level hardware: CLOCK, NVIC.*/
480 HAL_LPTIM_MspDeInit(hlptim);
481 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
482
483 /* Change the LPTIM channels state */
484 LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_RESET);
485
486 /* Change the LPTIM state */
487 hlptim->State = HAL_LPTIM_STATE_RESET;
488
489 /* Release Lock */
490 __HAL_UNLOCK(hlptim);
491
492 /* Return function status */
493 return HAL_OK;
494 }
495
496 /**
497 * @brief Initialize the LPTIM MSP.
498 * @param hlptim LPTIM handle
499 * @retval None
500 */
HAL_LPTIM_MspInit(LPTIM_HandleTypeDef * hlptim)501 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
502 {
503 /* Prevent unused argument(s) compilation warning */
504 UNUSED(hlptim);
505
506 /* NOTE : This function should not be modified, when the callback is needed,
507 the HAL_LPTIM_MspInit could be implemented in the user file
508 */
509 }
510
511 /**
512 * @brief DeInitialize LPTIM MSP.
513 * @param hlptim LPTIM handle
514 * @retval None
515 */
HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef * hlptim)516 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
517 {
518 /* Prevent unused argument(s) compilation warning */
519 UNUSED(hlptim);
520
521 /* NOTE : This function should not be modified, when the callback is needed,
522 the HAL_LPTIM_MspDeInit could be implemented in the user file
523 */
524 }
525
526 /**
527 * @}
528 */
529
530 /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
531 * @brief Start-Stop operation functions.
532 *
533 @verbatim
534 ==============================================================================
535 ##### LPTIM Start Stop operation functions #####
536 ==============================================================================
537 [..] This section provides functions allowing to:
538 (+) Start the PWM mode.
539 (+) Stop the PWM mode.
540 (+) Start the One pulse mode.
541 (+) Stop the One pulse mode.
542 (+) Start the Set once mode.
543 (+) Stop the Set once mode.
544 (+) Start the Encoder mode.
545 (+) Stop the Encoder mode.
546 (+) Start the Timeout mode.
547 (+) Stop the Timeout mode.
548 (+) Start the Counter mode.
549 (+) Stop the Counter mode.
550
551
552 @endverbatim
553 * @{
554 */
555
556 /**
557 * @brief Start the LPTIM PWM generation.
558 * @param hlptim LPTIM handle
559 * @param Channel LPTIM Channel to be enabled
560 * This parameter can be one of the following values:
561 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
562 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
563 * @retval HAL status
564 */
HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)565 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
566 {
567 /* Check the parameters */
568 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
569
570 /* Check LPTIM channel state */
571 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
572 {
573 return HAL_ERROR;
574 }
575
576 /* Set the LPTIM state */
577 hlptim->State = HAL_LPTIM_STATE_BUSY;
578
579 /* Set the LPTIM channel state */
580 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
581
582 /* Reset WAVE bit to set PWM mode */
583 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
584
585 /* Enable the Peripheral */
586 __HAL_LPTIM_ENABLE(hlptim);
587
588 /* Enable LPTIM signal on the corresponding output pin */
589 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
590
591 /* Start timer in continuous mode */
592 __HAL_LPTIM_START_CONTINUOUS(hlptim);
593
594 /* Change the LPTIM state */
595 hlptim->State = HAL_LPTIM_STATE_READY;
596
597 /* Return function status */
598 return HAL_OK;
599 }
600
601 /**
602 * @brief Stop the LPTIM PWM generation.
603 * @param hlptim LPTIM handle
604 * @param Channel LPTIM Channel to be disabled
605 * This parameter can be one of the following values:
606 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
607 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
608 * @retval HAL status
609 */
HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)610 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
611 {
612 /* Check the parameters */
613 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
614
615 /* Change the LPTIM state */
616 hlptim->State = HAL_LPTIM_STATE_BUSY;
617
618 /* Disable LPTIM signal from the corresponding output pin */
619 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
620
621 /* Disable the Peripheral */
622 __HAL_LPTIM_DISABLE(hlptim);
623
624 /* Set the LPTIM channel state */
625 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
626
627 /* Set the LPTIM state */
628 hlptim->State = HAL_LPTIM_STATE_READY;
629
630 /* Return function status */
631 return HAL_OK;
632 }
633
634 /**
635 * @brief Start the LPTIM PWM generation in interrupt mode.
636 * @param hlptim LPTIM handle
637 * @param Channel LPTIM Channel to be enabled
638 * This parameter can be one of the following values:
639 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
640 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
641 * @retval HAL status
642 */
HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)643 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
644 {
645 /* Check the parameters */
646 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
647
648 /* Check LPTIM channel state */
649 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
650 {
651 return HAL_ERROR;
652 }
653
654 /* Set the LPTIM state */
655 hlptim->State = HAL_LPTIM_STATE_BUSY;
656
657 /* Set the LPTIM channel state */
658 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
659
660 /* Reset WAVE bit to set PWM mode */
661 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
662
663 /* Enable the Peripheral */
664 __HAL_LPTIM_ENABLE(hlptim);
665 /* Clear flag */
666 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
667
668 switch (Channel)
669 {
670 case LPTIM_CHANNEL_1:
671 /* Enable interrupt */
672 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
673 LPTIM_IT_UPDATE);
674 break;
675 case LPTIM_CHANNEL_2:
676 /* Enable interrupt */
677 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
678 LPTIM_IT_UPDATE);
679 break;
680 default:
681 break;
682 }
683
684 /* Wait for the completion of the write operation to the LPTIM_DIER register */
685 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
686 {
687 return HAL_TIMEOUT;
688 }
689
690 /* If external trigger source is used, then enable external trigger interrupt */
691 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
692 {
693 /* Clear flag */
694 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
695
696 /* Enable external trigger interrupt */
697 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
698
699 /* Wait for the completion of the write operation to the LPTIM_DIER register */
700 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
701 {
702 return HAL_TIMEOUT;
703 }
704 }
705
706 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
707
708 /* Start timer in continuous mode */
709 __HAL_LPTIM_START_CONTINUOUS(hlptim);
710
711 /* Change the LPTIM state */
712 hlptim->State = HAL_LPTIM_STATE_READY;
713
714 /* Return function status */
715 return HAL_OK;
716 }
717
718 /**
719 * @brief Stop the LPTIM PWM generation in interrupt mode.
720 * @param hlptim LPTIM handle
721 * @param Channel LPTIM Channel to be disabled
722 * This parameter can be one of the following values:
723 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
724 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
725 * @retval HAL status
726 */
HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)727 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
728 {
729 /* Check the parameters */
730 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
731
732 /* Change the LPTIM state */
733 hlptim->State = HAL_LPTIM_STATE_BUSY;
734
735 /* Disable LPTIM signal from the corresponding output pin */
736 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
737
738 /* Disable the Peripheral */
739 __HAL_LPTIM_DISABLE(hlptim);
740
741 /* Enable the Peripheral */
742 __HAL_LPTIM_ENABLE(hlptim);
743
744 /* Clear flag */
745 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
746
747 switch (Channel)
748 {
749 case LPTIM_CHANNEL_1:
750 /* Disable interrupt */
751 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
752 LPTIM_IT_UPDATE);
753 break;
754 case LPTIM_CHANNEL_2:
755 /* Disable interrupt */
756 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
757 LPTIM_IT_UPDATE);
758 break;
759 default:
760 break;
761 }
762
763 /* Wait for the completion of the write operation to the LPTIM_DIER register */
764 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
765 {
766 return HAL_TIMEOUT;
767 }
768
769 /* If external trigger source is used, then enable external trigger interrupt */
770 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
771 {
772 /* Clear flag */
773 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
774
775 /* Enable external trigger interrupt */
776 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
777
778 /* Wait for the completion of the write operation to the LPTIM_DIER register */
779 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
780 {
781 return HAL_TIMEOUT;
782 }
783 }
784
785 /* Disable the Peripheral */
786 __HAL_LPTIM_DISABLE(hlptim);
787
788 /* Set the LPTIM channel state */
789 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
790
791 /* Set the LPTIM state */
792 hlptim->State = HAL_LPTIM_STATE_READY;
793
794 /* Return function status */
795 return HAL_OK;
796 }
797
798 /**
799 * @brief Start the LPTIM PWM generation in DMA mode.
800 * @param hlptim LPTIM handle
801 * @param Channel LPTIM Channel to be enabled
802 * This parameter can be one of the following values:
803 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
804 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
805 * @param pData The destination Buffer address
806 * @param Length The length of data to be transferred from LPTIM peripheral to memory
807 * @retval HAL status
808 */
HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel,const uint32_t * pData,uint32_t Length)809 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, const uint32_t *pData,
810 uint32_t Length)
811 {
812 DMA_HandleTypeDef *hdma;
813
814 /* Check the parameters */
815 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
816 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
817
818 if ((pData == NULL) || (Length == 0U))
819 {
820 return HAL_ERROR;
821 }
822
823 /* Check LPTIM channel state */
824 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
825 {
826 return HAL_ERROR;
827 }
828
829 /* Set the LPTIM state */
830 hlptim->State = HAL_LPTIM_STATE_BUSY;
831
832 /* Set the LPTIM channel state */
833 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
834
835 /* Reset WAVE bit to set PWM mode */
836 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
837
838 /* Enable the Peripheral */
839 __HAL_LPTIM_ENABLE(hlptim);
840
841 /* Enable update event DMA request */
842 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
843
844 /* Wait for the completion of the write operation to the LPTIM_DIER register */
845 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
846 {
847 return HAL_TIMEOUT;
848 }
849
850 switch (Channel)
851 {
852 case LPTIM_CHANNEL_1:
853 /* Set the DMA update event callbacks */
854 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
855 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
856
857 /* Set the DMA error callback */
858 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
859
860 /* Enable the DMA Channel */
861 hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
862 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR1, Length) != HAL_OK)
863 {
864 /* Return error status */
865 return HAL_ERROR;
866 }
867 break;
868 case LPTIM_CHANNEL_2:
869 /* Set the DMA update event callbacks */
870 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
871 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
872
873 /* Set the DMA error callback */
874 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
875
876 /* Enable the DMA Channel */
877 hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
878 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR2, Length) != HAL_OK)
879 {
880 /* Return error status */
881 return HAL_ERROR;
882 }
883 break;
884 default:
885 break;
886 }
887
888 /* Enable LPTIM signal on the corresponding output pin */
889 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
890
891 /* Start timer in continuous mode */
892 __HAL_LPTIM_START_CONTINUOUS(hlptim);
893
894 /* Change the LPTIM state */
895 hlptim->State = HAL_LPTIM_STATE_READY;
896
897 /* Return function status */
898 return HAL_OK;
899 }
900
901 /**
902 * @brief Stop the LPTIM PWM generation in DMA mode.
903 * @param hlptim LPTIM handle
904 * @param Channel LPTIM Channel to be disabled
905 * This parameter can be one of the following values:
906 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
907 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
908 * @retval HAL status
909 */
HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)910 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
911 {
912 /* Check the parameters */
913 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
914 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
915
916 /* Change the LPTIM state */
917 hlptim->State = HAL_LPTIM_STATE_BUSY;
918
919 /* Disable update event DMA request */
920 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
921
922 switch (Channel)
923 {
924 case LPTIM_CHANNEL_1:
925 /* Disable update event DMA request */
926 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
927 break;
928 case LPTIM_CHANNEL_2:
929 /* Disable update event DMA request */
930 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
931 break;
932 default:
933 break;
934 }
935
936 /* Disable LPTIM signal from the corresponding output pin */
937 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
938
939 /* Disable the Peripheral */
940 __HAL_LPTIM_DISABLE(hlptim);
941
942 /* Set the LPTIM channel state */
943 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
944
945 /* Set the LPTIM state */
946 hlptim->State = HAL_LPTIM_STATE_READY;
947
948 /* Return function status */
949 return HAL_OK;
950 }
951
952 /**
953 * @brief Start the LPTIM One pulse generation.
954 * @param hlptim LPTIM handle
955 * @param Channel LPTIM Channel to be enabled
956 * This parameter can be one of the following values:
957 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
958 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
959 * @retval HAL status
960 */
HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)961 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
962 {
963 /* Check the parameters */
964 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
965
966 /* Check LPTIM channel state */
967 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
968 {
969 return HAL_ERROR;
970 }
971
972 /* Set the LPTIM state */
973 hlptim->State = HAL_LPTIM_STATE_BUSY;
974
975 /* Set the LPTIM channel state */
976 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
977
978 /* Reset WAVE bit to set one pulse mode */
979 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
980
981 /* Enable the Peripheral */
982 __HAL_LPTIM_ENABLE(hlptim);
983
984 /* Enable LPTIM signal on the corresponding output pin */
985 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
986
987 /* Start timer in single (one shot) mode */
988 __HAL_LPTIM_START_SINGLE(hlptim);
989
990 /* Change the LPTIM state */
991 hlptim->State = HAL_LPTIM_STATE_READY;
992
993 /* Return function status */
994 return HAL_OK;
995 }
996
997 /**
998 * @brief Stop the LPTIM One pulse generation.
999 * @param hlptim LPTIM handle
1000 * @param Channel LPTIM Channel to be disabled
1001 * This parameter can be one of the following values:
1002 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1003 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1004 * @retval HAL status
1005 */
HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1006 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1007 {
1008 /* Check the parameters */
1009 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1010
1011 /* Set the LPTIM state */
1012 hlptim->State = HAL_LPTIM_STATE_BUSY;
1013
1014 /* Disable LPTIM signal on the corresponding output pin */
1015 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1016
1017 /* Disable the Peripheral */
1018 __HAL_LPTIM_DISABLE(hlptim);
1019
1020 /* Set the LPTIM channel state */
1021 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1022
1023 /* Set the LPTIM state */
1024 hlptim->State = HAL_LPTIM_STATE_READY;
1025
1026 /* Return function status */
1027 return HAL_OK;
1028 }
1029
1030 /**
1031 * @brief Start the LPTIM One pulse generation in interrupt mode.
1032 * @param hlptim LPTIM handle
1033 * @param Channel LPTIM Channel to be enabled
1034 * This parameter can be one of the following values:
1035 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1036 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1037 * @retval HAL status
1038 */
HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1039 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1040 {
1041 /* Check the parameters */
1042 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1043
1044 /* Check LPTIM channel state */
1045 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1046 {
1047 return HAL_ERROR;
1048 }
1049
1050 /* Set the LPTIM state */
1051 hlptim->State = HAL_LPTIM_STATE_BUSY;
1052
1053 /* Set the LPTIM channel state */
1054 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1055
1056 /* Reset WAVE bit to set one pulse mode */
1057 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
1058
1059 /* Enable the Peripheral */
1060 __HAL_LPTIM_ENABLE(hlptim);
1061
1062 /* Clear flag */
1063 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1064
1065 switch (Channel)
1066 {
1067 case LPTIM_CHANNEL_1:
1068 /* Enable interrupt */
1069 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1070 LPTIM_IT_UPDATE);
1071 break;
1072 case LPTIM_CHANNEL_2:
1073 /* Enable interrupt */
1074 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1075 LPTIM_IT_UPDATE);
1076 break;
1077 default:
1078 break;
1079 }
1080
1081 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1082 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1083 {
1084 return HAL_TIMEOUT;
1085 }
1086
1087 /* If external trigger source is used, then enable external trigger interrupt */
1088 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1089 {
1090 /* Clear flag */
1091 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1092 /* Enable external trigger interrupt */
1093 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1094 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1095 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1096 {
1097 return HAL_TIMEOUT;
1098 }
1099 }
1100
1101 /* Enable LPTIM signal on the corresponding output pin */
1102 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1103
1104 /* Start timer in single (one shot) mode */
1105 __HAL_LPTIM_START_SINGLE(hlptim);
1106
1107 /* Change the LPTIM state */
1108 hlptim->State = HAL_LPTIM_STATE_READY;
1109
1110 /* Return function status */
1111 return HAL_OK;
1112 }
1113
1114 /**
1115 * @brief Stop the LPTIM One pulse generation in interrupt mode.
1116 * @param hlptim LPTIM handle
1117 * @param Channel LPTIM Channel to be disabled
1118 * This parameter can be one of the following values:
1119 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1120 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1121 * @retval HAL status
1122 */
HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1123 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1124 {
1125 /* Check the parameters */
1126 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1127
1128 /* Set the LPTIM state */
1129 hlptim->State = HAL_LPTIM_STATE_BUSY;
1130
1131 /* Disable LPTIM signal on the corresponding output pin */
1132 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1133
1134 /* Disable the Peripheral */
1135 __HAL_LPTIM_DISABLE(hlptim);
1136
1137
1138 /* Enable the Peripheral */
1139 __HAL_LPTIM_ENABLE(hlptim);
1140
1141 /* Clear flag */
1142 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1143
1144 switch (Channel)
1145 {
1146 case LPTIM_CHANNEL_1:
1147 /* Disable interrupt */
1148 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1149 LPTIM_IT_UPDATE);
1150 break;
1151 case LPTIM_CHANNEL_2:
1152 /* Disable interrupt */
1153 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1154 LPTIM_IT_UPDATE);
1155 break;
1156 default:
1157 break;
1158 }
1159
1160 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1161 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1162 {
1163 return HAL_TIMEOUT;
1164 }
1165
1166 /* If external trigger source is used, then enable external trigger interrupt */
1167 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1168 {
1169 /* Clear flag */
1170 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1171 /* Enable external trigger interrupt */
1172 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1173 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1174 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1175 {
1176 return HAL_TIMEOUT;
1177 }
1178 }
1179
1180 /* Disable the Peripheral */
1181 __HAL_LPTIM_DISABLE(hlptim);
1182
1183 /* Set the LPTIM channel state */
1184 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1185
1186 /* Set the LPTIM state */
1187 hlptim->State = HAL_LPTIM_STATE_READY;
1188
1189 /* Return function status */
1190 return HAL_OK;
1191 }
1192
1193 /**
1194 * @brief Start the LPTIM in Set once mode.
1195 * @param hlptim LPTIM handle
1196 * @param Channel LPTIM Channel to be enabled
1197 * This parameter can be one of the following values:
1198 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1199 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1200 * @retval HAL status
1201 */
HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1202 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1203 {
1204 /* Check the parameters */
1205 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1206
1207 /* Check LPTIM channel state */
1208 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1209 {
1210 return HAL_ERROR;
1211 }
1212
1213 /* Set the LPTIM state */
1214 hlptim->State = HAL_LPTIM_STATE_BUSY;
1215
1216 /* Set the LPTIM channel state */
1217 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1218
1219 /* Set WAVE bit to enable the set once mode */
1220 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
1221
1222 /* Enable the Peripheral */
1223 __HAL_LPTIM_ENABLE(hlptim);
1224
1225 /* Enable LPTIM signal on the corresponding output pin */
1226 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1227
1228 /* Start timer in single (one shot) mode */
1229 __HAL_LPTIM_START_SINGLE(hlptim);
1230
1231 /* Change the LPTIM state */
1232 hlptim->State = HAL_LPTIM_STATE_READY;
1233
1234 /* Return function status */
1235 return HAL_OK;
1236 }
1237
1238 /**
1239 * @brief Stop the LPTIM Set once mode.
1240 * @param hlptim LPTIM handle
1241 * @param Channel LPTIM Channel to be disabled
1242 * This parameter can be one of the following values:
1243 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1244 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1245 * @retval HAL status
1246 */
HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1247 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1248 {
1249 /* Check the parameters */
1250 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1251
1252 /* Set the LPTIM state */
1253 hlptim->State = HAL_LPTIM_STATE_BUSY;
1254
1255 /* Disable LPTIM signal on the corresponding output pin */
1256 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1257
1258 /* Disable the Peripheral */
1259 __HAL_LPTIM_DISABLE(hlptim);
1260
1261 /* Set the LPTIM channel state */
1262 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1263
1264 /* Set the LPTIM state */
1265 hlptim->State = HAL_LPTIM_STATE_READY;
1266
1267 /* Return function status */
1268 return HAL_OK;
1269 }
1270
1271 /**
1272 * @brief Start the LPTIM Set once mode in interrupt mode.
1273 * @param hlptim LPTIM handle
1274 * @param Channel LPTIM Channel to be enabled
1275 * This parameter can be one of the following values:
1276 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1277 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1278 * @retval HAL status
1279 */
HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1280 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1281 {
1282 /* Check the parameters */
1283 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1284
1285 /* Check LPTIM channel state */
1286 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1287 {
1288 return HAL_ERROR;
1289 }
1290
1291 /* Set the LPTIM state */
1292 hlptim->State = HAL_LPTIM_STATE_BUSY;
1293
1294 /* Set the LPTIM channel state */
1295 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1296
1297 /* Set WAVE bit to enable the set once mode */
1298 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
1299
1300 /* Enable the Peripheral */
1301 __HAL_LPTIM_ENABLE(hlptim);
1302
1303 /* Clear flag */
1304 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1305
1306 switch (Channel)
1307 {
1308 case LPTIM_CHANNEL_1:
1309 /* Enable interrupt */
1310 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
1311 break;
1312 case LPTIM_CHANNEL_2:
1313 /* Enable interrupt */
1314 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
1315 break;
1316 default:
1317 break;
1318 }
1319
1320 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1321 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1322 {
1323 return HAL_TIMEOUT;
1324 }
1325
1326 /* If external trigger source is used, then enable external trigger interrupt */
1327 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1328 {
1329 /* Clear flag */
1330 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1331 /* Enable external trigger interrupt */
1332 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1333 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1334 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1335 {
1336 return HAL_TIMEOUT;
1337 }
1338 }
1339
1340 /* Enable LPTIM signal on the corresponding output pin */
1341 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1342
1343 /* Start timer in single (one shot) mode */
1344 __HAL_LPTIM_START_SINGLE(hlptim);
1345
1346 /* Change the LPTIM state */
1347 hlptim->State = HAL_LPTIM_STATE_READY;
1348
1349 /* Return function status */
1350 return HAL_OK;
1351 }
1352
1353 /**
1354 * @brief Stop the LPTIM Set once mode in interrupt mode.
1355 * @param hlptim LPTIM handle
1356 * @param Channel LPTIM Channel to be disabled
1357 * This parameter can be one of the following values:
1358 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1359 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1360 * @retval HAL status
1361 */
HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1362 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1363 {
1364 /* Check the parameters */
1365 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1366
1367 /* Set the LPTIM state */
1368 hlptim->State = HAL_LPTIM_STATE_BUSY;
1369
1370 /* Disable LPTIM signal on the corresponding output pin */
1371 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1372
1373 /* Disable the Peripheral */
1374 __HAL_LPTIM_DISABLE(hlptim);
1375
1376 /* Enable the Peripheral */
1377 __HAL_LPTIM_ENABLE(hlptim);
1378
1379 /* Clear flag */
1380 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1381
1382 switch (Channel)
1383 {
1384 case LPTIM_CHANNEL_1:
1385 /* Disable interrupt */
1386 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
1387 break;
1388 case LPTIM_CHANNEL_2:
1389 /* Disable interrupt */
1390 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
1391 break;
1392 default:
1393 break;
1394 }
1395
1396 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1397 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1398 {
1399 return HAL_TIMEOUT;
1400 }
1401
1402 /* If external trigger source is used, then enable external trigger interrupt */
1403 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1404 {
1405 /* Clear flag */
1406 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1407 /* Enable external trigger interrupt */
1408 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1409
1410 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1411 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1412 {
1413 return HAL_TIMEOUT;
1414 }
1415 }
1416
1417 /* Disable the Peripheral */
1418 __HAL_LPTIM_DISABLE(hlptim);
1419
1420 /* Set the LPTIM channel state */
1421 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1422
1423 /* Set the LPTIM state */
1424 hlptim->State = HAL_LPTIM_STATE_READY;
1425
1426 /* Return function status */
1427 return HAL_OK;
1428 }
1429
1430 /**
1431 * @brief Start the Encoder interface.
1432 * @param hlptim LPTIM handle
1433 * @retval HAL status
1434 */
HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef * hlptim)1435 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim)
1436 {
1437 uint32_t tmpcfgr;
1438
1439 /* Check the parameters */
1440 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1441 assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
1442 assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
1443 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
1444
1445 /* Set the LPTIM state */
1446 hlptim->State = HAL_LPTIM_STATE_BUSY;
1447
1448 /* Get the LPTIMx CFGR value */
1449 tmpcfgr = hlptim->Instance->CFGR;
1450
1451 /* Clear CKPOL bits */
1452 tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
1453
1454 /* Set Input polarity */
1455 tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
1456
1457 /* Write to LPTIMx CFGR */
1458 hlptim->Instance->CFGR = tmpcfgr;
1459
1460 /* Set ENC bit to enable the encoder interface */
1461 hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
1462
1463 /* Enable the Peripheral */
1464 __HAL_LPTIM_ENABLE(hlptim);
1465
1466 /* Start timer in continuous mode */
1467 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1468
1469 /* Change the LPTIM state */
1470 hlptim->State = HAL_LPTIM_STATE_READY;
1471
1472 /* Return function status */
1473 return HAL_OK;
1474 }
1475
1476 /**
1477 * @brief Stop the Encoder interface.
1478 * @param hlptim LPTIM handle
1479 * @retval HAL status
1480 */
HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef * hlptim)1481 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
1482 {
1483 /* Check the parameters */
1484 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1485
1486 /* Set the LPTIM state */
1487 hlptim->State = HAL_LPTIM_STATE_BUSY;
1488
1489 /* Disable the Peripheral */
1490 __HAL_LPTIM_DISABLE(hlptim);
1491
1492 /* Reset ENC bit to disable the encoder interface */
1493 hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
1494
1495 /* Change the LPTIM state */
1496 hlptim->State = HAL_LPTIM_STATE_READY;
1497
1498 /* Return function status */
1499 return HAL_OK;
1500 }
1501
1502 /**
1503 * @brief Start the Encoder interface in interrupt mode.
1504 * @param hlptim LPTIM handle
1505 * @retval HAL status
1506 */
HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef * hlptim)1507 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim)
1508 {
1509 uint32_t tmpcfgr;
1510
1511 /* Check the parameters */
1512 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1513 assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
1514 assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
1515 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
1516
1517 /* Set the LPTIM state */
1518 hlptim->State = HAL_LPTIM_STATE_BUSY;
1519
1520 /* Configure edge sensitivity for encoder mode */
1521 /* Get the LPTIMx CFGR value */
1522 tmpcfgr = hlptim->Instance->CFGR;
1523
1524 /* Clear CKPOL bits */
1525 tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
1526
1527 /* Set Input polarity */
1528 tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
1529
1530 /* Write to LPTIMx CFGR */
1531 hlptim->Instance->CFGR = tmpcfgr;
1532
1533 /* Set ENC bit to enable the encoder interface */
1534 hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
1535
1536 /* Enable the Peripheral */
1537 __HAL_LPTIM_ENABLE(hlptim);
1538
1539 /* Clear flag */
1540 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1541
1542 /* Enable "switch to up/down direction" interrupt */
1543 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
1544
1545 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1546 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1547 {
1548 return HAL_TIMEOUT;
1549 }
1550
1551
1552 /* Start timer in continuous mode */
1553 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1554
1555 /* Change the LPTIM state */
1556 hlptim->State = HAL_LPTIM_STATE_READY;
1557
1558 /* Return function status */
1559 return HAL_OK;
1560 }
1561
1562 /**
1563 * @brief Stop the Encoder interface in interrupt mode.
1564 * @param hlptim LPTIM handle
1565 * @retval HAL status
1566 */
HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef * hlptim)1567 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1568 {
1569 /* Check the parameters */
1570 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1571
1572 /* Set the LPTIM state */
1573 hlptim->State = HAL_LPTIM_STATE_BUSY;
1574
1575 /* Disable the Peripheral */
1576 __HAL_LPTIM_DISABLE(hlptim);
1577
1578 /* Reset ENC bit to disable the encoder interface */
1579 hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
1580 /* Enable the Peripheral */
1581 __HAL_LPTIM_ENABLE(hlptim);
1582
1583 /* Clear flag */
1584 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1585
1586 /* Disable "switch to down/up direction" interrupt */
1587 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
1588
1589 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1590 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1591 {
1592 return HAL_TIMEOUT;
1593 }
1594
1595 /* Disable the Peripheral */
1596 __HAL_LPTIM_DISABLE(hlptim);
1597
1598 /* Change the LPTIM state */
1599 hlptim->State = HAL_LPTIM_STATE_READY;
1600
1601 /* Return function status */
1602 return HAL_OK;
1603 }
1604
1605 /**
1606 * @brief Start the Timeout function.
1607 * @note The first trigger event will start the timer, any successive
1608 * trigger event will reset the counter and the timer restarts.
1609 * @param hlptim LPTIM handle
1610 * @param Timeout Specifies the TimeOut value to reset the counter.
1611 * This parameter must be a value between 0x0000 and 0xFFFF.
1612 * @retval HAL status
1613 */
HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Timeout)1614 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
1615 {
1616 /* Check the parameters */
1617 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1618 assert_param(IS_LPTIM_PULSE(Timeout));
1619
1620 /* Set the LPTIM state */
1621 hlptim->State = HAL_LPTIM_STATE_BUSY;
1622
1623 /* Set TIMOUT bit to enable the timeout function */
1624 hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
1625
1626 /* Enable the Peripheral */
1627 __HAL_LPTIM_ENABLE(hlptim);
1628
1629 /* Clear flag */
1630 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
1631
1632 /* Load the Timeout value in the compare register */
1633 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
1634
1635 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
1636 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
1637 {
1638 return HAL_TIMEOUT;
1639 }
1640
1641 /* Start timer in continuous mode */
1642 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1643
1644 /* Change the LPTIM state */
1645 hlptim->State = HAL_LPTIM_STATE_READY;
1646
1647 /* Return function status */
1648 return HAL_OK;
1649 }
1650
1651 /**
1652 * @brief Stop the Timeout function.
1653 * @param hlptim LPTIM handle
1654 * @retval HAL status
1655 */
HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef * hlptim)1656 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
1657 {
1658 /* Check the parameters */
1659 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1660
1661 /* Set the LPTIM state */
1662 hlptim->State = HAL_LPTIM_STATE_BUSY;
1663
1664 /* Disable the Peripheral */
1665 __HAL_LPTIM_DISABLE(hlptim);
1666
1667 /* Reset TIMOUT bit to enable the timeout function */
1668 hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
1669
1670 /* Change the LPTIM state */
1671 hlptim->State = HAL_LPTIM_STATE_READY;
1672
1673 /* Return function status */
1674 return HAL_OK;
1675 }
1676
1677 /**
1678 * @brief Start the Timeout function in interrupt mode.
1679 * @note The first trigger event will start the timer, any successive
1680 * trigger event will reset the counter and the timer restarts.
1681 * @param hlptim LPTIM handle
1682 * @param Timeout Specifies the TimeOut value to reset the counter.
1683 * This parameter must be a value between 0x0000 and 0xFFFF.
1684 * @retval HAL status
1685 */
HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Timeout)1686 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
1687 {
1688 /* Check the parameters */
1689 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1690 assert_param(IS_LPTIM_PULSE(Timeout));
1691
1692 /* Set the LPTIM state */
1693 hlptim->State = HAL_LPTIM_STATE_BUSY;
1694
1695 /* Set TIMOUT bit to enable the timeout function */
1696 hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
1697
1698 /* Enable the Peripheral */
1699 __HAL_LPTIM_ENABLE(hlptim);
1700
1701 /* Clear flag */
1702 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1703
1704 /* Enable Compare match CH1 interrupt */
1705 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
1706
1707 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1708 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1709 {
1710 return HAL_TIMEOUT;
1711 }
1712
1713 /* Clear flag */
1714 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
1715
1716 /* Load the Timeout value in the compare register */
1717 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
1718
1719 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
1720 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
1721 {
1722 return HAL_TIMEOUT;
1723 }
1724
1725 /* Start timer in continuous mode */
1726 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1727
1728 /* Change the LPTIM state */
1729 hlptim->State = HAL_LPTIM_STATE_READY;
1730
1731 /* Return function status */
1732 return HAL_OK;
1733 }
1734
1735 /**
1736 * @brief Stop the Timeout function in interrupt mode.
1737 * @param hlptim LPTIM handle
1738 * @retval HAL status
1739 */
HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef * hlptim)1740 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1741 {
1742 /* Check the parameters */
1743 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1744
1745 /* Set the LPTIM state */
1746 hlptim->State = HAL_LPTIM_STATE_BUSY;
1747
1748 /* Disable the Peripheral */
1749 __HAL_LPTIM_DISABLE(hlptim);
1750
1751 /* Reset TIMOUT bit to enable the timeout function */
1752 hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
1753
1754 /* Enable the Peripheral */
1755 __HAL_LPTIM_ENABLE(hlptim);
1756
1757 /* Clear flag */
1758 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1759
1760 /* Disable Compare match CH1 interrupt */
1761 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
1762
1763 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1764 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1765 {
1766 return HAL_TIMEOUT;
1767 }
1768
1769 /* Disable the Peripheral */
1770 __HAL_LPTIM_DISABLE(hlptim);
1771
1772 /* Change the LPTIM state */
1773 hlptim->State = HAL_LPTIM_STATE_READY;
1774
1775 /* Return function status */
1776 return HAL_OK;
1777 }
1778
1779 /**
1780 * @brief Start the Counter mode.
1781 * @param hlptim LPTIM handle
1782 * @retval HAL status
1783 */
HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef * hlptim)1784 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim)
1785 {
1786 /* Check the parameters */
1787 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1788
1789 /* Set the LPTIM state */
1790 hlptim->State = HAL_LPTIM_STATE_BUSY;
1791
1792 /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
1793 if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
1794 && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
1795 {
1796 /* Check if clock is prescaled */
1797 assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
1798 /* Set clock prescaler to 0 */
1799 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
1800 }
1801
1802 /* Enable the Peripheral */
1803 __HAL_LPTIM_ENABLE(hlptim);
1804
1805 /* Start timer in continuous mode */
1806 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1807
1808 /* Change the LPTIM state */
1809 hlptim->State = HAL_LPTIM_STATE_READY;
1810
1811 /* Return function status */
1812 return HAL_OK;
1813 }
1814
1815 /**
1816 * @brief Stop the Counter mode.
1817 * @param hlptim LPTIM handle
1818 * @retval HAL status
1819 */
HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef * hlptim)1820 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
1821 {
1822 /* Check the parameters */
1823 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1824
1825 /* Set the LPTIM state */
1826 hlptim->State = HAL_LPTIM_STATE_BUSY;
1827
1828 /* Disable the Peripheral */
1829 __HAL_LPTIM_DISABLE(hlptim);
1830
1831 /* Change the LPTIM state */
1832 hlptim->State = HAL_LPTIM_STATE_READY;
1833
1834 /* Return function status */
1835 return HAL_OK;
1836 }
1837
1838 /**
1839 * @brief Start the Counter mode in interrupt mode.
1840 * @param hlptim LPTIM handle
1841 * @retval HAL status
1842 */
HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef * hlptim)1843 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim)
1844 {
1845 /* Check the parameters */
1846 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1847
1848 /* Set the LPTIM state */
1849 hlptim->State = HAL_LPTIM_STATE_BUSY;
1850
1851 /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
1852 if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
1853 && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
1854 {
1855 /* Check if clock is prescaled */
1856 assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
1857 /* Set clock prescaler to 0 */
1858 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
1859 }
1860
1861 /* Enable the Peripheral */
1862 __HAL_LPTIM_ENABLE(hlptim);
1863
1864 /* Clear flag */
1865 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1866
1867 /* Enable interrupt */
1868 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
1869
1870 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1871 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1872 {
1873 return HAL_TIMEOUT;
1874 }
1875
1876 /* Start timer in continuous mode */
1877 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1878
1879 /* Change the LPTIM state */
1880 hlptim->State = HAL_LPTIM_STATE_READY;
1881
1882 /* Return function status */
1883 return HAL_OK;
1884 }
1885
1886 /**
1887 * @brief Stop the Counter mode in interrupt mode.
1888 * @param hlptim LPTIM handle
1889 * @retval HAL status
1890 */
HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef * hlptim)1891 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1892 {
1893 /* Check the parameters */
1894 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1895
1896 /* Set the LPTIM state */
1897 hlptim->State = HAL_LPTIM_STATE_BUSY;
1898
1899 /* Disable the Peripheral */
1900 __HAL_LPTIM_DISABLE(hlptim);
1901
1902
1903 /* Enable the Peripheral */
1904 __HAL_LPTIM_ENABLE(hlptim);
1905
1906 /* Clear flag */
1907 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1908
1909 /* Disable interrupt */
1910 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
1911
1912 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1913 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1914 {
1915 return HAL_TIMEOUT;
1916 }
1917
1918 /* Disable the Peripheral */
1919 __HAL_LPTIM_DISABLE(hlptim);
1920
1921 /* Change the LPTIM state */
1922 hlptim->State = HAL_LPTIM_STATE_READY;
1923
1924 /* Return function status */
1925 return HAL_OK;
1926 }
1927
1928 /**
1929 * @brief Starts the LPTIM Input Capture measurement.
1930 * @param hlptim LPTIM Input Capture handle
1931 * @param Channel LPTIM Channels to be enabled
1932 * This parameter can be one of the following values:
1933 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
1934 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
1935 * @retval HAL status
1936 */
HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1937 HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1938 {
1939 /* Check the parameters */
1940 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
1941 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1942
1943 /* Check LPTIM channel state */
1944 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1945 {
1946 return HAL_ERROR;
1947 }
1948
1949 /* Set the LPTIM state */
1950 hlptim->State = HAL_LPTIM_STATE_BUSY;
1951
1952 /* Set the LPTIM channel state */
1953 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1954
1955 /* Enable the Peripheral */
1956 __HAL_LPTIM_ENABLE(hlptim);
1957
1958 /* Start timer in continuous mode */
1959 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1960
1961 /* Enable capture */
1962 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1963
1964 /* Change the LPTIM state */
1965 hlptim->State = HAL_LPTIM_STATE_READY;
1966
1967 /* Return function status */
1968 return HAL_OK;
1969 }
1970
1971 /**
1972 * @brief Stops the LPTIM Input Capture measurement.
1973 * @param hlptim LPTIM Input Capture handle
1974 * @param Channel LPTIM Channels to be disabled
1975 * This parameter can be one of the following values:
1976 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
1977 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
1978 * @retval HAL status
1979 */
HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1980 HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1981 {
1982 /* Check the parameters */
1983 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
1984 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1985
1986 /* Set the LPTIM state */
1987 hlptim->State = HAL_LPTIM_STATE_BUSY;
1988
1989 /* Disable capture */
1990 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1991
1992 /* Disable the Peripheral */
1993 __HAL_LPTIM_DISABLE(hlptim);
1994
1995 /* Set the LPTIM channel state */
1996 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1997
1998 /* Set the LPTIM state */
1999 hlptim->State = HAL_LPTIM_STATE_READY;
2000
2001 /* Return function status */
2002 return HAL_OK;
2003 }
2004
2005 /**
2006 * @brief Starts the LPTIM Input Capture measurement in interrupt mode.
2007 * @param hlptim LPTIM Input Capture handle
2008 * @param Channel LPTIM Channels to be enabled
2009 * This parameter can be one of the following values:
2010 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2011 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2012 * @retval HAL status
2013 */
HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2014 HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2015 {
2016 /* Check the parameters */
2017 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
2018 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2019
2020 /* Check LPTIM channel state */
2021 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
2022 {
2023 return HAL_ERROR;
2024 }
2025
2026 /* Set the LPTIM state */
2027 hlptim->State = HAL_LPTIM_STATE_BUSY;
2028
2029 /* Set the LPTIM channel state */
2030 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
2031
2032 /* Enable the Peripheral */
2033 __HAL_LPTIM_ENABLE(hlptim);
2034
2035 switch (Channel)
2036 {
2037 case LPTIM_CHANNEL_1:
2038 /* Enable Capture/Compare 1 interrupt */
2039 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
2040 break;
2041 case LPTIM_CHANNEL_2:
2042 /* Disable Capture/Compare 2 interrupt */
2043 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC2);
2044 break;
2045 default:
2046 break;
2047 }
2048
2049 /* Wait for the completion of the write operation to the LPTIM_DIER register */
2050 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
2051 {
2052 return HAL_TIMEOUT;
2053 }
2054
2055 /* Start timer in continuous mode */
2056 __HAL_LPTIM_START_CONTINUOUS(hlptim);
2057
2058 /* Enable capture */
2059 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
2060
2061 /* Set the LPTIM state */
2062 hlptim->State = HAL_LPTIM_STATE_READY;
2063
2064 /* Return function status */
2065 return HAL_OK;
2066 }
2067
2068 /**
2069 * @brief Stops the LPTIM Input Capture measurement in interrupt mode.
2070 * @param hlptim LPTIM Input Capture handle
2071 * @param Channel LPTIM Channels to be disabled
2072 * This parameter can be one of the following values:
2073 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2074 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2075 * @retval HAL status
2076 */
HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2077 HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2078 {
2079 /* Check the parameters */
2080 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
2081 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2082
2083 /* Set the LPTIM state */
2084 hlptim->State = HAL_LPTIM_STATE_BUSY;
2085
2086 switch (Channel)
2087 {
2088 case LPTIM_CHANNEL_1:
2089 /* Disable Capture/Compare 1 interrupt */
2090 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
2091 break;
2092 case LPTIM_CHANNEL_2:
2093 /* Disable Capture/Compare 2 interrupt */
2094 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC2);
2095 break;
2096 default:
2097 return HAL_ERROR;
2098 break;
2099 }
2100 /* Disable capture */
2101 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
2102
2103 /* Disable the Peripheral */
2104 __HAL_LPTIM_DISABLE(hlptim);
2105
2106 /* Set the LPTIM channel state */
2107 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
2108
2109 /* Set the LPTIM state */
2110 hlptim->State = HAL_LPTIM_STATE_READY;
2111
2112 /* Return function status */
2113 return HAL_OK;
2114 }
2115
2116 /**
2117 * @brief Starts the LPTIM Input Capture measurement in DMA mode.
2118 * @param hlptim LPTIM Input Capture handle
2119 * @param Channel LPTIM Channels to be enabled
2120 * This parameter can be one of the following values:
2121 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2122 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2123 * @param pData The destination Buffer address
2124 * @param Length The length of data to be transferred from LPTIM peripheral to memory
2125 * @retval HAL status
2126 */
HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel,uint32_t * pData,uint32_t Length)2127 HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData,
2128 uint32_t Length)
2129 {
2130 DMA_HandleTypeDef *hdma;
2131
2132 /* Check the parameters */
2133 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
2134 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2135
2136 if ((pData == NULL) || (Length == 0U))
2137 {
2138 return HAL_ERROR;
2139 }
2140
2141 /* Check LPTIM channel state */
2142 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
2143 {
2144 return HAL_ERROR;
2145 }
2146
2147 /* Set the LPTIM state */
2148 hlptim->State = HAL_LPTIM_STATE_BUSY;
2149
2150 /* Set the LPTIM channel state */
2151 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
2152
2153 /* Enable the Peripheral */
2154 __HAL_LPTIM_ENABLE(hlptim);
2155
2156 switch (Channel)
2157 {
2158 case LPTIM_CHANNEL_1:
2159 /* Set the DMA capture callbacks */
2160 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMACaptureCplt;
2161 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
2162
2163 /* Set the DMA error callback */
2164 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
2165
2166 /* Enable the DMA Channel */
2167 hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
2168 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
2169 {
2170 /* Return error status */
2171 return HAL_ERROR;
2172 }
2173
2174 /* Enable Capture/Compare 1 DMA request */
2175 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC1);
2176 break;
2177
2178 case LPTIM_CHANNEL_2:
2179 /* Set the DMA capture callbacks */
2180 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMACaptureCplt;
2181 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
2182
2183 /* Set the DMA error callback */
2184 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
2185
2186 /* Enable the DMA Channel */
2187 hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
2188 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
2189 {
2190 /* Return error status */
2191 return HAL_ERROR;
2192 }
2193
2194 /* Enable Capture/Compare 2 DMA request */
2195 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC2);
2196 break;
2197
2198 default:
2199 break;
2200 }
2201
2202 /* Wait for the completion of the write operation to the LPTIM_DIER register */
2203 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
2204 {
2205 return HAL_TIMEOUT;
2206 }
2207
2208 /* Start timer in continuous mode */
2209 __HAL_LPTIM_START_CONTINUOUS(hlptim);
2210
2211 /* Enable capture */
2212 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
2213
2214 /* Set the LPTIM state */
2215 hlptim->State = HAL_LPTIM_STATE_READY;
2216
2217 /* Return function status */
2218 return HAL_OK;
2219 }
2220
2221 /**
2222 * @brief Stops the LPTIM Input Capture measurement in DMA mode.
2223 * @param hlptim LPTIM Input Capture handle
2224 * @param Channel LPTIM Channels to be disabled
2225 * This parameter can be one of the following values:
2226 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2227 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2228 * @retval HAL status
2229 */
HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2230 HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2231 {
2232 /* Check the parameters */
2233 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
2234 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2235
2236 /* Set the LPTIM state */
2237 hlptim->State = HAL_LPTIM_STATE_BUSY;
2238
2239 switch (Channel)
2240 {
2241 case LPTIM_CHANNEL_1:
2242 /* Disable Capture/Compare 1 DMA request */
2243 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC1);
2244 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
2245 break;
2246
2247 case LPTIM_CHANNEL_2:
2248 /* Disable Capture/Compare 2 DMA request */
2249 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC2);
2250 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
2251 break;
2252 default:
2253 return HAL_ERROR;
2254 break;
2255 }
2256
2257 /* Disable capture */
2258 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
2259
2260 /* Disable the Peripheral */
2261 __HAL_LPTIM_DISABLE(hlptim);
2262
2263 /* Set the LPTIM channel state */
2264 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
2265
2266 /* Set the LPTIM state */
2267 hlptim->State = HAL_LPTIM_STATE_READY;
2268
2269 /* Return function status */
2270 return HAL_OK;
2271 }
2272 /**
2273 * @}
2274 */
2275
2276 /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
2277 * @brief Read operation functions.
2278 *
2279 @verbatim
2280 ==============================================================================
2281 ##### LPTIM Read operation functions #####
2282 ==============================================================================
2283 [..] This section provides LPTIM Reading functions.
2284 (+) Read the counter value.
2285 (+) Read the period (Auto-reload) value.
2286 (+) Read the pulse (Compare)value.
2287 @endverbatim
2288 * @{
2289 */
2290
2291 /**
2292 * @brief Return the current counter value.
2293 * @param hlptim LPTIM handle
2294 * @retval Counter value.
2295 */
HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef * hlptim)2296 uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim)
2297 {
2298 /* Check the parameters */
2299 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
2300
2301 return (hlptim->Instance->CNT);
2302 }
2303
2304 /**
2305 * @brief Return the current Autoreload (Period) value.
2306 * @param hlptim LPTIM handle
2307 * @retval Autoreload value.
2308 */
HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef * hlptim)2309 uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim)
2310 {
2311 /* Check the parameters */
2312 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
2313
2314 return (hlptim->Instance->ARR);
2315 }
2316
2317 /**
2318 * @brief Return the current Compare (Pulse) value.
2319 * @param hlptim LPTIM handle
2320 * @param Channel LPTIM Channel to be selected
2321 * This parameter can be one of the following values:
2322 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2323 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2324 * @retval Compare value.
2325 */
HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2326 uint32_t HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2327 {
2328 uint32_t tmpccr;
2329
2330 /* Check the parameters */
2331 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2332
2333 switch (Channel)
2334 {
2335 case LPTIM_CHANNEL_1:
2336 tmpccr = hlptim->Instance->CCR1;
2337 break;
2338 case LPTIM_CHANNEL_2:
2339 tmpccr = hlptim->Instance->CCR2;
2340 break;
2341 default:
2342 tmpccr = 0;
2343 break;
2344 }
2345 return tmpccr;
2346 }
2347
2348 /**
2349 * @brief LPTimer Input Capture Get Offset(in counter step unit)
2350 * @note The real capture value corresponding to the input capture trigger can be calculated using
2351 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
2352 * The Offset value is depending on the glitch filter value for the channel
2353 * and the value of the prescaler for the kernel clock.
2354 * Please check Errata Sheet V1_8 for more details under "variable latency
2355 * on input capture channel" section.
2356 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
2357 * the configuration information for LPTIM module.
2358 * @param Channel This parameter can be one of the following values:
2359 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2360 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2361 * @retval The offset value
2362 */
HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2363 uint8_t HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2364 {
2365
2366 uint8_t offset ;
2367 uint32_t prescaler;
2368 uint32_t filter ;
2369
2370 /* Get prescaler value */
2371 prescaler = LL_LPTIM_GetPrescaler(hlptim->Instance);
2372
2373 /* Get filter value */
2374 filter = LL_LPTIM_IC_GetFilter(hlptim->Instance, Channel);
2375
2376 /* Get offset value */
2377 offset = LL_LPTIM_IC_GET_OFFSET(prescaler, filter);
2378
2379 /* return offset value */
2380 return offset;
2381 }
2382
2383 /**
2384 * @}
2385 */
2386 /** @defgroup LPTIM_Exported_Functions_Group5 LPTIM Config function
2387 * @brief Config channel
2388 *
2389 @verbatim
2390 ==============================================================================
2391 ##### LPTIM Config function #####
2392 ==============================================================================
2393 [..] This section provides LPTIM Config function.
2394 (+) Configure channel: Output Compare mode, Period, Polarity.
2395 @endverbatim
2396 * @{
2397 */
2398
2399 /**
2400 * @brief
2401 * @param hlptim LPTIM handle
2402 * @param sConfig The output configuration structure
2403 * @param Channel LPTIM Channel to be configured
2404 * This parameter can be one of the following values:
2405 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2406 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2407 * @note Successive calls to HAL_LPTIM_OC_ConfigChannel can only be performed
2408 * after a delay that must be greater or equal than the value of
2409 * (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal
2410 * division factor (1, 2, 4, ..., 128). Any successive call violating
2411 * this delay, leads to unpredictable results.
2412 * @retval HAL status
2413 */
HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig,uint32_t Channel)2414 HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig,
2415 uint32_t Channel)
2416 {
2417 HAL_StatusTypeDef status;
2418 /* Check the parameters */
2419 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2420 assert_param(IS_LPTIM_OC_POLARITY(sConfig->OCPolarity));
2421 assert_param(IS_LPTIM_PULSE(sConfig->Pulse));
2422
2423 hlptim->State = HAL_LPTIM_STATE_BUSY;
2424
2425 switch (Channel)
2426 {
2427 case LPTIM_CHANNEL_1:
2428 {
2429 /* Check the parameters */
2430 assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
2431
2432 /* Configure the LPTIM Channel 1 in Output Compare */
2433 status = LPTIM_OC1_SetConfig(hlptim, sConfig);
2434 if (status != HAL_OK)
2435 {
2436 return status;
2437 }
2438 break;
2439 }
2440 case LPTIM_CHANNEL_2:
2441 {
2442 /* Check the parameters */
2443 assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
2444
2445 /* Configure the LPTIM Channel 2 in Output Compare */
2446 status = LPTIM_OC2_SetConfig(hlptim, sConfig);
2447 if (status != HAL_OK)
2448 {
2449 return status;
2450 }
2451 break;
2452 }
2453 default:
2454 break;
2455 }
2456
2457 /* Change the LPTIM state */
2458 hlptim->State = HAL_LPTIM_STATE_READY;
2459
2460 /* Return function status */
2461 return HAL_OK;
2462 }
2463
2464 /**
2465 * @brief
2466 * @param hlptim LPTIM handle
2467 * @param sConfig The input configuration structure
2468 * @param Channel LPTIM Channel to be configured
2469 * This parameter can be one of the following values:
2470 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2471 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2472 * @note Successive calls to HAL_LPTIM_IC_ConfigChannel can only be performed
2473 * after a delay that must be greater or equal than the value of
2474 * (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal
2475 * division factor (1, 2, 4, ..., 128). Any successive call violating
2476 * this delay, leads to unpredictable results.
2477 * @retval HAL status
2478 */
HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig,uint32_t Channel)2479 HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig,
2480 uint32_t Channel)
2481 {
2482 /* Check the parameters */
2483 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2484 assert_param(IS_LPTIM_IC_PRESCALER(sConfig->ICPrescaler));
2485 assert_param(IS_LPTIM_IC_POLARITY(sConfig->ICPolarity));
2486 assert_param(IS_LPTIM_IC_FILTER(sConfig->ICFilter));
2487
2488 hlptim->State = HAL_LPTIM_STATE_BUSY;
2489
2490 switch (Channel)
2491 {
2492 case LPTIM_CHANNEL_1:
2493 {
2494 /* Check the parameters */
2495 assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
2496 assert_param(IS_LPTIM_IC1_SOURCE(hlptim->Instance, sConfig->ICInputSource));
2497
2498 /* Configure the LPTIM Channel 1 in Input Capture */
2499 LPTIM_IC1_SetConfig(hlptim, sConfig);
2500 break;
2501 }
2502 case LPTIM_CHANNEL_2:
2503 {
2504 /* Check the parameters */
2505 assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
2506 assert_param(IS_LPTIM_IC2_SOURCE(hlptim->Instance, sConfig->ICInputSource));
2507
2508 /* Configure the LPTIM Channel 2 in Input Capture */
2509 LPTIM_IC2_SetConfig(hlptim, sConfig);
2510 break;
2511 }
2512 default:
2513 break;
2514 }
2515
2516 /* Change the LPTIM state */
2517 hlptim->State = HAL_LPTIM_STATE_READY;
2518 /* Return function status */
2519 return HAL_OK;
2520 }
2521 /**
2522 * @}
2523 */
2524
2525 /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
2526 * @brief LPTIM IRQ handler.
2527 *
2528 @verbatim
2529 ==============================================================================
2530 ##### LPTIM IRQ handler and callbacks #####
2531 ==============================================================================
2532 [..] This section provides LPTIM IRQ handler and callback functions called within
2533 the IRQ handler:
2534 (+) LPTIM interrupt request handler
2535 (+) Compare match Callback
2536 (+) Auto-reload match Callback
2537 (+) External trigger event detection Callback
2538 (+) Compare register write complete Callback
2539 (+) Auto-reload register write complete Callback
2540 (+) Up-counting direction change Callback
2541 (+) Down-counting direction change Callback
2542
2543 @endverbatim
2544 * @{
2545 */
2546
2547 /**
2548 * @brief Handle LPTIM interrupt request.
2549 * @param hlptim LPTIM handle
2550 * @retval None
2551 */
HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef * hlptim)2552 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
2553 {
2554 /* Capture Compare 1 interrupt */
2555 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1) != RESET)
2556 {
2557 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1) != RESET)
2558 {
2559 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1);
2560 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
2561
2562 /* Input capture event */
2563 if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC1SEL) != 0x00U)
2564 {
2565 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2566 hlptim->IC_CaptureCallback(hlptim);
2567 #else
2568 HAL_LPTIM_IC_CaptureCallback(hlptim);
2569 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2570 }
2571 /* Output compare event */
2572 else
2573 {
2574 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2575 hlptim->CompareMatchCallback(hlptim);
2576 #else
2577 HAL_LPTIM_CompareMatchCallback(hlptim);
2578 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2579 }
2580 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2581 }
2582 }
2583
2584 /* Capture Compare 2 interrupt */
2585 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2) != RESET)
2586 {
2587 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2) != RESET)
2588 {
2589 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2);
2590 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
2591
2592 /* Input capture event */
2593 if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC2SEL) != 0x00U)
2594 {
2595 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2596 hlptim->IC_CaptureCallback(hlptim);
2597 #else
2598 HAL_LPTIM_IC_CaptureCallback(hlptim);
2599 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2600 }
2601 /* Output compare event */
2602 else
2603 {
2604 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2605 hlptim->CompareMatchCallback(hlptim);
2606 #else
2607 HAL_LPTIM_CompareMatchCallback(hlptim);
2608 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2609 }
2610 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2611 }
2612 }
2613
2614 /* Over Capture 1 interrupt */
2615 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1O) != RESET)
2616 {
2617 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1O) != RESET)
2618 {
2619 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1O);
2620 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
2621
2622 /* Over capture event */
2623 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2624 hlptim->IC_OverCaptureCallback(hlptim);
2625 #else
2626 HAL_LPTIM_IC_OverCaptureCallback(hlptim);
2627 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2628 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2629 }
2630 }
2631
2632 /* Over Capture 2 interrupt */
2633 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2O) != RESET)
2634 {
2635 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2O) != RESET)
2636 {
2637 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2O);
2638 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
2639
2640 /* Over capture event */
2641 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2642 hlptim->IC_OverCaptureCallback(hlptim);
2643 #else
2644 HAL_LPTIM_IC_OverCaptureCallback(hlptim);
2645 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2646 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2647 }
2648 }
2649
2650 /* Autoreload match interrupt */
2651 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
2652 {
2653 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
2654 {
2655 /* Clear Autoreload match flag */
2656 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
2657
2658 /* Autoreload match Callback */
2659 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2660 hlptim->AutoReloadMatchCallback(hlptim);
2661 #else
2662 HAL_LPTIM_AutoReloadMatchCallback(hlptim);
2663 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2664 }
2665 }
2666
2667 /* Trigger detected interrupt */
2668 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
2669 {
2670 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
2671 {
2672 /* Clear Trigger detected flag */
2673 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
2674
2675 /* Trigger detected callback */
2676 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2677 hlptim->TriggerCallback(hlptim);
2678 #else
2679 HAL_LPTIM_TriggerCallback(hlptim);
2680 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2681 }
2682 }
2683
2684 /* Compare write interrupt */
2685 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP1OK) != RESET)
2686 {
2687 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP1OK) != RESET)
2688 {
2689 /* Clear Compare write flag */
2690 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
2691 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
2692 /* Compare write Callback */
2693 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2694 hlptim->CompareWriteCallback(hlptim);
2695 #else
2696 HAL_LPTIM_CompareWriteCallback(hlptim);
2697 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2698 }
2699 }
2700
2701 /* Compare write interrupt */
2702 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP2OK) != RESET)
2703 {
2704 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP2OK) != RESET)
2705 {
2706 /* Clear Compare write flag */
2707 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
2708 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
2709 /* Compare write Callback */
2710 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2711 hlptim->CompareWriteCallback(hlptim);
2712 #else
2713 HAL_LPTIM_CompareWriteCallback(hlptim);
2714 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2715 }
2716 }
2717
2718 /* Autoreload write interrupt */
2719 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
2720 {
2721 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
2722 {
2723 /* Clear Autoreload write flag */
2724 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
2725
2726 /* Autoreload write Callback */
2727 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2728 hlptim->AutoReloadWriteCallback(hlptim);
2729 #else
2730 HAL_LPTIM_AutoReloadWriteCallback(hlptim);
2731 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2732 }
2733 }
2734
2735 /* Direction counter changed from Down to Up interrupt */
2736 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
2737 {
2738 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
2739 {
2740 /* Clear Direction counter changed from Down to Up flag */
2741 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
2742
2743 /* Direction counter changed from Down to Up Callback */
2744 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2745 hlptim->DirectionUpCallback(hlptim);
2746 #else
2747 HAL_LPTIM_DirectionUpCallback(hlptim);
2748 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2749 }
2750 }
2751
2752 /* Direction counter changed from Up to Down interrupt */
2753 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
2754 {
2755 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
2756 {
2757 /* Clear Direction counter changed from Up to Down flag */
2758 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
2759
2760 /* Direction counter changed from Up to Down Callback */
2761 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2762 hlptim->DirectionDownCallback(hlptim);
2763 #else
2764 HAL_LPTIM_DirectionDownCallback(hlptim);
2765 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2766 }
2767 }
2768
2769 /* Repetition counter underflowed (or contains zero) and the LPTIM counter
2770 overflowed */
2771 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UPDATE) != RESET)
2772 {
2773 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UPDATE) != RESET)
2774 {
2775 /* Clear update event flag */
2776 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UPDATE);
2777
2778 /* Update event Callback */
2779 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2780 hlptim->UpdateEventCallback(hlptim);
2781 #else
2782 HAL_LPTIM_UpdateEventCallback(hlptim);
2783 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2784 }
2785 }
2786
2787 /* Successful APB bus write to repetition counter register */
2788 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPOK) != RESET)
2789 {
2790 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPOK) != RESET)
2791 {
2792 /* Clear successful APB bus write to repetition counter flag */
2793 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
2794
2795 /* Successful APB bus write to repetition counter Callback */
2796 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2797 hlptim->RepCounterWriteCallback(hlptim);
2798 #else
2799 HAL_LPTIM_RepCounterWriteCallback(hlptim);
2800 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2801 }
2802 }
2803 }
2804
2805 /**
2806 * @brief Compare match callback in non-blocking mode.
2807 * @param hlptim LPTIM handle
2808 * @retval None
2809 */
HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef * hlptim)2810 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
2811 {
2812 /* Prevent unused argument(s) compilation warning */
2813 UNUSED(hlptim);
2814
2815 /* NOTE : This function should not be modified, when the callback is needed,
2816 the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
2817 */
2818 }
2819
2820 /**
2821 * @brief Autoreload match callback in non-blocking mode.
2822 * @param hlptim LPTIM handle
2823 * @retval None
2824 */
HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef * hlptim)2825 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
2826 {
2827 /* Prevent unused argument(s) compilation warning */
2828 UNUSED(hlptim);
2829
2830 /* NOTE : This function should not be modified, when the callback is needed,
2831 the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
2832 */
2833 }
2834
2835 /**
2836 * @brief Trigger detected callback in non-blocking mode.
2837 * @param hlptim LPTIM handle
2838 * @retval None
2839 */
HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef * hlptim)2840 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
2841 {
2842 /* Prevent unused argument(s) compilation warning */
2843 UNUSED(hlptim);
2844
2845 /* NOTE : This function should not be modified, when the callback is needed,
2846 the HAL_LPTIM_TriggerCallback could be implemented in the user file
2847 */
2848 }
2849
2850 /**
2851 * @brief Compare write callback in non-blocking mode.
2852 * @param hlptim LPTIM handle
2853 * @retval None
2854 */
HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef * hlptim)2855 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
2856 {
2857 /* Prevent unused argument(s) compilation warning */
2858 UNUSED(hlptim);
2859
2860 /* NOTE : This function should not be modified, when the callback is needed,
2861 the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
2862 */
2863 }
2864
2865 /**
2866 * @brief Autoreload write callback in non-blocking mode.
2867 * @param hlptim LPTIM handle
2868 * @retval None
2869 */
HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef * hlptim)2870 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
2871 {
2872 /* Prevent unused argument(s) compilation warning */
2873 UNUSED(hlptim);
2874
2875 /* NOTE : This function should not be modified, when the callback is needed,
2876 the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
2877 */
2878 }
2879
2880 /**
2881 * @brief Direction counter changed from Down to Up callback in non-blocking mode.
2882 * @param hlptim LPTIM handle
2883 * @retval None
2884 */
HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef * hlptim)2885 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
2886 {
2887 /* Prevent unused argument(s) compilation warning */
2888 UNUSED(hlptim);
2889
2890 /* NOTE : This function should not be modified, when the callback is needed,
2891 the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
2892 */
2893 }
2894
2895 /**
2896 * @brief Direction counter changed from Up to Down callback in non-blocking mode.
2897 * @param hlptim LPTIM handle
2898 * @retval None
2899 */
HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef * hlptim)2900 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
2901 {
2902 /* Prevent unused argument(s) compilation warning */
2903 UNUSED(hlptim);
2904
2905 /* NOTE : This function should not be modified, when the callback is needed,
2906 the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
2907 */
2908 }
2909
2910 /**
2911 * @brief Repetition counter underflowed (or contains zero) and LPTIM counter overflowed callback in non-blocking mode.
2912 * @param hlptim LPTIM handle
2913 * @retval None
2914 */
HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef * hlptim)2915 __weak void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim)
2916 {
2917 /* Prevent unused argument(s) compilation warning */
2918 UNUSED(hlptim);
2919
2920 /* NOTE : This function should not be modified, when the callback is needed,
2921 the HAL_LPTIM_UpdateEventCallback could be implemented in the user file
2922 */
2923 }
2924
2925 /**
2926 * @brief Successful APB bus write to repetition counter register callback in non-blocking mode.
2927 * @param hlptim LPTIM handle
2928 * @retval None
2929 */
HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef * hlptim)2930 __weak void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim)
2931 {
2932 /* Prevent unused argument(s) compilation warning */
2933 UNUSED(hlptim);
2934
2935 /* NOTE : This function should not be modified, when the callback is needed,
2936 the HAL_LPTIM_RepCounterWriteCallback could be implemented in the user file
2937 */
2938 }
2939
2940 /**
2941 * @brief Input Capture callback in non-blocking mode
2942 * @param hlptim LPTIM handle
2943 * @retval None
2944 */
HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef * hlptim)2945 __weak void HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef *hlptim)
2946 {
2947 /* Prevent unused argument(s) compilation warning */
2948 UNUSED(hlptim);
2949
2950 /* NOTE : This function should not be modified, when the callback is needed,
2951 the HAL_LPTIM_IC_CaptureCallback could be implemented in the user file
2952 */
2953 }
2954
2955 /**
2956 * @brief Over Capture callback in non-blocking mode
2957 * @param hlptim LPTIM handle
2958 * @retval None
2959 */
HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef * hlptim)2960 __weak void HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef *hlptim)
2961 {
2962 /* Prevent unused argument(s) compilation warning */
2963 UNUSED(hlptim);
2964
2965 /* NOTE : This function should not be modified, when the callback is needed,
2966 the HAL_LPTIM_IC_OverCaptureCallback could be implemented in the user file
2967 */
2968 }
2969
2970 /**
2971 * @brief Input Capture half complete callback in non-blocking mode
2972 * @param hlptim LPTIM IC handle
2973 * @retval None
2974 */
HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef * hlptim)2975 __weak void HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
2976 {
2977 /* Prevent unused argument(s) compilation warning */
2978 UNUSED(hlptim);
2979
2980 /* NOTE : This function should not be modified, when the callback is needed,
2981 the HAL_LPTIM_IC_CaptureHalfCpltCallback could be implemented in the user file
2982 */
2983 }
2984
2985 /**
2986 * @brief Update event half complete callback in non-blocking mode
2987 * @param hlptim LPTIM handle
2988 * @retval None
2989 */
HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef * hlptim)2990 __weak void HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
2991 {
2992 /* Prevent unused argument(s) compilation warning */
2993 UNUSED(hlptim);
2994
2995 /* NOTE : This function should not be modified, when the callback is needed,
2996 the HAL_LPTIM_UpdateEventHalfCpltCallback could be implemented in the user file
2997 */
2998 }
2999
3000 /**
3001 * @brief Error callback in non-blocking mode
3002 * @param hlptim LPTIM handle
3003 * @retval None
3004 */
HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef * hlptim)3005 __weak void HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef *hlptim)
3006 {
3007 /* Prevent unused argument(s) compilation warning */
3008 UNUSED(hlptim);
3009
3010 /* NOTE : This function should not be modified, when the callback is needed,
3011 the HAL_LPTIM_ErrorCallback could be implemented in the user file
3012 */
3013 }
3014
3015
3016 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3017 /**
3018 * @brief Register a User LPTIM callback to be used instead of the weak predefined callback
3019 * @param hlptim LPTIM handle
3020 * @param CallbackID ID of the callback to be registered
3021 * This parameter can be one of the following values:
3022 * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
3023 * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
3024 * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
3025 * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
3026 * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
3027 * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
3028 * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
3029 * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
3030 * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
3031 * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID
3032 * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
3033 * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID
3034 * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID
3035 * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID
3036 * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
3037 * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID
3038 * @param pCallback pointer to the callback function
3039 * @retval status
3040 */
HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef * hlptim,HAL_LPTIM_CallbackIDTypeDef CallbackID,pLPTIM_CallbackTypeDef pCallback)3041 HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim,
3042 HAL_LPTIM_CallbackIDTypeDef CallbackID,
3043 pLPTIM_CallbackTypeDef pCallback)
3044 {
3045 HAL_StatusTypeDef status = HAL_OK;
3046
3047 if (pCallback == NULL)
3048 {
3049 return HAL_ERROR;
3050 }
3051
3052 if (hlptim->State == HAL_LPTIM_STATE_READY)
3053 {
3054 switch (CallbackID)
3055 {
3056 case HAL_LPTIM_MSPINIT_CB_ID :
3057 hlptim->MspInitCallback = pCallback;
3058 break;
3059
3060 case HAL_LPTIM_MSPDEINIT_CB_ID :
3061 hlptim->MspDeInitCallback = pCallback;
3062 break;
3063
3064 case HAL_LPTIM_COMPARE_MATCH_CB_ID :
3065 hlptim->CompareMatchCallback = pCallback;
3066 break;
3067
3068 case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
3069 hlptim->AutoReloadMatchCallback = pCallback;
3070 break;
3071
3072 case HAL_LPTIM_TRIGGER_CB_ID :
3073 hlptim->TriggerCallback = pCallback;
3074 break;
3075
3076 case HAL_LPTIM_COMPARE_WRITE_CB_ID :
3077 hlptim->CompareWriteCallback = pCallback;
3078 break;
3079
3080 case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
3081 hlptim->AutoReloadWriteCallback = pCallback;
3082 break;
3083
3084 case HAL_LPTIM_DIRECTION_UP_CB_ID :
3085 hlptim->DirectionUpCallback = pCallback;
3086 break;
3087
3088 case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
3089 hlptim->DirectionDownCallback = pCallback;
3090 break;
3091
3092 case HAL_LPTIM_UPDATE_EVENT_CB_ID :
3093 hlptim->UpdateEventCallback = pCallback;
3094 break;
3095
3096 case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
3097 hlptim->RepCounterWriteCallback = pCallback;
3098 break;
3099
3100 case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
3101 hlptim->UpdateEventHalfCpltCallback = pCallback;
3102 break;
3103
3104 case HAL_LPTIM_ERROR_CB_ID :
3105 hlptim->ErrorCallback = pCallback;
3106 break;
3107
3108 case HAL_LPTIM_IC_CAPTURE_CB_ID :
3109 hlptim->IC_CaptureCallback = pCallback;
3110 break;
3111
3112 case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
3113 hlptim->IC_CaptureHalfCpltCallback = pCallback;
3114 break;
3115
3116 case HAL_LPTIM_OVER_CAPTURE_CB_ID :
3117 hlptim->IC_OverCaptureCallback = pCallback;
3118 break;
3119
3120 default :
3121 /* Return error status */
3122 status = HAL_ERROR;
3123 break;
3124 }
3125 }
3126 else if (hlptim->State == HAL_LPTIM_STATE_RESET)
3127 {
3128 switch (CallbackID)
3129 {
3130 case HAL_LPTIM_MSPINIT_CB_ID :
3131 hlptim->MspInitCallback = pCallback;
3132 break;
3133
3134 case HAL_LPTIM_MSPDEINIT_CB_ID :
3135 hlptim->MspDeInitCallback = pCallback;
3136 break;
3137
3138 default :
3139 /* Return error status */
3140 status = HAL_ERROR;
3141 break;
3142 }
3143 }
3144 else
3145 {
3146 /* Return error status */
3147 status = HAL_ERROR;
3148 }
3149
3150 return status;
3151 }
3152
3153 /**
3154 * @brief Unregister a LPTIM callback
3155 * LLPTIM callback is redirected to the weak predefined callback
3156 * @param hlptim LPTIM handle
3157 * @param CallbackID ID of the callback to be unregistered
3158 * This parameter can be one of the following values:
3159 * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
3160 * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
3161 * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
3162 * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
3163 * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
3164 * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
3165 * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
3166 * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
3167 * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
3168 * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID
3169 * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
3170 * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID
3171 * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID
3172 * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID
3173 * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
3174 * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID
3175 * @retval status
3176 */
HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef * hlptim,HAL_LPTIM_CallbackIDTypeDef CallbackID)3177 HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim,
3178 HAL_LPTIM_CallbackIDTypeDef CallbackID)
3179 {
3180 HAL_StatusTypeDef status = HAL_OK;
3181
3182 if (hlptim->State == HAL_LPTIM_STATE_READY)
3183 {
3184 switch (CallbackID)
3185 {
3186 case HAL_LPTIM_MSPINIT_CB_ID :
3187 /* Legacy weak MspInit Callback */
3188 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
3189 break;
3190
3191 case HAL_LPTIM_MSPDEINIT_CB_ID :
3192 /* Legacy weak Msp DeInit Callback */
3193 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
3194 break;
3195
3196 case HAL_LPTIM_COMPARE_MATCH_CB_ID :
3197 /* Legacy weak Compare match Callback */
3198 hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
3199 break;
3200
3201 case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
3202 /* Legacy weak Auto-reload match Callback */
3203 hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
3204 break;
3205
3206 case HAL_LPTIM_TRIGGER_CB_ID :
3207 /* Legacy weak External trigger event detection Callback */
3208 hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
3209 break;
3210
3211 case HAL_LPTIM_COMPARE_WRITE_CB_ID :
3212 /* Legacy weak Compare register write complete Callback */
3213 hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
3214 break;
3215
3216 case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
3217 /* Legacy weak Auto-reload register write complete Callback */
3218 hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
3219 break;
3220
3221 case HAL_LPTIM_DIRECTION_UP_CB_ID :
3222 /* Legacy weak Up-counting direction change Callback */
3223 hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
3224 break;
3225
3226 case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
3227 /* Legacy weak Down-counting direction change Callback */
3228 hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
3229 break;
3230
3231 case HAL_LPTIM_UPDATE_EVENT_CB_ID :
3232 /* Legacy weak Update event detection Callback */
3233 hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
3234 break;
3235
3236 case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
3237 /* Legacy weak Repetition counter register write complete Callback */
3238 hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
3239 break;
3240
3241 case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
3242 /* Legacy weak Update event half complete detection Callback */
3243 hlptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
3244 break;
3245
3246 case HAL_LPTIM_ERROR_CB_ID :
3247 /* Legacy weak error Callback */
3248 hlptim->ErrorCallback = HAL_LPTIM_ErrorCallback;
3249 break;
3250
3251 case HAL_LPTIM_IC_CAPTURE_CB_ID :
3252 /* Legacy weak IC Capture Callback */
3253 hlptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback;
3254 break;
3255
3256 case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
3257 /* Legacy weak IC Capture half complete Callback */
3258 hlptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
3259 break;
3260
3261 case HAL_LPTIM_OVER_CAPTURE_CB_ID :
3262 /* Legacy weak IC over capture Callback */
3263 hlptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback;
3264 break;
3265
3266 default :
3267 /* Return error status */
3268 status = HAL_ERROR;
3269 break;
3270 }
3271 }
3272 else if (hlptim->State == HAL_LPTIM_STATE_RESET)
3273 {
3274 switch (CallbackID)
3275 {
3276 case HAL_LPTIM_MSPINIT_CB_ID :
3277 /* Legacy weak MspInit Callback */
3278 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
3279 break;
3280
3281 case HAL_LPTIM_MSPDEINIT_CB_ID :
3282 /* Legacy weak Msp DeInit Callback */
3283 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
3284 break;
3285
3286 default :
3287 /* Return error status */
3288 status = HAL_ERROR;
3289 break;
3290 }
3291 }
3292 else
3293 {
3294 /* Return error status */
3295 status = HAL_ERROR;
3296 }
3297
3298 return status;
3299 }
3300 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3301
3302 /**
3303 * @}
3304 */
3305
3306 /** @defgroup LPTIM_Group5 Peripheral State functions
3307 * @brief Peripheral State functions.
3308 *
3309 @verbatim
3310 ==============================================================================
3311 ##### Peripheral State functions #####
3312 ==============================================================================
3313 [..]
3314 This subsection permits to get in run-time the status of the peripheral.
3315
3316 @endverbatim
3317 * @{
3318 */
3319
3320 /**
3321 * @brief Return the LPTIM handle state.
3322 * @param hlptim LPTIM handle
3323 * @retval HAL state
3324 */
HAL_LPTIM_GetState(const LPTIM_HandleTypeDef * hlptim)3325 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim)
3326 {
3327 /* Return LPTIM handle state */
3328 return hlptim->State;
3329 }
3330
3331 /**
3332 * @}
3333 */
3334
3335
3336 /**
3337 * @}
3338 */
3339
3340 /* Private functions ---------------------------------------------------------*/
3341
3342 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
3343 * @{
3344 */
3345 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3346 /**
3347 * @brief Reset interrupt callbacks to the legacy weak callbacks.
3348 * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains
3349 * the configuration information for LPTIM module.
3350 * @retval None
3351 */
LPTIM_ResetCallback(LPTIM_HandleTypeDef * lptim)3352 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
3353 {
3354 /* Reset the LPTIM callback to the legacy weak callbacks */
3355 lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
3356 lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
3357 lptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
3358 lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
3359 lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
3360 lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
3361 lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
3362 lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
3363 lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
3364 lptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
3365 lptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback;
3366 lptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
3367 lptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback;
3368 lptim->ErrorCallback = HAL_LPTIM_ErrorCallback;
3369 }
3370 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3371
3372 /**
3373 * @brief LPTimer Wait for flag set
3374 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3375 * the configuration information for LPTIM module.
3376 * @param flag The lptim flag
3377 * @retval HAL status
3378 */
LPTIM_WaitForFlag(const LPTIM_HandleTypeDef * hlptim,uint32_t flag)3379 static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag)
3380 {
3381 HAL_StatusTypeDef result = HAL_OK;
3382 uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
3383 do
3384 {
3385 count--;
3386 if (count == 0UL)
3387 {
3388 result = HAL_TIMEOUT;
3389 }
3390 } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
3391
3392 return result;
3393 }
3394
3395 /**
3396 * @brief LPTIM DMA error callback
3397 * @param hdma pointer to DMA handle.
3398 * @retval None
3399 */
LPTIM_DMAError(DMA_HandleTypeDef * hdma)3400 void LPTIM_DMAError(DMA_HandleTypeDef *hdma)
3401 {
3402 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3403
3404 hlptim->State = HAL_LPTIM_STATE_READY;
3405
3406 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3407 hlptim->ErrorCallback(hlptim);
3408 #else
3409 HAL_LPTIM_ErrorCallback(hlptim);
3410 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3411 }
3412
3413 /**
3414 * @brief LPTIM DMA Capture complete callback.
3415 * @param hdma pointer to DMA handle.
3416 * @retval None
3417 */
LPTIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)3418 void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
3419 {
3420 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3421
3422 hlptim->State = HAL_LPTIM_STATE_READY;
3423
3424 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3425 {
3426 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3427 }
3428 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3429 {
3430 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3431 }
3432 else
3433 {
3434 /* nothing to do */
3435 }
3436
3437 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3438 hlptim->IC_CaptureCallback(hlptim);
3439 #else
3440 HAL_LPTIM_IC_CaptureCallback(hlptim);
3441 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3442
3443 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3444 }
3445
3446 /**
3447 * @brief LPTIM DMA Capture half complete callback.
3448 * @param hdma pointer to DMA handle.
3449 * @retval None
3450 */
LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)3451 void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
3452 {
3453 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3454
3455 hlptim->State = HAL_LPTIM_STATE_READY;
3456
3457 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3458 {
3459 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3460 }
3461 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3462 {
3463 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3464 }
3465 else
3466 {
3467 /* nothing to do */
3468 }
3469
3470 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3471 hlptim->IC_CaptureHalfCpltCallback(hlptim);
3472 #else
3473 HAL_LPTIM_IC_CaptureHalfCpltCallback(hlptim);
3474 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3475
3476 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3477 }
3478
3479 /**
3480 * @brief LPTIM DMA Update event complete callback.
3481 * @param hdma pointer to DMA handle.
3482 * @retval None
3483 */
LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef * hdma)3484 void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma)
3485 {
3486 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3487
3488 hlptim->State = HAL_LPTIM_STATE_READY;
3489
3490 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3491 {
3492 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3493 }
3494 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3495 {
3496 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3497 }
3498 else
3499 {
3500 /* nothing to do */
3501 }
3502
3503 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3504 hlptim->UpdateEventCallback(hlptim);
3505 #else
3506 HAL_LPTIM_UpdateEventCallback(hlptim);
3507 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3508
3509 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3510 }
3511
3512 /**
3513 * @brief LPTIM DMA Capture half complete callback.
3514 * @param hdma pointer to DMA handle.
3515 * @retval None
3516 */
LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef * hdma)3517 void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma)
3518 {
3519 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3520
3521 hlptim->State = HAL_LPTIM_STATE_READY;
3522
3523 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3524 {
3525 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3526 }
3527 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3528 {
3529 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3530 }
3531 else
3532 {
3533 /* nothing to do */
3534 }
3535
3536 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3537 hlptim->UpdateEventHalfCpltCallback(hlptim);
3538 #else
3539 HAL_LPTIM_UpdateEventHalfCpltCallback(hlptim);
3540 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3541
3542 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3543 }
3544 /**
3545 * @brief LPTimer Output Compare 1 configuration
3546 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3547 * the configuration information for LPTIM module.
3548 * @param sConfig The output configuration structure
3549 * @retval None
3550 */
LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig)3551 static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig)
3552 {
3553 uint32_t tmpccmr1;
3554 uint32_t tmpcfgr;
3555
3556 tmpccmr1 = hlptim->Instance->CCMR1;
3557 tmpccmr1 &= ~(LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_CC1SEL_Msk);
3558
3559 if (hlptim->Instance == LPTIM4)
3560 {
3561 tmpcfgr = hlptim->Instance->CFGR;
3562 tmpcfgr &= ~LPTIM_CFGR_WAVPOL_Msk;
3563 tmpcfgr |= sConfig->OCPolarity << LPTIM_CFGR_WAVPOL_Pos;
3564
3565 /* Write to CFGR register */
3566 hlptim->Instance->CFGR = tmpcfgr;
3567 }
3568 else
3569 {
3570 tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC1P_Pos;
3571 }
3572
3573 /* Enable the Peripheral */
3574 __HAL_LPTIM_ENABLE(hlptim);
3575
3576 /* Clear flag */
3577 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
3578
3579 /* Write to CCR1 register */
3580 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, sConfig->Pulse);
3581
3582 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
3583 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
3584 {
3585 return HAL_TIMEOUT;
3586 }
3587
3588 /* Disable the Peripheral */
3589 __HAL_LPTIM_DISABLE(hlptim);
3590
3591 /* Write to CCMR1 register */
3592 hlptim->Instance->CCMR1 = tmpccmr1;
3593
3594 return HAL_OK;
3595 }
3596
3597 /**
3598 * @brief LPTimer Output Compare 2 configuration
3599 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3600 * the configuration information for LPTIM module.
3601 * @param sConfig The output configuration structure
3602 * @retval None
3603 */
LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig)3604 static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig)
3605 {
3606 uint32_t tmpccmr1;
3607
3608 tmpccmr1 = hlptim->Instance->CCMR1;
3609 tmpccmr1 &= ~(LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_CC2SEL_Msk);
3610 tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC2P_Pos;
3611
3612 /* Enable the Peripheral */
3613 __HAL_LPTIM_ENABLE(hlptim);
3614
3615 /* Clear flag */
3616 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
3617
3618 /* Write to CCR2 register */
3619 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, sConfig->Pulse);
3620
3621 /* Wait for the completion of the write operation to the LPTIM_CCR2 register */
3622 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) != HAL_OK)
3623 {
3624 return HAL_TIMEOUT;
3625 }
3626
3627 /* Disable the Peripheral */
3628 __HAL_LPTIM_DISABLE(hlptim);
3629
3630 /* Write to CCMR1 register */
3631 hlptim->Instance->CCMR1 = tmpccmr1;
3632
3633 return HAL_OK;
3634 }
3635
3636 /**
3637 * @brief LPTimer Input Capture 1 configuration
3638 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3639 * the configuration information for LPTIM module.
3640 * @param sConfig The input configuration structure
3641 * @retval None
3642 */
LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig)3643 static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig)
3644 {
3645 uint32_t tmpccmr1;
3646 uint32_t tmpcfgr2;
3647
3648 tmpccmr1 = hlptim->Instance->CCMR1;
3649 tmpccmr1 &= ~(LPTIM_CCMR1_IC1PSC_Msk | LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_IC1F_Msk);
3650 tmpccmr1 |= sConfig->ICPrescaler |
3651 sConfig->ICPolarity |
3652 sConfig->ICFilter |
3653 LPTIM_CCMR1_CC1SEL;
3654
3655 tmpcfgr2 = hlptim->Instance->CFGR2;
3656 tmpcfgr2 &= ~(LPTIM_CFGR2_IC1SEL_Msk);
3657 tmpcfgr2 |= sConfig->ICInputSource;
3658
3659 /* Write to CCMR1 register */
3660 hlptim->Instance->CCMR1 = tmpccmr1;
3661
3662 /* Write to CFGR2 register */
3663 hlptim->Instance->CFGR2 = tmpcfgr2;
3664 }
3665
3666 /**
3667 * @brief LPTimer Input Capture 2 configuration
3668 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3669 * the configuration information for LPTIM module.
3670 * @param sConfig The input configuration structure
3671 * @retval None
3672 */
LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig)3673 static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig)
3674 {
3675 uint32_t tmpccmr1;
3676 uint32_t tmpcfgr2;
3677
3678 tmpccmr1 = hlptim->Instance->CCMR1;
3679 tmpccmr1 &= ~(LPTIM_CCMR1_IC2PSC_Msk | LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_IC2F_Msk);
3680 tmpccmr1 |= (sConfig->ICPrescaler << (LPTIM_CCMR1_IC2PSC_Pos - LPTIM_CCMR1_IC1PSC_Pos)) |
3681 (sConfig->ICPolarity << (LPTIM_CCMR1_CC2P_Pos - LPTIM_CCMR1_CC1P_Pos)) |
3682 (sConfig->ICFilter << (LPTIM_CCMR1_IC2F_Pos - LPTIM_CCMR1_IC1F_Pos)) |
3683 LPTIM_CCMR1_CC2SEL;
3684
3685 tmpcfgr2 = hlptim->Instance->CFGR2;
3686 tmpcfgr2 &= ~(LPTIM_CFGR2_IC2SEL_Msk);
3687 tmpcfgr2 |= sConfig->ICInputSource;
3688
3689 /* Write to CCMR1 register */
3690 hlptim->Instance->CCMR1 = tmpccmr1;
3691
3692 /* Write to CFGR2 register */
3693 hlptim->Instance->CFGR2 = tmpcfgr2;
3694 }
3695
3696 /**
3697 * @brief Start the DMA data transfer.
3698 * @param hdma DMA handle
3699 * @param src The source memory Buffer address.
3700 * @param dst The destination memory Buffer address.
3701 * @param length The size of a source block transfer in byte.
3702 * @retval HAL status
3703 */
LPTIM_DMA_Start_IT(DMA_HandleTypeDef * hdma,uint32_t src,uint32_t dst,uint32_t length)3704 HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
3705 uint32_t length)
3706 {
3707 HAL_StatusTypeDef status;
3708
3709 /* Enable the DMA channel */
3710 if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3711 {
3712 if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U))
3713 {
3714 /* Enable the DMA channel */
3715 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length;
3716 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)src;
3717 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)dst;
3718
3719 status = HAL_DMAEx_List_Start_IT(hdma);
3720 }
3721 else
3722 {
3723 status = HAL_ERROR;
3724 }
3725 }
3726 else
3727 {
3728 status = HAL_DMA_Start_IT(hdma, src, dst, length);
3729 }
3730
3731 return status;
3732 }
3733 /**
3734 * @}
3735 */
3736 #endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 */
3737
3738 #endif /* HAL_LPTIM_MODULE_ENABLED */
3739 /**
3740 * @}
3741 */
3742
3743 /**
3744 * @}
3745 */
3746
