1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_flash_ex.c
4 * @author MCD Application Team
5 * @brief Extended FLASH HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the FLASH extended peripheral:
8 * + Extended programming operations functions
9 *
10 ******************************************************************************
11 * @attention
12 *
13 * Copyright (c) 2021 STMicroelectronics.
14 * All rights reserved.
15 *
16 * This software is licensed under terms that can be found in the LICENSE file
17 * in the root directory of this software component.
18 * If no LICENSE file comes with this software, it is provided AS-IS.
19 *
20 ******************************************************************************
21 @verbatim
22 ==============================================================================
23 ##### Flash Extended features #####
24 ==============================================================================
25
26 [..] Comparing to other previous devices, the FLASH interface for STM32U5xx
27 devices contains the following additional features
28
29 (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
30 capability (RWW)
31 (+) Dual bank memory organization
32 (+) Watermark-based secure area including the secure hide areas
33 (+) Block-based secure pages
34
35 ##### How to use this driver #####
36 ==============================================================================
37 [..] This driver provides functions to configure and program the FLASH memory
38 of all STM32U5xx devices. It includes:
39 (#) Flash Memory Erase functions:
40 (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
41 HAL_FLASH_Lock() functions
42 (++) Erase function: page Erase and Bank/Mass Erase
43 (++) There are two modes of erase :
44 (+++) Polling Mode using HAL_FLASHEx_Erase()
45 (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
46
47 (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to:
48 (++) Configure the write protection for each area
49 (++) Set the Read protection Level
50 (++) Program the user Option Bytes
51 (++) Configure the watermark security for each area including the secure hide areas
52 (++) Configure the boot lock (BOOT_LOCK)
53 (++) Configure the Boot addresses
54
55 (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to:
56 (++) Get the value of a write protection area
57 (++) Know if the read protection is activated
58 (++) Get the value of the user Option Bytes
59 (++) Get the configuration of a watermark security area including the secure hide areas
60 (++) Get the boot lock (BOOT_LOCK) configuration
61 (++) Get the value of a boot address
62
63 (#) Block-based secure / privilege area configuration function: Use HAL_FLASHEx_ConfigBBAttributes()
64 (++) Bit-field allowing to secure or un-secure each page
65 (++) Bit-field allowing to privilege or un-privilege each page
66
67 (#) Get the block-based secure / privilege area configuration function: Use HAL_FLASHEx_GetBBSec()
68 (++) Return the configuration of the block-based security and privilege for all the pages
69
70 (#) Activation of the secure hide area function: Use HAL_FLASHEx_EnableSecHideProtection()
71 (++) Deny the access to the secure hide area
72
73 (#) Privilege mode configuration function: Use HAL_FLASHEx_ConfigPrivMode()
74 (++) FLASH register can be protected against non-privilege accesses
75
76 (#) Get the privilege mode configuration function: Use HAL_FLASHEx_GetPrivMode()
77 (++) Return if the FLASH registers are protected against non-privilege accesses
78
79 (#) Security inversion configuration function: Use HAL_FLASHEx_ConfigSecInversion()
80 (++) FLASH secure state can be override
81
82 (#) Get the security inversion configuration function: Use HAL_FLASHEx_GetSecInversion()
83 (++) Return if FLASH secure state is override
84
85 (#) Enable bank low-power mode function: Use HAL_FLASHEx_EnablePowerDown()
86 (++) Enable low-power mode for Flash Bank 1 and/or Bank 2
87
88 (#) Enable low-power read mode function: Use HAL_FLASHEx_ConfigLowPowerRead()
89 (++) Enable low-power read mode for Flash memory
90
91 (#) Get the low-power read mode configuration function: Use HAL_FLASHEx_GetLowPowerRead()
92 (++) Return if FLASH is in low-power read mode or normal read mode
93
94 (#) Get Flash operation function: Use HAL_FLASHEx_GetOperation()
95 (++) Return information about the on-going Flash operation. After a
96 system reset, return information about the interrupted Flash operation, if any.
97
98 @endverbatim
99 ******************************************************************************
100 */
101
102 /* Includes ------------------------------------------------------------------*/
103 #include "stm32u5xx_hal.h"
104
105 /** @addtogroup STM32U5xx_HAL_Driver
106 * @{
107 */
108
109 /** @defgroup FLASHEx FLASHEx
110 * @brief FLASH Extended HAL module driver
111 * @{
112 */
113
114 #ifdef HAL_FLASH_MODULE_ENABLED
115
116 /* Private typedef -----------------------------------------------------------*/
117 /* Private define ------------------------------------------------------------*/
118 /* Private macro -------------------------------------------------------------*/
119 /* Private variables ---------------------------------------------------------*/
120 /* Private function prototypes -----------------------------------------------*/
121 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
122 * @{
123 */
124 static void FLASH_MassErase(uint32_t Banks);
125 static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset,
126 FunctionalState WRPLock);
127 static void FLASH_OB_RDPConfig(uint32_t RDPLevel);
128 static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
129 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
130 static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage,
131 uint32_t WMHDPEndPage);
132 static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig);
133 #endif /* __ARM_FEATURE_CMSE */
134 static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr);
135 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRPEndOffset,
136 FunctionalState *WRPLock);
137 static uint32_t FLASH_OB_GetRDP(void);
138 static uint32_t FLASH_OB_GetUser(void);
139 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
140 static void FLASH_OB_GetWMSEC(uint32_t *WMSecConfig, uint32_t *WMSecStartPage, uint32_t *WMSecEndPage,
141 uint32_t *WMHDPEndPage);
142 static uint32_t FLASH_OB_GetBootLock(void);
143 #endif /* __ARM_FEATURE_CMSE */
144 static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t *BootAddr);
145 static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_t RDPKey2);
146 /**
147 * @}
148 */
149
150 /* Exported functions -------------------------------------------------------*/
151 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
152 * @{
153 */
154
155 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
156 * @brief Extended IO operation functions
157 *
158 @verbatim
159 ===============================================================================
160 ##### Extended programming operation functions #####
161 ===============================================================================
162 [..]
163 This subsection provides a set of functions allowing to manage the Extended FLASH
164 programming operations Operations.
165
166 @endverbatim
167 * @{
168 */
169 /**
170 * @brief Perform a mass erase or erase the specified FLASH memory pages.
171 * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
172 * contains the configuration information for the erasing.
173 *
174 * @param[out] PageError pointer to variable that contains the configuration
175 * information on faulty page in case of error (0xFFFFFFFF means that all
176 * the pages have been correctly erased).
177 *
178 * @retval HAL Status
179 */
HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef * pEraseInit,uint32_t * PageError)180 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
181 {
182 HAL_StatusTypeDef status;
183 uint32_t page_index;
184 __IO uint32_t *reg_cr;
185
186 /* Check the parameters */
187 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
188
189 /* Process Locked */
190 __HAL_LOCK(&pFlash);
191
192 /* Reset error code */
193 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
194
195 /* Wait for last operation to be completed */
196 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
197
198 if (status == HAL_OK)
199 {
200 /* Current operation type */
201 pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
202
203 /* Access to SECCR or NSCR depends on operation type */
204 reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH->NSCR);
205
206 if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE)
207 {
208 /* Mass erase to be done */
209 FLASH_MassErase(pEraseInit->Banks);
210
211 /* Wait for last operation to be completed */
212 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
213 }
214 else
215 {
216 /*Initialization of PageError variable*/
217 *PageError = 0xFFFFFFFFU;
218
219 for (page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
220 {
221 FLASH_PageErase(page_index, pEraseInit->Banks);
222
223 /* Wait for last operation to be completed */
224 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
225
226 if (status != HAL_OK)
227 {
228 /* In case of error, stop erase procedure and return the faulty page */
229 *PageError = page_index;
230 break;
231 }
232 }
233 }
234
235 /* If the erase operation is completed, disable the associated bits */
236 CLEAR_BIT((*reg_cr), (pEraseInit->TypeErase) & (~(FLASH_NON_SECURE_MASK)));
237 }
238
239 /* Process Unlocked */
240 __HAL_UNLOCK(&pFlash);
241
242 return status;
243 }
244
245 /**
246 * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
247 * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
248 * contains the configuration information for the erasing.
249 *
250 * @retval HAL Status
251 */
HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef * pEraseInit)252 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
253 {
254 HAL_StatusTypeDef status;
255 __IO uint32_t *reg_cr;
256
257 /* Check the parameters */
258 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
259
260 /* Process Locked */
261 __HAL_LOCK(&pFlash);
262
263 /* Reset error code */
264 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
265
266 /* Wait for last operation to be completed */
267 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
268
269 if (status != HAL_OK)
270 {
271 /* Process Unlocked */
272 __HAL_UNLOCK(&pFlash);
273 }
274 else
275 {
276 /* Set internal variables used by the IRQ handler */
277 pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
278 pFlash.Bank = pEraseInit->Banks;
279
280 /* Access to SECCR or NSCR depends on operation type */
281 reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH->NSCR);
282
283 /* Enable End of Operation and Error interrupts */
284 (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_OPERR);
285
286 if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE)
287 {
288 /* Mass erase to be done */
289 FLASH_MassErase(pEraseInit->Banks);
290 }
291 else
292 {
293 /* Erase by page to be done */
294 pFlash.NbPagesToErase = pEraseInit->NbPages;
295 pFlash.Page = pEraseInit->Page;
296
297 /* Erase first page and wait for IT */
298 FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
299 }
300 }
301
302 return status;
303 }
304
305 /**
306 * @brief Program Option bytes.
307 * @param pOBInit pointer to an FLASH_OBInitStruct structure that
308 * contains the configuration information for the programming.
309 *
310 * @note To configure any option bytes, the option lock bit OPTLOCK must be
311 * cleared with the call of HAL_FLASH_OB_Unlock() function.
312 * @note New option bytes configuration will be taken into account in two cases:
313 * - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
314 * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
315 *
316 * @retval HAL Status
317 */
HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef * pOBInit)318 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
319 {
320 HAL_StatusTypeDef status;
321
322 /* Check the parameters */
323 assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
324
325 /* Process Locked */
326 __HAL_LOCK(&pFlash);
327
328 /* Reset error code */
329 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
330
331 /* Wait for last operation to be completed */
332 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
333
334 if (status == HAL_OK)
335 {
336 /* Write protection configuration */
337 if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U)
338 {
339 /* Configure of Write protection on the selected area */
340 FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset, pOBInit->WRPLock);
341 }
342
343 /* Read protection configuration */
344 if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
345 {
346 /* Configure the Read protection level */
347 FLASH_OB_RDPConfig(pOBInit->RDPLevel);
348 }
349
350 /* Read protection key configuration */
351 if ((pOBInit->OptionType & OPTIONBYTE_RDPKEY) != 0U)
352 {
353 /* Configure the Read protection key */
354 FLASH_OB_RDPKeyConfig(pOBInit->RDPKeyType, pOBInit->RDPKey1, pOBInit->RDPKey2);
355 }
356
357 /* User Configuration */
358 if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
359 {
360 /* Configure the user option bytes */
361 FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
362 }
363
364 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
365 /* Watermark secure configuration */
366 if ((pOBInit->OptionType & OPTIONBYTE_WMSEC) != 0U)
367 {
368 /* Configure the watermark-based secure area */
369 FLASH_OB_WMSECConfig(pOBInit->WMSecConfig, pOBInit->WMSecStartPage, pOBInit->WMSecEndPage,
370 pOBInit->WMHDPEndPage);
371 }
372
373 /* Unique boot entry point configuration */
374 if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U)
375 {
376 /* Configure the unique boot entry point */
377 FLASH_OB_BootLockConfig(pOBInit->BootLock);
378 }
379 #endif /* __ARM_FEATURE_CMSE */
380
381 /* Boot address configuration */
382 if ((pOBInit->OptionType & OPTIONBYTE_BOOTADDR) != 0U)
383 {
384 /* Configure the boot address */
385 FLASH_OB_BootAddrConfig(pOBInit->BootAddrConfig, pOBInit->BootAddr);
386 }
387
388 /* Set OPTSTRT Bit */
389 SET_BIT(FLASH->NSCR, FLASH_NSCR_OPTSTRT);
390
391 /* Wait for last operation to be completed */
392 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
393 }
394
395 /* Process Unlocked */
396 __HAL_UNLOCK(&pFlash);
397
398 return status;
399 }
400
401 /**
402 * @brief Get the Option bytes configuration.
403 * @param pOBInit pointer to an FLASH_OBInitStruct structure that contains the
404 * configuration information.
405 * @note The fields pOBInit->WRPArea, pOBInit->WMSecConfig and pOBInit->BootAddrConfig
406 * should indicate which area/address is requested for the WRP, WM Security or
407 * Boot Address, else no information will be returned
408 *
409 * @retval None
410 */
HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef * pOBInit)411 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
412 {
413 pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
414
415 if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||
416 (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
417 {
418 pOBInit->OptionType |= OPTIONBYTE_WRP;
419 /* Get write protection on the selected area */
420 FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset), &(pOBInit->WRPLock));
421 }
422
423 /* Get Read protection level */
424 pOBInit->RDPLevel = FLASH_OB_GetRDP();
425
426 /* Get the user option bytes */
427 pOBInit->USERConfig = FLASH_OB_GetUser();
428
429 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
430 /* Get the configuration of the watermark secure area for the selected area */
431 if ((pOBInit->WMSecConfig == OB_WMSEC_AREA1) || (pOBInit->WMSecConfig == OB_WMSEC_AREA2))
432 {
433 pOBInit->OptionType |= OPTIONBYTE_WMSEC;
434 FLASH_OB_GetWMSEC(&(pOBInit->WMSecConfig), &(pOBInit->WMSecStartPage), &(pOBInit->WMSecEndPage),
435 &(pOBInit->WMHDPEndPage));
436 }
437
438 pOBInit->OptionType |= OPTIONBYTE_BOOT_LOCK;
439
440 /* Get the configuration of the unique boot entry point */
441 pOBInit->BootLock = FLASH_OB_GetBootLock();
442 #endif /* __ARM_FEATURE_CMSE */
443
444 /* Get the value of the selected boot address */
445 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
446 if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1) ||
447 (pOBInit->BootAddrConfig == OB_BOOTADDR_SEC0))
448 #else
449 if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1))
450 #endif /* __ARM_FEATURE_CMSE */
451 {
452 pOBInit->OptionType |= OPTIONBYTE_BOOTADDR;
453 FLASH_OB_GetBootAddr(pOBInit->BootAddrConfig, &(pOBInit->BootAddr));
454 }
455 }
456
457 /**
458 * @brief Configure the block-based secure area.
459 *
460 * @param pBBAttributes pointer to an FLASH_BBAttributesTypeDef structure that
461 * contains the configuration information for the programming.
462 *
463 * @note The field pBBAttributes->Bank should indicate which area is requested
464 * for the block-based attributes.
465 * @note The field pBBAttributes->BBAttributesType should indicate which
466 * block-base attribute type is requested: Secure or Privilege.
467 *
468 * @retval HAL Status
469 */
HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef * pBBAttributes)470 HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes)
471 {
472 HAL_StatusTypeDef status;
473 uint8_t index;
474 __IO uint32_t *reg;
475
476 /* Check the parameters */
477 assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank));
478 assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType));
479
480 /* Wait for last operation to be completed */
481 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
482
483 if (status == HAL_OK)
484 {
485 /* Set the first Block-Based register to write */
486 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
487 if (pBBAttributes->BBAttributesType == FLASH_BB_SEC)
488 {
489 if (pBBAttributes->Bank == FLASH_BANK_1)
490 {
491 reg = &(FLASH->SECBB1R1);
492 }
493 else
494 {
495 reg = &(FLASH->SECBB2R1);
496 }
497 }
498 else
499 #endif /* __ARM_FEATURE_CMSE */
500 {
501 if (pBBAttributes->Bank == FLASH_BANK_1)
502 {
503 reg = &(FLASH->PRIVBB1R1);
504 }
505 else
506 {
507 reg = &(FLASH->PRIVBB2R1);
508 }
509 }
510
511 /* Modify the register values and check that new attributes are taken in account */
512 for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++)
513 {
514 *reg = pBBAttributes->BBAttributes_array[index];
515 if ((*reg) != pBBAttributes->BBAttributes_array[index])
516 {
517 status = HAL_ERROR;
518 }
519 reg++;
520 }
521
522 /* ISB instruction is called to be sure next instructions are performed with correct attributes */
523 __ISB();
524 }
525
526 /* Process Unlocked */
527 __HAL_UNLOCK(&pFlash);
528
529 return status;
530 }
531
532 /**
533 * @brief Return the block-based attributes.
534 *
535 * @param pBBAttributes [in/out] pointer to an FLASH_BBAttributesTypeDef structure
536 * that contains the configuration information.
537 * @note The field pBBAttributes->Bank should indicate which area is requested
538 * for the block-based attributes.
539 * @note The field pBBAttributes->BBAttributesType should indicate which
540 * block-base attribute type is requested: Secure or Privilege.
541 *
542 * @retval None
543 */
HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef * pBBAttributes)544 void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes)
545 {
546 uint8_t index;
547 __IO uint32_t *reg;
548
549 /* Check the parameters */
550 assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank));
551 assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType));
552
553 /* Set the first Block-Based register to read */
554 if (pBBAttributes->BBAttributesType == FLASH_BB_SEC)
555 {
556 if (pBBAttributes->Bank == FLASH_BANK_1)
557 {
558 reg = &(FLASH->SECBB1R1);
559 }
560 else
561 {
562 reg = &(FLASH->SECBB2R1);
563 }
564 }
565 else
566 {
567 if (pBBAttributes->Bank == FLASH_BANK_1)
568 {
569 reg = &(FLASH->PRIVBB1R1);
570 }
571 else
572 {
573 reg = &(FLASH->PRIVBB2R1);
574 }
575 }
576
577 /* Read the register values */
578 for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++)
579 {
580 pBBAttributes->BBAttributes_array[index] = (*reg);
581 reg++;
582 }
583 }
584
585 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
586 /**
587 * @brief Activation of the protection of the secure hide area.
588 *
589 * @param Banks indicate the bank concerned by the activation
590 * This parameter can be one of the following values:
591 * @arg FLASH_BANK_1: Bank1 to be protected
592 * @arg FLASH_BANK_2: Bank2 to be protected
593 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be protected
594 *
595 * @retval None
596 */
HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks)597 void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks)
598 {
599 /* Check the parameters */
600 assert_param(IS_FLASH_BANK(Banks));
601
602 if ((Banks & FLASH_BANK_1) != 0U)
603 {
604 SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP1_ACCDIS);
605 }
606
607 if ((Banks & FLASH_BANK_2) != 0U)
608 {
609 SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP2_ACCDIS);
610 }
611 }
612 #endif /* __ARM_FEATURE_CMSE */
613
614 /**
615 * @}
616 */
617
618 /** @addtogroup FLASHEx_Exported_Functions_Group2 FLASHEx Exported Functions Group2
619 * @{
620 */
621
622 /**
623 * @brief Configuration of the privilege attribute.
624 *
625 * @param PrivMode indicate privilege mode configuration
626 * This parameter can be one of the following values:
627 * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged
628 * or unprivileged access
629 * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied
630 * to unprivileged access
631 * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged
632 * or unprivileged access
633 * @arg FLASH_NSPRIV_DENIED: access to non-secure Flash registers is denied
634 * to unprivilege access
635 *
636 * @retval None
637 */
HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode)638 void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode)
639 {
640 /* Check the parameters */
641 assert_param(IS_FLASH_CFGPRIVMODE(PrivMode));
642
643 MODIFY_REG(FLASH->PRIVCFGR, (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV), PrivMode);
644 }
645
646 /**
647 * @brief Return the value of the privilege attribute.
648 *
649 * @retval It indicates the privilege mode configuration.
650 * This return value can be one of the following values:
651 * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged
652 * or unprivileged access
653 * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied
654 * to unprivileged access
655 * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged
656 * or unprivileged access
657 * @arg FLASH_NSPRIV_DENIED: access to Flash registers is denied
658 * to unprivilege accessP
659 */
HAL_FLASHEx_GetPrivMode(void)660 uint32_t HAL_FLASHEx_GetPrivMode(void)
661 {
662 return (FLASH->PRIVCFGR & (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV));
663 }
664
665 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
666 /**
667 * @brief Configuration of the security inversion.
668 *
669 * @param SecInvState indicate the flash security state configuration
670 * This parameter can be one of the following values:
671 * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted
672 * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted
673 *
674 * @retval HAL Status
675 */
HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState)676 HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState)
677 {
678 HAL_StatusTypeDef status;
679
680 /* Check the parameters */
681 assert_param(IS_FLASH_CFGSECINV(SecInvState));
682
683 /* Process Locked */
684 __HAL_LOCK(&pFlash);
685
686 /* Wait for last operation to be completed */
687 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
688
689 if (status == HAL_OK)
690 {
691 MODIFY_REG(FLASH->SECCR, FLASH_SECCR_INV, SecInvState);
692 }
693
694 /* Process Unlocked */
695 __HAL_UNLOCK(&pFlash);
696
697 return status;
698 }
699
700 /**
701 * @brief Return the value of the security inversion.
702 *
703 * @retval It indicates the flash security state configuration
704 * This return value can be one of the following values:
705 * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted
706 * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted
707 */
HAL_FLASHEx_GetSecInversion(void)708 uint32_t HAL_FLASHEx_GetSecInversion(void)
709 {
710 return (FLASH->SECCR & FLASH_SECCR_INV);
711 }
712 #endif /* __ARM_FEATURE_CMSE */
713
714 /**
715 * @brief Enable the Power-down Mode for Flash Banks
716 * @param Banks indicate which bank to put in power-down mode
717 * This parameter can be one of the following values:
718 * @arg FLASH_BANK_1: Flash Bank 1
719 * @arg FLASH_BANK_2: Flash Bank 2
720 * @arg FLASH_BANK_BOTH: Flash Bank 1 and Bank 2
721 * @retval HAL Status
722 */
HAL_FLASHEx_EnablePowerDown(uint32_t Banks)723 HAL_StatusTypeDef HAL_FLASHEx_EnablePowerDown(uint32_t Banks)
724 {
725 HAL_StatusTypeDef status = HAL_OK;
726 uint32_t tickstart;
727
728 /* Check the parameters */
729 assert_param(IS_FLASH_BANK(Banks));
730
731 /* Request power-down mode for Bank 1 */
732 if ((Banks & FLASH_BANK_1) != 0U)
733 {
734 /* Check PD1 and PDREQ1 bits (Bank 1 is not in power-down mode and not being
735 already under power-down request) */
736 if ((FLASH->NSSR & FLASH_NSSR_PD1) != 0U)
737 {
738 status = HAL_ERROR;
739 }
740 else if ((FLASH->ACR & FLASH_ACR_PDREQ1) != 0U)
741 {
742 status = HAL_ERROR;
743 }
744 else
745 {
746 /* Unlock PDREQ1 bit */
747 WRITE_REG(FLASH->PDKEY1R, FLASH_PDKEY1_1);
748 WRITE_REG(FLASH->PDKEY1R, FLASH_PDKEY1_2);
749
750 /* Set PDREQ1 in FLASH_ACR register */
751 SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1);
752
753 /* Check PD1 bit */
754 tickstart = HAL_GetTick();
755 while (((FLASH->NSSR & FLASH_NSSR_PD1) != FLASH_NSSR_PD1))
756 {
757 if ((HAL_GetTick() - tickstart) > FLASH_TIMEOUT_VALUE)
758 {
759 return HAL_TIMEOUT;
760 }
761 }
762 }
763 }
764
765 /* Request power-down mode for Bank 2 */
766 if ((Banks & FLASH_BANK_2) != 0U)
767 {
768 /* Check PD2 and PDREQ2 bits (Bank 2 is not in power-down mode and not being
769 already under power-down request) */
770 if ((FLASH->NSSR & FLASH_NSSR_PD2) != 0U)
771 {
772 status = HAL_ERROR;
773 }
774 else if ((FLASH->ACR & FLASH_ACR_PDREQ2) != 0U)
775 {
776 status = HAL_ERROR;
777 }
778 else
779 {
780 /* Unlock PDREQ2 bit */
781 WRITE_REG(FLASH->PDKEY2R, FLASH_PDKEY2_1);
782 WRITE_REG(FLASH->PDKEY2R, FLASH_PDKEY2_2);
783
784 /* Set PDREQ2 in FLASH_ACR register */
785 SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ2);
786
787 /* Check PD2 bit */
788 tickstart = HAL_GetTick();
789 while (((FLASH->NSSR & FLASH_NSSR_PD2) != FLASH_NSSR_PD2))
790 {
791 if ((HAL_GetTick() - tickstart) > FLASH_TIMEOUT_VALUE)
792 {
793 return HAL_TIMEOUT;
794 }
795 }
796 }
797 }
798
799 return status;
800 }
801
802 /**
803 * @brief Configuration of the Low-Power read Mode.
804 *
805 * @param ConfigLPM indicate the Low-Power read Mode configuration.
806 * This parameter can be one of the following values:
807 * @arg FLASH_LPM_ENABLE: Flash is in low-power read mode
808 * @arg FLASH_LPM_DISABLE: Flash is in normal read mode
809 *
810 * @retval HAL Status
811 */
HAL_FLASHEx_ConfigLowPowerRead(uint32_t ConfigLPM)812 HAL_StatusTypeDef HAL_FLASHEx_ConfigLowPowerRead(uint32_t ConfigLPM)
813 {
814 HAL_StatusTypeDef status = HAL_OK;
815
816 /* Check the parameters */
817 assert_param(IS_FLASH_CFGLPM(ConfigLPM));
818
819 /* Set LPM Bit in FLASH_ACR register */
820 MODIFY_REG(FLASH->ACR, FLASH_ACR_LPM, ConfigLPM);
821
822 /* Check that low power read mode has been activated */
823 if (READ_BIT(FLASH->ACR, FLASH_ACR_LPM) != ConfigLPM)
824 {
825 status = HAL_ERROR;
826 }
827
828 return status;
829 }
830
831 /**
832 * @brief Return the value of the Low-Power read Mode.
833 *
834 * @retval It indicates the flash low-power read mode configuration
835 * This return value can be one of the following values:
836 * @arg FLASH_LPM_ENABLE: Flash is in low-power read mode
837 * @arg FLASH_LPM_DISABLE: Flash is in normal read mode
838 */
HAL_FLASHEx_GetLowPowerRead(void)839 uint32_t HAL_FLASHEx_GetLowPowerRead(void)
840 {
841 return (FLASH->ACR & FLASH_ACR_LPM);
842 }
843
844 /**
845 * @brief Return the on-going Flash Operation. After a system reset, return
846 * the interrupted Flash operation, if any.
847 * @param pFlashOperation [out] pointer to a FLASH_OperationTypeDef structure
848 * that contains the Flash operation information.
849 *
850 * @retval None
851 */
HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef * pFlashOperation)852 void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation)
853 {
854 uint32_t opsr_reg = FLASH->OPSR;
855
856 /* Get Flash operation Type */
857 pFlashOperation->OperationType = opsr_reg & FLASH_OPSR_CODE_OP;
858
859 /* Get Flash operation memory */
860 pFlashOperation->FlashArea = opsr_reg & (FLASH_OPSR_SYSF_OP | FLASH_OPSR_BK_OP);
861
862 /* Get Flash operation address */
863 pFlashOperation->Address = opsr_reg & FLASH_OPSR_ADDR_OP;
864 }
865
866 /**
867 * @}
868 */
869
870 /**
871 * @}
872 */
873
874 /* Private functions ---------------------------------------------------------*/
875
876 /** @addtogroup FLASHEx_Private_Functions
877 * @{
878 */
879 /**
880 * @brief Mass erase of FLASH memory.
881 * @param Banks Banks to be erased
882 * This parameter can be one of the following values:
883 * @arg FLASH_BANK_1: Bank1 to be erased
884 * @arg FLASH_BANK_2: Bank2 to be erased
885 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
886 * @retval None
887 */
FLASH_MassErase(uint32_t Banks)888 static void FLASH_MassErase(uint32_t Banks)
889 {
890 __IO uint32_t *reg_cr;
891
892 /* Check the parameters */
893 assert_param(IS_FLASH_BANK(Banks));
894
895 /* Access to SECCR or NSCR registers depends on operation type */
896 reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
897
898 /* Set the Mass Erase Bit for the bank 1 and proceed to erase */
899 if ((Banks & FLASH_BANK_1) != 0U)
900 {
901 SET_BIT((*reg_cr), FLASH_NSCR_MER1 | FLASH_NSCR_STRT);
902 }
903
904 /* Set the Mass Erase Bit for the bank 2 and proceed to erase */
905 if ((Banks & FLASH_BANK_2) != 0U)
906 {
907 SET_BIT((*reg_cr), FLASH_NSCR_MER2 | FLASH_NSCR_STRT);
908 }
909 }
910
911 /**
912 * @brief Erase the specified FLASH memory page.
913 * @param Page FLASH page to erase
914 * This parameter must be a value between 0 and (max number of pages in the bank - 1)
915 * @param Banks Bank(s) where the page will be erased
916 * This parameter can be one of the following values:
917 * @arg FLASH_BANK_1: Page in bank 1 to be erased
918 * @arg FLASH_BANK_2: Page in bank 2 to be erased
919 * @retval None
920 */
FLASH_PageErase(uint32_t Page,uint32_t Banks)921 void FLASH_PageErase(uint32_t Page, uint32_t Banks)
922 {
923 __IO uint32_t *reg_cr;
924
925 /* Check the parameters */
926 assert_param(IS_FLASH_PAGE(Page));
927 assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
928
929 /* Access to SECCR or NSCR registers depends on operation type */
930 reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
931
932 if ((Banks & FLASH_BANK_1) != 0U)
933 {
934 CLEAR_BIT((*reg_cr), FLASH_NSCR_BKER);
935 }
936 else
937 {
938 SET_BIT((*reg_cr), FLASH_NSCR_BKER);
939 }
940
941 /* Proceed to erase the page */
942 MODIFY_REG((*reg_cr), (FLASH_NSCR_PNB | FLASH_NSCR_PER | FLASH_NSCR_STRT), \
943 ((Page << FLASH_NSCR_PNB_Pos) | FLASH_NSCR_PER | FLASH_NSCR_STRT));
944 }
945
946 /**
947 * @brief Configure the write protection of the desired pages.
948 *
949 * @note When the memory read protection level is selected (RDP level = 1),
950 * it is not possible to program or erase Flash memory if the CPU debug
951 * features are connected (JTAG or single wire) or boot code is being
952 * executed from RAM or System flash, even if WRP is not activated.
953 * @note To configure the WRP options, the option lock bit OPTLOCK must be
954 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
955 * @note To validate the WRP options, the option bytes must be reloaded
956 * through the call of the HAL_FLASH_OB_Launch() function.
957 *
958 * @param WRPArea specifies the area to be configured.
959 * This parameter can be one of the following values:
960 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
961 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
962 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A
963 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B
964 *
965 * @param WRPStartOffset specifies the start page of the write protected area
966 * This parameter can be page number between 0 and (max number of pages in the bank - 1)
967 *
968 * @param WRPEndOffset specifies the end page of the write protected area
969 * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1)
970 *
971 * @param WRPLock enables the lock of the write protected area
972 * This parameter can be set to ENABLE or DISABLE
973 *
974 * @retval None
975 */
FLASH_OB_WRPConfig(uint32_t WRPArea,uint32_t WRPStartOffset,uint32_t WRPEndOffset,FunctionalState WRPLock)976 static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset,
977 FunctionalState WRPLock)
978 {
979 /* Check the parameters */
980 assert_param(IS_OB_WRPAREA(WRPArea));
981 assert_param(IS_FLASH_PAGE(WRPStartOffset));
982 assert_param(IS_FLASH_PAGE(WRPEndOffset));
983 assert_param(IS_FUNCTIONAL_STATE(WRPLock));
984
985 /* Configure the write protected area */
986 if (WRPArea == OB_WRPAREA_BANK1_AREAA)
987 {
988 FLASH->WRP1AR = (((uint32_t)(~WRPLock) << FLASH_WRP1AR_UNLOCK_Pos) | \
989 (WRPEndOffset << FLASH_WRP1AR_WRP1A_PEND_Pos) | \
990 WRPStartOffset);
991 }
992 else if (WRPArea == OB_WRPAREA_BANK1_AREAB)
993 {
994 FLASH->WRP1BR = (((uint32_t)(~WRPLock) << FLASH_WRP1BR_UNLOCK_Pos) | \
995 (WRPEndOffset << FLASH_WRP1BR_WRP1B_PEND_Pos) | \
996 WRPStartOffset);
997 }
998 else if (WRPArea == OB_WRPAREA_BANK2_AREAA)
999 {
1000 FLASH->WRP2AR = (((uint32_t)(~WRPLock) << FLASH_WRP2AR_UNLOCK_Pos) | \
1001 (WRPEndOffset << FLASH_WRP2AR_WRP2A_PEND_Pos) | \
1002 WRPStartOffset);
1003 }
1004 else if (WRPArea == OB_WRPAREA_BANK2_AREAB)
1005 {
1006 FLASH->WRP2BR = (((uint32_t)(~WRPLock) << FLASH_WRP2BR_UNLOCK_Pos) | \
1007 (WRPEndOffset << FLASH_WRP2BR_WRP2B_PEND_Pos) | \
1008 WRPStartOffset);
1009 }
1010 else
1011 {
1012 /* Empty statement (to be compliant MISRA 15.7) */
1013 }
1014 }
1015
1016 /**
1017 * @brief Set the read protection level.
1018 *
1019 * @note To configure the RDP level, the option lock bit OPTLOCK must be
1020 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
1021 * @note To validate the RDP level, the option bytes must be reloaded
1022 * through the call of the HAL_FLASH_OB_Launch() function.
1023 * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
1024 * to go back to other levels !!!
1025 *
1026 * @param RDPLevel specifies the read protection level.
1027 * This parameter can be one of the following values:
1028 * @arg OB_RDP_LEVEL_0: No protection
1029 * @arg OB_RDP_LEVEL_0_5: No debug access to secure area
1030 * @arg OB_RDP_LEVEL_1: Read protection of the memory
1031 * @arg OB_RDP_LEVEL_2: Full chip protection
1032 *
1033 * @retval None
1034 */
FLASH_OB_RDPConfig(uint32_t RDPLevel)1035 static void FLASH_OB_RDPConfig(uint32_t RDPLevel)
1036 {
1037 /* Check the parameters */
1038 assert_param(IS_OB_RDP_LEVEL(RDPLevel));
1039
1040 /* Configure the RDP level in the option bytes register */
1041 MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
1042 }
1043
1044 /**
1045 * @brief Set the read protection key.
1046 * @param RDPKeyType specifies the read protection key type.
1047 * This parameter can be one of the following values:
1048 * @arg OB_RDP_KEY_OEM1: OEM1 key
1049 * @arg OB_RDP_KEY_OEM2: OEM2 key
1050 * @param RDPKey1 specifies the RDP key 1.
1051 * @param RDPKey2 specifies the RDP key 2.
1052 * @retval None
1053 */
FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType,uint32_t RDPKey1,uint32_t RDPKey2)1054 static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_t RDPKey2)
1055 {
1056 /* Check the parameters */
1057 assert_param(IS_OB_RDP_KEY_TYPE(RDPKeyType));
1058
1059 /* Configure the RDP OEM key */
1060 if (RDPKeyType == OB_RDP_KEY_OEM1)
1061 {
1062 WRITE_REG(FLASH->OEM1KEYR1, RDPKey1);
1063 WRITE_REG(FLASH->OEM1KEYR2, RDPKey2);
1064 }
1065 else
1066 {
1067 WRITE_REG(FLASH->OEM2KEYR1, RDPKey1);
1068 WRITE_REG(FLASH->OEM2KEYR2, RDPKey2);
1069 }
1070 }
1071
1072 /**
1073 * @brief Program the FLASH User Option Byte.
1074 *
1075 * @note To configure the user option bytes, the option lock bit OPTLOCK must
1076 * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
1077 * @note To validate the user option bytes, the option bytes must be reloaded
1078 * through the call of the HAL_FLASH_OB_Launch() function.
1079 * @param UserType: The FLASH User Option Bytes to be modified.
1080 * This parameter can be a combination of @ref FLASH_OB_USER_Type
1081 * @param UserConfig The selected User Option Bytes values.
1082 * This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
1083 * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
1084 * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST,
1085 * @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
1086 * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
1087 * @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK,
1088 * @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC,
1089 * @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST,
1090 * @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
1091 * @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV,
1092 * @ref FLASH_OB_USER_IO_VDDIO2_HSLV and @ref OB_USER_TZEN
1093 * @retval None
1094 */
FLASH_OB_UserConfig(uint32_t UserType,uint32_t UserConfig)1095 static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
1096 {
1097 uint32_t optr_reg_val = 0;
1098 uint32_t optr_reg_mask = 0;
1099
1100 /* Check the parameters */
1101 assert_param(IS_OB_USER_TYPE(UserType));
1102
1103 if ((UserType & OB_USER_BOR_LEV) != 0U)
1104 {
1105 /* BOR level option byte should be modified */
1106 assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
1107
1108 /* Set value and mask for BOR level option byte */
1109 optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
1110 optr_reg_mask |= FLASH_OPTR_BOR_LEV;
1111 }
1112
1113 if ((UserType & OB_USER_NRST_STOP) != 0U)
1114 {
1115 /* nRST_STOP option byte should be modified */
1116 assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
1117
1118 /* Set value and mask for nRST_STOP option byte */
1119 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
1120 optr_reg_mask |= FLASH_OPTR_nRST_STOP;
1121 }
1122
1123 if ((UserType & OB_USER_NRST_STDBY) != 0U)
1124 {
1125 /* nRST_STDBY option byte should be modified */
1126 assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
1127
1128 /* Set value and mask for nRST_STDBY option byte */
1129 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
1130 optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
1131 }
1132
1133 if ((UserType & OB_USER_NRST_SHDW) != 0U)
1134 {
1135 /* nRST_SHDW option byte should be modified */
1136 assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
1137
1138 /* Set value and mask for nRST_SHDW option byte */
1139 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
1140 optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
1141 }
1142
1143 if ((UserType & OB_USER_SRAM_RST) != 0U)
1144 {
1145 /* SRAM_RST option byte should be modified */
1146 assert_param(IS_OB_USER_SRAM_RST(UserConfig & FLASH_OPTR_SRAM_RST));
1147
1148 /* Set value and mask for SRAM_RST option byte */
1149 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_RST);
1150 optr_reg_mask |= FLASH_OPTR_SRAM_RST;
1151 }
1152
1153 if ((UserType & OB_USER_IWDG_SW) != 0U)
1154 {
1155 /* IWDG_SW option byte should be modified */
1156 assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
1157
1158 /* Set value and mask for IWDG_SW option byte */
1159 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
1160 optr_reg_mask |= FLASH_OPTR_IWDG_SW;
1161 }
1162
1163 if ((UserType & OB_USER_IWDG_STOP) != 0U)
1164 {
1165 /* IWDG_STOP option byte should be modified */
1166 assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
1167
1168 /* Set value and mask for IWDG_STOP option byte */
1169 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
1170 optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
1171 }
1172
1173 if ((UserType & OB_USER_IWDG_STDBY) != 0U)
1174 {
1175 /* IWDG_STDBY option byte should be modified */
1176 assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
1177
1178 /* Set value and mask for IWDG_STDBY option byte */
1179 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
1180 optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
1181 }
1182
1183 if ((UserType & OB_USER_WWDG_SW) != 0U)
1184 {
1185 /* WWDG_SW option byte should be modified */
1186 assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
1187
1188 /* Set value and mask for WWDG_SW option byte */
1189 optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
1190 optr_reg_mask |= FLASH_OPTR_WWDG_SW;
1191 }
1192
1193 if ((UserType & OB_USER_SWAP_BANK) != 0U)
1194 {
1195 /* SWAP_BANK option byte should be modified */
1196 assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTR_SWAP_BANK));
1197
1198 /* Set value and mask for SWAP_BANK option byte */
1199 optr_reg_val |= (UserConfig & FLASH_OPTR_SWAP_BANK);
1200 optr_reg_mask |= FLASH_OPTR_SWAP_BANK;
1201 }
1202
1203 if ((UserType & OB_USER_DUALBANK) != 0U)
1204 {
1205 /* DUALBANK option byte should be modified */
1206 assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK));
1207
1208 /* Set value and mask for DUALBANK option byte */
1209 optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK);
1210 optr_reg_mask |= FLASH_OPTR_DUALBANK;
1211 }
1212
1213 if ((UserType & OB_USER_BKPRAM_ECC) != 0U)
1214 {
1215 /* BKPRAM_ECC option byte should be modified */
1216 assert_param(IS_OB_USER_BKPRAM_ECC(UserConfig & FLASH_OPTR_BKPRAM_ECC));
1217
1218 /* Set value and mask for BKPRAM_ECC option byte */
1219 optr_reg_val |= (UserConfig & FLASH_OPTR_BKPRAM_ECC);
1220 optr_reg_mask |= FLASH_OPTR_BKPRAM_ECC;
1221 }
1222 #if defined(SRAM3_BASE)
1223 if ((UserType & OB_USER_SRAM3_ECC) != 0U)
1224 {
1225 /* SRAM3_ECC option byte should be modified */
1226 assert_param(IS_OB_USER_SRAM3_ECC(UserConfig & FLASH_OPTR_SRAM3_ECC));
1227
1228 /* Set value and mask for SRAM3_ECC option byte */
1229 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM3_ECC);
1230 optr_reg_mask |= FLASH_OPTR_SRAM3_ECC;
1231 }
1232 #endif /* SRAM3_BASE */
1233 if ((UserType & OB_USER_SRAM2_ECC) != 0U)
1234 {
1235 /* SRAM2_ECC option byte should be modified */
1236 assert_param(IS_OB_USER_SRAM2_ECC(UserConfig & FLASH_OPTR_SRAM2_ECC));
1237
1238 /* Set value and mask for SRAM2_ECC option byte */
1239 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_ECC);
1240 optr_reg_mask |= FLASH_OPTR_SRAM2_ECC;
1241 }
1242
1243 if ((UserType & OB_USER_SRAM2_RST) != 0U)
1244 {
1245 /* SRAM2_RST option byte should be modified */
1246 assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));
1247
1248 /* Set value and mask for SRAM2_RST option byte */
1249 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);
1250 optr_reg_mask |= FLASH_OPTR_SRAM2_RST;
1251 }
1252
1253 if ((UserType & OB_USER_NSWBOOT0) != 0U)
1254 {
1255 /* nSWBOOT0 option byte should be modified */
1256 assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
1257
1258 /* Set value and mask for nSWBOOT0 option byte */
1259 optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
1260 optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
1261 }
1262
1263 if ((UserType & OB_USER_NBOOT0) != 0U)
1264 {
1265 /* nBOOT0 option byte should be modified */
1266 assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
1267
1268 /* Set value and mask for nBOOT0 option byte */
1269 optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
1270 optr_reg_mask |= FLASH_OPTR_nBOOT0;
1271 }
1272
1273 if ((UserType & OB_USER_PA15_PUPEN) != 0U)
1274 {
1275 /* PA15_PUPEN option byte should be modified */
1276 assert_param(IS_OB_USER_PA15_PUPEN(UserConfig & FLASH_OPTR_PA15_PUPEN));
1277
1278 /* Set value and mask for nBOOT0 option byte */
1279 optr_reg_val |= (UserConfig & FLASH_OPTR_PA15_PUPEN);
1280 optr_reg_mask |= FLASH_OPTR_PA15_PUPEN;
1281 }
1282
1283 if ((UserType & OB_USER_IO_VDD_HSLV) != 0U)
1284 {
1285 /* IO_VDD_HSLV option byte should be modified */
1286 assert_param(IS_OB_USER_IO_VDD_HSLV(UserConfig & FLASH_OPTR_IO_VDD_HSLV));
1287
1288 /* Set value and mask for IO_VDD_HSLV option byte */
1289 optr_reg_val |= (UserConfig & FLASH_OPTR_IO_VDD_HSLV);
1290 optr_reg_mask |= FLASH_OPTR_IO_VDD_HSLV;
1291 }
1292
1293 if ((UserType & OB_USER_IO_VDDIO2_HSLV) != 0U)
1294 {
1295 /* IO_VDDIO2_HSLV option byte should be modified */
1296 assert_param(IS_OB_USER_IO_VDDIO2_HSLV(UserConfig & FLASH_OPTR_IO_VDDIO2_HSLV));
1297
1298 /* Set value and mask for IO_VDDIO2_HSLV option byte */
1299 optr_reg_val |= (UserConfig & FLASH_OPTR_IO_VDDIO2_HSLV);
1300 optr_reg_mask |= FLASH_OPTR_IO_VDDIO2_HSLV;
1301 }
1302
1303 if ((UserType & OB_USER_TZEN) != 0U)
1304 {
1305 /* TZEN option byte should be modified */
1306 assert_param(IS_OB_USER_TZEN(UserConfig & FLASH_OPTR_TZEN));
1307
1308 /* Set value and mask for TZEN option byte */
1309 optr_reg_val |= (UserConfig & FLASH_OPTR_TZEN);
1310 optr_reg_mask |= FLASH_OPTR_TZEN;
1311 }
1312
1313 /* Configure the option bytes register */
1314 MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
1315 }
1316
1317 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1318 /**
1319 * @brief Configure the watermarked-based secure area.
1320 *
1321 * @param WMSecConfig specifies the area to be configured.
1322 * This parameter can be a combination of the following values:
1323 * @arg OB_WMSEC_AREA1 or @arg OB_WMSEC_AREA2: Select Flash Secure Area 1 or Area 2
1324 * @arg OB_WMSEC_SECURE_AREA_CONFIG: configure Flash Secure Area
1325 * @arg OB_WMSEC_HDP_AREA_CONFIG: configure Flash secure hide Area
1326 * @arg OB_WMSEC_HDP_AREA_ENABLE: enable secure hide Area in Secure Area
1327 * @arg OB_WMSEC_HDP_AREA_DISABLE: disable secure hide Area in Secure Area
1328 *
1329 * @param WMSecStartPage specifies the start page of the secure area
1330 * This parameter can be page number between 0 and (max number of pages in the bank - 1)
1331 *
1332 * @param WMSecEndPage specifies the end page of the secure area
1333 * This parameter can be page number between WMSecStartPage and (max number of pages in the bank - 1)
1334 *
1335 * @param WMHDPEndPage specifies the end page of the secure hide area
1336 * This parameter can be a page number between WMSecStartPage and WMSecEndPage
1337 *
1338 * @retval None
1339 */
FLASH_OB_WMSECConfig(uint32_t WMSecConfig,uint32_t WMSecStartPage,uint32_t WMSecEndPage,uint32_t WMHDPEndPage)1340 static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage,
1341 uint32_t WMHDPEndPage)
1342 {
1343 uint32_t tmp_secwm1 = 0U;
1344 uint32_t tmp_secwm2 = 0U;
1345
1346 /* Check the parameters */
1347 assert_param(IS_OB_WMSEC_CONFIG(WMSecConfig));
1348 assert_param(IS_OB_WMSEC_AREA_EXCLUSIVE(WMSecConfig & 0x3U));
1349 assert_param(IS_FLASH_PAGE(WMSecStartPage));
1350 assert_param(IS_FLASH_PAGE(WMSecEndPage));
1351 assert_param(IS_FLASH_PAGE(WMHDPEndPage));
1352
1353 /* Read SECWM registers */
1354 if ((WMSecConfig & OB_WMSEC_AREA1) != 0U)
1355 {
1356 tmp_secwm1 = FLASH->SECWM1R1;
1357 tmp_secwm2 = FLASH->SECWM1R2;
1358 }
1359 else if ((WMSecConfig & OB_WMSEC_AREA2) != 0U)
1360 {
1361 tmp_secwm1 = FLASH->SECWM2R1;
1362 tmp_secwm2 = FLASH->SECWM2R2;
1363 }
1364 else
1365 {
1366 /* Nothing to do */
1367 }
1368
1369 /* Configure Secure Area */
1370 if ((WMSecConfig & OB_WMSEC_SECURE_AREA_CONFIG) != 0U)
1371 {
1372 tmp_secwm1 = ((WMSecEndPage << FLASH_SECWM1R1_SECWM1_PEND_Pos) | WMSecStartPage);
1373 }
1374
1375 /* Configure Secure Hide Area */
1376 if ((WMSecConfig & OB_WMSEC_HDP_AREA_CONFIG) != 0U)
1377 {
1378 tmp_secwm2 &= (~FLASH_SECWM1R2_HDP1_PEND);
1379 tmp_secwm2 |= (WMHDPEndPage << FLASH_SECWM1R2_HDP1_PEND_Pos);
1380 }
1381
1382 /* Enable Secure Hide Area */
1383 if ((WMSecConfig & OB_WMSEC_HDP_AREA_ENABLE) != 0U)
1384 {
1385 tmp_secwm2 |= FLASH_SECWM1R2_HDP1EN;
1386 }
1387
1388 /* Disable Secure Hide Area */
1389 if ((WMSecConfig & OB_WMSEC_HDP_AREA_DISABLE) != 0U)
1390 {
1391 tmp_secwm2 &= (~FLASH_SECWM1R2_HDP1EN);
1392 }
1393
1394 /* Write SECWM registers */
1395 if ((WMSecConfig & OB_WMSEC_AREA1) != 0U)
1396 {
1397 FLASH->SECWM1R1 = tmp_secwm1;
1398 FLASH->SECWM1R2 = tmp_secwm2;
1399 }
1400 else if ((WMSecConfig & OB_WMSEC_AREA2) != 0U)
1401 {
1402 FLASH->SECWM2R1 = tmp_secwm1;
1403 FLASH->SECWM2R2 = tmp_secwm2;
1404 }
1405 else
1406 {
1407 /* Nothing to do */
1408 }
1409 }
1410
1411 /**
1412 * @brief Configure the boot lock.
1413 *
1414 * @param BootLockConfig specifies the activation of the BOOT_LOCK.
1415 * This parameter can be one of the following values:
1416 * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated
1417 * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated
1418 *
1419 * @retval None
1420 */
FLASH_OB_BootLockConfig(uint32_t BootLockConfig)1421 static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig)
1422 {
1423 /* Check the parameters */
1424 assert_param(IS_OB_BOOT_LOCK(BootLockConfig));
1425
1426 /* Configure the option bytes register */
1427 MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_BOOT_LOCK, BootLockConfig);
1428 }
1429 #endif /* __ARM_FEATURE_CMSE */
1430
1431 /**
1432 * @brief Configure the boot address.
1433 *
1434 * @param BootAddrConfig specifies the area to be configured.
1435 * This parameter can be one of the following values:
1436 * @arg OB_BOOTADDR_NS0: Non-secure boot address 0
1437 * @arg OB_BOOTADDR_NS1: Non-secure boot address 1
1438 * @arg OB_BOOTADDR_SEC0: Secure boot address 0
1439 *
1440 * @param BootAddr: specifies the address used for the boot
1441 * This parameter can be page number between 0 and 0xFFFFFF00
1442 *
1443 * @retval None
1444 */
FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig,uint32_t BootAddr)1445 static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr)
1446 {
1447 /* Check the parameters */
1448 assert_param(IS_OB_BOOTADDR_CONFIG(BootAddrConfig));
1449
1450 if (BootAddrConfig == OB_BOOTADDR_NS0)
1451 {
1452 FLASH->NSBOOTADD0R = BootAddr;
1453 }
1454 else if (BootAddrConfig == OB_BOOTADDR_NS1)
1455 {
1456 FLASH->NSBOOTADD1R = BootAddr;
1457 }
1458 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1459 else if (BootAddrConfig == OB_BOOTADDR_SEC0)
1460 {
1461 MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_SECBOOTADD0, BootAddr);
1462 }
1463 #endif /* __ARM_FEATURE_CMSE */
1464 else
1465 {
1466 /* Empty statement (to be compliant MISRA 15.7) */
1467 }
1468 }
1469
1470 /**
1471 * @brief Return the FLASH Write Protection Option Bytes value.
1472 *
1473 * @param[in] WRPArea specifies the area to be returned.
1474 * This parameter can be one of the following values:
1475 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
1476 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
1477 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A
1478 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B
1479 *
1480 * @param[out] WRPStartOffset specifies the address where to copied the start page
1481 * of the write protected area
1482 *
1483 * @param[out] WRPEndOffset specifies the address where to copied the end page of
1484 * the write protected area
1485 *
1486 * @param[out] WRPLock specifies the lock status of the write protected area.
1487 * The returned value can be ENABLE or DISABLE
1488 *
1489 * @retval None
1490 */
FLASH_OB_GetWRP(uint32_t WRPArea,uint32_t * WRPStartOffset,uint32_t * WRPEndOffset,FunctionalState * WRPLock)1491 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRPEndOffset,
1492 FunctionalState *WRPLock)
1493 {
1494 /* Get the configuration of the write protected area */
1495 if (WRPArea == OB_WRPAREA_BANK1_AREAA)
1496 {
1497 *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_PSTRT);
1498 *WRPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_PEND) >> FLASH_WRP1AR_WRP1A_PEND_Pos);
1499 *WRPLock = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_UNLOCK) != 0U) ? DISABLE : ENABLE;
1500 }
1501 else if (WRPArea == OB_WRPAREA_BANK1_AREAB)
1502 {
1503 *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_PSTRT);
1504 *WRPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_PEND) >> FLASH_WRP1BR_WRP1B_PEND_Pos);
1505 *WRPLock = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_UNLOCK) != 0U) ? DISABLE : ENABLE;
1506 }
1507 else if (WRPArea == OB_WRPAREA_BANK2_AREAA)
1508 {
1509 *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_PSTRT);
1510 *WRPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_PEND) >> FLASH_WRP2AR_WRP2A_PEND_Pos);
1511 *WRPLock = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_UNLOCK) != 0U) ? DISABLE : ENABLE;
1512 }
1513 else if (WRPArea == OB_WRPAREA_BANK2_AREAB)
1514 {
1515 *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_PSTRT);
1516 *WRPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_PEND) >> FLASH_WRP2BR_WRP2B_PEND_Pos);
1517 *WRPLock = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_UNLOCK) != 0U) ? DISABLE : ENABLE;
1518 }
1519 else
1520 {
1521 /* Empty statement (to be compliant MISRA 15.7) */
1522 }
1523 }
1524
1525 /**
1526 * @brief Return the FLASH Read Protection level.
1527 * @retval FLASH ReadOut Protection Level.
1528 * This return value can be one of the following values:
1529 * @arg OB_RDP_LEVEL_0: No protection
1530 * @arg OB_RDP_LEVEL_0_5: No debug access to secure area
1531 * @arg OB_RDP_LEVEL_1: Read protection of the memory
1532 * @arg OB_RDP_LEVEL_2: Full chip protection
1533 */
FLASH_OB_GetRDP(void)1534 static uint32_t FLASH_OB_GetRDP(void)
1535 {
1536 uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
1537
1538 if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_0_5) && (rdp_level != OB_RDP_LEVEL_2))
1539 {
1540 return (OB_RDP_LEVEL_1);
1541 }
1542 else
1543 {
1544 return rdp_level;
1545 }
1546 }
1547
1548 /**
1549 * @brief Return the FLASH User Option Byte value.
1550 * @retval The FLASH User Option Bytes values.
1551 * The return value can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
1552 * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
1553 * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST,
1554 * @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
1555 * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
1556 * @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK,
1557 * @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC,
1558 * @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST,
1559 * @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
1560 * @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV,
1561 * @ref FLASH_OB_USER_IO_VDDIO2_HSLV and @ref OB_USER_TZEN
1562 */
FLASH_OB_GetUser(void)1563 static uint32_t FLASH_OB_GetUser(void)
1564 {
1565 uint32_t user_config = READ_REG(FLASH->OPTR);
1566 CLEAR_BIT(user_config, FLASH_OPTR_RDP);
1567
1568 return user_config;
1569 }
1570
1571 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1572 /**
1573 * @brief Return the watermarked-based secure area configuration.
1574 *
1575 * @param WMSecConfig [in/out] specifies the area to be returned.
1576 * This parameter can be one of the following values:
1577 * @arg OB_WMSEC_AREA1: select Flash Secure Area 1
1578 * @arg OB_WMSEC_AREA2: select Flash Secure Area 2
1579 * When return from the function, this parameter will be a combinaison of the following values:
1580 * @arg OB_WMSEC_AREAA or @arg OB_WMSEC_AREAB: selected Flash Secure Area A or Area B
1581 * @arg OB_WMSEC_HDP_AREA_ENABLE: Secure Hide Area in Secure Area enabled
1582 * @arg OB_WMSEC_HDP_AREA_DISABLE: Secure Hide Area in Secure Area disabled
1583 *
1584 * @param WMSecStartPage [out] specifies the start page of the secure area
1585 *
1586 * @param WMSecEndPage [out] specifies the end page of the secure area
1587 *
1588 * @param WMHDPEndPage [out] specifies the end page of the secure hide area
1589 *
1590 *
1591 * @retval None
1592 */
FLASH_OB_GetWMSEC(uint32_t * WMSecConfig,uint32_t * WMSecStartPage,uint32_t * WMSecEndPage,uint32_t * WMHDPEndPage)1593 static void FLASH_OB_GetWMSEC(uint32_t *WMSecConfig, uint32_t *WMSecStartPage, uint32_t *WMSecEndPage,
1594 uint32_t *WMHDPEndPage)
1595 {
1596 uint32_t tmp_secwm1 = 0U;
1597 uint32_t tmp_secwm2 = 0U;
1598
1599 /* Check the parameters */
1600 assert_param(IS_OB_WMSEC_CONFIG(*WMSecConfig));
1601 assert_param(IS_FLASH_BANK_EXCLUSIVE((*WMSecConfig) & 0x3U));
1602
1603 /* Read SECWM registers */
1604 if (((*WMSecConfig) & OB_WMSEC_AREA1) != 0U)
1605 {
1606 tmp_secwm1 = FLASH->SECWM1R1;
1607 tmp_secwm2 = FLASH->SECWM1R2;
1608 }
1609 else if (((*WMSecConfig) & OB_WMSEC_AREA2) != 0U)
1610 {
1611 tmp_secwm1 = FLASH->SECWM2R1;
1612 tmp_secwm2 = FLASH->SECWM2R2;
1613 }
1614 else
1615 {
1616 /* Empty statement (to be compliant MISRA 15.7) */
1617 }
1618
1619 /* Configuration of secure area */
1620 *WMSecStartPage = (tmp_secwm1 & FLASH_SECWM1R1_SECWM1_PSTRT);
1621 *WMSecEndPage = ((tmp_secwm1 & FLASH_SECWM1R1_SECWM1_PEND) >> FLASH_SECWM1R1_SECWM1_PEND_Pos);
1622
1623 /* Configuration of secure hide area */
1624 *WMHDPEndPage = ((tmp_secwm2 & FLASH_SECWM1R2_HDP1_PEND) >> FLASH_SECWM1R2_HDP1_PEND_Pos);
1625
1626 if ((tmp_secwm2 & FLASH_SECWM1R2_HDP1EN) == 0U)
1627 {
1628 *WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_DISABLE);
1629 }
1630 else
1631 {
1632 *WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_ENABLE);
1633 }
1634
1635 }
1636
1637 /**
1638 * @brief Return the boot lock configuration.
1639 *
1640 * @retval Value of Boot Lock configuration.
1641 * It can be one of the following values:
1642 * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated
1643 * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated
1644 */
FLASH_OB_GetBootLock(void)1645 static uint32_t FLASH_OB_GetBootLock(void)
1646 {
1647 return (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_BOOT_LOCK);
1648 }
1649 #endif /* __ARM_FEATURE_CMSE */
1650
1651 /**
1652 * @brief Return the boot address.
1653 *
1654 * @param[in] BootAddrConfig specifies the area to be returned.
1655 * This parameter can be one of the following values:
1656 * @arg OB_BOOTADDR_NS0: Non-secure boot address 0
1657 * @arg OB_BOOTADDR_NS1: Non-secure boot address 1
1658 * @arg OB_BOOTADDR_SEC0: Secure boot address 0
1659 *
1660 * @param[out] BootAddr specifies the boot address value
1661 *
1662 * @retval None
1663 */
FLASH_OB_GetBootAddr(uint32_t BootAddrConfig,uint32_t * BootAddr)1664 static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t *BootAddr)
1665 {
1666 if (BootAddrConfig == OB_BOOTADDR_NS0)
1667 {
1668 *BootAddr = (FLASH->NSBOOTADD0R & FLASH_NSBOOTADD0R_NSBOOTADD0);
1669 }
1670 else if (BootAddrConfig == OB_BOOTADDR_NS1)
1671 {
1672 *BootAddr = (FLASH->NSBOOTADD1R & FLASH_NSBOOTADD1R_NSBOOTADD1);
1673 }
1674 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1675 else if (BootAddrConfig == OB_BOOTADDR_SEC0)
1676 {
1677 *BootAddr = (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_SECBOOTADD0);
1678 }
1679 #endif /* __ARM_FEATURE_CMSE */
1680 else
1681 {
1682 /* Empty statement (to be compliant MISRA 15.7) */
1683 }
1684 }
1685
1686 /**
1687 * @}
1688 */
1689
1690 #endif /* HAL_FLASH_MODULE_ENABLED */
1691
1692 /**
1693 * @}
1694 */
1695
1696 /**
1697 * @}
1698 */
1699
