1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and Configuration functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2021 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 @verbatim
23 ==============================================================================
24 ##### How to use this driver #####
25 ==============================================================================
26
27 [..]
28 *** How to configure Interrupts using CORTEX HAL driver ***
29 ===========================================================
30 [..]
31 This section provides functions allowing to configure the NVIC interrupts (IRQ).
32 The Cortex-M33 exceptions are managed by CMSIS functions.
33
34 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
35 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
36 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
37
38 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
39 The pending IRQ priority will be managed only by the sub priority.
40
41 -@- IRQ priority order (sorted by highest to lowest priority):
42 (+@) Lowest pre-emption priority
43 (+@) Lowest sub priority
44 (+@) Lowest hardware priority (IRQ number)
45
46 [..]
47 *** How to configure SysTick using CORTEX HAL driver ***
48 ========================================================
49 [..]
50 Setup SysTick Timer for time base.
51
52 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
53 is a CMSIS function that:
54 (++) Configures the SysTick Reload register with value passed as function parameter.
55 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
56 (++) Resets the SysTick Counter register.
57 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
58 (++) Enables the SysTick Interrupt.
59 (++) Starts the SysTick Counter.
60
61 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
62 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
63 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
64 inside the stm32u5xx_hal_cortex.h file.
65
66 (+) You can change the SysTick IRQ priority by calling the
67 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
68 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
69
70 (+) To adjust the SysTick time base, use the following formula:
71
72 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
73 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
74 (++) Reload Value should not exceed 0xFFFFFF
75
76 [..]
77 *** How to configure MPU (secure and non secure) using CORTEX HAL driver ***
78 ===========================================================
79 [..]
80 This section provides functions allowing to Enable and configure the MPU secure and non-secure.
81
82 (#) Enable the MPU using HAL_MPU_Enable() function.
83 (#) Disable the MPU using HAL_MPU_Disable() function.
84 (#) Enable the MPU using HAL_MPU_Enable_NS() function to address the non secure MPU.
85 (#) Disable the MPU using HAL_MPU_Disable_NS() function to address the non secure MPU.
86 (#) Configure the MPU region using HAL_MPU_ConfigRegion()
87 and HAL_MPU_ConfigRegion_NS() to address the non secure MPU.
88 (#) Configure the MPU Memory attributes using HAL_MPU_ConfigMemoryAttributes()
89 and HAL_MPU_ConfigMemoryAttributes_NS() to address the non secure MPU.
90
91 @endverbatim
92 ******************************************************************************
93
94 The table below gives the allowed values of the pre-emption priority and subpriority according
95 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
96
97 ========================================================================================================================
98 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
99 ========================================================================================================================
100 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
101 | | | 4 bits for subpriority
102 ------------------------------------------------------------------------------------------------------------------------
103 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
104 | | | 3 bits for subpriority
105 ------------------------------------------------------------------------------------------------------------------------
106 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
107 | | | 2 bits for subpriority
108 ------------------------------------------------------------------------------------------------------------------------
109 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
110 | | | 1 bit for subpriority
111 ------------------------------------------------------------------------------------------------------------------------
112 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
113 | | | 0 bit for subpriority
114 ========================================================================================================================
115 */
116
117 /* Includes ------------------------------------------------------------------*/
118 #include "stm32u5xx_hal.h"
119
120 /** @addtogroup STM32U5xx_HAL_Driver
121 * @{
122 */
123
124 /** @addtogroup CORTEX
125 * @{
126 */
127
128 #ifdef HAL_CORTEX_MODULE_ENABLED
129
130 /* Private types -------------------------------------------------------------*/
131 /* Private variables ---------------------------------------------------------*/
132 /* Private constants ---------------------------------------------------------*/
133 /* Private macros ------------------------------------------------------------*/
134 /* Private functions ---------------------------------------------------------*/
135 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
136 * @{
137 */
138 static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit);
139 static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit);
140 /**
141 * @}
142 */
143 /* Exported functions --------------------------------------------------------*/
144
145 /** @addtogroup CORTEX_Exported_Functions
146 * @{
147 */
148
149
150 /** @addtogroup CORTEX_Exported_Functions_Group1
151 * @brief Initialization and Configuration functions
152 *
153 @verbatim
154 ==============================================================================
155 ##### Initialization and Configuration functions #####
156 ==============================================================================
157 [..]
158 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
159 SysTick functionalities
160
161 @endverbatim
162 * @{
163 */
164
165
166 /**
167 * @brief Set the priority grouping field (pre-emption priority and subpriority)
168 * using the required unlock sequence.
169 * @param PriorityGroup: The priority grouping bits length.
170 * This parameter can be one of the following values:
171 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
172 * 4 bits for subpriority
173 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
174 * 3 bits for subpriority
175 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
176 * 2 bits for subpriority
177 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
178 * 1 bit for subpriority
179 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
180 * 0 bit for subpriority
181 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
182 * The pending IRQ priority will be managed only by the subpriority.
183 * @retval None
184 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)185 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
186 {
187 /* Check the parameters */
188 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
189
190 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
191 NVIC_SetPriorityGrouping(PriorityGroup);
192 }
193
194 /**
195 * @brief Set the priority of an interrupt.
196 * @param IRQn: External interrupt number.
197 * This parameter can be an enumerator of IRQn_Type enumeration
198 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
199 * CMSIS device file (stm32u5xxxx.h))
200 * @param PreemptPriority: The pre-emption priority for the IRQn channel.
201 * This parameter can be a value between 0 and 15
202 * A lower priority value indicates a higher priority
203 * @param SubPriority: the subpriority level for the IRQ channel.
204 * This parameter can be a value between 0 and 15
205 * A lower priority value indicates a higher priority.
206 * @retval None
207 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)208 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
209 {
210 uint32_t prioritygroup;
211
212 /* Check the parameters */
213 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
214 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
215
216 prioritygroup = NVIC_GetPriorityGrouping();
217
218 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
219 }
220
221 /**
222 * @brief Enable a device specific interrupt in the NVIC interrupt controller.
223 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
224 * function should be called before.
225 * @param IRQn External interrupt number.
226 * This parameter can be an enumerator of IRQn_Type enumeration
227 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
228 * CMSIS device file (stm32u5xxxx.h))
229 * @retval None
230 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)231 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
232 {
233 /* Check the parameters */
234 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
235
236 /* Enable interrupt */
237 NVIC_EnableIRQ(IRQn);
238 }
239
240 /**
241 * @brief Disable a device specific interrupt in the NVIC interrupt controller.
242 * @param IRQn External interrupt number.
243 * This parameter can be an enumerator of IRQn_Type enumeration
244 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
245 * CMSIS device file (stm32u5xxxx.h))
246 * @retval None
247 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)248 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
249 {
250 /* Check the parameters */
251 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
252
253 /* Disable interrupt */
254 NVIC_DisableIRQ(IRQn);
255 }
256
257 /**
258 * @brief Initiate a system reset request to reset the MCU.
259 * @retval None
260 */
HAL_NVIC_SystemReset(void)261 void HAL_NVIC_SystemReset(void)
262 {
263 /* System Reset */
264 NVIC_SystemReset();
265 }
266
267 /**
268 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
269 * Counter is in free running mode to generate periodic interrupts.
270 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
271 * @retval status: - 0 Function succeeded.
272 * - 1 Function failed.
273 */
HAL_SYSTICK_Config(uint32_t TicksNumb)274 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
275 {
276 return SysTick_Config(TicksNumb);
277 }
278 /**
279 * @}
280 */
281
282 /** @addtogroup CORTEX_Exported_Functions_Group2
283 * @brief Cortex control functions
284 *
285 @verbatim
286 ==============================================================================
287 ##### Peripheral Control functions #####
288 ==============================================================================
289 [..]
290 This subsection provides a set of functions allowing to control the CORTEX
291 (NVIC, SYSTICK, MPU) functionalities.
292
293
294 @endverbatim
295 * @{
296 */
297
298 /**
299 * @brief Get the priority grouping field from the NVIC Interrupt Controller.
300 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
301 */
HAL_NVIC_GetPriorityGrouping(void)302 uint32_t HAL_NVIC_GetPriorityGrouping(void)
303 {
304 /* Get the PRIGROUP[10:8] field value */
305 return NVIC_GetPriorityGrouping();
306 }
307
308 /**
309 * @brief Get the priority of an interrupt.
310 * @param IRQn: External interrupt number.
311 * This parameter can be an enumerator of IRQn_Type enumeration
312 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
313 * CMSIS device file (stm32u5xxxx.h))
314 * @param PriorityGroup: the priority grouping bits length.
315 * This parameter can be one of the following values:
316 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
317 * 4 bits for subpriority
318 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
319 * 3 bits for subpriority
320 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
321 * 2 bits for subpriority
322 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
323 * 1 bit for subpriority
324 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
325 * 0 bit for subpriority
326 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
327 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
328 * @retval None
329 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)330 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority,
331 uint32_t *const pSubPriority)
332 {
333 /* Check the parameters */
334 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
335 /* Get priority for Cortex-M system or device specific interrupts */
336 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
337 }
338
339 /**
340 * @brief Set Pending bit of an external interrupt.
341 * @param IRQn External interrupt number
342 * This parameter can be an enumerator of IRQn_Type enumeration
343 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
344 * CMSIS device file (stm32u5xxxx.h))
345 * @retval None
346 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)347 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
348 {
349 /* Set interrupt pending */
350 NVIC_SetPendingIRQ(IRQn);
351 }
352
353 /**
354 * @brief Get Pending Interrupt (read the pending register in the NVIC
355 * and return the pending bit for the specified interrupt).
356 * @param IRQn External interrupt number.
357 * This parameter can be an enumerator of IRQn_Type enumeration
358 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
359 * CMSIS device file (stm32u5xxxx.h))
360 * @retval status: - 0 Interrupt status is not pending.
361 * - 1 Interrupt status is pending.
362 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)363 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
364 {
365 /* Return 1 if pending else 0 */
366 return NVIC_GetPendingIRQ(IRQn);
367 }
368
369 /**
370 * @brief Clear the pending bit of an external interrupt.
371 * @param IRQn External interrupt number.
372 * This parameter can be an enumerator of IRQn_Type enumeration
373 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
374 * CMSIS device file (stm32u5xxxx.h))
375 * @retval None
376 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)377 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
378 {
379 /* Clear pending interrupt */
380 NVIC_ClearPendingIRQ(IRQn);
381 }
382
383 /**
384 * @brief Get active interrupt (read the active register in NVIC and return the active bit).
385 * @param IRQn External interrupt number
386 * This parameter can be an enumerator of IRQn_Type enumeration
387 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
388 * CMSIS device file (stm32u5xxxx.h))
389 * @retval status: - 0 Interrupt status is not pending.
390 * - 1 Interrupt status is pending.
391 */
HAL_NVIC_GetActive(IRQn_Type IRQn)392 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
393 {
394 /* Return 1 if active else 0 */
395 return NVIC_GetActive(IRQn);
396 }
397
398 /**
399 * @brief Configure the SysTick clock source.
400 * @param CLKSource: specifies the SysTick clock source.
401 * This parameter can be one of the following values:
402 * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source.
403 * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source.
404 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
405 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
406 * @retval None
407 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)408 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
409 {
410 /* Check the parameters */
411 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
412 switch (CLKSource)
413 {
414 /* Select HCLK as Systick clock source */
415 case SYSTICK_CLKSOURCE_HCLK:
416 SET_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
417 break;
418 /* Select HCLK_DIV8 as Systick clock source */
419 case SYSTICK_CLKSOURCE_HCLK_DIV8:
420 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
421 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (0x00000000U));
422 break;
423 /* Select LSI as Systick clock source */
424 case SYSTICK_CLKSOURCE_LSI:
425 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
426 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_0);
427 break;
428 /* Select LSE as Systick clock source */
429 case SYSTICK_CLKSOURCE_LSE:
430 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
431 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_1);
432 break;
433 default:
434 /* Nothing to do */
435 break;
436 }
437 }
438
439 /**
440 * @brief Handle SYSTICK interrupt request.
441 * @retval None
442 */
HAL_SYSTICK_IRQHandler(void)443 void HAL_SYSTICK_IRQHandler(void)
444 {
445 HAL_SYSTICK_Callback();
446 }
447
448 /**
449 * @brief SYSTICK callback.
450 * @retval None
451 */
HAL_SYSTICK_Callback(void)452 __weak void HAL_SYSTICK_Callback(void)
453 {
454 /* NOTE : This function should not be modified, when the callback is needed,
455 the HAL_SYSTICK_Callback could be implemented in the user file
456 */
457 }
458
459
460 /**
461 * @brief Enable the MPU.
462 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
463 * NMI, FAULTMASK and privileged access to the default memory
464 * This parameter can be one of the following values:
465 * @arg MPU_HFNMI_PRIVDEF_NONE
466 * @arg MPU_HARDFAULT_NMI
467 * @arg MPU_PRIVILEGED_DEFAULT
468 * @arg MPU_HFNMI_PRIVDEF
469 * @retval None
470 */
HAL_MPU_Enable(uint32_t MPU_Control)471 void HAL_MPU_Enable(uint32_t MPU_Control)
472 {
473 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
474
475 /* Enable the MPU */
476 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
477
478 /* Enable fault exceptions */
479 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
480
481 /* Follow ARM recommendation with */
482 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
483 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
484 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
485 }
486
487 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
488 /**
489 * @brief Enable the non-secure MPU.
490 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
491 * NMI, FAULTMASK and privileged access to the default memory
492 * This parameter can be one of the following values:
493 * @arg MPU_HFNMI_PRIVDEF_NONE
494 * @arg MPU_HARDFAULT_NMI
495 * @arg MPU_PRIVILEGED_DEFAULT
496 * @arg MPU_HFNMI_PRIVDEF
497 * @retval None
498 */
HAL_MPU_Enable_NS(uint32_t MPU_Control)499 void HAL_MPU_Enable_NS(uint32_t MPU_Control)
500 {
501 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
502
503 /* Enable the MPU */
504 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
505
506 /* Enable fault exceptions */
507 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
508
509 /* Follow ARM recommendation with */
510 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
511 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
512 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
513 }
514 #endif /* __ARM_FEATURE_CMSE */
515
516 /**
517 * @brief Disable the MPU.
518 * @retval None
519 */
HAL_MPU_Disable(void)520 void HAL_MPU_Disable(void)
521 {
522 __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
523
524 /* Disable fault exceptions */
525 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
526
527 /* Disable the MPU */
528 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
529
530 /* Follow ARM recommendation with */
531 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
532 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
533 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
534 }
535
536 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
537 /**
538 * @brief Disable the non-secure MPU.
539 * @retval None
540 */
HAL_MPU_Disable_NS(void)541 void HAL_MPU_Disable_NS(void)
542 {
543 __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
544
545 /* Disable fault exceptions */
546 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
547
548 /* Disable the MPU */
549 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
550
551 /* Follow ARM recommendation with */
552 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
553 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
554 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
555 }
556 #endif /* __ARM_FEATURE_CMSE */
557
558 /**
559 * @brief Initialize and configure the Region and the memory to be protected.
560 * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
561 * the initialization and configuration information.
562 * @retval None
563 */
HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef * const pMPU_RegionInit)564 void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit)
565 {
566 MPU_ConfigRegion(MPU, pMPU_RegionInit);
567 }
568
569 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
570 /**
571 * @brief Initialize and configure the Region and the memory to be protected for non-secure MPU.
572 * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
573 * the initialization and configuration information.
574 * @retval None
575 */
HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef * const pMPU_RegionInit)576 void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit)
577 {
578 MPU_ConfigRegion(MPU_NS, pMPU_RegionInit);
579 }
580 #endif /* __ARM_FEATURE_CMSE */
581
582 /**
583 * @brief Initialize and configure the memory attributes.
584 * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains
585 * the initialization and configuration information.
586 * @retval None
587 */
HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef * const pMPU_AttributesInit)588 void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
589 {
590 MPU_ConfigMemoryAttributes(MPU, pMPU_AttributesInit);
591 }
592
593 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
594 /**
595 * @brief Initialize and configure the memory attributes for non-secure MPU.
596 * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains
597 * the initialization and configuration information.
598 * @retval None
599 */
HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef * const pMPU_AttributesInit)600 void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
601 {
602 MPU_ConfigMemoryAttributes(MPU_NS, pMPU_AttributesInit);
603 }
604 #endif /* __ARM_FEATURE_CMSE */
605
606 /**
607 * @}
608 */
609
610 /**
611 * @}
612 */
613
614 /** @addtogroup CORTEX_Private_Functions
615 * @{
616 */
MPU_ConfigRegion(MPU_Type * MPUx,const MPU_Region_InitTypeDef * const pMPU_RegionInit)617 static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit)
618 {
619 /* Check the parameters */
620 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
621 assert_param(IS_MPU_INSTANCE(MPUx));
622 #endif /* __ARM_FEATURE_CMSE */
623 assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number));
624 assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable));
625
626 /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */
627 __DMB();
628
629 /* Set the Region number */
630 MPUx->RNR = pMPU_RegionInit->Number;
631
632 if (pMPU_RegionInit->Enable != MPU_REGION_DISABLE)
633 {
634 /* Check the parameters */
635 assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec));
636 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission));
637 assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable));
638
639 MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) |
640 ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) |
641 ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) |
642 ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos));
643
644 MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) |
645 ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) |
646 ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos));
647 }
648 else
649 {
650 MPUx->RLAR = 0U;
651 MPUx->RBAR = 0U;
652 }
653 }
654
MPU_ConfigMemoryAttributes(MPU_Type * MPUx,const MPU_Attributes_InitTypeDef * const pMPU_AttributesInit)655 static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
656 {
657 __IO uint32_t *p_mair;
658 uint32_t attr_values;
659 uint32_t attr_number;
660
661 /* Check the parameters */
662 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
663 assert_param(IS_MPU_INSTANCE(MPUx));
664 #endif /* __ARM_FEATURE_CMSE */
665 assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_AttributesInit->Number));
666 /* No need to check Attributes value as all 0x0..0xFF possible */
667
668 /* Follow ARM recommendation with Data Memory Barrier prior to MPUx configuration */
669 __DMB();
670
671 if (pMPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4)
672 {
673 /* Program MPU_MAIR0 */
674 p_mair = &(MPUx->MAIR0);
675 attr_number = pMPU_AttributesInit->Number;
676 }
677 else
678 {
679 /* Program MPU_MAIR1 */
680 p_mair = &(MPUx->MAIR1);
681 attr_number = (uint32_t)pMPU_AttributesInit->Number - 4U;
682 }
683
684 attr_values = *(p_mair);
685 attr_values &= ~(0xFFUL << (attr_number * 8U));
686 *(p_mair) = attr_values | ((uint32_t)pMPU_AttributesInit->Attributes << (attr_number * 8U));
687 }
688 /**
689 * @}
690 */
691
692 #endif /* HAL_CORTEX_MODULE_ENABLED */
693 /**
694 * @}
695 */
696
697 /**
698 * @}
699 */
700
701
