1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_ll_usb.h 4 * @author MCD Application Team 5 * @brief Header file of USB Low Layer HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_LL_USB_H 21 #define STM32U5xx_LL_USB_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif /* __cplusplus */ 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) 31 /** @addtogroup STM32U5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup USB_LL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** 42 * @brief USB Mode definition 43 */ 44 45 typedef enum 46 { 47 USB_DEVICE_MODE = 0, 48 USB_HOST_MODE = 1, 49 USB_DRD_MODE = 2 50 } USB_ModeTypeDef; 51 52 /** 53 * @brief URB States definition 54 */ 55 typedef enum 56 { 57 URB_IDLE = 0, 58 URB_DONE, 59 URB_NOTREADY, 60 URB_NYET, 61 URB_ERROR, 62 URB_STALL 63 } USB_URBStateTypeDef; 64 65 /** 66 * @brief Host channel States definition 67 */ 68 typedef enum 69 { 70 HC_IDLE = 0, 71 HC_XFRC, 72 HC_HALTED, 73 HC_ACK, 74 HC_NAK, 75 HC_NYET, 76 HC_STALL, 77 HC_XACTERR, 78 HC_BBLERR, 79 HC_DATATGLERR 80 } USB_HCStateTypeDef; 81 82 83 /** 84 * @brief USB Instance Initialization Structure definition 85 */ 86 typedef struct 87 { 88 uint32_t dev_endpoints; /*!< Device Endpoints number. 89 This parameter depends on the used USB core. 90 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 91 92 uint32_t Host_channels; /*!< Host Channels number. 93 This parameter Depends on the used USB core. 94 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 95 96 uint32_t dma_enable; /*!< USB DMA state. 97 If DMA is not supported this parameter shall be set by default to zero */ 98 99 uint32_t speed; /*!< USB Core speed. 100 This parameter can be any value of @ref PCD_Speed/HCD_Speed 101 (HCD_SPEED_xxx, HCD_SPEED_xxx) */ 102 103 uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ 104 105 uint32_t phy_itface; /*!< Select the used PHY interface. 106 This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ 107 108 uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ 109 110 uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */ 111 112 uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ 113 114 uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ 115 116 uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ 117 118 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 119 uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ 120 121 uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ 122 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 123 #if defined (USB_DRD_FS) 124 uint32_t bulk_doublebuffer_enable; /*!< Enable or disable the double buffer mode on bulk EP */ 125 126 uint32_t iso_singlebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ 127 #endif /* defined (USB_DRD_FS) */ 128 } USB_CfgTypeDef; 129 130 typedef struct 131 { 132 uint8_t num; /*!< Endpoint number 133 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 134 135 uint8_t is_in; /*!< Endpoint direction 136 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 137 138 uint8_t is_stall; /*!< Endpoint stall condition 139 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 140 141 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 142 uint8_t is_iso_incomplete; /*!< Endpoint isoc condition 143 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 144 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 145 146 uint8_t type; /*!< Endpoint type 147 This parameter can be any value of @ref USB_LL_EP_Type */ 148 149 uint8_t data_pid_start; /*!< Initial data PID 150 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 151 152 #if defined (USB_DRD_FS) 153 uint16_t pmaadress; /*!< PMA Address 154 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 155 156 uint16_t pmaaddr0; /*!< PMA Address0 157 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 158 159 uint16_t pmaaddr1; /*!< PMA Address1 160 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 161 162 uint8_t doublebuffer; /*!< Double buffer enable 163 This parameter can be 0 or 1 */ 164 #endif /* defined (USB_DRD_FS) */ 165 166 uint32_t maxpacket; /*!< Endpoint Max packet size 167 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ 168 169 uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ 170 171 uint32_t xfer_len; /*!< Current transfer length */ 172 173 uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ 174 175 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 176 uint8_t even_odd_frame; /*!< IFrame parity 177 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 178 179 uint16_t tx_fifo_num; /*!< Transmission FIFO number 180 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 181 182 uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ 183 184 uint32_t xfer_size; /*!< requested transfer size */ 185 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 186 187 #if defined (USB_DRD_FS) 188 uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */ 189 190 uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ 191 #endif /* defined (USB_DRD_FS) */ 192 } USB_EPTypeDef; 193 194 typedef struct 195 { 196 uint8_t dev_addr; /*!< USB device address. 197 This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ 198 #if defined (USB_DRD_FS) 199 uint8_t phy_ch_num; /*!< Host channel number. 200 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 201 202 uint8_t ch_dir; /*!< channel direction 203 This parameter store the physical channel direction IN/OUT/BIDIR */ 204 #else 205 uint8_t ch_num; /*!< Host channel number. 206 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 207 208 uint8_t ep_is_in; /*!< Endpoint direction 209 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 210 #endif /* defined (USB_DRD_FS) */ 211 212 uint8_t ep_num; /*!< Endpoint number. 213 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 214 uint8_t speed; /*!< USB Host Channel speed. 215 This parameter can be any value of @ref HCD_Device_Speed: 216 (HCD_DEVICE_SPEED_xxx) */ 217 218 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 219 uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ 220 uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ 221 uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ 222 uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */ 223 uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */ 224 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 225 226 uint8_t hub_port_nbr; /*!< USB HUB port number */ 227 uint8_t hub_addr; /*!< USB HUB address */ 228 229 uint8_t ep_type; /*!< Endpoint Type. 230 This parameter can be any value of @ref USB_LL_EP_Type */ 231 232 uint16_t max_packet; /*!< Endpoint Max packet size. 233 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ 234 235 uint8_t data_pid; /*!< Initial data PID. 236 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 237 238 uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ 239 240 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 241 uint32_t XferSize; /*!< OTG Channel transfer size. */ 242 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 243 244 uint32_t xfer_len; /*!< Current transfer length. */ 245 #if defined (USB_DRD_FS) 246 uint32_t xfer_len_db; /*!< Current transfer length used in double buffer mode. */ 247 #endif /* defined (USB_DRD_FS) */ 248 249 uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ 250 251 uint8_t toggle_in; /*!< IN transfer current toggle flag. 252 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 253 254 uint8_t toggle_out; /*!< OUT transfer current toggle flag 255 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 256 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 257 uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ 258 uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ 259 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 260 261 uint32_t ErrCnt; /*!< Host channel error count. */ 262 263 #if defined (USB_DRD_FS) 264 uint16_t pmaadress; /*!< PMA Address 265 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 266 267 uint16_t pmaaddr0; /*!< PMA Address0 268 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 269 270 uint16_t pmaaddr1; /*!< PMA Address1 271 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 272 273 uint8_t doublebuffer; /*!< Double buffer enable 274 This parameter can be 0 or 1 */ 275 #endif /* defined (USB_DRD_FS) */ 276 277 USB_URBStateTypeDef urb_state; /*!< URB state. 278 This parameter can be any value of @ref USB_URBStateTypeDef */ 279 280 USB_HCStateTypeDef state; /*!< Host Channel state. 281 This parameter can be any value of @ref USB_HCStateTypeDef */ 282 } USB_HCTypeDef; 283 284 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 285 typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; 286 typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; 287 typedef USB_EPTypeDef USB_OTG_EPTypeDef; 288 typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; 289 typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; 290 typedef USB_HCTypeDef USB_OTG_HCTypeDef; 291 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 292 #if defined (USB_DRD_FS) 293 typedef USB_ModeTypeDef USB_DRD_ModeTypeDef; 294 typedef USB_CfgTypeDef USB_DRD_CfgTypeDef; 295 typedef USB_EPTypeDef USB_DRD_EPTypeDef; 296 typedef USB_URBStateTypeDef USB_DRD_URBStateTypeDef; 297 typedef USB_HCStateTypeDef USB_DRD_HCStateTypeDef; 298 typedef USB_HCTypeDef USB_DRD_HCTypeDef; 299 #endif /* defined (USB_DRD_FS) */ 300 301 /* Exported constants --------------------------------------------------------*/ 302 303 /** @defgroup PCD_Exported_Constants PCD Exported Constants 304 * @{ 305 */ 306 307 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 308 /** @defgroup USB_OTG_CORE VERSION ID 309 * @{ 310 */ 311 #define USB_OTG_CORE_ID_300A 0x4F54300AU 312 #define USB_OTG_CORE_ID_310A 0x4F54310AU 313 /** 314 * @} 315 */ 316 317 /** @defgroup USB_Core_Mode_ USB Core Mode 318 * @{ 319 */ 320 #define USB_OTG_MODE_DEVICE 0U 321 #define USB_OTG_MODE_HOST 1U 322 #define USB_OTG_MODE_DRD 2U 323 /** 324 * @} 325 */ 326 327 /** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed 328 * @{ 329 */ 330 #define USB_OTG_SPEED_HIGH 0U 331 #define USB_OTG_SPEED_HIGH_IN_FULL 1U 332 #define USB_OTG_SPEED_FULL 3U 333 /** 334 * @} 335 */ 336 337 /** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY 338 * @{ 339 */ 340 #define USB_OTG_EMBEDDED_PHY 2U 341 #define USB_OTG_HS_EMBEDDED_PHY 3U 342 /** 343 * @} 344 */ 345 346 /** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value 347 * @{ 348 */ 349 #ifndef USBD_HS_TRDT_VALUE 350 #define USBD_HS_TRDT_VALUE 9U 351 #endif /* USBD_HS_TRDT_VALUE */ 352 #ifndef USBD_FS_TRDT_VALUE 353 #define USBD_FS_TRDT_VALUE 5U 354 #define USBD_DEFAULT_TRDT_VALUE 9U 355 #endif /* USBD_HS_TRDT_VALUE */ 356 /** 357 * @} 358 */ 359 360 /** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS 361 * @{ 362 */ 363 #define USB_OTG_HS_MAX_PACKET_SIZE 512U 364 #define USB_OTG_FS_MAX_PACKET_SIZE 64U 365 #define USB_OTG_MAX_EP0_SIZE 64U 366 /** 367 * @} 368 */ 369 370 /** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency 371 * @{ 372 */ 373 #define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) 374 #define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) 375 #define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) 376 /** 377 * @} 378 */ 379 380 /** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval 381 * @{ 382 */ 383 #define DCFG_FRAME_INTERVAL_80 0U 384 #define DCFG_FRAME_INTERVAL_85 1U 385 #define DCFG_FRAME_INTERVAL_90 2U 386 #define DCFG_FRAME_INTERVAL_95 3U 387 /** 388 * @} 389 */ 390 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 391 /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS 392 * @{ 393 */ 394 #define EP_MPS_64 0U 395 #define EP_MPS_32 1U 396 #define EP_MPS_16 2U 397 #define EP_MPS_8 3U 398 /** 399 * @} 400 */ 401 402 /** @defgroup USB_LL_EP_Type USB Low Layer EP Type 403 * @{ 404 */ 405 #define EP_TYPE_CTRL 0U 406 #define EP_TYPE_ISOC 1U 407 #define EP_TYPE_BULK 2U 408 #define EP_TYPE_INTR 3U 409 #define EP_TYPE_MSK 3U 410 /** 411 * @} 412 */ 413 414 /** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed 415 * @{ 416 */ 417 #define EP_SPEED_LOW 0U 418 #define EP_SPEED_FULL 1U 419 #define EP_SPEED_HIGH 2U 420 /** 421 * @} 422 */ 423 424 /** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type 425 * @{ 426 */ 427 #define HC_PID_DATA0 0U 428 #define HC_PID_DATA2 1U 429 #define HC_PID_DATA1 2U 430 #define HC_PID_SETUP 3U 431 /** 432 * @} 433 */ 434 435 /** @defgroup USB_LL Device Speed 436 * @{ 437 */ 438 #define USBD_HS_SPEED 0U 439 #define USBD_HSINFS_SPEED 1U 440 #define USBH_HS_SPEED 0U 441 #define USBD_FS_SPEED 2U 442 #define USBH_FSLS_SPEED 1U 443 /** 444 * @} 445 */ 446 447 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 448 /** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines 449 * @{ 450 */ 451 #define STS_GOUT_NAK 1U 452 #define STS_DATA_UPDT 2U 453 #define STS_XFER_COMP 3U 454 #define STS_SETUP_COMP 4U 455 #define STS_SETUP_UPDT 6U 456 /** 457 * @} 458 */ 459 460 /** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines 461 * @{ 462 */ 463 #define HCFG_30_60_MHZ 0U 464 #define HCFG_48_MHZ 1U 465 #define HCFG_6_MHZ 2U 466 /** 467 * @} 468 */ 469 470 /** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines 471 * @{ 472 */ 473 #define HFIR_6_MHZ 6000U 474 #define HFIR_60_MHZ 60000U 475 #define HFIR_48_MHZ 48000U 476 /** 477 * @} 478 */ 479 480 /** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines 481 * @{ 482 */ 483 #define HPRT0_PRTSPD_HIGH_SPEED 0U 484 #define HPRT0_PRTSPD_FULL_SPEED 1U 485 #define HPRT0_PRTSPD_LOW_SPEED 2U 486 /** 487 * @} 488 */ 489 490 #define HCCHAR_CTRL 0U 491 #define HCCHAR_ISOC 1U 492 #define HCCHAR_BULK 2U 493 #define HCCHAR_INTR 3U 494 495 #define GRXSTS_PKTSTS_IN 2U 496 #define GRXSTS_PKTSTS_IN_XFER_COMP 3U 497 #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U 498 #define GRXSTS_PKTSTS_CH_HALTED 7U 499 500 #define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU 501 502 #define HC_MAX_PKT_CNT 256U 503 #define ISO_SPLT_MPS 188U 504 505 #define HCSPLT_BEGIN 1U 506 #define HCSPLT_MIDDLE 2U 507 #define HCSPLT_END 3U 508 #define HCSPLT_FULL 4U 509 510 #define TEST_J 1U 511 #define TEST_K 2U 512 #define TEST_SE0_NAK 3U 513 #define TEST_PACKET 4U 514 #define TEST_FORCE_EN 5U 515 516 #define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) 517 #define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) 518 519 #define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) 520 #define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\ 521 + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) 522 523 #define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\ 524 + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) 525 526 #define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) 527 528 #define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) 529 #define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\ 530 + USB_OTG_HOST_CHANNEL_BASE\ 531 + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) 532 533 534 #define EP_ADDR_MSK 0xFU 535 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 536 #if defined (USB_DRD_FS) 537 #define EP_ADDR_MSK 0x7U 538 539 #ifndef USE_USB_DOUBLE_BUFFER 540 #define USE_USB_DOUBLE_BUFFER 1U 541 #endif /* USE_USB_DOUBLE_BUFFER */ 542 543 #define USB_EMBEDDED_PHY 2U 544 545 /*!< USB Speed */ 546 #define USB_DRD_SPEED_FS 1U 547 #define USB_DRD_SPEED_LS 2U 548 #define USB_DRD_SPEED_LSFS 3U 549 550 /*!< Channel Direction */ 551 #define CH_IN_DIR 1U 552 #define CH_OUT_DIR 0U 553 554 /*!< Number of used channels in the Application */ 555 #ifndef USB_DRD_USED_CHANNELS 556 #define USB_DRD_USED_CHANNELS 8U 557 #endif /* USB_DRD_USED_CHANNELS */ 558 559 /** 560 * used for USB_HC_DoubleBuffer API 561 */ 562 #define USB_DRD_BULK_DBUFF_ENBALE 1U 563 #define USB_DRD_BULK_DBUFF_DISABLE 2U 564 #define USB_DRD_ISOC_DBUFF_ENBALE 3U 565 #define USB_DRD_ISOC_DBUFF_DISABLE 4U 566 567 /* First available address in PMA */ 568 #define PMA_START_ADDR (0x10U + (8U *(USB_DRD_USED_CHANNELS - 2U))) 569 #define PMA_END_ADDR USB_DRD_PMA_SIZE 570 571 /* Exported macro ------------------------------------------------------------*/ 572 /** 573 * @} 574 */ 575 /******************** Bit definition for USB_COUNTn_RX register *************/ 576 #define USB_CNTRX_NBLK_MSK (0x1FU << 26) 577 #define USB_CNTRX_BLSIZE (0x1U << 31) 578 579 580 /*Set Channel/Endpoint to the USB Register */ 581 #define USB_DRD_SET_CHEP(USBx, bEpChNum, wRegValue) (*(__IO uint32_t *)\ 582 (&(USBx)->CHEP0R + (bEpChNum)) = (uint32_t)(wRegValue)) 583 584 /*Get Channel/Endpoint from the USB Register */ 585 #define USB_DRD_GET_CHEP(USBx, bEpChNum) (*(__IO uint32_t *)(&(USBx)->CHEP0R + (bEpChNum))) 586 587 588 /** 589 * @brief free buffer used from the application realizing it to the line 590 * toggles bit SW_BUF in the double buffered endpoint register 591 * @param USBx USB device. 592 * @param bEpChNum, bDir 593 * @retval None 594 */ 595 #define USB_DRD_FREE_USER_BUFFER(USBx, bEpChNum, bDir) \ 596 do { \ 597 if ((bDir) == 0U) \ 598 { \ 599 /* OUT double buffered endpoint */ \ 600 USB_DRD_TX_DTOG((USBx), (bEpChNum)); \ 601 } \ 602 else if ((bDir) == 1U) \ 603 { \ 604 /* IN double buffered endpoint */ \ 605 USB_DRD_RX_DTOG((USBx), (bEpChNum)); \ 606 } \ 607 } while(0) 608 609 610 /** 611 * @brief Set the Setup bit in the corresponding channel, when a Setup 612 transaction is needed. 613 * @param USBx USB device. 614 * @param bEpChNum 615 * @retval None 616 */ 617 #define USB_DRD_CHEP_TX_SETUP(USBx, bEpChNum) \ 618 do { \ 619 uint32_t _wRegVal; \ 620 \ 621 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) ; \ 622 \ 623 /* Set Setup bit */ \ 624 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_SETUP)); \ 625 } while(0) 626 627 628 /** 629 * @brief Clears bit ERR_RX in the Channel register 630 * @param USBx USB peripheral instance register address. 631 * @param bChNum Endpoint Number. 632 * @retval None 633 */ 634 #define USB_DRD_CLEAR_CHEP_RX_ERR(USBx, bChNum) \ 635 do { \ 636 uint32_t _wRegVal; \ 637 \ 638 _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \ 639 _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRRX) & (~USB_CHEP_VTRX)) | \ 640 (USB_CHEP_VTTX | USB_CHEP_ERRTX); \ 641 \ 642 USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \ 643 } while(0) /* USB_DRD_CLEAR_CHEP_RX_ERR */ 644 645 646 /** 647 * @brief Clears bit ERR_TX in the Channel register 648 * @param USBx USB peripheral instance register address. 649 * @param bChNum Endpoint Number. 650 * @retval None 651 */ 652 #define USB_DRD_CLEAR_CHEP_TX_ERR(USBx, bChNum) \ 653 do { \ 654 uint32_t _wRegVal; \ 655 \ 656 _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \ 657 _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRTX) & (~USB_CHEP_VTTX)) | \ 658 (USB_CHEP_VTRX|USB_CHEP_ERRRX); \ 659 \ 660 USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \ 661 } while(0) /* USB_DRD_CLEAR_CHEP_TX_ERR */ 662 663 664 /** 665 * @brief sets the status for tx transfer (bits STAT_TX[1:0]). 666 * @param USBx USB peripheral instance register address. 667 * @param bEpChNum Endpoint Number. 668 * @param wState new state 669 * @retval None 670 */ 671 #define USB_DRD_SET_CHEP_TX_STATUS(USBx, bEpChNum, wState) \ 672 do { \ 673 uint32_t _wRegVal; \ 674 \ 675 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_TX_DTOGMASK; \ 676 /* toggle first bit ? */ \ 677 if ((USB_CHEP_TX_DTOG1 & (wState)) != 0U) \ 678 { \ 679 _wRegVal ^= USB_CHEP_TX_DTOG1; \ 680 } \ 681 /* toggle second bit ? */ \ 682 if ((USB_CHEP_TX_DTOG2 & (wState)) != 0U) \ 683 { \ 684 _wRegVal ^= USB_CHEP_TX_DTOG2; \ 685 } \ 686 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX| USB_CHEP_VTTX)); \ 687 } while(0) /* USB_DRD_SET_CHEP_TX_STATUS */ 688 689 690 /** 691 * @brief sets the status for rx transfer (bits STAT_TX[1:0]) 692 * @param USBx USB peripheral instance register address. 693 * @param bEpChNum Endpoint Number. 694 * @param wState new state 695 * @retval None 696 */ 697 #define USB_DRD_SET_CHEP_RX_STATUS(USBx, bEpChNum, wState) \ 698 do { \ 699 uint32_t _wRegVal; \ 700 \ 701 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_RX_DTOGMASK; \ 702 /* toggle first bit ? */ \ 703 if ((USB_CHEP_RX_DTOG1 & (wState)) != 0U) \ 704 { \ 705 _wRegVal ^= USB_CHEP_RX_DTOG1; \ 706 } \ 707 /* toggle second bit ? */ \ 708 if ((USB_CHEP_RX_DTOG2 & (wState)) != 0U) \ 709 { \ 710 _wRegVal ^= USB_CHEP_RX_DTOG2; \ 711 } \ 712 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ 713 } while(0) /* USB_DRD_SET_CHEP_RX_STATUS */ 714 715 716 /** 717 * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] 718 * /STAT_RX[1:0]) 719 * @param USBx USB peripheral instance register address. 720 * @param bEpChNum Endpoint Number. 721 * @retval status 722 */ 723 #define USB_DRD_GET_CHEP_TX_STATUS(USBx, bEpChNum) \ 724 ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_TX_STTX) 725 726 #define USB_DRD_GET_CHEP_RX_STATUS(USBx, bEpChNum) \ 727 ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_RX_STRX) 728 729 730 /** 731 * @brief set EP_KIND bit. 732 * @param USBx USB peripheral instance register address. 733 * @param bEpChNum Endpoint Number. 734 * @retval None 735 */ 736 #define USB_DRD_SET_CHEP_KIND(USBx, bEpChNum) \ 737 do { \ 738 uint32_t _wRegVal; \ 739 \ 740 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ 741 \ 742 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_KIND)); \ 743 } while(0) /* USB_DRD_SET_CHEP_KIND */ 744 745 746 /** 747 * @brief clear EP_KIND bit. 748 * @param USBx USB peripheral instance register address. 749 * @param bEpChNum Endpoint Number. 750 * @retval None 751 */ 752 #define USB_DRD_CLEAR_CHEP_KIND(USBx, bEpChNum) \ 753 do { \ 754 uint32_t _wRegVal; \ 755 \ 756 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_EP_KIND_MASK; \ 757 \ 758 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ 759 } while(0) /* USB_DRD_CLEAR_CHEP_KIND */ 760 761 762 /** 763 * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. 764 * @param USBx USB peripheral instance register address. 765 * @param bEpChNum Endpoint Number. 766 * @retval None 767 */ 768 #define USB_DRD_CLEAR_RX_CHEP_CTR(USBx, bEpChNum) \ 769 do { \ 770 uint32_t _wRegVal; \ 771 \ 772 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFF7FFFU & USB_CHEP_REG_MASK); \ 773 \ 774 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTTX)); \ 775 } while(0) /* USB_CLEAR_RX_CHEP_CTR */ 776 777 #define USB_DRD_CLEAR_TX_CHEP_CTR(USBx, bEpChNum) \ 778 do { \ 779 uint32_t _wRegVal; \ 780 \ 781 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFFFF7FU & USB_CHEP_REG_MASK); \ 782 \ 783 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX)); \ 784 } while(0) /* USB_CLEAR_TX_CHEP_CTR */ 785 786 787 /** 788 * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. 789 * @param USBx USB peripheral instance register address. 790 * @param bEpChNum Endpoint Number. 791 * @retval None 792 */ 793 #define USB_DRD_RX_DTOG(USBx, bEpChNum) \ 794 do { \ 795 uint32_t _wEPVal; \ 796 \ 797 _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ 798 \ 799 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX)); \ 800 } while(0) /* USB_DRD_RX_DTOG */ 801 802 #define USB_DRD_TX_DTOG(USBx, bEpChNum) \ 803 do { \ 804 uint32_t _wEPVal; \ 805 \ 806 _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ 807 \ 808 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX)); \ 809 } while(0) /* USB_TX_DTOG */ 810 811 812 /** 813 * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. 814 * @param USBx USB peripheral instance register address. 815 * @param bEpChNum Endpoint Number. 816 * @retval None 817 */ 818 #define USB_DRD_CLEAR_RX_DTOG(USBx, bEpChNum) \ 819 do { \ 820 uint32_t _wRegVal; \ 821 \ 822 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \ 823 \ 824 if ((_wRegVal & USB_CHEP_DTOG_RX) != 0U) \ 825 { \ 826 USB_DRD_RX_DTOG((USBx), (bEpChNum)); \ 827 } \ 828 } while(0) /* USB_DRD_CLEAR_RX_DTOG */ 829 830 #define USB_DRD_CLEAR_TX_DTOG(USBx, bEpChNum) \ 831 do { \ 832 uint32_t _wRegVal; \ 833 \ 834 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \ 835 \ 836 if ((_wRegVal & USB_CHEP_DTOG_TX) != 0U) \ 837 { \ 838 USB_DRD_TX_DTOG((USBx), (bEpChNum)); \ 839 } \ 840 } while(0) /* USB_DRD_CLEAR_TX_DTOG */ 841 842 843 /** 844 * @brief Sets address in an endpoint register. 845 * @param USBx USB peripheral instance register address. 846 * @param bEpChNum Endpoint Number. 847 * @param bAddr Address. 848 * @retval None 849 */ 850 #define USB_DRD_SET_CHEP_ADDRESS(USBx, bEpChNum, bAddr) \ 851 do { \ 852 uint32_t _wRegVal; \ 853 \ 854 /*Read the USB->CHEPx into _wRegVal, Reset(DTOGRX/STRX/DTOGTX/STTX) and set the EpAddress*/ \ 855 _wRegVal = (USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK) | (bAddr); \ 856 \ 857 /*Set _wRegVal in USB->CHEPx and set Transmit/Receive Valid Transfer (x=bEpChNum)*/ \ 858 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ 859 } while(0) /* USB_DRD_SET_CHEP_ADDRESS */ 860 861 862 /* PMA API Buffer Descriptor Management ------------------------------------------------------------*/ 863 /* Buffer Descriptor Table TXBD0/RXBD0 --- > TXBD7/RXBD7 8 possible descriptor 864 * The buffer descriptor is located inside the packet buffer memory (USB_PMA_BUFF) 865 * TXBD [Reserve |Countx| Address_Tx] 866 * RXBD [BLSIEZ|NUM_Block |CounRx| Address_Rx] */ 867 868 /* Set TX Buffer Descriptor Address Field */ 869 #define USB_DRD_SET_CHEP_TX_ADDRESS(USBx, bEpChNum, wAddr) \ 870 do { \ 871 /* Reset old Address */ \ 872 (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_ADDMSK; \ 873 \ 874 /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \ 875 (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \ 876 } while(0) /* USB_DRD_SET_CHEP_TX_ADDRESS */ 877 878 /* Set RX Buffer Descriptor Address Field */ 879 #define USB_DRD_SET_CHEP_RX_ADDRESS(USBx, bEpChNum, wAddr) \ 880 do { \ 881 /* Reset old Address */ \ 882 (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_RXBD_ADDMSK; \ 883 \ 884 /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \ 885 (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \ 886 } while(0) /* USB_SET_CHEP_RX_ADDRESS */ 887 888 889 /** 890 * @brief Sets counter of rx buffer with no. of blocks. 891 * @param pdwReg Register pointer 892 * @param wCount Counter. 893 * @param wNBlocks no. of Blocks. 894 * @retval None 895 */ 896 #define USB_DRD_CALC_BLK32(pdwReg, wCount, wNBlocks) \ 897 do { \ 898 /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \ 899 (wNBlocks) =((uint32_t)(wCount) >> 5U); \ 900 if (((uint32_t)(wCount) % 32U) == 0U) \ 901 { \ 902 (wNBlocks)--; \ 903 } \ 904 \ 905 (pdwReg)|= (uint32_t)((((wNBlocks) << 26U)) | USB_CNTRX_BLSIZE); \ 906 } while(0) /* USB_DRD_CALC_BLK32 */ 907 908 #define USB_DRD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ 909 do { \ 910 /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \ 911 (wNBlocks) = (uint32_t)((uint32_t)(wCount) >> 1U); \ 912 if (((wCount) & 0x1U) != 0U) \ 913 { \ 914 (wNBlocks)++; \ 915 } \ 916 (pdwReg) |= (uint32_t)((wNBlocks) << 26U); \ 917 } while(0) /* USB_DRD_CALC_BLK2 */ 918 919 #define USB_DRD_SET_CHEP_CNT_RX_REG(pdwReg, wCount) \ 920 do { \ 921 uint32_t wNBlocks; \ 922 \ 923 (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ 924 \ 925 if ((wCount) > 62U) \ 926 { \ 927 USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ 928 } \ 929 else \ 930 { \ 931 if ((wCount) == 0U) \ 932 { \ 933 (pdwReg) |= USB_CNTRX_BLSIZE; \ 934 } \ 935 else \ 936 { \ 937 USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ 938 } \ 939 } \ 940 } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ 941 942 943 /** 944 * @brief sets counter for the tx/rx buffer. 945 * @param USBx USB peripheral instance register address. 946 * @param bEpChNum Endpoint Number. 947 * @param wCount Counter value. 948 * @retval None 949 */ 950 #define USB_DRD_SET_CHEP_TX_CNT(USBx,bEpChNum, wCount) \ 951 do { \ 952 /* Reset old TX_Count value */ \ 953 (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_COUNTMSK; \ 954 \ 955 /* Set the wCount in the dedicated EP_TXBuffer */ \ 956 (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \ 957 } while(0) 958 959 #define USB_DRD_SET_CHEP_RX_DBUF0_CNT(USBx, bEpChNum, wCount) \ 960 USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD), (wCount)) 961 962 #define USB_DRD_SET_CHEP_RX_CNT(USBx, bEpChNum, wCount) \ 963 USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD), (wCount)) 964 965 /** 966 * @brief gets counter of the tx buffer. 967 * @param USBx USB peripheral instance register address. 968 * @param bEpChNum Endpoint Number. 969 * @retval Counter value 970 */ 971 #define USB_DRD_GET_CHEP_TX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD & 0x03FF0000U) >> 16U) 972 #define USB_DRD_GET_CHEP_RX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD & 0x03FF0000U) >> 16U) 973 974 #define USB_DRD_GET_EP_TX_CNT USB_GET_CHEP_TX_CNT 975 #define USB_DRD_GET_CH_TX_CNT USB_GET_CHEP_TX_CNT 976 977 #define USB_DRD_GET_EP_RX_CNT USB_DRD_GET_CHEP_RX_CNT 978 #define USB_DRD_GET_CH_RX_CNT USB_DRD_GET_CHEP_RX_CNT 979 /** 980 * @brief Sets buffer 0/1 address in a double buffer endpoint. 981 * @param USBx USB peripheral instance register address. 982 * @param bEpChNum Endpoint Number. 983 * @param wBuf0Addr buffer 0 address. 984 * @retval Counter value 985 */ 986 #define USB_DRD_SET_CHEP_DBUF0_ADDR(USBx, bEpChNum, wBuf0Addr) \ 987 USB_DRD_SET_CHEP_TX_ADDRESS((USBx), (bEpChNum), (wBuf0Addr)) 988 989 #define USB_DRD_SET_CHEP_DBUF1_ADDR(USBx, bEpChNum, wBuf1Addr) \ 990 USB_DRD_SET_CHEP_RX_ADDRESS((USBx), (bEpChNum), (wBuf1Addr)) 991 992 993 /** 994 * @brief Sets addresses in a double buffer endpoint. 995 * @param USBx USB peripheral instance register address. 996 * @param bEpChNum Endpoint Number. 997 * @param wBuf0Addr: buffer 0 address. 998 * @param wBuf1Addr = buffer 1 address. 999 * @retval None 1000 */ 1001 #define USB_DRD_SET_CHEP_DBUF_ADDR(USBx, bEpChNum, wBuf0Addr, wBuf1Addr) \ 1002 do { \ 1003 USB_DRD_SET_CHEP_DBUF0_ADDR((USBx), (bEpChNum), (wBuf0Addr)); \ 1004 USB_DRD_SET_CHEP_DBUF1_ADDR((USBx), (bEpChNum), (wBuf1Addr)); \ 1005 } while(0) /* USB_DRD_SET_CHEP_DBUF_ADDR */ 1006 1007 1008 /** 1009 * @brief Gets buffer 0/1 address of a double buffer endpoint. 1010 * @param USBx USB peripheral instance register address. 1011 * @param bEpChNum Endpoint Number. 1012 * @param bDir endpoint dir EP_DBUF_OUT = OUT 1013 * EP_DBUF_IN = IN 1014 * @param wCount: Counter value 1015 * @retval None 1016 */ 1017 #define USB_DRD_SET_CHEP_DBUF0_CNT(USBx, bEpChNum, bDir, wCount) \ 1018 do { \ 1019 if ((bDir) == 0U) \ 1020 { \ 1021 /* OUT endpoint */ \ 1022 USB_DRD_SET_CHEP_RX_DBUF0_CNT((USBx), (bEpChNum), (wCount)); \ 1023 } \ 1024 else \ 1025 { \ 1026 if ((bDir) == 1U) \ 1027 { \ 1028 /* IN endpoint */ \ 1029 USB_DRD_SET_CHEP_TX_CNT((USBx), (bEpChNum), (wCount)); \ 1030 } \ 1031 } \ 1032 } while(0) /* USB_DRD_SET_CHEP_DBUF0_CNT */ 1033 1034 #define USB_DRD_SET_CHEP_DBUF1_CNT(USBx, bEpChNum, bDir, wCount) \ 1035 do { \ 1036 if ((bDir) == 0U) \ 1037 { \ 1038 /* OUT endpoint */ \ 1039 USB_DRD_SET_CHEP_RX_CNT((USBx), (bEpChNum), (wCount)); \ 1040 } \ 1041 else \ 1042 { \ 1043 if ((bDir) == 1U) \ 1044 { \ 1045 /* IN endpoint */ \ 1046 (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_TXBD_COUNTMSK; \ 1047 (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \ 1048 } \ 1049 } \ 1050 } while(0) /* USB_DRD_SET_CHEP_DBUF1_CNT */ 1051 1052 #define USB_DRD_SET_CHEP_DBUF_CNT(USBx, bEpChNum, bDir, wCount) \ 1053 do { \ 1054 USB_DRD_SET_CHEP_DBUF0_CNT((USBx), (bEpChNum), (bDir), (wCount)); \ 1055 USB_DRD_SET_CHEP_DBUF1_CNT((USBx), (bEpChNum), (bDir), (wCount)); \ 1056 } while(0) /* USB_DRD_SET_EPCH_DBUF_CNT */ 1057 1058 /** 1059 * @brief Gets buffer 0/1 rx/tx counter for double buffering. 1060 * @param USBx USB peripheral instance register address. 1061 * @param bEpChNum Endpoint Number. 1062 * @retval None 1063 */ 1064 #define USB_DRD_GET_CHEP_DBUF0_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_TX_CNT((USBx), (bEpChNum))) 1065 #define USB_DRD_GET_CHEP_DBUF1_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_RX_CNT((USBx), (bEpChNum))) 1066 #endif /* defined (USB_DRD_FS) */ 1067 /** 1068 * @} 1069 */ 1070 1071 /* Exported macro ------------------------------------------------------------*/ 1072 /** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros 1073 * @{ 1074 */ 1075 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 1076 #define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) 1077 #define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) 1078 1079 #define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) 1080 #define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) 1081 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 1082 /** 1083 * @} 1084 */ 1085 1086 /* Exported functions --------------------------------------------------------*/ 1087 /** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions 1088 * @{ 1089 */ 1090 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 1091 HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); 1092 HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); 1093 HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); 1094 HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); 1095 HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); 1096 HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); 1097 HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed); 1098 HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); 1099 HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); 1100 HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); 1101 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); 1102 HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); 1103 HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); 1104 HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); 1105 HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, 1106 uint8_t ch_ep_num, uint16_t len, uint8_t dma); 1107 1108 void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); 1109 HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); 1110 HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); 1111 HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); 1112 HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); 1113 HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); 1114 HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); 1115 HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); 1116 HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx); 1117 HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup); 1118 uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); 1119 uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); 1120 uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx); 1121 uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); 1122 uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx); 1123 uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); 1124 uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx); 1125 uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); 1126 void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); 1127 1128 HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); 1129 HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq); 1130 HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); 1131 HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state); 1132 uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); 1133 uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); 1134 HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, 1135 uint8_t epnum, uint8_t dev_address, uint8_t speed, 1136 uint8_t ep_type, uint16_t mps); 1137 HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, 1138 USB_OTG_HCTypeDef *hc, uint8_t dma); 1139 1140 uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); 1141 HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); 1142 HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); 1143 HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); 1144 HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); 1145 HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); 1146 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 1147 1148 #if defined (USB_DRD_FS) 1149 HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); 1150 HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); 1151 HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx); 1152 HAL_StatusTypeDef USB_DisableGlobalInt(USB_DRD_TypeDef *USBx); 1153 HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef mode); 1154 1155 HAL_StatusTypeDef USB_FlushRxFifo(USB_DRD_TypeDef const *USBx); 1156 HAL_StatusTypeDef USB_FlushTxFifo(USB_DRD_TypeDef const *USBx, uint32_t num); 1157 1158 #if defined (HAL_PCD_MODULE_ENABLED) 1159 HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 1160 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 1161 HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 1162 HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 1163 HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 1164 HAL_StatusTypeDef USB_EPStopXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 1165 #endif /* defined (HAL_PCD_MODULE_ENABLED) */ 1166 1167 HAL_StatusTypeDef USB_SetDevAddress(USB_DRD_TypeDef *USBx, uint8_t address); 1168 HAL_StatusTypeDef USB_DevConnect(USB_DRD_TypeDef *USBx); 1169 HAL_StatusTypeDef USB_DevDisconnect(USB_DRD_TypeDef *USBx); 1170 HAL_StatusTypeDef USB_StopDevice(USB_DRD_TypeDef *USBx); 1171 uint32_t USB_ReadInterrupts(USB_DRD_TypeDef const *USBx); 1172 1173 HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx); 1174 HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); 1175 HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); 1176 HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); 1177 HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc); 1178 1179 uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx); 1180 uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); 1181 HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx); 1182 HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t db_state); 1183 HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t epnum, 1184 uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); 1185 1186 HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx); 1187 HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx); 1188 1189 void USB_WritePMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, 1190 uint16_t wPMABufAddr, uint16_t wNBytes); 1191 1192 void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, 1193 uint16_t wPMABufAddr, uint16_t wNBytes); 1194 #endif /* defined (USB_DRD_FS) */ 1195 /** 1196 * @} 1197 */ 1198 1199 /** 1200 * @} 1201 */ 1202 1203 /** 1204 * @} 1205 */ 1206 1207 /** 1208 * @} 1209 */ 1210 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ 1211 1212 #ifdef __cplusplus 1213 } 1214 #endif /* __cplusplus */ 1215 1216 1217 #endif /* STM32U5xx_LL_USB_H */ 1218
