1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U5xx_LL_DAC_H
21 #define STM32U5xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u5xx.h"
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined(DAC1)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 /* - channel register offset of sample-and-hold sample time register SHSRx */
55 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
56 CR, MCR, CCR, SHHR, SHRR of channel 1 */
57 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
58 CR, MCR, CCR, SHHR, SHRR of channel 2 */
59 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
60
61 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
62 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
63 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
64
65 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
66 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
67 DHR12Rx channel 1 (shifted left of 20 bits) */
68 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
69 DHR12Rx channel 1 (shifted left of 24 bits) */
70
71 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
72 DHR12Rx channel 1 (shifted left of 28 bits) */
73 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
74 DHR12Rx channel 1 (shifted left of 20 bits) */
75 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
76 DHR12Rx channel 1 (shifted left of 24 bits) */
77
78 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
79 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
80 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
81 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
82 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
83
84 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
85
86 #define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
87 DORx channel 2 (shifted left of 5 bits) */
88 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
89
90 #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
91 #define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
92 SHSRx channel 2 (shifted left of 6 bits) */
93 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
94
95
96 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
97 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
98 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
99 to position 0 */
100 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
101 to position 0 */
102
103 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
104 channel 1 or 2 versus DHR12Rx channel 1
105 (shifted left of 28 bits) */
106 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
107 channel 1 or 2 versus DHR12Rx channel 1
108 (shifted left of 20 bits) */
109 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
110 channel 1 or 2 versus DHR12Rx channel 1
111 (shifted left of 24 bits) */
112 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
113 channel 1 or 2 versus DORx channel 1
114 (shifted left of 5 bits) */
115 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
116 channel 1 or 2 versus SHSRx channel 1
117 (shifted left of 6 bits) */
118
119 /* DAC registers bits positions */
120 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
121 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
122 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
123
124 /* Miscellaneous data */
125 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
126 bits (voltage range determined by analog voltage
127 references Vref+ and Vref-, refer to reference manual) */
128
129 /**
130 * @}
131 */
132
133
134 /* Private macros ------------------------------------------------------------*/
135 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
136 * @{
137 */
138
139 /**
140 * @brief Driver macro reserved for internal use: set a pointer to
141 * a register from a register basis from which an offset
142 * is applied.
143 * @param __REG__ Register basis from which the offset is applied.
144 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
145 * @retval Pointer to register address
146 */
147 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
148 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
149
150 /**
151 * @}
152 */
153
154
155 /* Exported types ------------------------------------------------------------*/
156 #if defined(USE_FULL_LL_DRIVER)
157 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
158 * @{
159 */
160
161 /**
162 * @brief Structure definition of some features of DAC instance.
163 */
164 typedef struct
165 {
166 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
167 internal (SW start) or from external peripheral
168 (timer event, external interrupt line).
169 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
170
171 This feature can be modified afterwards using unitary
172 function @ref LL_DAC_SetTriggerSource(). */
173
174 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
175 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
176
177 This feature can be modified afterwards using unitary
178 function @ref LL_DAC_SetWaveAutoGeneration(). */
179
180 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
181 If waveform automatic generation mode is set to noise, this parameter
182 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
183 If waveform automatic generation mode is set to triangle,
184 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
185 @note If waveform automatic generation mode is disabled,
186 this parameter is discarded.
187
188 This feature can be modified afterwards using unitary
189 function @ref LL_DAC_SetWaveNoiseLFSR(),
190 @ref LL_DAC_SetWaveTriangleAmplitude()
191 depending on the wave automatic generation selected. */
192
193 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
194 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
195
196 This feature can be modified afterwards using unitary
197 function @ref LL_DAC_SetOutputBuffer(). */
198
199 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
200 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
201
202 This feature can be modified afterwards using unitary
203 function @ref LL_DAC_SetOutputConnection(). */
204
205 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
206 channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
207
208 This feature can be modified afterwards using unitary
209 function @ref LL_DAC_SetOutputMode(). */
210 } LL_DAC_InitTypeDef;
211
212 /**
213 * @}
214 */
215 #endif /* USE_FULL_LL_DRIVER */
216
217 /* Exported constants --------------------------------------------------------*/
218 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
219 * @{
220 */
221
222 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
223 * @brief Flags defines which can be used with LL_DAC_ReadReg function
224 * @{
225 */
226 /* DAC channel 1 flags */
227 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
228 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
229 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
230 #define LL_DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY) /*!< DAC channel 1 flag ready */
231 #define LL_DAC_FLAG_DORSTAT1 (DAC_SR_DORSTAT1) /*!< DAC channel 1 flag output register */
232
233 /* DAC channel 2 flags */
234 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
235 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
236 #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
237 #define LL_DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY) /*!< DAC channel 2 flag ready */
238 #define LL_DAC_FLAG_DORSTAT2 (DAC_SR_DORSTAT2) /*!< DAC channel 2 flag output register */
239
240 /**
241 * @}
242 */
243
244 /** @defgroup DAC_LL_EC_IT DAC interruptions
245 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
246 * @{
247 */
248 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
249
250 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
251
252 /**
253 * @}
254 */
255
256 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
257 * @{
258 */
259 #define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
260 #define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
261 /**
262 * @}
263 */
264
265 /** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode
266 * @brief High frequency interface mode defines that can be used
267 * with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
268 * @{
269 */
270 #define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
271 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
272 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */
273 /**
274 * @}
275 */
276
277 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
278 * @{
279 */
280 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */
281 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
282 /**
283 * @}
284 */
285
286 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
287 * @{
288 */
289 #define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */
290 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */
291 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
292 #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
293 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
294 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
295 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
296 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
297 #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
298 #define LL_DAC_TRIG_EXT_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 CH1. */
299 #define LL_DAC_TRIG_EXT_LPTIM3_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 CH1. */
300 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
301
302 #define LL_DAC_TRIG_EXT_LPTIM1_OUT LL_DAC_TRIG_EXT_LPTIM1_CH1 /*!< Keep old definition for compatibility */
303 #define LL_DAC_TRIG_EXT_LPTIM3_OUT LL_DAC_TRIG_EXT_LPTIM3_CH1 /*!< Keep old definition for compatibility */
304 /**
305 * @}
306 */
307
308 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
309 * @{
310 */
311 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
312 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
313 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
314 /**
315 * @}
316 */
317
318 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
319 * @{
320 */
321 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
322 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
323 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
324 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
325 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
326 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
327 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
328 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
329 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
330 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
331 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
332 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
333 /**
334 * @}
335 */
336
337 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
338 * @{
339 */
340 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
341 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
342 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
343 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
344 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
345 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
346 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
347 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
348 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
349 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
350 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
351 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
352 /**
353 * @}
354 */
355
356 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
357 * @{
358 */
359 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */
360 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
361 /**
362 * @}
363 */
364
365 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
366 * @{
367 */
368 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
369 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
370 /**
371 * @}
372 */
373
374 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
375 * @{
376 */
377 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
378 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
379 /**
380 * @}
381 */
382
383 /** @defgroup DAC_LL_EC_SIGNED_FORMAT DAC channel signed format
384 * @{
385 */
386 #define LL_DAC_SIGNED_FORMAT_DISABLE 0x00000000UL /*!< The selected DAC channel data format is not signed */
387 #define LL_DAC_SIGNED_FORMAT_ENABLE (DAC_MCR_SINFORMAT1) /*!< The selected DAC channel data format is signed */
388 /**
389 * @}
390 */
391
392 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
393 * @{
394 */
395 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
396 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
397 /**
398 * @}
399 */
400
401 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
402 * @{
403 */
404 /* List of DAC registers intended to be used (most commonly) with */
405 /* DMA transfer. */
406 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
407 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
408 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
409 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
410 /**
411 * @}
412 */
413
414 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
415 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
416 * not timeout values.
417 * For details on delays values, refer to descriptions in source code
418 * above each literal definition.
419 * @{
420 */
421
422 /* Delay for DAC channel voltage settling time from DAC channel startup */
423 /* (transition from disable to enable). */
424 /* Note: DAC channel startup time depends on board application environment: */
425 /* impedance connected to DAC channel output. */
426 /* The delay below is specified under conditions: */
427 /* - voltage maximum transition (lowest to highest value) */
428 /* - until voltage reaches final value +-1LSB */
429 /* - DAC channel output buffer enabled */
430 /* - load impedance of 5kOhm (min), 50pF (max) */
431 /* Literal set to maximum value (refer to device datasheet, */
432 /* parameter "tWAKEUP"). */
433 /* Unit: us */
434 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
435
436 /* Delay for DAC channel voltage settling time. */
437 /* Note: DAC channel startup time depends on board application environment: */
438 /* impedance connected to DAC channel output. */
439 /* The delay below is specified under conditions: */
440 /* - voltage maximum transition (lowest to highest value) */
441 /* - until voltage reaches final value +-1LSB */
442 /* - DAC channel output buffer enabled */
443 /* - load impedance of 5kOhm min, 50pF max */
444 /* Literal set to maximum value (refer to device datasheet, */
445 /* parameter "tSETTLING"). */
446 /* Unit: us */
447 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */
448
449 /**
450 * @}
451 */
452
453 /**
454 * @}
455 */
456
457 /* Exported macro ------------------------------------------------------------*/
458 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
459 * @{
460 */
461
462 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
463 * @{
464 */
465
466 /**
467 * @brief Write a value in DAC register
468 * @param __INSTANCE__ DAC Instance
469 * @param __REG__ Register to be written
470 * @param __VALUE__ Value to be written in the register
471 * @retval None
472 */
473 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
474
475 /**
476 * @brief Read a value in DAC register
477 * @param __INSTANCE__ DAC Instance
478 * @param __REG__ Register to be read
479 * @retval Register value
480 */
481 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
482
483 /**
484 * @}
485 */
486
487 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
488 * @{
489 */
490
491 /**
492 * @brief Helper macro to get DAC channel number in decimal format
493 * from literals LL_DAC_CHANNEL_x.
494 * Example:
495 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
496 * will return decimal number "1".
497 * @note The input can be a value from functions where a channel
498 * number is returned.
499 * @param __CHANNEL__ This parameter can be one of the following values:
500 * @arg @ref LL_DAC_CHANNEL_1
501 * @arg @ref LL_DAC_CHANNEL_2
502 * @retval 1...2
503 */
504 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
505 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
506
507 /**
508 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
509 * from number in decimal format.
510 * Example:
511 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
512 * will return a data equivalent to "LL_DAC_CHANNEL_1".
513 * @note If the input parameter does not correspond to a DAC channel,
514 * this macro returns value '0'.
515 * @param __DECIMAL_NB__ 1...2
516 * @retval Returned value can be one of the following values:
517 * @arg @ref LL_DAC_CHANNEL_1
518 * @arg @ref LL_DAC_CHANNEL_2
519 */
520 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
521 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
522
523 /**
524 * @brief Helper macro to define the DAC conversion data full-scale digital
525 * value corresponding to the selected DAC resolution.
526 * @note DAC conversion data full-scale corresponds to voltage range
527 * determined by analog voltage references Vref+ and Vref-
528 * (refer to reference manual).
529 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
530 * @arg @ref LL_DAC_RESOLUTION_12B
531 * @arg @ref LL_DAC_RESOLUTION_8B
532 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
533 */
534 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
535 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
536
537 /**
538 * @brief Helper macro to calculate the DAC conversion data (unit: digital
539 * value) corresponding to a voltage (unit: mVolt).
540 * @note This helper macro is intended to provide input data in voltage
541 * rather than digital value,
542 * to be used with LL DAC functions such as
543 * @ref LL_DAC_ConvertData12RightAligned().
544 * @note Analog reference voltage (Vref+) must be either known from
545 * user board environment or can be calculated using ADC measurement
546 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
547 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
548 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
549 * (unit: mVolt).
550 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
551 * @arg @ref LL_DAC_RESOLUTION_12B
552 * @arg @ref LL_DAC_RESOLUTION_8B
553 * @retval DAC conversion data (unit: digital value)
554 */
555 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
556 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
557 / (__VREFANALOG_VOLTAGE__) \
558 )
559
560 /**
561 * @}
562 */
563
564 /**
565 * @}
566 */
567
568
569 /* Exported functions --------------------------------------------------------*/
570 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
571 * @{
572 */
573 /** @defgroup DAC_LL_EF_Channel_Configuration Configuration of DAC instance
574 * @{
575 */
576 /**
577 * @brief Set the high frequency interface mode for the selected DAC instance
578 * @rmtoll MCR HFSEL LL_DAC_SetHighFrequencyMode
579 * @param DACx DAC instance
580 * @param HighFreqMode This parameter can be one of the following values:
581 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
582 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
583 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
584 * @retval None
585 */
LL_DAC_SetHighFrequencyMode(DAC_TypeDef * DACx,uint32_t HighFreqMode)586 __STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode)
587 {
588 MODIFY_REG(DACx->MCR, DAC_MCR_HFSEL, HighFreqMode);
589 }
590
591 /**
592 * @brief Get the high frequency interface mode for the selected DAC instance
593 * @rmtoll MCR HFSEL LL_DAC_GetHighFrequencyMode
594 * @param DACx DAC instance
595 * @retval Returned value can be one of the following values:
596 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
597 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
598 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
599 */
LL_DAC_GetHighFrequencyMode(const DAC_TypeDef * DACx)600 __STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(const DAC_TypeDef *DACx)
601 {
602 return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_HFSEL));
603 }
604 /**
605 * @}
606 */
607
608
609 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
610 * @{
611 */
612
613 /**
614 * @brief Set the operating mode for the selected DAC channel:
615 * calibration or normal operating mode.
616 * @rmtoll CR CEN1 LL_DAC_SetMode\n
617 * CR CEN2 LL_DAC_SetMode
618 * @param DACx DAC instance
619 * @param DAC_Channel This parameter can be one of the following values:
620 * @arg @ref LL_DAC_CHANNEL_1
621 * @arg @ref LL_DAC_CHANNEL_2
622 * @param ChannelMode This parameter can be one of the following values:
623 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
624 * @arg @ref LL_DAC_MODE_CALIBRATION
625 * @retval None
626 */
LL_DAC_SetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t ChannelMode)627 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
628 {
629 MODIFY_REG(DACx->CR,
630 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
631 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
632 }
633
634 /**
635 * @brief Get the operating mode for the selected DAC channel:
636 * calibration or normal operating mode.
637 * @rmtoll CR CEN1 LL_DAC_GetMode\n
638 * CR CEN2 LL_DAC_GetMode
639 * @param DACx DAC instance
640 * @param DAC_Channel This parameter can be one of the following values:
641 * @arg @ref LL_DAC_CHANNEL_1
642 * @arg @ref LL_DAC_CHANNEL_2
643 * @retval Returned value can be one of the following values:
644 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
645 * @arg @ref LL_DAC_MODE_CALIBRATION
646 */
LL_DAC_GetMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)647 __STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
648 {
649 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
650 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
651 );
652 }
653
654 /**
655 * @brief Set the offset trimming value for the selected DAC channel.
656 * Trimming has an impact when output buffer is enabled
657 * and is intended to replace factory calibration default values.
658 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
659 * CCR OTRIM2 LL_DAC_SetTrimmingValue
660 * @param DACx DAC instance
661 * @param DAC_Channel This parameter can be one of the following values:
662 * @arg @ref LL_DAC_CHANNEL_1
663 * @arg @ref LL_DAC_CHANNEL_2
664 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
665 * @retval None
666 */
LL_DAC_SetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TrimmingValue)667 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
668 {
669 MODIFY_REG(DACx->CCR,
670 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
671 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
672 }
673
674 /**
675 * @brief Get the offset trimming value for the selected DAC channel.
676 * Trimming has an impact when output buffer is enabled
677 * and is intended to replace factory calibration default values.
678 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
679 * CCR OTRIM2 LL_DAC_GetTrimmingValue
680 * @param DACx DAC instance
681 * @param DAC_Channel This parameter can be one of the following values:
682 * @arg @ref LL_DAC_CHANNEL_1
683 * @arg @ref LL_DAC_CHANNEL_2
684 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
685 */
LL_DAC_GetTrimmingValue(const DAC_TypeDef * DACx,uint32_t DAC_Channel)686 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
687 {
688 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
689 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
690 );
691 }
692
693 /**
694 * @brief Set the conversion trigger source for the selected DAC channel.
695 * @note For conversion trigger source to be effective, DAC trigger
696 * must be enabled using function @ref LL_DAC_EnableTrigger().
697 * @note To set conversion trigger source, DAC channel must be disabled.
698 * Otherwise, the setting is discarded.
699 * @note Availability of parameters of trigger sources from timer
700 * depends on timers availability on the selected device.
701 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
702 * CR TSEL2 LL_DAC_SetTriggerSource
703 * @param DACx DAC instance
704 * @param DAC_Channel This parameter can be one of the following values:
705 * @arg @ref LL_DAC_CHANNEL_1
706 * @arg @ref LL_DAC_CHANNEL_2
707 * @param TriggerSource This parameter can be one of the following values:
708 * @arg @ref LL_DAC_TRIG_SOFTWARE
709 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
710 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
711 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
712 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
713 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
714 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
715 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
716 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
717 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1
718 * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_CH1
719 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
720 * @retval None
721 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)722 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
723 {
724 MODIFY_REG(DACx->CR,
725 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
726 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
727 }
728
729 /**
730 * @brief Get the conversion trigger source for the selected DAC channel.
731 * @note For conversion trigger source to be effective, DAC trigger
732 * must be enabled using function @ref LL_DAC_EnableTrigger().
733 * @note Availability of parameters of trigger sources from timer
734 * depends on timers availability on the selected device.
735 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
736 * CR TSEL2 LL_DAC_GetTriggerSource
737 * @param DACx DAC instance
738 * @param DAC_Channel This parameter can be one of the following values:
739 * @arg @ref LL_DAC_CHANNEL_1
740 * @arg @ref LL_DAC_CHANNEL_2
741 * @retval Returned value can be one of the following values:
742 * @arg @ref LL_DAC_TRIG_SOFTWARE
743 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
744 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
745 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
746 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
747 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
748 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
749 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
750 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
751 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1
752 * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_CH1
753 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
754 */
LL_DAC_GetTriggerSource(const DAC_TypeDef * DACx,uint32_t DAC_Channel)755 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
756 {
757 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
758 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
759 );
760 }
761
762 /**
763 * @brief Set the waveform automatic generation mode
764 * for the selected DAC channel.
765 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
766 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
767 * @param DACx DAC instance
768 * @param DAC_Channel This parameter can be one of the following values:
769 * @arg @ref LL_DAC_CHANNEL_1
770 * @arg @ref LL_DAC_CHANNEL_2
771 * @param WaveAutoGeneration This parameter can be one of the following values:
772 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
773 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
774 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
775 * @retval None
776 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)777 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
778 {
779 MODIFY_REG(DACx->CR,
780 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
781 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
782 }
783
784 /**
785 * @brief Get the waveform automatic generation mode
786 * for the selected DAC channel.
787 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
788 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
789 * @param DACx DAC instance
790 * @param DAC_Channel This parameter can be one of the following values:
791 * @arg @ref LL_DAC_CHANNEL_1
792 * @arg @ref LL_DAC_CHANNEL_2
793 * @retval Returned value can be one of the following values:
794 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
795 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
796 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
797 */
LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef * DACx,uint32_t DAC_Channel)798 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
799 {
800 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
801 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
802 );
803 }
804
805 /**
806 * @brief Set the noise waveform generation for the selected DAC channel:
807 * Noise mode and parameters LFSR (linear feedback shift register).
808 * @note For wave generation to be effective, DAC channel
809 * wave generation mode must be enabled using
810 * function @ref LL_DAC_SetWaveAutoGeneration().
811 * @note This setting can be set when the selected DAC channel is disabled
812 * (otherwise, the setting operation is ignored).
813 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
814 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
815 * @param DACx DAC instance
816 * @param DAC_Channel This parameter can be one of the following values:
817 * @arg @ref LL_DAC_CHANNEL_1
818 * @arg @ref LL_DAC_CHANNEL_2
819 * @param NoiseLFSRMask This parameter can be one of the following values:
820 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
821 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
822 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
823 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
824 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
825 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
826 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
827 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
828 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
829 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
830 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
831 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
832 * @retval None
833 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)834 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
835 {
836 MODIFY_REG(DACx->CR,
837 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
838 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
839 }
840
841 /**
842 * @brief Get the noise waveform generation for the selected DAC channel:
843 * Noise mode and parameters LFSR (linear feedback shift register).
844 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
845 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
846 * @param DACx DAC instance
847 * @param DAC_Channel This parameter can be one of the following values:
848 * @arg @ref LL_DAC_CHANNEL_1
849 * @arg @ref LL_DAC_CHANNEL_2
850 * @retval Returned value can be one of the following values:
851 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
852 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
853 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
854 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
855 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
856 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
857 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
858 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
859 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
860 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
861 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
862 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
863 */
LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef * DACx,uint32_t DAC_Channel)864 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
865 {
866 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
867 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
868 );
869 }
870
871 /**
872 * @brief Set the triangle waveform generation for the selected DAC channel:
873 * triangle mode and amplitude.
874 * @note For wave generation to be effective, DAC channel
875 * wave generation mode must be enabled using
876 * function @ref LL_DAC_SetWaveAutoGeneration().
877 * @note This setting can be set when the selected DAC channel is disabled
878 * (otherwise, the setting operation is ignored).
879 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
880 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
881 * @param DACx DAC instance
882 * @param DAC_Channel This parameter can be one of the following values:
883 * @arg @ref LL_DAC_CHANNEL_1
884 * @arg @ref LL_DAC_CHANNEL_2
885 * @param TriangleAmplitude This parameter can be one of the following values:
886 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
887 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
888 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
889 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
890 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
891 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
892 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
893 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
894 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
895 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
896 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
897 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
898 * @retval None
899 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)900 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
901 uint32_t TriangleAmplitude)
902 {
903 MODIFY_REG(DACx->CR,
904 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
905 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
906 }
907
908 /**
909 * @brief Get the triangle waveform generation for the selected DAC channel:
910 * triangle mode and amplitude.
911 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
912 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
913 * @param DACx DAC instance
914 * @param DAC_Channel This parameter can be one of the following values:
915 * @arg @ref LL_DAC_CHANNEL_1
916 * @arg @ref LL_DAC_CHANNEL_2
917 * @retval Returned value can be one of the following values:
918 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
919 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
920 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
921 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
922 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
923 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
924 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
925 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
926 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
927 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
928 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
929 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
930 */
LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef * DACx,uint32_t DAC_Channel)931 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
932 {
933 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
934 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
935 );
936 }
937
938 /**
939 * @brief Set the output for the selected DAC channel.
940 * @note This function set several features:
941 * - mode normal or sample-and-hold
942 * - buffer
943 * - connection to GPIO or internal path.
944 * These features can also be set individually using
945 * dedicated functions:
946 * - @ref LL_DAC_SetOutputBuffer()
947 * - @ref LL_DAC_SetOutputMode()
948 * - @ref LL_DAC_SetOutputConnection()
949 * @note On this STM32 series, output connection depends on output mode
950 * (normal or sample and hold) and output buffer state.
951 * - if output connection is set to internal path and output buffer
952 * is enabled (whatever output mode):
953 * output connection is also connected to GPIO pin
954 * (both connections to GPIO pin and internal path).
955 * - if output connection is set to GPIO pin, output buffer
956 * is disabled, output mode set to sample and hold:
957 * output connection is also connected to internal path
958 * (both connections to GPIO pin and internal path).
959 * @note Mode sample-and-hold requires an external capacitor
960 * to be connected between DAC channel output and ground.
961 * Capacitor value depends on load on DAC channel output and
962 * sample-and-hold timings configured.
963 * As indication, capacitor typical value is 100nF
964 * (refer to device datasheet, parameter "CSH").
965 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
966 * CR MODE2 LL_DAC_ConfigOutput
967 * @param DACx DAC instance
968 * @param DAC_Channel This parameter can be one of the following values:
969 * @arg @ref LL_DAC_CHANNEL_1
970 * @arg @ref LL_DAC_CHANNEL_2
971 * @param OutputMode This parameter can be one of the following values:
972 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
973 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
974 * @param OutputBuffer This parameter can be one of the following values:
975 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
976 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
977 * @param OutputConnection This parameter can be one of the following values:
978 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
979 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
980 * @retval None
981 */
LL_DAC_ConfigOutput(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode,uint32_t OutputBuffer,uint32_t OutputConnection)982 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
983 uint32_t OutputBuffer, uint32_t OutputConnection)
984 {
985 MODIFY_REG(DACx->MCR,
986 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
987 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
988 }
989
990 /**
991 * @brief Set the output mode normal or sample-and-hold
992 * for the selected DAC channel.
993 * @note Mode sample-and-hold requires an external capacitor
994 * to be connected between DAC channel output and ground.
995 * Capacitor value depends on load on DAC channel output and
996 * sample-and-hold timings configured.
997 * As indication, capacitor typical value is 100nF
998 * (refer to device datasheet, parameter "CSH").
999 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
1000 * CR MODE2 LL_DAC_SetOutputMode
1001 * @param DACx DAC instance
1002 * @param DAC_Channel This parameter can be one of the following values:
1003 * @arg @ref LL_DAC_CHANNEL_1
1004 * @arg @ref LL_DAC_CHANNEL_2
1005 * @param OutputMode This parameter can be one of the following values:
1006 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1007 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1008 * @retval None
1009 */
LL_DAC_SetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode)1010 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
1011 {
1012 MODIFY_REG(DACx->MCR,
1013 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1014 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1015 }
1016
1017 /**
1018 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
1019 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
1020 * CR MODE2 LL_DAC_GetOutputMode
1021 * @param DACx DAC instance
1022 * @param DAC_Channel This parameter can be one of the following values:
1023 * @arg @ref LL_DAC_CHANNEL_1
1024 * @arg @ref LL_DAC_CHANNEL_2
1025 * @retval Returned value can be one of the following values:
1026 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1027 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1028 */
LL_DAC_GetOutputMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1029 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1030 {
1031 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1032 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1033 );
1034 }
1035
1036 /**
1037 * @brief Set the output buffer for the selected DAC channel.
1038 * @note On this STM32 series, when buffer is enabled, its offset can be
1039 * trimmed: factory calibration default values can be
1040 * replaced by user trimming values, using function
1041 * @ref LL_DAC_SetTrimmingValue().
1042 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
1043 * CR MODE2 LL_DAC_SetOutputBuffer
1044 * @param DACx DAC instance
1045 * @param DAC_Channel This parameter can be one of the following values:
1046 * @arg @ref LL_DAC_CHANNEL_1
1047 * @arg @ref LL_DAC_CHANNEL_2
1048 * @param OutputBuffer This parameter can be one of the following values:
1049 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1050 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1051 * @retval None
1052 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)1053 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
1054 {
1055 MODIFY_REG(DACx->MCR,
1056 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1057 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1058 }
1059
1060 /**
1061 * @brief Get the output buffer state for the selected DAC channel.
1062 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
1063 * CR MODE2 LL_DAC_GetOutputBuffer
1064 * @param DACx DAC instance
1065 * @param DAC_Channel This parameter can be one of the following values:
1066 * @arg @ref LL_DAC_CHANNEL_1
1067 * @arg @ref LL_DAC_CHANNEL_2
1068 * @retval Returned value can be one of the following values:
1069 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1070 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1071 */
LL_DAC_GetOutputBuffer(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1072 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1073 {
1074 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1075 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1076 );
1077 }
1078
1079 /**
1080 * @brief Set the output connection for the selected DAC channel.
1081 * @note On this STM32 series, output connection depends on output mode (normal or
1082 * sample and hold) and output buffer state.
1083 * - if output connection is set to internal path and output buffer
1084 * is enabled (whatever output mode):
1085 * output connection is also connected to GPIO pin
1086 * (both connections to GPIO pin and internal path).
1087 * - if output connection is set to GPIO pin, output buffer
1088 * is disabled, output mode set to sample and hold:
1089 * output connection is also connected to internal path
1090 * (both connections to GPIO pin and internal path).
1091 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
1092 * CR MODE2 LL_DAC_SetOutputConnection
1093 * @param DACx DAC instance
1094 * @param DAC_Channel This parameter can be one of the following values:
1095 * @arg @ref LL_DAC_CHANNEL_1
1096 * @arg @ref LL_DAC_CHANNEL_2
1097 * @param OutputConnection This parameter can be one of the following values:
1098 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1099 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1100 * @retval None
1101 */
LL_DAC_SetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputConnection)1102 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1103 {
1104 MODIFY_REG(DACx->MCR,
1105 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1106 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1107 }
1108
1109 /**
1110 * @brief Get the output connection for the selected DAC channel.
1111 * @note On this STM32 series, output connection depends on output mode (normal or
1112 * sample and hold) and output buffer state.
1113 * - if output connection is set to internal path and output buffer
1114 * is enabled (whatever output mode):
1115 * output connection is also connected to GPIO pin
1116 * (both connections to GPIO pin and internal path).
1117 * - if output connection is set to GPIO pin, output buffer
1118 * is disabled, output mode set to sample and hold:
1119 * output connection is also connected to internal path
1120 * (both connections to GPIO pin and internal path).
1121 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
1122 * CR MODE2 LL_DAC_GetOutputConnection
1123 * @param DACx DAC instance
1124 * @param DAC_Channel This parameter can be one of the following values:
1125 * @arg @ref LL_DAC_CHANNEL_1
1126 * @arg @ref LL_DAC_CHANNEL_2
1127 * @retval Returned value can be one of the following values:
1128 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1129 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1130 */
LL_DAC_GetOutputConnection(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1131 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1132 {
1133 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1134 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1135 );
1136 }
1137
1138 /**
1139 * @brief Set the sample-and-hold timing for the selected DAC channel:
1140 * sample time
1141 * @note Sample time must be set when DAC channel is disabled
1142 * or during DAC operation when DAC channel flag BWSTx is reset,
1143 * otherwise the setting is ignored.
1144 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1145 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
1146 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
1147 * @param DACx DAC instance
1148 * @param DAC_Channel This parameter can be one of the following values:
1149 * @arg @ref LL_DAC_CHANNEL_1
1150 * @arg @ref LL_DAC_CHANNEL_2
1151 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1152 * @retval None
1153 */
LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SampleTime)1154 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1155 {
1156 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1157 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1158
1159 MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
1160 }
1161
1162 /**
1163 * @brief Get the sample-and-hold timing for the selected DAC channel:
1164 * sample time
1165 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
1166 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
1167 * @param DACx DAC instance
1168 * @param DAC_Channel This parameter can be one of the following values:
1169 * @arg @ref LL_DAC_CHANNEL_1
1170 * @arg @ref LL_DAC_CHANNEL_2
1171 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1172 */
LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1173 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1174 {
1175 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1176 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1177
1178 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1179 }
1180
1181 /**
1182 * @brief Set the sample-and-hold timing for the selected DAC channel:
1183 * hold time
1184 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
1185 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
1186 * @param DACx DAC instance
1187 * @param DAC_Channel This parameter can be one of the following values:
1188 * @arg @ref LL_DAC_CHANNEL_1
1189 * @arg @ref LL_DAC_CHANNEL_2
1190 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1191 * @retval None
1192 */
LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t HoldTime)1193 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1194 {
1195 MODIFY_REG(DACx->SHHR,
1196 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1197 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1198 }
1199
1200 /**
1201 * @brief Get the sample-and-hold timing for the selected DAC channel:
1202 * hold time
1203 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
1204 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
1205 * @param DACx DAC instance
1206 * @param DAC_Channel This parameter can be one of the following values:
1207 * @arg @ref LL_DAC_CHANNEL_1
1208 * @arg @ref LL_DAC_CHANNEL_2
1209 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1210 */
LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1211 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1212 {
1213 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1214 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1215 );
1216 }
1217
1218 /**
1219 * @brief Set the sample-and-hold timing for the selected DAC channel:
1220 * refresh time
1221 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
1222 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
1223 * @param DACx DAC instance
1224 * @param DAC_Channel This parameter can be one of the following values:
1225 * @arg @ref LL_DAC_CHANNEL_1
1226 * @arg @ref LL_DAC_CHANNEL_2
1227 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1228 * @retval None
1229 */
LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t RefreshTime)1230 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1231 {
1232 MODIFY_REG(DACx->SHRR,
1233 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1234 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1235 }
1236
1237 /**
1238 * @brief Get the sample-and-hold timing for the selected DAC channel:
1239 * refresh time
1240 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
1241 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
1242 * @param DACx DAC instance
1243 * @param DAC_Channel This parameter can be one of the following values:
1244 * @arg @ref LL_DAC_CHANNEL_1
1245 * @arg @ref LL_DAC_CHANNEL_2
1246 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1247 */
LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1248 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1249 {
1250 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1251 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1252 );
1253 }
1254
1255 /**
1256 * @brief Set the signed format for the selected DAC channel.
1257 * @note On this STM32 series, signed format can be used to inject
1258 * Q1.15, Q1.11, Q1.7 signed format data to DAC.
1259 * Ex when using 12bits data format (Q1.11 is used):
1260 * 0x800 will output 0v level
1261 * 0xFFF will output mid-scale level
1262 * 0x000 will output mid-scale level
1263 * 0x7FF will output full-scale level
1264 * @rmtoll MCR SINFORMAT1 LL_DAC_SetSignedFormat\n
1265 * MCR SINFORMAT2 LL_DAC_SetSignedFormat
1266 * @param DACx DAC instance
1267 * @param DAC_Channel This parameter can be one of the following values:
1268 * @arg @ref LL_DAC_CHANNEL_1
1269 * @arg @ref LL_DAC_CHANNEL_2
1270 * @param SignedFormat This parameter can be one of the following values:
1271 * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
1272 * @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
1273 * @retval None
1274 */
LL_DAC_SetSignedFormat(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SignedFormat)1275 __STATIC_INLINE void LL_DAC_SetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SignedFormat)
1276 {
1277 MODIFY_REG(DACx->MCR,
1278 DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1279 SignedFormat << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1280 }
1281
1282 /**
1283 * @brief Get the signed format state for the selected DAC channel.
1284 * @rmtoll MCR SINFORMAT1 LL_DAC_GetSignedFormat\n
1285 * MCR SINFORMAT2 LL_DAC_GetSignedFormat
1286 * @param DACx DAC instance
1287 * @param DAC_Channel This parameter can be one of the following values:
1288 * @arg @ref LL_DAC_CHANNEL_1
1289 * @arg @ref LL_DAC_CHANNEL_2
1290 * @retval Returned value can be one of the following values:
1291 * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
1292 * @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
1293 */
LL_DAC_GetSignedFormat(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1294 __STATIC_INLINE uint32_t LL_DAC_GetSignedFormat(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1295 {
1296 return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1297 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1298 );
1299 }
1300
1301 /**
1302 * @}
1303 */
1304
1305 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
1306 * @{
1307 */
1308
1309 /**
1310 * @brief Enable DAC DMA transfer request of the selected channel.
1311 * @note To configure DMA source address (peripheral address),
1312 * use function @ref LL_DAC_DMA_GetRegAddr().
1313 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
1314 * CR DMAEN2 LL_DAC_EnableDMAReq
1315 * @param DACx DAC instance
1316 * @param DAC_Channel This parameter can be one of the following values:
1317 * @arg @ref LL_DAC_CHANNEL_1
1318 * @arg @ref LL_DAC_CHANNEL_2
1319 * @retval None
1320 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1321 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1322 {
1323 SET_BIT(DACx->CR,
1324 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1325 }
1326
1327 /**
1328 * @brief Disable DAC DMA transfer request of the selected channel.
1329 * @note To configure DMA source address (peripheral address),
1330 * use function @ref LL_DAC_DMA_GetRegAddr().
1331 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
1332 * CR DMAEN2 LL_DAC_DisableDMAReq
1333 * @param DACx DAC instance
1334 * @param DAC_Channel This parameter can be one of the following values:
1335 * @arg @ref LL_DAC_CHANNEL_1
1336 * @arg @ref LL_DAC_CHANNEL_2
1337 * @retval None
1338 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1339 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1340 {
1341 CLEAR_BIT(DACx->CR,
1342 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1343 }
1344
1345 /**
1346 * @brief Get DAC DMA transfer request state of the selected channel.
1347 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1348 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
1349 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
1350 * @param DACx DAC instance
1351 * @param DAC_Channel This parameter can be one of the following values:
1352 * @arg @ref LL_DAC_CHANNEL_1
1353 * @arg @ref LL_DAC_CHANNEL_2
1354 * @retval State of bit (1 or 0).
1355 */
LL_DAC_IsDMAReqEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1356 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1357 {
1358 return ((READ_BIT(DACx->CR,
1359 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1360 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1361 }
1362
1363 /**
1364 * @brief Enable DAC DMA Double data mode of the selected channel.
1365 * @rmtoll MCR DMADOUBLE1 LL_DAC_EnableDMADoubleDataMode\n
1366 * MCR DMADOUBLE2 LL_DAC_EnableDMADoubleDataMode
1367 * @param DACx DAC instance
1368 * @param DAC_Channel This parameter can be one of the following values:
1369 * @arg @ref LL_DAC_CHANNEL_1
1370 * @arg @ref LL_DAC_CHANNEL_2
1371 * @retval None
1372 */
LL_DAC_EnableDMADoubleDataMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)1373 __STATIC_INLINE void LL_DAC_EnableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1374 {
1375 SET_BIT(DACx->MCR,
1376 DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1377 }
1378
1379 /**
1380 * @brief Disable DAC DMA Double data mode of the selected channel.
1381 * @rmtoll MCR DMADOUBLE1 LL_DAC_DisableDMADoubleDataMode\n
1382 * MCR DMADOUBLE2 LL_DAC_DisableDMADoubleDataMode
1383 * @param DACx DAC instance
1384 * @param DAC_Channel This parameter can be one of the following values:
1385 * @arg @ref LL_DAC_CHANNEL_1
1386 * @arg @ref LL_DAC_CHANNEL_2
1387 * @retval None
1388 */
LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)1389 __STATIC_INLINE void LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1390 {
1391 CLEAR_BIT(DACx->MCR,
1392 DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1393 }
1394
1395 /**
1396 * @brief Get DAC DMA double data mode state of the selected channel.
1397 * (0: DAC DMA double data mode is disabled, 1: DAC DMA double data mode is enabled)
1398 * @rmtoll MCR DMADOUBLE1 LL_DAC_IsDMADoubleDataModeEnabled\n
1399 * MCR DMADOUBLE2 LL_DAC_IsDMADoubleDataModeEnabled
1400 * @param DACx DAC instance
1401 * @param DAC_Channel This parameter can be one of the following values:
1402 * @arg @ref LL_DAC_CHANNEL_1
1403 * @arg @ref LL_DAC_CHANNEL_2
1404 * @retval State of bit (1 or 0).
1405 */
LL_DAC_IsDMADoubleDataModeEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1406 __STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1407 {
1408 return ((READ_BIT(DACx->MCR,
1409 DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1410 == (DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1411 }
1412
1413 /**
1414 * @brief Function to help to configure DMA transfer to DAC: retrieve the
1415 * DAC register address from DAC instance and a list of DAC registers
1416 * intended to be used (most commonly) with DMA transfer.
1417 * @note These DAC registers are data holding registers:
1418 * when DAC conversion is requested, DAC generates a DMA transfer
1419 * request to have data available in DAC data holding registers.
1420 * @note This macro is intended to be used with LL DMA driver, refer to
1421 * function "LL_DMA_ConfigAddresses()".
1422 * Example:
1423 * LL_DMA_ConfigAddresses(DMA1,
1424 * LL_DMA_CHANNEL_1,
1425 * (uint32_t)&< array or variable >,
1426 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
1427 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1428 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1429 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1430 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1431 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1432 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1433 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1434 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
1435 * @param DACx DAC instance
1436 * @param DAC_Channel This parameter can be one of the following values:
1437 * @arg @ref LL_DAC_CHANNEL_1
1438 * @arg @ref LL_DAC_CHANNEL_2
1439 * @param Register This parameter can be one of the following values:
1440 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1441 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1442 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1443 * @retval DAC register address
1444 */
LL_DAC_DMA_GetRegAddr(const DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)1445 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1446 {
1447 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1448 /* DAC channel selected. */
1449 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
1450 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
1451 }
1452 /**
1453 * @}
1454 */
1455
1456 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1457 * @{
1458 */
1459
1460 /**
1461 * @brief Enable DAC selected channel.
1462 * @rmtoll CR EN1 LL_DAC_Enable\n
1463 * CR EN2 LL_DAC_Enable
1464 * @note After enable from off state, DAC channel requires a delay
1465 * for output voltage to reach accuracy +/- 1 LSB.
1466 * Refer to device datasheet, parameter "tWAKEUP".
1467 * @param DACx DAC instance
1468 * @param DAC_Channel This parameter can be one of the following values:
1469 * @arg @ref LL_DAC_CHANNEL_1
1470 * @arg @ref LL_DAC_CHANNEL_2
1471 * @retval None
1472 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1473 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1474 {
1475 SET_BIT(DACx->CR,
1476 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1477 }
1478
1479 /**
1480 * @brief Disable DAC selected channel.
1481 * @rmtoll CR EN1 LL_DAC_Disable\n
1482 * CR EN2 LL_DAC_Disable
1483 * @param DACx DAC instance
1484 * @param DAC_Channel This parameter can be one of the following values:
1485 * @arg @ref LL_DAC_CHANNEL_1
1486 * @arg @ref LL_DAC_CHANNEL_2
1487 * @retval None
1488 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1489 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1490 {
1491 CLEAR_BIT(DACx->CR,
1492 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1493 }
1494
1495 /**
1496 * @brief Get DAC enable state of the selected channel.
1497 * (0: DAC channel is disabled, 1: DAC channel is enabled)
1498 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
1499 * CR EN2 LL_DAC_IsEnabled
1500 * @param DACx DAC instance
1501 * @param DAC_Channel This parameter can be one of the following values:
1502 * @arg @ref LL_DAC_CHANNEL_1
1503 * @arg @ref LL_DAC_CHANNEL_2
1504 * @retval State of bit (1 or 0).
1505 */
LL_DAC_IsEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1506 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1507 {
1508 return ((READ_BIT(DACx->CR,
1509 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1510 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1511 }
1512
1513 /**
1514 * @brief Get DAC ready for conversion state of the selected channel.
1515 * (0: DAC channel is not ready, 1: DAC channel is ready)
1516 * @rmtoll SR DAC1RDY LL_DAC_IsReady\n
1517 * SR DAC2RDY LL_DAC_IsReady
1518 * @param DACx DAC instance
1519 * @param DAC_Channel This parameter can be one of the following values:
1520 * @arg @ref LL_DAC_CHANNEL_1
1521 * @arg @ref LL_DAC_CHANNEL_2
1522 * @retval State of bit (1 or 0).
1523 */
LL_DAC_IsReady(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1524 __STATIC_INLINE uint32_t LL_DAC_IsReady(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1525 {
1526 return ((READ_BIT(DACx->SR,
1527 DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1528 == (DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1529 }
1530
1531 /**
1532 * @brief Enable DAC trigger of the selected channel.
1533 * @note - If DAC trigger is disabled, DAC conversion is performed
1534 * automatically once the data holding register is updated,
1535 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1536 * @ref LL_DAC_ConvertData12RightAligned(), ...
1537 * - If DAC trigger is enabled, DAC conversion is performed
1538 * only when a hardware of software trigger event is occurring.
1539 * Select trigger source using
1540 * function @ref LL_DAC_SetTriggerSource().
1541 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1542 * CR TEN2 LL_DAC_EnableTrigger
1543 * @param DACx DAC instance
1544 * @param DAC_Channel This parameter can be one of the following values:
1545 * @arg @ref LL_DAC_CHANNEL_1
1546 * @arg @ref LL_DAC_CHANNEL_2
1547 * @retval None
1548 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1549 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1550 {
1551 SET_BIT(DACx->CR,
1552 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1553 }
1554
1555 /**
1556 * @brief Disable DAC trigger of the selected channel.
1557 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1558 * CR TEN2 LL_DAC_DisableTrigger
1559 * @param DACx DAC instance
1560 * @param DAC_Channel This parameter can be one of the following values:
1561 * @arg @ref LL_DAC_CHANNEL_1
1562 * @arg @ref LL_DAC_CHANNEL_2
1563 * @retval None
1564 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1565 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1566 {
1567 CLEAR_BIT(DACx->CR,
1568 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1569 }
1570
1571 /**
1572 * @brief Get DAC trigger state of the selected channel.
1573 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1574 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1575 * CR TEN2 LL_DAC_IsTriggerEnabled
1576 * @param DACx DAC instance
1577 * @param DAC_Channel This parameter can be one of the following values:
1578 * @arg @ref LL_DAC_CHANNEL_1
1579 * @arg @ref LL_DAC_CHANNEL_2
1580 * @retval State of bit (1 or 0).
1581 */
LL_DAC_IsTriggerEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1582 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1583 {
1584 return ((READ_BIT(DACx->CR,
1585 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1586 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1587 }
1588
1589 /**
1590 * @brief Trig DAC conversion by software for the selected DAC channel.
1591 * @note Preliminarily, DAC trigger must be set to software trigger
1592 * using function
1593 * @ref LL_DAC_Init()
1594 * @ref LL_DAC_SetTriggerSource()
1595 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1596 * and DAC trigger must be enabled using
1597 * function @ref LL_DAC_EnableTrigger().
1598 * @note For devices featuring DAC with 2 channels: this function
1599 * can perform a SW start of both DAC channels simultaneously.
1600 * Two channels can be selected as parameter.
1601 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1602 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1603 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1604 * @param DACx DAC instance
1605 * @param DAC_Channel This parameter can a combination of the following values:
1606 * @arg @ref LL_DAC_CHANNEL_1
1607 * @arg @ref LL_DAC_CHANNEL_2
1608 * @retval None
1609 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1610 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1611 {
1612 SET_BIT(DACx->SWTRIGR,
1613 (DAC_Channel & DAC_SWTR_CHX_MASK));
1614 }
1615
1616 /**
1617 * @brief Set the data to be loaded in the data holding register
1618 * in format 12 bits left alignment (LSB aligned on bit 0),
1619 * for the selected DAC channel.
1620 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1621 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1622 * @param DACx DAC instance
1623 * @param DAC_Channel This parameter can be one of the following values:
1624 * @arg @ref LL_DAC_CHANNEL_1
1625 * @arg @ref LL_DAC_CHANNEL_2
1626 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1627 * @retval None
1628 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1629 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1630 {
1631 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1632 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1633
1634 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1635 }
1636
1637 /**
1638 * @brief Set the data to be loaded in the data holding register
1639 * in format 12 bits left alignment (MSB aligned on bit 15),
1640 * for the selected DAC channel.
1641 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1642 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1643 * @param DACx DAC instance
1644 * @param DAC_Channel This parameter can be one of the following values:
1645 * @arg @ref LL_DAC_CHANNEL_1
1646 * @arg @ref LL_DAC_CHANNEL_2
1647 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1648 * @retval None
1649 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1650 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1651 {
1652 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1653 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1654
1655 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1656 }
1657
1658 /**
1659 * @brief Set the data to be loaded in the data holding register
1660 * in format 8 bits left alignment (LSB aligned on bit 0),
1661 * for the selected DAC channel.
1662 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1663 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1664 * @param DACx DAC instance
1665 * @param DAC_Channel This parameter can be one of the following values:
1666 * @arg @ref LL_DAC_CHANNEL_1
1667 * @arg @ref LL_DAC_CHANNEL_2
1668 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1669 * @retval None
1670 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1671 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1672 {
1673 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1674 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1675
1676 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1677 }
1678
1679
1680 /**
1681 * @brief Set the data to be loaded in the data holding register
1682 * in format 12 bits left alignment (LSB aligned on bit 0),
1683 * for both DAC channels.
1684 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1685 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1686 * @param DACx DAC instance
1687 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1688 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1689 * @retval None
1690 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1691 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1692 uint32_t DataChannel2)
1693 {
1694 MODIFY_REG(DACx->DHR12RD,
1695 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1696 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1697 }
1698
1699 /**
1700 * @brief Set the data to be loaded in the data holding register
1701 * in format 12 bits left alignment (MSB aligned on bit 15),
1702 * for both DAC channels.
1703 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1704 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1705 * @param DACx DAC instance
1706 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1707 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1708 * @retval None
1709 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1710 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1711 uint32_t DataChannel2)
1712 {
1713 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1714 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1715 /* the 4 LSB must be taken into account for the shift value. */
1716 MODIFY_REG(DACx->DHR12LD,
1717 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1718 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1719 }
1720
1721 /**
1722 * @brief Set the data to be loaded in the data holding register
1723 * in format 8 bits left alignment (LSB aligned on bit 0),
1724 * for both DAC channels.
1725 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1726 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1727 * @param DACx DAC instance
1728 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1729 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1730 * @retval None
1731 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1732 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1733 uint32_t DataChannel2)
1734 {
1735 MODIFY_REG(DACx->DHR8RD,
1736 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1737 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1738 }
1739
1740
1741 /**
1742 * @brief Retrieve output data currently generated for the selected DAC channel.
1743 * @note Whatever alignment and resolution settings
1744 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1745 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1746 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1747 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1748 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1749 * @param DACx DAC instance
1750 * @param DAC_Channel This parameter can be one of the following values:
1751 * @arg @ref LL_DAC_CHANNEL_1
1752 * @arg @ref LL_DAC_CHANNEL_2
1753 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1754 */
LL_DAC_RetrieveOutputData(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1755 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1756 {
1757 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1758 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1759
1760 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1761 }
1762
1763 /**
1764 * @}
1765 */
1766
1767 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1768 * @{
1769 */
1770
1771 /**
1772 * @brief Get DAC calibration offset flag for DAC channel 1
1773 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
1774 * @param DACx DAC instance
1775 * @retval State of bit (1 or 0).
1776 */
LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef * DACx)1777 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
1778 {
1779 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
1780 }
1781
1782
1783 /**
1784 * @brief Get DAC calibration offset flag for DAC channel 2
1785 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
1786 * @param DACx DAC instance
1787 * @retval State of bit (1 or 0).
1788 */
LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef * DACx)1789 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx)
1790 {
1791 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
1792 }
1793
1794
1795 /**
1796 * @brief Get DAC busy writing sample time flag for DAC channel 1
1797 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
1798 * @param DACx DAC instance
1799 * @retval State of bit (1 or 0).
1800 */
LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef * DACx)1801 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
1802 {
1803 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
1804 }
1805
1806 /**
1807 * @brief Get DAC busy writing sample time flag for DAC channel 2
1808 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
1809 * @param DACx DAC instance
1810 * @retval State of bit (1 or 0).
1811 */
LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef * DACx)1812 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx)
1813 {
1814 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
1815 }
1816
1817
1818 /**
1819 * @brief Get DAC ready status flag for DAC channel 1
1820 * @rmtoll SR DAC1RDY LL_DAC_IsActiveFlag_DAC1RDY
1821 * @param DACx DAC instance
1822 * @retval State of bit (1 or 0).
1823 */
LL_DAC_IsActiveFlag_DAC1RDY(const DAC_TypeDef * DACx)1824 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(const DAC_TypeDef *DACx)
1825 {
1826 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC1RDY) == (LL_DAC_FLAG_DAC1RDY)) ? 1UL : 0UL);
1827 }
1828
1829
1830 /**
1831 * @brief Get DAC ready status flag for DAC channel 2
1832 * @rmtoll SR DAC2RDY LL_DAC_IsActiveFlag_DAC2RDY
1833 * @param DACx DAC instance
1834 * @retval State of bit (1 or 0).
1835 */
LL_DAC_IsActiveFlag_DAC2RDY(const DAC_TypeDef * DACx)1836 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(const DAC_TypeDef *DACx)
1837 {
1838 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC2RDY) == (LL_DAC_FLAG_DAC2RDY)) ? 1UL : 0UL);
1839 }
1840
1841
1842 /**
1843 * @brief Get DAC output register status flag for DAC channel 1
1844 * @rmtoll SR DORSTAT1 LL_DAC_IsActiveFlag_DORSTAT1
1845 * @param DACx DAC instance
1846 * @retval State of bit (1 or 0).
1847 */
LL_DAC_IsActiveFlag_DORSTAT1(const DAC_TypeDef * DACx)1848 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(const DAC_TypeDef *DACx)
1849 {
1850 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT1) == (LL_DAC_FLAG_DORSTAT1)) ? 1UL : 0UL);
1851 }
1852
1853
1854 /**
1855 * @brief Get DAC output register status flag for DAC channel 2
1856 * @rmtoll SR DORSTAT2 LL_DAC_IsActiveFlag_DORSTAT2
1857 * @param DACx DAC instance
1858 * @retval State of bit (1 or 0).
1859 */
LL_DAC_IsActiveFlag_DORSTAT2(const DAC_TypeDef * DACx)1860 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(const DAC_TypeDef *DACx)
1861 {
1862 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT2) == (LL_DAC_FLAG_DORSTAT2)) ? 1UL : 0UL);
1863 }
1864
1865 /**
1866 * @brief Get DAC underrun flag for DAC channel 1
1867 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1868 * @param DACx DAC instance
1869 * @retval State of bit (1 or 0).
1870 */
LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef * DACx)1871 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
1872 {
1873 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1874 }
1875
1876
1877 /**
1878 * @brief Get DAC underrun flag for DAC channel 2
1879 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1880 * @param DACx DAC instance
1881 * @retval State of bit (1 or 0).
1882 */
LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef * DACx)1883 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
1884 {
1885 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1886 }
1887
1888
1889 /**
1890 * @brief Clear DAC underrun flag for DAC channel 1
1891 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1892 * @param DACx DAC instance
1893 * @retval None
1894 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1895 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1896 {
1897 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1898 }
1899
1900
1901 /**
1902 * @brief Clear DAC underrun flag for DAC channel 2
1903 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1904 * @param DACx DAC instance
1905 * @retval None
1906 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1907 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1908 {
1909 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1910 }
1911
1912
1913 /**
1914 * @}
1915 */
1916
1917 /** @defgroup DAC_LL_EF_IT_Management IT management
1918 * @{
1919 */
1920
1921 /**
1922 * @brief Enable DMA underrun interrupt for DAC channel 1
1923 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1924 * @param DACx DAC instance
1925 * @retval None
1926 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1927 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1928 {
1929 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1930 }
1931
1932
1933 /**
1934 * @brief Enable DMA underrun interrupt for DAC channel 2
1935 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1936 * @param DACx DAC instance
1937 * @retval None
1938 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1939 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1940 {
1941 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1942 }
1943
1944
1945 /**
1946 * @brief Disable DMA underrun interrupt for DAC channel 1
1947 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1948 * @param DACx DAC instance
1949 * @retval None
1950 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1951 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1952 {
1953 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1954 }
1955
1956
1957 /**
1958 * @brief Disable DMA underrun interrupt for DAC channel 2
1959 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1960 * @param DACx DAC instance
1961 * @retval None
1962 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1963 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1964 {
1965 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1966 }
1967
1968
1969 /**
1970 * @brief Get DMA underrun interrupt for DAC channel 1
1971 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1972 * @param DACx DAC instance
1973 * @retval State of bit (1 or 0).
1974 */
LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef * DACx)1975 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
1976 {
1977 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1978 }
1979
1980
1981 /**
1982 * @brief Get DMA underrun interrupt for DAC channel 2
1983 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1984 * @param DACx DAC instance
1985 * @retval State of bit (1 or 0).
1986 */
LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef * DACx)1987 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
1988 {
1989 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1990 }
1991
1992
1993 /**
1994 * @brief Enable DAC autonomous mode.
1995 * @rmtoll AUTOCR AUTOMODE LL_DAC_EnableAutonomousMode
1996 * @param DACx DAC instance
1997 * @retval None
1998 */
LL_DAC_EnableAutonomousMode(DAC_TypeDef * DACx)1999 __STATIC_INLINE void LL_DAC_EnableAutonomousMode(DAC_TypeDef *DACx)
2000 {
2001 SET_BIT(DACx->AUTOCR, DAC_AUTOCR_AUTOMODE);
2002 }
2003
2004 /**
2005 * @brief Disable DAC autonomous mode.
2006 * @rmtoll AUTOCR AUTOMODE LL_DAC_DisableAutonomousMode
2007 * @param DACx DAC instance
2008 * @retval None
2009 */
LL_DAC_DisableAutonomousMode(DAC_TypeDef * DACx)2010 __STATIC_INLINE void LL_DAC_DisableAutonomousMode(DAC_TypeDef *DACx)
2011 {
2012 CLEAR_BIT(DACx->AUTOCR, DAC_AUTOCR_AUTOMODE);
2013 }
2014
2015 /**
2016 * @brief Get DAC autonomous mode state.
2017 * (0: DAC autonomous mode is disabled, 1: DAC autonomous mode is enabled)
2018 * @param DACx DAC instance
2019 * @retval State of bit (1 or 0).
2020 */
LL_DAC_IsAutonomousModeEnabled(const DAC_TypeDef * DACx)2021 __STATIC_INLINE uint32_t LL_DAC_IsAutonomousModeEnabled(const DAC_TypeDef *DACx)
2022 {
2023 return ((READ_BIT(DACx->AUTOCR, DAC_AUTOCR_AUTOMODE) == (DAC_AUTOCR_AUTOMODE)) ? 1UL : 0UL);
2024 }
2025
2026 /**
2027 * @}
2028 */
2029
2030 #if defined(USE_FULL_LL_DRIVER)
2031 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
2032 * @{
2033 */
2034
2035 ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
2036 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
2037 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
2038
2039 /**
2040 * @}
2041 */
2042 #endif /* USE_FULL_LL_DRIVER */
2043
2044 /**
2045 * @}
2046 */
2047
2048 /**
2049 * @}
2050 */
2051
2052 #endif /* DAC1 */
2053
2054 /**
2055 * @}
2056 */
2057
2058 #ifdef __cplusplus
2059 }
2060 #endif
2061
2062 #endif /* STM32U5xx_LL_DAC_H */
2063
