1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_fdcan.h 4 * @author MCD Application Team 5 * @brief Header file of FDCAN HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_FDCAN_H 21 #define STM32U5xx_HAL_FDCAN_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 #if defined(FDCAN1) 31 32 /** @addtogroup STM32U5xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup FDCAN 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup FDCAN_Exported_Types FDCAN Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief HAL State structures definition 47 */ 48 typedef enum 49 { 50 HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */ 51 HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */ 52 HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */ 53 HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */ 54 } HAL_FDCAN_StateTypeDef; 55 56 /** 57 * @brief FDCAN Init structure definition 58 */ 59 typedef struct 60 { 61 uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider. 62 The clock is common to all FDCAN instances. 63 This parameter is applied only at initialisation of 64 first FDCAN instance. 65 This parameter can be a value of @ref FDCAN_clock_divider. */ 66 67 uint32_t FrameFormat; /*!< Specifies the FDCAN frame format. 68 This parameter can be a value of @ref FDCAN_frame_format */ 69 70 uint32_t Mode; /*!< Specifies the FDCAN mode. 71 This parameter can be a value of @ref FDCAN_operating_mode */ 72 73 FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode. 74 This parameter can be set to ENABLE or DISABLE */ 75 76 FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature. 77 This parameter can be set to ENABLE or DISABLE */ 78 79 FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling. 80 This parameter can be set to ENABLE or DISABLE */ 81 82 uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is 83 divided for generating the nominal bit time quanta. 84 This parameter must be a number between 1 and 512 */ 85 86 uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN 87 hardware is allowed to lengthen or shorten a bit to perform 88 resynchronization. 89 This parameter must be a number between 1 and 128 */ 90 91 uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. 92 This parameter must be a number between 2 and 256 */ 93 94 uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. 95 This parameter must be a number between 2 and 128 */ 96 97 uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is 98 divided for generating the data bit time quanta. 99 This parameter must be a number between 1 and 32 */ 100 101 uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN 102 hardware is allowed to lengthen or shorten a data bit to 103 perform resynchronization. 104 This parameter must be a number between 1 and 16 */ 105 106 uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1. 107 This parameter must be a number between 1 and 32 */ 108 109 uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2. 110 This parameter must be a number between 1 and 16 */ 111 112 uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters. 113 This parameter must be a number between 0 and 28 */ 114 115 uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters. 116 This parameter must be a number between 0 and 8 */ 117 118 uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection. 119 This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */ 120 121 } FDCAN_InitTypeDef; 122 123 /** 124 * @brief FDCAN filter structure definition 125 */ 126 typedef struct 127 { 128 uint32_t IdType; /*!< Specifies the identifier type. 129 This parameter can be a value of @ref FDCAN_id_type */ 130 131 uint32_t FilterIndex; /*!< Specifies the filter which will be initialized. 132 This parameter must be a number between: 133 - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID 134 - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */ 135 136 uint32_t FilterType; /*!< Specifies the filter type. 137 This parameter can be a value of @ref FDCAN_filter_type. 138 The value FDCAN_FILTER_RANGE_NO_EIDM is permitted 139 only when IdType is FDCAN_EXTENDED_ID. */ 140 141 uint32_t FilterConfig; /*!< Specifies the filter configuration. 142 This parameter can be a value of @ref FDCAN_filter_config */ 143 144 uint32_t FilterID1; /*!< Specifies the filter identification 1. 145 This parameter must be a number between: 146 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 147 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 148 149 uint32_t FilterID2; /*!< Specifies the filter identification 2. 150 This parameter must be a number between: 151 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 152 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 153 154 } FDCAN_FilterTypeDef; 155 156 /** 157 * @brief FDCAN Tx header structure definition 158 */ 159 typedef struct 160 { 161 uint32_t Identifier; /*!< Specifies the identifier. 162 This parameter must be a number between: 163 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 164 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 165 166 uint32_t IdType; /*!< Specifies the identifier type for the message that will be 167 transmitted. 168 This parameter can be a value of @ref FDCAN_id_type */ 169 170 uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted. 171 This parameter can be a value of @ref FDCAN_frame_type */ 172 173 uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted. 174 This parameter can be a value of @ref FDCAN_data_length_code */ 175 176 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 177 This parameter can be a value of @ref FDCAN_error_state_indicator */ 178 179 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without 180 bit rate switching. 181 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 182 183 uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or 184 FD format. 185 This parameter can be a value of @ref FDCAN_format */ 186 187 uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control. 188 This parameter can be a value of @ref FDCAN_EFC */ 189 190 uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO 191 element for identification of Tx message status. 192 This parameter must be a number between 0 and 0xFF */ 193 194 } FDCAN_TxHeaderTypeDef; 195 196 /** 197 * @brief FDCAN Rx header structure definition 198 */ 199 typedef struct 200 { 201 uint32_t Identifier; /*!< Specifies the identifier. 202 This parameter must be a number between: 203 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 204 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 205 206 uint32_t IdType; /*!< Specifies the identifier type of the received message. 207 This parameter can be a value of @ref FDCAN_id_type */ 208 209 uint32_t RxFrameType; /*!< Specifies the the received message frame type. 210 This parameter can be a value of @ref FDCAN_frame_type */ 211 212 uint32_t DataLength; /*!< Specifies the received frame length. 213 This parameter can be a value of @ref FDCAN_data_length_code */ 214 215 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 216 This parameter can be a value of @ref FDCAN_error_state_indicator */ 217 218 uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit 219 rate switching. 220 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 221 222 uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD 223 format. 224 This parameter can be a value of @ref FDCAN_format */ 225 226 uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame 227 reception. 228 This parameter must be a number between 0 and 0xFFFF */ 229 230 uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element. 231 This parameter must be a number between: 232 - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID 233 - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID 234 When the frame is a Non-Filter matching frame, this parameter 235 is unused. */ 236 237 uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter. 238 Acceptance of non-matching frames may be enabled via 239 HAL_FDCAN_ConfigGlobalFilter(). 240 This parameter takes 0 if the frame matched an Rx filter or 241 1 if it did not match any Rx filter */ 242 243 } FDCAN_RxHeaderTypeDef; 244 245 /** 246 * @brief FDCAN Tx event FIFO structure definition 247 */ 248 typedef struct 249 { 250 uint32_t Identifier; /*!< Specifies the identifier. 251 This parameter must be a number between: 252 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 253 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 254 255 uint32_t IdType; /*!< Specifies the identifier type for the transmitted message. 256 This parameter can be a value of @ref FDCAN_id_type */ 257 258 uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message. 259 This parameter can be a value of @ref FDCAN_frame_type */ 260 261 uint32_t DataLength; /*!< Specifies the length of the transmitted frame. 262 This parameter can be a value of @ref FDCAN_data_length_code */ 263 264 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 265 This parameter can be a value of @ref FDCAN_error_state_indicator */ 266 267 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit 268 rate switching. 269 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 270 271 uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD 272 format. 273 This parameter can be a value of @ref FDCAN_format */ 274 275 uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame 276 transmission. 277 This parameter must be a number between 0 and 0xFFFF */ 278 279 uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element 280 for identification of Tx message status. 281 This parameter must be a number between 0 and 0xFF */ 282 283 uint32_t EventType; /*!< Specifies the event type. 284 This parameter can be a value of @ref FDCAN_event_type */ 285 286 } FDCAN_TxEventFifoTypeDef; 287 288 /** 289 * @brief FDCAN High Priority Message Status structure definition 290 */ 291 typedef struct 292 { 293 uint32_t FilterList; /*!< Specifies the filter list of the matching filter element. 294 This parameter can be: 295 - 0 : Standard Filter List 296 - 1 : Extended Filter List */ 297 298 uint32_t FilterIndex; /*!< Specifies the index of matching filter element. 299 This parameter can be a number between: 300 - 0 and (SRAMCAN_FLS_NBR-1), if FilterList is 0 (Standard) 301 - 0 and (SRAMCAN_FLE_NBR-1), if FilterList is 1 (Extended) */ 302 303 uint32_t MessageStorage; /*!< Specifies the HP Message Storage. 304 This parameter can be a value of @ref FDCAN_hp_msg_storage */ 305 306 uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the 307 message was stored. 308 This parameter is valid only when MessageStorage is: 309 FDCAN_HP_STORAGE_RXFIFO0 310 or 311 FDCAN_HP_STORAGE_RXFIFO1 */ 312 313 } FDCAN_HpMsgStatusTypeDef; 314 315 /** 316 * @brief FDCAN Protocol Status structure definition 317 */ 318 typedef struct 319 { 320 uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus. 321 This parameter can be a value of @ref FDCAN_protocol_error_code */ 322 323 uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase 324 of a CAN FD format frame with its BRS flag set. 325 This parameter can be a value of @ref FDCAN_protocol_error_code */ 326 327 uint32_t Activity; /*!< Specifies the FDCAN module communication state. 328 This parameter can be a value of @ref FDCAN_communication_state */ 329 330 uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status. 331 This parameter can be: 332 - 0 : The FDCAN is in Error_Active state 333 - 1 : The FDCAN is in Error_Passive state */ 334 335 uint32_t Warning; /*!< Specifies the FDCAN module warning status. 336 This parameter can be: 337 - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the 338 Error_Warning limit of 96 339 - 1 : at least one of error counters has reached the Error_Warning 340 limit of 96 */ 341 342 uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status. 343 This parameter can be: 344 - 0 : The FDCAN is not in Bus_Off state 345 - 1 : The FDCAN is in Bus_Off state */ 346 347 uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message. 348 This parameter can be: 349 - 0 : Last received CAN FD message did not have its ESI flag set 350 - 1 : Last received CAN FD message had its ESI flag set */ 351 352 uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message. 353 This parameter can be: 354 - 0 : Last received CAN FD message did not have its BRS flag set 355 - 1 : Last received CAN FD message had its BRS flag set */ 356 357 uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received 358 since last protocol status. 359 This parameter can be: 360 - 0 : No CAN FD message received 361 - 1 : CAN FD message received */ 362 363 uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status. 364 This parameter can be: 365 - 0 : No protocol exception event occurred since last read access 366 - 1 : Protocol exception event occurred */ 367 368 uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value. 369 This parameter can be a number between 0 and 127 */ 370 371 } FDCAN_ProtocolStatusTypeDef; 372 373 /** 374 * @brief FDCAN Error Counters structure definition 375 */ 376 typedef struct 377 { 378 uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. 379 This parameter can be a number between 0 and 255 */ 380 381 uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. 382 This parameter can be a number between 0 and 127 */ 383 384 uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status. 385 This parameter can be: 386 - 0 : The Receive Error Counter (RxErrorCnt) is below the error 387 passive level of 128 388 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error 389 passive level of 128 */ 390 391 uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. 392 This parameter can be a number between 0 and 255. 393 This counter is incremented each time when a FDCAN protocol error causes 394 the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255; 395 the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag 396 FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ 397 398 } FDCAN_ErrorCountersTypeDef; 399 400 /** 401 * @brief FDCAN Message RAM blocks 402 */ 403 typedef struct 404 { 405 uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address. 406 This parameter must be a 32-bit word address */ 407 408 uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address. 409 This parameter must be a 32-bit word address */ 410 411 uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address. 412 This parameter must be a 32-bit word address */ 413 414 uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address. 415 This parameter must be a 32-bit word address */ 416 417 uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address. 418 This parameter must be a 32-bit word address */ 419 420 uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address. 421 This parameter must be a 32-bit word address */ 422 423 } FDCAN_MsgRamAddressTypeDef; 424 425 /** 426 * @brief FDCAN handle structure definition 427 */ 428 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 429 typedef struct __FDCAN_HandleTypeDef 430 #else 431 typedef struct 432 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 433 { 434 FDCAN_GlobalTypeDef *Instance; /*!< Register base address */ 435 436 FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */ 437 438 FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */ 439 440 uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index 441 of latest Tx FIFO/Queue request */ 442 443 __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */ 444 445 HAL_LockTypeDef Lock; /*!< FDCAN locking object */ 446 447 __IO uint32_t ErrorCode; /*!< FDCAN Error code */ 448 449 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 450 void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */ 451 void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */ 452 void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */ 453 void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Tx Fifo Empty callback */ 454 void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */ 455 void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */ 456 void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN High priority message callback */ 457 void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timestamp wraparound callback */ 458 void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timeout occurred callback */ 459 void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */ 460 void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */ 461 462 void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */ 463 void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */ 464 465 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 466 467 } FDCAN_HandleTypeDef; 468 469 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 470 /** 471 * @brief HAL FDCAN common Callback ID enumeration definition 472 */ 473 typedef enum 474 { 475 HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */ 476 HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x01U, /*!< FDCAN High priority message callback ID */ 477 HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x02U, /*!< FDCAN Timestamp wraparound callback ID */ 478 HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x03U, /*!< FDCAN Timeout occurred callback ID */ 479 HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x04U, /*!< FDCAN Error callback ID */ 480 481 HAL_FDCAN_MSPINIT_CB_ID = 0x05U, /*!< FDCAN MspInit callback ID */ 482 HAL_FDCAN_MSPDEINIT_CB_ID = 0x06U, /*!< FDCAN MspDeInit callback ID */ 483 484 } HAL_FDCAN_CallbackIDTypeDef; 485 486 /** 487 * @brief HAL FDCAN Callback pointer definition 488 */ 489 typedef void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan); /*!< pointer to a common FDCAN callback function */ 490 typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback function */ 491 typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */ 492 typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */ 493 typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */ 494 typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback function */ 495 typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */ 496 497 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 498 499 /** 500 * @} 501 */ 502 503 /* Exported constants --------------------------------------------------------*/ 504 /** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants 505 * @{ 506 */ 507 508 /** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code 509 * @{ 510 */ 511 #define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 512 #define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 513 #define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */ 514 #define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */ 515 #define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */ 516 #define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */ 517 #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ 518 #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ 519 #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ 520 #define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ 521 #define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ 522 #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ 523 #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ 524 #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ 525 #define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */ 526 #define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */ 527 528 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 529 #define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error */ 530 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 531 /** 532 * @} 533 */ 534 535 /** @defgroup FDCAN_frame_format FDCAN Frame Format 536 * @{ 537 */ 538 #define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */ 539 #define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */ 540 #define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */ 541 /** 542 * @} 543 */ 544 545 /** @defgroup FDCAN_operating_mode FDCAN Operating Mode 546 * @{ 547 */ 548 #define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ 549 #define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */ 550 #define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */ 551 #define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */ 552 #define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */ 553 /** 554 * @} 555 */ 556 557 /** @defgroup FDCAN_clock_divider FDCAN Clock Divider 558 * @{ 559 */ 560 #define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */ 561 #define FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2 */ 562 #define FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4 */ 563 #define FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6 */ 564 #define FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8 */ 565 #define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */ 566 #define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */ 567 #define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */ 568 #define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */ 569 #define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */ 570 #define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */ 571 #define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */ 572 #define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */ 573 #define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */ 574 #define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */ 575 #define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */ 576 /** 577 * @} 578 */ 579 580 /** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode 581 * @{ 582 */ 583 #define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */ 584 #define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */ 585 /** 586 * @} 587 */ 588 589 /** @defgroup FDCAN_id_type FDCAN ID Type 590 * @{ 591 */ 592 #define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */ 593 #define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */ 594 /** 595 * @} 596 */ 597 598 /** @defgroup FDCAN_frame_type FDCAN Frame Type 599 * @{ 600 */ 601 #define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */ 602 #define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */ 603 /** 604 * @} 605 */ 606 607 /** @defgroup FDCAN_data_length_code FDCAN Data Length Code 608 * @{ 609 */ 610 #define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */ 611 #define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U) /*!< 1 bytes data field */ 612 #define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U) /*!< 2 bytes data field */ 613 #define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U) /*!< 3 bytes data field */ 614 #define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U) /*!< 4 bytes data field */ 615 #define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U) /*!< 5 bytes data field */ 616 #define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U) /*!< 6 bytes data field */ 617 #define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U) /*!< 7 bytes data field */ 618 #define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U) /*!< 8 bytes data field */ 619 #define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */ 620 #define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */ 621 #define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */ 622 #define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */ 623 #define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */ 624 #define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */ 625 #define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */ 626 /** 627 * @} 628 */ 629 630 /** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator 631 * @{ 632 */ 633 #define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */ 634 #define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */ 635 /** 636 * @} 637 */ 638 639 /** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching 640 * @{ 641 */ 642 #define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */ 643 #define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */ 644 /** 645 * @} 646 */ 647 648 /** @defgroup FDCAN_format FDCAN format 649 * @{ 650 */ 651 #define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */ 652 #define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */ 653 /** 654 * @} 655 */ 656 657 /** @defgroup FDCAN_EFC FDCAN Event FIFO control 658 * @{ 659 */ 660 #define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */ 661 #define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */ 662 /** 663 * @} 664 */ 665 666 /** @defgroup FDCAN_filter_type FDCAN Filter Type 667 * @{ 668 */ 669 #define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */ 670 #define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */ 671 #define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */ 672 #define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */ 673 /** 674 * @} 675 */ 676 677 /** @defgroup FDCAN_filter_config FDCAN Filter Configuration 678 * @{ 679 */ 680 #define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */ 681 #define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */ 682 #define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */ 683 #define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */ 684 #define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */ 685 #define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */ 686 #define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */ 687 /** 688 * @} 689 */ 690 691 /** @defgroup FDCAN_Tx_location FDCAN Tx Location 692 * @{ 693 */ 694 #define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */ 695 #define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */ 696 #define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */ 697 /** 698 * @} 699 */ 700 701 /** @defgroup FDCAN_Rx_location FDCAN Rx Location 702 * @{ 703 */ 704 #define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */ 705 #define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */ 706 /** 707 * @} 708 */ 709 710 /** @defgroup FDCAN_event_type FDCAN Event Type 711 * @{ 712 */ 713 #define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */ 714 #define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */ 715 /** 716 * @} 717 */ 718 719 /** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage 720 * @{ 721 */ 722 #define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */ 723 #define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */ 724 #define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */ 725 #define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */ 726 /** 727 * @} 728 */ 729 730 /** @defgroup FDCAN_protocol_error_code FDCAN protocol error code 731 * @{ 732 */ 733 #define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */ 734 #define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */ 735 #define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */ 736 #define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */ 737 #define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */ 738 #define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */ 739 #define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */ 740 #define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */ 741 /** 742 * @} 743 */ 744 745 /** @defgroup FDCAN_communication_state FDCAN communication state 746 * @{ 747 */ 748 #define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */ 749 #define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */ 750 #define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */ 751 #define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */ 752 /** 753 * @} 754 */ 755 756 /** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode 757 * @{ 758 */ 759 #define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */ 760 #define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */ 761 /** 762 * @} 763 */ 764 765 /** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames 766 * @{ 767 */ 768 #define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */ 769 #define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */ 770 #define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */ 771 /** 772 * @} 773 */ 774 775 /** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames 776 * @{ 777 */ 778 #define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */ 779 #define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */ 780 /** 781 * @} 782 */ 783 784 /** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line 785 * @{ 786 */ 787 #define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */ 788 #define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */ 789 /** 790 * @} 791 */ 792 793 /** @defgroup FDCAN_Timestamp FDCAN timestamp 794 * @{ 795 */ 796 #define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */ 797 #define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */ 798 /** 799 * @} 800 */ 801 802 /** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler 803 * @{ 804 */ 805 #define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */ 806 #define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2 */ 807 #define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3 */ 808 #define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4 */ 809 #define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5 */ 810 #define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6 */ 811 #define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7 */ 812 #define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8 */ 813 #define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9 */ 814 #define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */ 815 #define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */ 816 #define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */ 817 #define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */ 818 #define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */ 819 #define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */ 820 #define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */ 821 /** 822 * @} 823 */ 824 825 /** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation 826 * @{ 827 */ 828 #define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */ 829 #define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */ 830 #define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */ 831 #define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */ 832 /** 833 * @} 834 */ 835 836 /** @defgroup Interrupt_Masks Interrupt masks 837 * @{ 838 */ 839 #define FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU) /*!< FDCAN interrupts mask */ 840 #define FDCAN_ILS_MASK ((uint32_t)0x0000007FU) /*!< FDCAN interrupts group mask */ 841 /** 842 * @} 843 */ 844 845 /** @defgroup FDCAN_flags FDCAN Flags 846 * @{ 847 */ 848 #define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */ 849 #define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */ 850 #define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */ 851 #define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */ 852 #define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */ 853 #define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */ 854 #define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */ 855 #define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */ 856 #define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */ 857 #define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */ 858 #define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */ 859 #define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */ 860 #define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */ 861 #define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */ 862 #define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */ 863 #define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */ 864 #define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */ 865 #define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */ 866 #define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */ 867 #define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */ 868 #define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */ 869 #define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */ 870 #define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */ 871 #define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */ 872 /** 873 * @} 874 */ 875 876 /** @defgroup FDCAN_Interrupts FDCAN Interrupts 877 * @{ 878 */ 879 880 /** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts 881 * @{ 882 */ 883 #define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */ 884 #define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */ 885 #define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */ 886 /** 887 * @} 888 */ 889 890 /** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts 891 * @{ 892 */ 893 #define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */ 894 /** 895 * @} 896 */ 897 898 /** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts 899 * @{ 900 */ 901 #define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */ 902 #define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */ 903 /** 904 * @} 905 */ 906 907 /** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts 908 * @{ 909 */ 910 #define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */ 911 #define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */ 912 #define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */ 913 /** 914 * @} 915 */ 916 917 /** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts 918 * @{ 919 */ 920 #define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */ 921 #define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */ 922 #define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */ 923 /** 924 * @} 925 */ 926 927 /** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts 928 * @{ 929 */ 930 #define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */ 931 #define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */ 932 #define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */ 933 /** 934 * @} 935 */ 936 937 /** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts 938 * @{ 939 */ 940 #define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */ 941 #define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */ 942 #define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */ 943 #define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */ 944 #define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */ 945 #define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */ 946 /** 947 * @} 948 */ 949 950 /** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts 951 * @{ 952 */ 953 #define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */ 954 #define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */ 955 #define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */ 956 /** 957 * @} 958 */ 959 960 /** 961 * @} 962 */ 963 964 /** @defgroup FDCAN_Interrupts_List FDCAN Interrupts List 965 * @{ 966 */ 967 #define FDCAN_IT_LIST_RX_FIFO0 (FDCAN_IT_RX_FIFO0_MESSAGE_LOST | \ 968 FDCAN_IT_RX_FIFO0_FULL | \ 969 FDCAN_IT_RX_FIFO0_NEW_MESSAGE) /*!< RX FIFO 0 Interrupts List */ 970 #define FDCAN_IT_LIST_RX_FIFO1 (FDCAN_IT_RX_FIFO1_MESSAGE_LOST | \ 971 FDCAN_IT_RX_FIFO1_FULL | \ 972 FDCAN_IT_RX_FIFO1_NEW_MESSAGE) /*!< RX FIFO 1 Interrupts List */ 973 #define FDCAN_IT_LIST_SMSG (FDCAN_IT_TX_ABORT_COMPLETE | \ 974 FDCAN_IT_TX_COMPLETE | \ 975 FDCAN_IT_RX_HIGH_PRIORITY_MSG) /*!< Status Message Interrupts List */ 976 #define FDCAN_IT_LIST_TX_FIFO_ERROR (FDCAN_IT_TX_EVT_FIFO_ELT_LOST | \ 977 FDCAN_IT_TX_EVT_FIFO_FULL | \ 978 FDCAN_IT_TX_EVT_FIFO_NEW_DATA | \ 979 FDCAN_IT_TX_FIFO_EMPTY) /*!< TX FIFO Error Interrupts List */ 980 #define FDCAN_IT_LIST_MISC (FDCAN_IT_TIMEOUT_OCCURRED | \ 981 FDCAN_IT_RAM_ACCESS_FAILURE | \ 982 FDCAN_IT_TIMESTAMP_WRAPAROUND) /*!< Misc. Interrupts List */ 983 #define FDCAN_IT_LIST_BIT_LINE_ERROR (FDCAN_IT_ERROR_PASSIVE | \ 984 FDCAN_IT_ERROR_LOGGING_OVERFLOW) /*!< Bit and Line Error Interrupts List */ 985 #define FDCAN_IT_LIST_PROTOCOL_ERROR (FDCAN_IT_RESERVED_ADDRESS_ACCESS | \ 986 FDCAN_IT_DATA_PROTOCOL_ERROR | \ 987 FDCAN_IT_ARB_PROTOCOL_ERROR | \ 988 FDCAN_IT_RAM_WATCHDOG | \ 989 FDCAN_IT_BUS_OFF | \ 990 FDCAN_IT_ERROR_WARNING) /*!< Protocol Error Interrupts List */ 991 /** 992 * @} 993 */ 994 995 /** @defgroup FDCAN_Interrupts_Group FDCAN Interrupts Group 996 * @{ 997 */ 998 #define FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RXFIFO0 /*!< RX FIFO 0 Interrupts Group: 999 RF0LL: Rx FIFO 0 Message Lost 1000 RF0FL: Rx FIFO 0 is Full 1001 RF0NL: Rx FIFO 0 Has New Message */ 1002 #define FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RXFIFO1 /*!< RX FIFO 1 Interrupts Group: 1003 RF1LL: Rx FIFO 1 Message Lost 1004 RF1FL: Rx FIFO 1 is Full 1005 RF1NL: Rx FIFO 1 Has New Message */ 1006 #define FDCAN_IT_GROUP_SMSG FDCAN_ILS_SMSG /*!< Status Message Interrupts Group: 1007 TCFL: Transmission Cancellation Finished 1008 TCL: Transmission Completed 1009 HPML: High Priority Message */ 1010 #define FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFERR /*!< TX FIFO Error Interrupts Group: 1011 TEFLL: Tx Event FIFO Element Lost 1012 TEFFL: Tx Event FIFO Full 1013 TEFNL: Tx Event FIFO New Entry 1014 TFEL: Tx FIFO Empty Interrupt Line */ 1015 #define FDCAN_IT_GROUP_MISC FDCAN_ILS_MISC /*!< Misc. Interrupts Group: 1016 TOOL: Timeout Occurred 1017 MRAFL: Message RAM Access Failure 1018 TSWL: Timestamp Wraparound */ 1019 #define FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_BERR /*!< Bit and Line Error Interrupts Group: 1020 EPL: Error Passive 1021 ELOL: Error Logging Overflow */ 1022 #define FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_PERR /*!< Protocol Error Group: 1023 ARAL: Access to Reserved Address Line 1024 PEDL: Protocol Error in Data Phase Line 1025 PEAL: Protocol Error in Arbitration Phase Line 1026 WDIL: Watchdog Interrupt Line 1027 BOL: Bus_Off Status 1028 EWL: Warning Status */ 1029 /** 1030 * @} 1031 */ 1032 1033 /** 1034 * @} 1035 */ 1036 1037 /* Exported macro ------------------------------------------------------------*/ 1038 /** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros 1039 * @{ 1040 */ 1041 1042 /** @brief Reset FDCAN handle state. 1043 * @param __HANDLE__ FDCAN handle. 1044 * @retval None 1045 */ 1046 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 1047 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1048 (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \ 1049 (__HANDLE__)->MspInitCallback = NULL; \ 1050 (__HANDLE__)->MspDeInitCallback = NULL; \ 1051 } while(0) 1052 #else 1053 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET) 1054 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 1055 1056 /** 1057 * @brief Enable the specified FDCAN interrupts. 1058 * @param __HANDLE__ FDCAN handle. 1059 * @param __INTERRUPT__ FDCAN interrupt. 1060 * This parameter can be any combination of @arg FDCAN_Interrupts 1061 * @retval None 1062 */ 1063 #define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1064 (__HANDLE__)->Instance->IE |= (__INTERRUPT__) 1065 1066 /** 1067 * @brief Disable the specified FDCAN interrupts. 1068 * @param __HANDLE__ FDCAN handle. 1069 * @param __INTERRUPT__ FDCAN interrupt. 1070 * This parameter can be any combination of @arg FDCAN_Interrupts 1071 * @retval None 1072 */ 1073 #define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1074 ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__) 1075 1076 /** 1077 * @brief Check whether the specified FDCAN interrupt is set or not. 1078 * @param __HANDLE__ FDCAN handle. 1079 * @param __INTERRUPT__ FDCAN interrupt. 1080 * This parameter can be one of @arg FDCAN_Interrupts 1081 * @retval ITStatus 1082 */ 1083 #define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) 1084 1085 /** 1086 * @brief Clear the specified FDCAN interrupts. 1087 * @param __HANDLE__ FDCAN handle. 1088 * @param __INTERRUPT__ specifies the interrupts to clear. 1089 * This parameter can be any combination of @arg FDCAN_Interrupts 1090 * @retval None 1091 */ 1092 #define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \ 1093 ((__HANDLE__)->Instance->IR) = (__INTERRUPT__) 1094 1095 /** 1096 * @brief Check whether the specified FDCAN flag is set or not. 1097 * @param __HANDLE__ FDCAN handle. 1098 * @param __FLAG__ FDCAN flag. 1099 * This parameter can be one of @arg FDCAN_flags 1100 * @retval FlagStatus 1101 */ 1102 #define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR & (__FLAG__)) 1103 1104 /** 1105 * @brief Clear the specified FDCAN flags. 1106 * @param __HANDLE__ FDCAN handle. 1107 * @param __FLAG__ specifies the flags to clear. 1108 * This parameter can be any combination of @arg FDCAN_flags 1109 * @retval None 1110 */ 1111 #define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1112 ((__HANDLE__)->Instance->IR) = (__FLAG__) 1113 1114 /** @brief Check if the specified FDCAN interrupt source is enabled or disabled. 1115 * @param __HANDLE__ FDCAN handle. 1116 * @param __INTERRUPT__ specifies the FDCAN interrupt source to check. 1117 * This parameter can be a value of @arg FDCAN_Interrupts 1118 * @retval ITStatus 1119 */ 1120 #define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) 1121 1122 /** 1123 * @} 1124 */ 1125 1126 /* Exported functions --------------------------------------------------------*/ 1127 /** @addtogroup FDCAN_Exported_Functions 1128 * @{ 1129 */ 1130 1131 /** @addtogroup FDCAN_Exported_Functions_Group1 1132 * @{ 1133 */ 1134 /* Initialization and de-initialization functions *****************************/ 1135 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan); 1136 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan); 1137 void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan); 1138 void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan); 1139 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan); 1140 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan); 1141 1142 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 1143 /* Callbacks Register/UnRegister functions ***********************************/ 1144 HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, 1145 pFDCAN_CallbackTypeDef pCallback); 1146 HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID); 1147 HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, 1148 pFDCAN_TxEventFifoCallbackTypeDef pCallback); 1149 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan); 1150 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, 1151 pFDCAN_RxFifo0CallbackTypeDef pCallback); 1152 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan); 1153 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, 1154 pFDCAN_RxFifo1CallbackTypeDef pCallback); 1155 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan); 1156 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, 1157 pFDCAN_TxBufferCompleteCallbackTypeDef pCallback); 1158 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan); 1159 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, 1160 pFDCAN_TxBufferAbortCallbackTypeDef pCallback); 1161 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan); 1162 HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, 1163 pFDCAN_ErrorStatusCallbackTypeDef pCallback); 1164 HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan); 1165 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 1166 /** 1167 * @} 1168 */ 1169 1170 /** @addtogroup FDCAN_Exported_Functions_Group2 1171 * @{ 1172 */ 1173 /* Configuration functions ****************************************************/ 1174 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig); 1175 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, 1176 uint32_t NonMatchingExt, uint32_t RejectRemoteStd, 1177 uint32_t RejectRemoteExt); 1178 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask); 1179 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode); 1180 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue); 1181 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler); 1182 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation); 1183 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 1184 uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan); 1185 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 1186 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, 1187 uint32_t TimeoutPeriod); 1188 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1189 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1190 uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan); 1191 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1192 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, 1193 uint32_t TdcFilter); 1194 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); 1195 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); 1196 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan); 1197 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan); 1198 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); 1199 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); 1200 /** 1201 * @} 1202 */ 1203 1204 /** @addtogroup FDCAN_Exported_Functions_Group3 1205 * @{ 1206 */ 1207 /* Control functions **********************************************************/ 1208 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); 1209 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); 1210 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, 1211 const uint8_t *pTxData); 1212 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan); 1213 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); 1214 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, 1215 FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); 1216 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent); 1217 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan, 1218 FDCAN_HpMsgStatusTypeDef *HpMsgStatus); 1219 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan, 1220 FDCAN_ProtocolStatusTypeDef *ProtocolStatus); 1221 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan, 1222 FDCAN_ErrorCountersTypeDef *ErrorCounters); 1223 uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); 1224 uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); 1225 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan); 1226 uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan); 1227 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); 1228 /** 1229 * @} 1230 */ 1231 1232 /** @addtogroup FDCAN_Exported_Functions_Group4 1233 * @{ 1234 */ 1235 /* Interrupts management ******************************************************/ 1236 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine); 1237 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, 1238 uint32_t BufferIndexes); 1239 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs); 1240 void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan); 1241 /** 1242 * @} 1243 */ 1244 1245 /** @addtogroup FDCAN_Exported_Functions_Group5 1246 * @{ 1247 */ 1248 /* Callback functions *********************************************************/ 1249 void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); 1250 void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); 1251 void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); 1252 void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan); 1253 void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); 1254 void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); 1255 void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan); 1256 void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan); 1257 void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan); 1258 void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan); 1259 void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); 1260 /** 1261 * @} 1262 */ 1263 1264 /** @addtogroup FDCAN_Exported_Functions_Group6 1265 * @{ 1266 */ 1267 /* Peripheral State functions *************************************************/ 1268 uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan); 1269 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan); 1270 /** 1271 * @} 1272 */ 1273 1274 /** 1275 * @} 1276 */ 1277 1278 /* Private types -------------------------------------------------------------*/ 1279 /* Private variables ---------------------------------------------------------*/ 1280 /** @defgroup FDCAN_Private_Variables FDCAN Private Variables 1281 * @{ 1282 */ 1283 1284 /** 1285 * @} 1286 */ 1287 1288 /* Private constants ---------------------------------------------------------*/ 1289 /** @defgroup FDCAN_Private_Constants FDCAN Private Constants 1290 * @{ 1291 */ 1292 1293 /** 1294 * @} 1295 */ 1296 1297 /* Private macros ------------------------------------------------------------*/ 1298 /** @defgroup FDCAN_Private_Macros FDCAN Private Macros 1299 * @{ 1300 */ 1301 #define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \ 1302 ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \ 1303 ((FORMAT) == FDCAN_FRAME_FD_BRS )) 1304 #define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \ 1305 ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \ 1306 ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \ 1307 ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \ 1308 ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK )) 1309 #define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \ 1310 ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \ 1311 ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \ 1312 ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \ 1313 ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \ 1314 ((CKDIV) == FDCAN_CLOCK_DIV10) || \ 1315 ((CKDIV) == FDCAN_CLOCK_DIV12) || \ 1316 ((CKDIV) == FDCAN_CLOCK_DIV14) || \ 1317 ((CKDIV) == FDCAN_CLOCK_DIV16) || \ 1318 ((CKDIV) == FDCAN_CLOCK_DIV18) || \ 1319 ((CKDIV) == FDCAN_CLOCK_DIV20) || \ 1320 ((CKDIV) == FDCAN_CLOCK_DIV22) || \ 1321 ((CKDIV) == FDCAN_CLOCK_DIV24) || \ 1322 ((CKDIV) == FDCAN_CLOCK_DIV26) || \ 1323 ((CKDIV) == FDCAN_CLOCK_DIV28) || \ 1324 ((CKDIV) == FDCAN_CLOCK_DIV30)) 1325 #define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U)) 1326 #define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U)) 1327 #define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U)) 1328 #define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U)) 1329 #define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U)) 1330 #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U)) 1331 #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U)) 1332 #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U)) 1333 #define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_)) 1334 #define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_)) 1335 #define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \ 1336 ((MODE) == FDCAN_TX_QUEUE_OPERATION)) 1337 #define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \ 1338 ((ID_TYPE) == FDCAN_EXTENDED_ID)) 1339 #define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \ 1340 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \ 1341 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \ 1342 ((CONFIG) == FDCAN_FILTER_REJECT ) || \ 1343 ((CONFIG) == FDCAN_FILTER_HP ) || \ 1344 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \ 1345 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP)) 1346 #define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \ 1347 ((LOCATION) == FDCAN_TX_BUFFER2 )) 1348 #define IS_FDCAN_TX_LOCATION_LIST(LOCATION) (((LOCATION) >= FDCAN_TX_BUFFER0) && \ 1349 ((LOCATION) <= (FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2))) 1350 #define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \ 1351 ((FIFO) == FDCAN_RX_FIFO1)) 1352 #define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \ 1353 ((MODE) == FDCAN_RX_FIFO_OVERWRITE)) 1354 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \ 1355 ((TYPE) == FDCAN_FILTER_DUAL ) || \ 1356 ((TYPE) == FDCAN_FILTER_MASK )) 1357 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \ 1358 ((TYPE) == FDCAN_FILTER_DUAL ) || \ 1359 ((TYPE) == FDCAN_FILTER_MASK ) || \ 1360 ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM)) 1361 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \ 1362 ((TYPE) == FDCAN_REMOTE_FRAME)) 1363 #define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \ 1364 ((DLC) == FDCAN_DLC_BYTES_1 ) || \ 1365 ((DLC) == FDCAN_DLC_BYTES_2 ) || \ 1366 ((DLC) == FDCAN_DLC_BYTES_3 ) || \ 1367 ((DLC) == FDCAN_DLC_BYTES_4 ) || \ 1368 ((DLC) == FDCAN_DLC_BYTES_5 ) || \ 1369 ((DLC) == FDCAN_DLC_BYTES_6 ) || \ 1370 ((DLC) == FDCAN_DLC_BYTES_7 ) || \ 1371 ((DLC) == FDCAN_DLC_BYTES_8 ) || \ 1372 ((DLC) == FDCAN_DLC_BYTES_12) || \ 1373 ((DLC) == FDCAN_DLC_BYTES_16) || \ 1374 ((DLC) == FDCAN_DLC_BYTES_20) || \ 1375 ((DLC) == FDCAN_DLC_BYTES_24) || \ 1376 ((DLC) == FDCAN_DLC_BYTES_32) || \ 1377 ((DLC) == FDCAN_DLC_BYTES_48) || \ 1378 ((DLC) == FDCAN_DLC_BYTES_64)) 1379 #define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \ 1380 ((ESI) == FDCAN_ESI_PASSIVE)) 1381 #define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \ 1382 ((BRS) == FDCAN_BRS_ON )) 1383 #define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \ 1384 ((FDF) == FDCAN_FD_CAN )) 1385 #define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \ 1386 ((EFC) == FDCAN_STORE_TX_EVENTS)) 1387 #define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U) 1388 #define IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U) 1389 #define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \ 1390 ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \ 1391 ((DESTINATION) == FDCAN_REJECT )) 1392 #define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \ 1393 ((DESTINATION) == FDCAN_REJECT_REMOTE)) 1394 #define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \ 1395 ((IT_LINE) == FDCAN_INTERRUPT_LINE1)) 1396 #define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \ 1397 ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL)) 1398 #define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \ 1399 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \ 1400 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \ 1401 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \ 1402 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \ 1403 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \ 1404 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \ 1405 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \ 1406 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \ 1407 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \ 1408 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \ 1409 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \ 1410 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \ 1411 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \ 1412 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \ 1413 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16)) 1414 #define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \ 1415 ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \ 1416 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \ 1417 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 )) 1418 1419 #define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET) 1420 1421 #define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 1422 /** 1423 * @} 1424 */ 1425 1426 /* Private functions prototypes ----------------------------------------------*/ 1427 /* Private functions ---------------------------------------------------------*/ 1428 1429 /** 1430 * @} 1431 */ 1432 1433 /** 1434 * @} 1435 */ 1436 #endif /* FDCAN1 */ 1437 1438 #ifdef __cplusplus 1439 } 1440 #endif 1441 1442 #endif /* STM32U5xx_HAL_FDCAN_H */ 1443
