1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32mp1xx_ll_spi.h"
22 #include "stm32mp1xx_ll_bus.h"
23 #include "stm32mp1xx_ll_rcc.h"
24 #ifdef GENERATOR_I2S_PRESENT
25 #include "stm32mp1xx_ll_rcc.h"
26 #endif /* GENERATOR_I2S_PRESENT*/
27 #ifdef USE_FULL_ASSERT
28 #include "stm32_assert.h"
29 #else
30 #define assert_param(expr) ((void)0U)
31 #endif /* USE_FULL_ASSERT */
32
33 /** @addtogroup STM32MP1xx_LL_Driver
34 * @{
35 */
36
37 #if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
38
39 /** @addtogroup SPI_LL
40 * @{
41 */
42
43 /* Private types -------------------------------------------------------------*/
44 /* Private variables ---------------------------------------------------------*/
45 /* Private constants ---------------------------------------------------------*/
46 /* Private macros ------------------------------------------------------------*/
47 /** @addtogroup SPI_LL_Private_Macros
48 * @{
49 */
50
51 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) || \
52 ((__VALUE__) == LL_SPI_MODE_SLAVE))
53
54 #define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) || \
55 ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) || \
56 ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) || \
57 ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) || \
58 ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) || \
59 ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) || \
60 ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) || \
61 ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) || \
62 ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) || \
63 ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) || \
64 ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) || \
65 ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) || \
66 ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) || \
67 ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) || \
68 ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) || \
69 ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE))
70
71 #define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) || \
72 ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) || \
73 ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) || \
74 ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) || \
75 ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) || \
76 ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) || \
77 ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) || \
78 ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) || \
79 ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) || \
80 ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) || \
81 ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) || \
82 ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) || \
83 ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) || \
84 ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) || \
85 ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) || \
86 ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE))
87
88 #define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) || \
89 ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN))
90
91 #define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) || \
92 ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN))
93
94 #define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) || \
95 ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) || \
96 ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED))
97
98 #define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) || \
99 ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) || \
100 ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS))
101
102 #define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) || \
103 ((__VALUE__) == LL_SPI_PROTOCOL_TI))
104
105 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) || \
106 ((__VALUE__) == LL_SPI_PHASE_2EDGE))
107
108 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) || \
109 ((__VALUE__) == LL_SPI_POLARITY_HIGH))
110
111 #define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) || \
112 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) || \
113 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) || \
114 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) || \
115 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) || \
116 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) || \
117 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) || \
118 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
119
120 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) || \
121 ((__VALUE__) == LL_SPI_MSB_FIRST))
122
123 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) || \
124 ((__VALUE__) == LL_SPI_SIMPLEX_TX) || \
125 ((__VALUE__) == LL_SPI_SIMPLEX_RX) || \
126 ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) || \
127 ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
128
129 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) || \
130 ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) || \
131 ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) || \
132 ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) || \
133 ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) || \
134 ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) || \
135 ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) || \
136 ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) || \
137 ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) || \
138 ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) || \
139 ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) || \
140 ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) || \
141 ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) || \
142 ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) || \
143 ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) || \
144 ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) || \
145 ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) || \
146 ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) || \
147 ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) || \
148 ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) || \
149 ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) || \
150 ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) || \
151 ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) || \
152 ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) || \
153 ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) || \
154 ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) || \
155 ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) || \
156 ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) || \
157 ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT))
158
159 #define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) || \
160 ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) || \
161 ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) || \
162 ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) || \
163 ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) || \
164 ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) || \
165 ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) || \
166 ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) || \
167 ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) || \
168 ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) || \
169 ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) || \
170 ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) || \
171 ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) || \
172 ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) || \
173 ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) || \
174 ((__VALUE__) == LL_SPI_FIFO_TH_16DATA))
175
176 #define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) || \
177 ((__VALUE__) == LL_SPI_CRC_5BIT) || \
178 ((__VALUE__) == LL_SPI_CRC_6BIT) || \
179 ((__VALUE__) == LL_SPI_CRC_7BIT) || \
180 ((__VALUE__) == LL_SPI_CRC_8BIT) || \
181 ((__VALUE__) == LL_SPI_CRC_9BIT) || \
182 ((__VALUE__) == LL_SPI_CRC_10BIT) || \
183 ((__VALUE__) == LL_SPI_CRC_11BIT) || \
184 ((__VALUE__) == LL_SPI_CRC_12BIT) || \
185 ((__VALUE__) == LL_SPI_CRC_13BIT) || \
186 ((__VALUE__) == LL_SPI_CRC_14BIT) || \
187 ((__VALUE__) == LL_SPI_CRC_15BIT) || \
188 ((__VALUE__) == LL_SPI_CRC_16BIT) || \
189 ((__VALUE__) == LL_SPI_CRC_17BIT) || \
190 ((__VALUE__) == LL_SPI_CRC_18BIT) || \
191 ((__VALUE__) == LL_SPI_CRC_19BIT) || \
192 ((__VALUE__) == LL_SPI_CRC_20BIT) || \
193 ((__VALUE__) == LL_SPI_CRC_21BIT) || \
194 ((__VALUE__) == LL_SPI_CRC_22BIT) || \
195 ((__VALUE__) == LL_SPI_CRC_23BIT) || \
196 ((__VALUE__) == LL_SPI_CRC_24BIT) || \
197 ((__VALUE__) == LL_SPI_CRC_25BIT) || \
198 ((__VALUE__) == LL_SPI_CRC_26BIT) || \
199 ((__VALUE__) == LL_SPI_CRC_27BIT) || \
200 ((__VALUE__) == LL_SPI_CRC_28BIT) || \
201 ((__VALUE__) == LL_SPI_CRC_29BIT) || \
202 ((__VALUE__) == LL_SPI_CRC_30BIT) || \
203 ((__VALUE__) == LL_SPI_CRC_31BIT) || \
204 ((__VALUE__) == LL_SPI_CRC_32BIT))
205
206 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) || \
207 ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) || \
208 ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
209
210 #define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) || \
211 ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) || \
212 ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) || \
213 ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET))
214
215 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) || \
216 ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
217
218 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL)
219
220 /**
221 * @}
222 */
223
224 /* Private function prototypes -----------------------------------------------*/
225
226 /* Exported functions --------------------------------------------------------*/
227 /** @addtogroup SPI_LL_Exported_Functions
228 * @{
229 */
230
231 /** @addtogroup SPI_LL_EF_Init
232 * @{
233 */
234
235 /**
236 * @brief De-initialize the SPI registers to their default reset values.
237 * @param SPIx SPI Instance
238 * @retval An ErrorStatus enumeration value:
239 * - SUCCESS: SPI registers are de-initialized
240 * - ERROR: SPI registers are not de-initialized
241 */
LL_SPI_DeInit(SPI_TypeDef * SPIx)242 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
243 {
244 ErrorStatus status = ERROR;
245
246 /* Check the parameters */
247 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
248
249 #if defined(SPI1)
250 if (SPIx == SPI1)
251 {
252 /* Force reset of SPI clock */
253 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
254
255 /* Release reset of SPI clock */
256 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
257
258 /* Update the return status */
259 status = SUCCESS;
260 }
261 #endif /* SPI1 */
262 #if defined(SPI2)
263 if (SPIx == SPI2)
264 {
265 /* Force reset of SPI clock */
266 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
267
268 /* Release reset of SPI clock */
269 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
270
271 /* Update the return status */
272 status = SUCCESS;
273 }
274 #endif /* SPI2 */
275 #if defined(SPI3)
276 if (SPIx == SPI3)
277 {
278 /* Force reset of SPI clock */
279 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
280
281 /* Release reset of SPI clock */
282 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
283
284 /* Update the return status */
285 status = SUCCESS;
286 }
287 #endif /* SPI3 */
288 #if defined(SPI4)
289 if (SPIx == SPI4)
290 {
291 /* Force reset of SPI clock */
292 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
293
294 /* Release reset of SPI clock */
295 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
296
297 /* Update the return status */
298 status = SUCCESS;
299 }
300 #endif /* SPI4 */
301 #if defined(SPI5)
302 if (SPIx == SPI5)
303 {
304 /* Force reset of SPI clock */
305 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
306
307 /* Release reset of SPI clock */
308 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
309
310 /* Update the return status */
311 status = SUCCESS;
312 }
313 #endif /* SPI5 */
314 #if defined(SPI6)
315 if (SPIx == SPI6)
316 {
317 /* Force reset of SPI clock */
318 LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_SPI6);
319
320 /* Release reset of SPI clock */
321 LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_SPI6);
322
323 /* Update the return status */
324 status = SUCCESS;
325 }
326 #endif /* SPI6 */
327
328 return status;
329 }
330
331 /**
332 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
333 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled
334 * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
335 * Otherwise, ERROR result will be returned.
336 * @param SPIx SPI Instance
337 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
338 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
339 */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)340 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
341 {
342 ErrorStatus status = ERROR;
343 uint32_t tmp_nss;
344 uint32_t tmp_mode;
345 uint32_t tmp_nss_polarity;
346
347 /* Check the SPI Instance SPIx*/
348 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
349
350 /* Check the SPI parameters from SPI_InitStruct*/
351 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
352 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
353 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
354 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
355 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
356 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
357 assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate));
358 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
359 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
360
361 /* Check the SPI instance is not enabled */
362 if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
363 {
364 /*---------------------------- SPIx CFG1 Configuration ------------------------
365 * Configure SPIx CFG1 with parameters:
366 * - Master Baud Rate : SPI_CFG1_MBR[2:0] bits
367 * - CRC Computation Enable : SPI_CFG1_CRCEN bit
368 * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits
369 */
370 MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE,
371 SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth);
372
373 tmp_nss = SPI_InitStruct->NSS;
374 tmp_mode = SPI_InitStruct->Mode;
375 tmp_nss_polarity = LL_SPI_GetNSSPolarity(SPIx);
376
377 /* Checks to setup Internal SS signal level and avoid a MODF Error */
378 if ((tmp_nss == LL_SPI_NSS_SOFT) && (((tmp_nss_polarity == LL_SPI_NSS_POLARITY_LOW) && \
379 (tmp_mode == LL_SPI_MODE_MASTER)) || \
380 ((tmp_nss_polarity == LL_SPI_NSS_POLARITY_HIGH) && \
381 (tmp_mode == LL_SPI_MODE_SLAVE))))
382 {
383 LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
384 }
385
386 /*---------------------------- SPIx CFG2 Configuration ------------------------
387 * Configure SPIx CFG2 with parameters:
388 * - NSS management : SPI_CFG2_SSM, SPI_CFG2_SSOE bits
389 * - ClockPolarity : SPI_CFG2_CPOL bit
390 * - ClockPhase : SPI_CFG2_CPHA bit
391 * - BitOrder : SPI_CFG2_LSBFRST bit
392 * - Master/Slave Mode : SPI_CFG2_MASTER bit
393 * - SPI Mode : SPI_CFG2_COMM[1:0] bits
394 */
395 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE |
396 SPI_CFG2_CPOL | SPI_CFG2_CPHA |
397 SPI_CFG2_LSBFRST | SPI_CFG2_MASTER | SPI_CFG2_COMM,
398 SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity |
399 SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder |
400 SPI_InitStruct->Mode | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM));
401
402 /*---------------------------- SPIx CR1 Configuration ------------------------
403 * Configure SPIx CR1 with parameter:
404 * - Half Duplex Direction : SPI_CR1_HDDIR bit
405 */
406 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR);
407
408 /*---------------------------- SPIx CRCPOLY Configuration ----------------------
409 * Configure SPIx CRCPOLY with parameter:
410 * - CRCPoly : CRCPOLY[31:0] bits
411 */
412 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
413 {
414 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
415 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
416 }
417
418 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
419 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
420
421 status = SUCCESS;
422 }
423
424 return status;
425 }
426
427 /**
428 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
429 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
430 * whose fields will be set to default values.
431 * @retval None
432 */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)433 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
434 {
435 /* Set SPI_InitStruct fields to default values */
436 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
437 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
438 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
439 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
440 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
441 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
442 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
443 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
444 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
445 SPI_InitStruct->CRCPoly = 7UL;
446 }
447
448 /**
449 * @}
450 */
451
452 /**
453 * @}
454 */
455
456 /**
457 * @}
458 */
459 /** @addtogroup I2S_LL
460 * @{
461 */
462
463 /* Private types -------------------------------------------------------------*/
464 /* Private variables ---------------------------------------------------------*/
465 /* Private constants ---------------------------------------------------------*/
466 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
467 * @{
468 */
469 /* I2S registers Masks */
470 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
471 SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_CKPOL | \
472 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_MCKOE | \
473 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
474
475 /**
476 * @}
477 */
478 /* Private macros ------------------------------------------------------------*/
479 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
480 * @{
481 */
482
483 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) || \
484 ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) || \
485 ((__VALUE__) == LL_I2S_DATAFORMAT_24B) || \
486 ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) || \
487 ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
488
489 #define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__) (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH) || \
490 ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH))
491
492 #define IS_LL_I2S_CKPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) || \
493 ((__VALUE__) == LL_I2S_POLARITY_HIGH))
494
495 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) || \
496 ((__VALUE__) == LL_I2S_STANDARD_MSB) || \
497 ((__VALUE__) == LL_I2S_STANDARD_LSB) || \
498 ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) || \
499 ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
500
501 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) || \
502 ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) || \
503 ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX) || \
504 ((__VALUE__) == LL_I2S_MODE_MASTER_TX) || \
505 ((__VALUE__) == LL_I2S_MODE_MASTER_RX) || \
506 ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX))
507
508 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) || \
509 ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
510
511 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) && \
512 ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) || \
513 ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
514
515 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) <= 0xFFUL)
516
517 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) || \
518 ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
519
520 #define IS_LL_I2S_FIFO_TH (__VALUE__) (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA) || \
521 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA) || \
522 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA) || \
523 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA) || \
524 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA) || \
525 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA) || \
526 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA) || \
527 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA))
528
529 #define IS_LL_I2S_BIT_ORDER(__VALUE__) (((__VALUE__) == LL_I2S_LSB_FIRST) || \
530 ((__VALUE__) == LL_I2S_MSB_FIRST))
531 /**
532 * @}
533 */
534
535 /* Private function prototypes -----------------------------------------------*/
536
537 /* Exported functions --------------------------------------------------------*/
538 /** @addtogroup I2S_LL_Exported_Functions
539 * @{
540 */
541
542 /** @addtogroup I2S_LL_EF_Init
543 * @{
544 */
545
546 /**
547 * @brief De-initialize the SPI/I2S registers to their default reset values.
548 * @param SPIx SPI Instance
549 * @retval An ErrorStatus enumeration value:
550 * - SUCCESS: SPI registers are de-initialized
551 * - ERROR: SPI registers are not de-initialized
552 */
LL_I2S_DeInit(SPI_TypeDef * SPIx)553 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
554 {
555 return LL_SPI_DeInit(SPIx);
556 }
557
558 /**
559 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
560 * @note As some bits in I2S configuration registers can only be written when the SPI is disabled
561 * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
562 * Otherwise, ERROR result will be returned.
563 * @note I2S (SPI) source clock must be ready before calling this function. Otherwise will results
564 * in wrong programming.
565 * @param SPIx SPI Instance
566 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
567 * @retval An ErrorStatus enumeration value:
568 * - SUCCESS: SPI registers are Initialized
569 * - ERROR: SPI registers are not Initialized
570 */
LL_I2S_Init(SPI_TypeDef * SPIx,LL_I2S_InitTypeDef * I2S_InitStruct)571 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
572 {
573 uint32_t i2sdiv = 0UL;
574 uint32_t i2sodd = 0UL;
575 uint32_t packetlength = 1UL;
576 uint32_t ispcm = 0UL;
577 uint32_t tmp;
578 uint32_t sourceclock = 0UL;
579
580 ErrorStatus status = ERROR;
581
582 /* Check the I2S parameters */
583 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
584 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
585 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
586 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
587 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
588 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
589 assert_param(IS_LL_I2S_CKPOL(I2S_InitStruct->ClockPolarity));
590
591 /* Check that SPE bit is set to 0 in order to be sure that SPI/I2S block is disabled.
592 * In this case, it is useless to check if the I2SMOD bit is set to 0 because
593 * this bit I2SMOD only serves to select the desired mode.
594 */
595 if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
596 {
597 /*---------------------------- SPIx I2SCFGR Configuration --------------------
598 * Configure SPIx I2SCFGR with parameters:
599 * - Mode : SPI_I2SCFGR_I2SCFG[2:0] bits
600 * - Standard : SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
601 * - DataFormat : SPI_I2SCFGR_CHLEN, SPI_I2SCFGR_DATFMT and SPI_I2SCFGR_DATLEN[1:0] bits
602 * - ClockPolarity : SPI_I2SCFGR_CKPOL bit
603 * - MCLKOutput : SPI_I2SPR_MCKOE bit
604 * - I2S mode : SPI_I2SCFGR_I2SMOD bit
605 */
606
607 /* Write to SPIx I2SCFGR */
608 MODIFY_REG(SPIx->I2SCFGR,
609 I2S_I2SCFGR_CLEAR_MASK,
610 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
611 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
612 I2S_InitStruct->MCLKOutput | SPI_I2SCFGR_I2SMOD);
613
614 /*---------------------------- SPIx I2SCFGR Configuration ----------------------
615 * Configure SPIx I2SCFGR with parameters:
616 * - AudioFreq : SPI_I2SCFGR_I2SDIV[7:0] and SPI_I2SCFGR_ODD bits
617 */
618
619 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
620 * else, default values are used: i2sodd = 0U, i2sdiv = 0U.
621 */
622 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
623 {
624 /* Check the frame length (For the Prescaler computing)
625 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
626 */
627 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
628 {
629 /* Packet length is 32 bits */
630 packetlength = 2UL;
631 }
632
633 /* Check if PCM standard is used */
634 if ((I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_SHORT) ||
635 (I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_LONG))
636 {
637 ispcm = 1UL;
638 }
639
640 /* Get the I2S (SPI) source clock value */
641 #if defined(SPI1)
642 if (SPIx == SPI1)
643 {
644 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI1_CLKSOURCE);
645 }
646 #endif /* SPI1 */
647 #if defined(SPI2)
648 if (SPIx == SPI2)
649 {
650 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI23_CLKSOURCE);
651 }
652 #endif /* SPI2 */
653 #if defined(SPI3)
654 if (SPIx == SPI3)
655 {
656 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI23_CLKSOURCE);
657 }
658 #endif /* SPI3 */
659
660 /* Compute the Real divider depending on the MCLK output state with a fixed point */
661 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
662 {
663 /* MCLK output is enabled */
664 tmp = (((sourceclock / (256UL >> ispcm)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
665 }
666 else
667 {
668 /* MCLK output is disabled */
669 tmp = (((sourceclock / ((32UL >> ispcm) * packetlength)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
670 }
671
672 /* Remove the fixed point */
673 tmp = tmp / 16UL;
674
675 /* Check the parity of the divider */
676 i2sodd = tmp & 0x1UL;
677
678 /* Compute the i2sdiv prescaler */
679 i2sdiv = tmp / 2UL;
680 }
681
682 /* Test if the obtain values are forbidden or out of range */
683 if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL))
684 {
685 /* Set the default values */
686 i2sdiv = 0UL;
687 i2sodd = 0UL;
688 }
689
690 /* Write to SPIx I2SCFGR register the computed value */
691 MODIFY_REG(SPIx->I2SCFGR,
692 SPI_I2SCFGR_ODD | SPI_I2SCFGR_I2SDIV,
693 (i2sodd << SPI_I2SCFGR_ODD_Pos) | (i2sdiv << SPI_I2SCFGR_I2SDIV_Pos));
694
695 status = SUCCESS;
696 }
697
698 return status;
699 }
700
701 /**
702 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
703 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
704 * whose fields will be set to default values.
705 * @retval None
706 */
LL_I2S_StructInit(LL_I2S_InitTypeDef * I2S_InitStruct)707 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
708 {
709 /*--------------- Reset I2S init structure parameters values -----------------*/
710 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
711 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
712 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
713 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
714 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
715 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
716 }
717
718 /**
719 * @brief Set linear and parity prescaler.
720 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
721 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
722 * @param SPIx SPI Instance
723 * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
724 * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
725 * @param PrescalerParity This parameter can be one of the following values:
726 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
727 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
728 * @retval None
729 */
LL_I2S_ConfigPrescaler(SPI_TypeDef * SPIx,uint32_t PrescalerLinear,uint32_t PrescalerParity)730 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
731 {
732 /* Check the I2S parameters */
733 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
734 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
735 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
736
737 /* Write to SPIx I2SPR */
738 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos) |
739 (PrescalerParity << SPI_I2SCFGR_ODD_Pos));
740 }
741
742 /**
743 * @}
744 */
745
746 /**
747 * @}
748 */
749
750 /**
751 * @}
752 */
753
754 #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
755
756 /**
757 * @}
758 */
759 #endif /* USE_FULL_LL_DRIVER */
760
